AK4121VF

ASAHI KASEI [AK4121] AK4121 Asynchronous Sample Rate Converter GENERAL DESCRIPTION AK4121 is a stereo asynchronous sample rate converter. The input sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. Using the AK4121 simplifies system design, since the AK4121’s internal PLL eliminates the need for a master clock in slave mode. Then the AK4121 is suitable for applications requiring multiple sample rates, such as Car Audio, DVD recorders, and digital audio recording. FEATURES † Stereo asynchronous sample rate converter † Input sample rate range (FSI): 8kHz to 96kHz † Output sample rate (FSO): 32kHz/44.1kHz/48kHz/96kHz † Input to output Sample rate ratio: FSO/FSI = 0.33 to 6 † THD+N: –113dB † I/F format: MSB justified, LSB justified (24/20/16bit) and I2S † Clock for Master mode: 256/384/512/768fso † De-emphasis filter: 32kHz/44.1kHz/48kHz † SRC Bypass mode † Soft Mute function † Power Supply: VDD: 3.0 to 3.6V, TVDD: 3.0 to 5.5V (for input tolerant) † Ta: –40 to +85qC PDN DEM0 DEM1 SMUTE TVDD VDD DVSS (MCLK) SDTI ILRCK Serial Audio I/F IBICK De-em filter Sample Rate Converter soft mute Serial Audio I/F SDTO OLRCK OBICK CMODE2 AVSS CMODE1 PLL CMODE0 FILT IDIF2 IDIF1 IDIF0 ODIF1 MS0191-E-03 ODIF0 2004/08 -1- ASAHI KASEI [AK4121] „ Ordering Guide 40 a +85qC 24pin VSOP (0.65mm pitch) Evaluation Board for AK4121 AK4121VF AKD4121 „ Pin Layout FILT 1 24 VDD AVSS 2 23 DVSS PDN 3 22 TVDD SMUTE 4 21 MCLK DEM0 5 20 OLRCK DEM1 6 19 OBICK ILRCK 7 18 SDTO IBICK 8 17 ODIF1 SDTI 9 16 ODIF0 IDIF0 10 15 CMODE2 IDIF1 11 14 CMODE1 IDIF2 12 13 CMODE0 Top View „ Major Difference between AK4120 and AK4121 Items MCLK Input AK4120 Needed (supports 256/512fs) Input sample rate (max) Vdd Input 5V Tolerant De-emphasis Filter Soft Mute Digital Volume Digital Mixer 48kHz 2.7V ~ 3.6V X X X O O MS0191-E-03 AK4121 NOT Needed (Slave mode) / Needed (Master Mode: supports 256/384/512/768fs) 96kHz 3.0V ~ 3.6V O O O X X 2004/08 -2- ASAHI KASEI [AK4121] PIN/FUNCTION No. 1 2 Pin Name FILT AVSS 3 PDN 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SMUTE DEM0 DEM1 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 CMODE0 CMODE1 CMODE2 ODIF0 ODIF1 SDTO OBICK OLRCK MCLK TVDD DVSS VDD I/O O I I I I I I I I I I I I I I I I O I/O I/O I I I I Function Loop-Filter Pin for PLL Analog Ground Pin Power-Down pin When “L”, the AK4121 is powered-down and reset. Soft Mute Pin De-emphasis Filter Control Pin #0 De-emphasis Filter Control Pin #1 L/R Clock Pin for Input Audio Serial Data Clock Pin for Input Audio Serial Data Input Pin Input Data Format pin #0 Input Data Format pin #1 Input Data Format pin #2 Clock Mode Select Pin #0 Clock Mode Select Pin #1 Clock Mode Select Pin #2 Output Data Format pin #0 Output Data Format pin #1 Audio Serial Data Output Pin Audio Serial Data Clock Pin for Output L/R Clock Pin for Output Master Clock Pin for Output Input Buffer Power Supply Pin, 3.3V or 5V Digital Ground Pin Power Supply Pin, 3.3V MS0191-E-03 2004/08 -3- ASAHI KASEI [AK4121] ABSOLUTE MAXIMUM RATINGS (AVSS=DVSS=0V; Note 1) Parameter Symbol min max Units VDD TVDD ' GND IIN VIN Ta Tstg 0.3 0.3 4.6 6.0 0.3 r10 TVDD+0.3 85 150 V V V mA V qC qC Power Supplies: Core Input Buffer |AVSS-DVSS| (Note 1) Input Current, Any Pin Except Supplies Input Voltage Ambient Temperature (Power applied) Storage Temperature 0.3 40 65 Note 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS=DVSS=0V; Note 2) Parameter Power Supplies: Core Input Buffer Symbol VDD TVDD min 3.0 VDD typ 3.3 5 max 3.6 5.5 Units V V Note 2. All voltages with respect to ground. SRC PERFORMANCE (Ta=40a85qC; VDD=3.0a3.6V; TVDD=3.0~5.5V; data=20bit; measurement bandwidth=20Hz~FSO/2; unless otherwise specified.) Parameter Symbol min typ max Resolution 20 Input Sample Rate FSI 8 96 Output Sample Rate FSO 32 96 Dynamic Range (Input= 1kHz, 60dBFS, Note 3) 114 FSO/FSI=44.1kHz/48kHz 114 FSO/FSI=48kHz/44.1kHz 114 FSO/FSI=32kHz/48kHz 115 FSO/FSI=96kHz/32kHz Worst Case (FSO/FSI=32kHz/44.1kHz) 112 Dynamic Range (Input= 1kHz, 60dBFS, A-weighted, Note 3) 117 FSO/FSI=44.1kHz/48kHz THD+N (Input= 1kHz, 0dBFS, Note 3) 113 FSO/FSI=44.1kHz/48kHz FSO/FSI=48kHz/44.1kHz 112 FSO/FSI=32kHz/48kHz 113 FSO/FSI=96kHz/32kHz 111 Worst Case (FSO/FSI=48kHz/8kHz) 103 Ratio between Input and Output Sample Rate FSO/FSI (FSO/FSI, Note 4, Note 5) 0.33 6 Units Bits kHz kHz dB dB dB dB dB dB dB dB dB dB dB - Note 3. Measured by Rohde & Schwarz UPD04, Rejection Filter= wide, 8192point FFT. Note 4. The “0.33” is the ratio of FSO/FSI when FSI is 96kHz and FSO is 32kHz Note 5. The “6” is the ratio when FSI is 8kHz and FSO is 48kHz. MS0191-E-03 2004/08 -4- ASAHI KASEI [AK4121] DIGITAL FILTER (Ta=40a85qC; VDD=3.0a3.6V; TVDD=3.0~5.5V) Parameter Symbol min Digital Filter Passband 0.001dB 0.985 d FSO/FSI d 6.000 PB 0 0.905 d FSO/FSI  0.985 PB 0 0.714 d FSO/FSI  0.905 PB 0 0.656 d FSO/FSI  0.714 PB 0 0.536 d FSO/FSI  0.656 PB 0 0.492 d FSO/FSI  0.536 PB 0 0.452 d FSO/FSI  0.492 PB 0 0.333 d FSO/FSI  0.452 PB 0 Stopband 0.985 d FSO/FSI d 6.000 SB 0.5417FSI 0.905 d FSO/FSI  0.985 SB 0.5021FSI 0.714 d FSO/FSI  0.905 SB 0.3965FSI 0.656 d FSO/FSI  0.714 SB 0.3643FSI 0.536 d FSO/FSI  0.656 SB 0.2974FSI 0.492 d FSO/FSI  0.536 SB 0.2732FSI 0.452 d FSO/FSI  0.492 SB 0.2510FSI 0.333 d FSO/FSI  0.452 SB 0.1822FSI Passband Ripple PR Stopband Attenuation SA 96 Group Delay (Note 6) GD - typ max Units 0.4583FSI 0.4167FSI 0.3195FSI 0.2852FSI 0.2245FSI 0.2003FSI 0.1781FSI 0.1092FSI kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB dB 1/fs r0.01 57.5 - Note 6. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output, when LRCK for Output data corresponds with LRCK for Input.(at 20bit MSB justified, 16bit and 20bit LSB justified) DC CHARACTERISTICS (Ta=40a85qC; VDD=3.0~3.6V; TVDD=3.0~5.5V) Parameter Power Supply Current Normal operation: FSI=FSO=48kHz at Slave Mode: VDD=3.3V FSI=FSO=96kHz at Master Mode: VDD=3.3V : VDD=3.6V Power down: PDN = “L” (Note 7) High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=400PA) Low-Level Output Voltage (Iout=400PA) Input Leakage Current Symbol VIH VIL VOH VOL Iin min 0.7xVDD VDD-0.4 - typ max Units 10 20 40 100 0.3xVDD 0.4 r 10 mA mA mA PA V V V V PA 10 - Note 7. All digital inputs including clock pins are held VSS. MS0191-E-03 2004/08 -5- ASAHI KASEI [AK4121] SWITCHING CHARACTERISTICS (Ta=40a85qC; VDD=3.0~3.6V; TVDD=3.0~5.5V; CL=20pF) Parameter Symbol min Master Clock Input (MCLK) Frequency fCLK 8.192 Duty Cycle dCLK 40 L/R clock for Input data (ILRCK) Frequency fs 8 Duty Cycle Duty 48 L/R clock for Output data (OLRCK) Frequency (Note 9) fs 32 Duty Cycle Slave Mode Duty 48 Master Mode Duty Audio Interface Timing Input IBICK Period 1/64fs tBCK IBICK Pulse Width Low 65 tBCKL IBICK Pulse Width High 65 tBCKH ILRCK Edge to IBICK “n” (Note 9) 30 tBLR 30 tLRB BICK “n” to ILRCK Edge (Note 9) 30 tSDH SDTI Hold Time from IBICK “n” 30 tSDS SDTI Setup Time to IBICK “n” Output (Slave Mode) OBICK Period 1/64fs tBCK OBICK Pulse Width Low 65 tBCKL OBICK Pulse Width High 65 tBCKH OLRCK Edge to OBICK “n” (Note 9) 30 tBLR 30 tLRB OBICK “n” to OLRCK Edge (Note 9) tLRS OLRCK to SDTO (MSB) tBSD OBICK “p” to SDTO Output (Master Mode) BICK Frequency fBCK BICK Duty dBCK tMBLR 20 BICK “p” to LRCK tBSD 20 BICK “p” to SDTO Power-down & Reset Timing PDN Pulse Width (Note 10) tPD 150 typ max Units - 36.864 60 MHz % 50 96 52 kHz % 96 52 kHz % % 50 50 ns ns ns ns ns ns ns 30 30 ns ns ns ns ns ns ns 20 30 Hz % ns ns 64fs 50 ns Note 8. Min is 8kHz when BYPASS=“H”. Note 9. BICK rising edge must not occur at the same time as LRCK edge. Note 10. The AK4121 must be reset by bringing PDN “L” to “H” upon power-up. MS0191-E-03 2004/08 -6- ASAHI KASEI [AK4121] „ Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD 70%VDD SDTO 30%VDD tSDS tSDH VIH SDTI VIL Audio Interface Timing at Slave Mode MS0191-E-03 2004/08 -7- ASAHI KASEI [AK4121] LRCK 50%VDD tMBLR dBCK 50%VDD BICK tBSD 50%VDD SDTO Audio Interface Timing at Master Mode tPD VIH PDN VIL Power-down & Reset Timing Note: BICK means IBICK and OBICK. LRCK means ILRCK and OLRCK. MS0191-E-03 2004/08 -8- ASAHI KASEI [AK4121] OPERATION OVERVIEW „ System Clock The input port works in slave mode only. The output port works in slave or master mode. An internal system clock is created by the internal PLL using ILRCK. The MCLK is not needed when the output port is in slave mode, and in slave mode set the MCLK pin to DVSS. The CMODE2-0 pins select the master/slave and bypass mode. The CMODE2-0 pins should be controlled when pin PDN=“L”. Mode 0 1 2 3 4 5 6 7 CMODE2 L L L L H H H H CMODE1 L L H H L L H H CMODE0 MCLK L 256fso (fso~96kHz) H 384fso (fso~96kHz) L 512fso (fso~48kHz) H 768fso (fso~48kHz) L Not used. Set to DVSS H L H Not used. Set to DVSS Table 1. Master/Slave control Master/Slave (Output Port) Master Master Master Master Slave (Reserved) (Reserved) Master (BYPASS mode) „ Audio Interface Format The IDIF2-0 pins select the data mode for the input port. The ODIF1-0 pins select the data mode for the output port. In all modes the audio data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of OBICK. Select these modes when PDN=“L”. When in BYPASS mode, both IBICK and OBICK are fixed to 64fs. Mode 0 1 2 3 4 Mode 0 1 2 3 IDIF2 L L L L H ODIF1 L L H H IDIF1 L L H H L ODIF0 L H L H IDIF0 SDTI Format L 16bit LSB Justified H 20bit LSB Justified L 20bit MSB Justified H 20/16bit I2S Compatible L 24bit LSB Justified Table 2. Input Audio Data Formats SDTO Format OBICK (Slave) 16bit LSB Justified 64fs 20bit LSB Justified 64fs 20/16bit MSB Justified t40fs or 32fs 20/16bit I2S Compatible t40fs or 32fs Table 3. Output Audio Data Formats MS0191-E-03 IBICK (Slave) t32fs t40fs t40fs t40fs or 32fs t48fs OBICK (Master) 64fs 64fs 64fs 64fs 2004/08 -9- ASAHI KASEI [AK4121] LRCK 0 1 12 13 14 15 16 31 0 1 12 13 14 15 16 31 0 1 0 1 BICK (64fs) SDTI 16bit Don’t care 15 0 Don’t care 15 0 Don’t care 15 0 15 0 15:MSB, 0:LSB SDTI 20bit 19 Don’t care 18 17 16 19 18 16 17 19:MSB, 0:LSB Lch Data Rch Data Figure 1. LSB justified Timing LRCK 0 1 2 18 19 20 30 31 0 1 2 18 19 20 30 31 BICK (64fs) SDTI 19 18 1 0 Don’t care 19 18 1 0 Don’t care 19 18 0 1 20:MSB, 0:LSB Lch Data Rch Data Figure 2. MSB justified Timing LRCK 0 1 2 3 19 20 21 31 0 1 2 3 19 20 21 31 BICK (64fs) SDTI 19 18 1 0 Don’t care 19 18 1 0 Don’t care 19 19:MSB, 0:LSB Lch Data Rch Data 2 Figure 3. I S Timing MS0191-E-03 2004/08 - 10 - ASAHI KASEI [AK4121] „ Soft Mute Operation When the SMUTE pin goes to “H”, the output signal is attenuated from 0dB to fdB during 1024 OLRCK cycles. When the SMUTE pin returns to “0”, the mute is cancelled and the attenuation gradually changes to 0dB during 1024 OLRCK cycles. If the soft mute is cancelled before attenuating to f, the attenuation is discontinued and returns to 0dB. This return takes the same number of clock cycles as the point at which the soft mute cancel was initiated, i.e. if 500 clock cycles passed and then a soft mute cancel was issued, it will take 500 clock cycles to return to 0dB. The soft mute is used primarily when changing the signal source. SMUTE 0dB Attenuation Level at SDTO -fdB (2) (1) (1) Notes: (1) Transition time. 1024 OLRCK cycles (1024/fso). (2) If the soft mute is cancelled before attenuating to f after starting the operation, the attenuation is discontinued and returned to 0dB by the same number of clock cycles. Figure 4. Soft Mute „ De-emphasis Filter A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc=50/15μs) and is enabled or disabled with DEM0 and DEM1. DEM1 DEM0 Mode 0 0 44.1kHz Default 0 1 OFF 1 0 48kHz 1 1 32kHz Table 4. De-emphasis Filter Control MS0191-E-03 2004/08 - 11 - ASAHI KASEI [AK4121] „ System Reset Bringing the PDN=“L” places the AK4121 in power-down mode and initializes the digital filter. The AK4121 should be reset once by bringing PDN=“L” upon power-up. Regarding the SDTO valid time, please refer following table. Until then, the SDTO outputs “L”. Case 1 External clocks (input port) don’t care (state1) (state2) don’t care SDTI don’t care (state1) (state2) don’t care External clocks (output port) don’t care (state1) (state2) don’t care PDN ta tb (note) (internal state) Power-down SDTO PLL lock & fs detection “0” data normal operation normal data PLL lock & fs detection PD “0” data normal operation Power-down normal data “0” data Case 2 External clocks (input port) (no clock) (state1) don’t care SDTI (don’t care) (state1) don’t care External clocks (output port) (don’t care) (state1) don’t care PDN (note) PLL Unlock (internal state) Power-down SDTO PLL lock & fs detection “0” data normal operation Power-down normal data “0” data Note: