[AK4136]
AK4136
32bit 384kHz SRC
1. General Description
The AK4136 is a 2ch digital sample rate converter (SRC). The input sample rate ranges from 8kHz to
384kHz. The output sample rate is from 8kHz to 384kHz. The AK4136 has an internal Oscillator.
Therefore it does not need any external master clocks and simplifies system configuration. The AK4136
is suitable for a high-resolution audio application interfacing to different sample rates such as Network
Audios, USB DACs and Car Audios.
Application: AV Receivers, CD/SACD Players, Network Audios, USB DACs, USB Headphones,
Sound Plate/Bars, Car Audios, Automotive External Amplifiers, Measuring Instruments,
Control Systems, Public Audios (PA), IC-Recorders, Bluetooth Headphones, HD
Audio/Voice Conference Systems
2. Features
2 channels input/output
Asynchronous Sample Rate Converter
PCM
Input Sample Rate Range (FSI): 8kHz ~ 384kHz
Output Sample Rate Range (FSO): 8kHz ~ 384kHz
Input to Output Sample Rate Ratio: FSO/FSI = 1/6 ~ 12
THD+N: Up to -140dB
Dynamic Range: 176dB (A-weighted)
I/F format: MSB justified, LSB justified, I2S compatible and TDM
Oscillator for Internal Operation Clock
Clock for Master mode: 128/192/256/384/512/768fso
On-chip X’tal oscillator
Digital De-emphasis Filter (32kHz, 44.1kHz, 48kHz) (Serial Mode Only)
Soft Mute Function
SRC Bypass mode (Master/Slave, PCM)
uP Interface：I2C bus/SPI 4-wire
Power Supply
DVDD: 3.0~3.6V (internal LDO enabled)
DVDD: 1.7~1.9V (internal LDO disabled)
Ta: -40 ~ +105°C
Package: 48-pin LQFP (0.5mm pitch)
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3. Table of Contents
1.
2.
3.
4.
5.
General Description ............................................................................................................................ 1
Features .............................................................................................................................................. 1
Table of Contents ................................................................................................................................ 2
Block Diagram ..................................................................................................................................... 5
Pin Configurations and Functions ....................................................................................................... 6
■ Pin Configurations ............................................................................................................................. 6
■ Pin Functions..................................................................................................................................... 7
6. Absolute Maximum Ratings .............................................................................................................. 10
7. Recommended Operation Conditions............................................................................................... 10
8. SRC Characteristics ...........................................................................................................................11
■ PCMIN → PCMOUT .......................................................................................................................11
9. Power Consumptions ........................................................................................................................ 12
■ Internal LDO Mode .......................................................................................................................... 12
■ DV18 External Supply Mode ........................................................................................................... 12
10.
Filter Characteristics ...................................................................................................................... 13
■ Sharp Roll-Off Filter Characteristics ............................................................................................... 13
■ Slow Roll-Off Filter Characteristics ................................................................................................. 14
■ Short Delay Sharp Roll-Off Filter Characteristics ........................................................................... 15
■ Short Delay Slow Roll-Off Filter Characteristics ............................................................................. 16
11.
Input and Output Examples ........................................................................................................... 16
12.
DC Characteristics......................................................................................................................... 17
13.
Switching Characteristics .............................................................................................................. 17
■ Timing Diagrams ............................................................................................................................. 23
14.
Functional Descriptions ................................................................................................................. 30
■ Power-up Sequence ........................................................................................................................ 30
■ SRC Bypass Mode .......................................................................................................................... 31
■ System Clock and Audio Interface Format for Input PORT ............................................................ 33
■ System Clock for Output PORT ...................................................................................................... 37
■ Audio Interface Format for Output PORT ....................................................................................... 39
■ Cascade Connection in TDM Mode ................................................................................................ 44
■ Soft Mute Function .......................................................................................................................... 45
■ Dither Circuit.................................................................................................................................... 46
■ Digital Filter...................................................................................................................................... 47
■ De-emphasis Filter .......................................................................................................................... 47
■ Regulator ......................................................................................................................................... 47
■ System Reset .................................................................................................................................. 48
■ Internal Reset Function for Clock Change ...................................................................................... 49
■ When the Frequency of ILRCK at Input Port Is Changed Without A Reset by The PDN Pin or
RSTN Bit ............................................................................................................................................... 51
■ When the Frequency of OLRCK at Output Port Is Changed Without A Reset by The PDN Pin or
RSTN Bit ............................................................................................................................................... 51
■ Pop Noise Reduction in Sampling Rate Conversion ...................................................................... 51
■ Internal Status Pin ........................................................................................................................... 52
■ Serial Control Interface ................................................................................................................... 53
■ Register Map ................................................................................................................................... 57
■ Register Definitions ......................................................................................................................... 58
15.
Jitter Tolerance .............................................................................................................................. 61
16.
Recommended External Circuit .................................................................................................... 62
17.
Package ......................................................................................................................................... 64
■ Outline Dimensions ......................................................................................................................... 64
■ Material & Lead Finish .................................................................................................................... 64
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■ Marking ............................................................................................................................................ 65
18.
Ordering Guide .............................................................................................................................. 65
19.
Revision History............................................................................................................................. 66
IMPORTANT NOTICE .............................................................................................................................. 67
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AK4137
bit
DR（A-Weighted）
THD+N
fsi
fso
Ratio I/O
Output Clock
(Master Mode Operation)
SRC Conversion
SRC Bypass Function
Soft Mute
DITHER
De-emphasis
Internal Regulator
External 1.8V Input
Crystal Oscillator
Pop Noise reduction on
Rate Switching
Micro Controller I/F
016000098-E-00
AK4136
32
186
150
8 ~ 768kHz
8 ~ 768kHz
1/6 ~ 24
←
176
140
8 ~ 384kHz
8 ~ 384kHz
1/6 ~ 12
64/128/256/384/512/768fso
128/256/384/512/768fso
PCM → PCM, DSD → DSD
DSD → PCM, PCM → DSD
DoP → DSD, DoP → PCM
Available (Master, Slave)
Available
Semi-Auto Mode
Mute Time Setting Adjustment
PCM → PCM conversion only
Available
Available
3V→1.8V
Available
Available
←
Available
Semi-Auto Mode and Mute Time
Adjustment are only available by
register settings.
Available (only by register settings)
Available (only by register settings)
←
←
←
Available
←
I2C, 4-wire
←
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[AK4136]
SDTI
ILRCK
IBICK
TDM
ODIF1
ODIF0
OBIT1
OBIT0
SRCEN
4. Block Diagram
BYPASS
PCM
Input
Serial
Audio
I/F
PCM
FIR
DEM
PCM
Output
Serial
Audio
I/F
SRC
COMB
SMUTE
SRC
Dither
Internal
OSC
PDN
OBICK
DVSS
DVDD
CM2
CM1
Clock
Div.
CM0
XTO
X’tal
OSC
XTI/OMCLK/TDMI
CDTO
SDA/CDTI/SLOW
CSN/SMUTE
SCL/CCLK/SD
CAD0/IDIF0
CAD1/IDIF1
IDIF2
DV18
Internal
Regulator
UP/IF
VSEL
I2C
OLRCK
TEST1
TEST0
REF
PSN
SDTO
Figure 1. Block Diagram
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5. Pin Configurations and Functions
DVDD
DVDD
DVSS
XTI/OMCLK/TDMI
CLKMODE
XTO
TDM
OLRCK
OBICK
SDTO
NC
NC
36
35
34
33
32
31
30
29
28
27
26
25
■ Pin Configurations
OBIT0
37
24
NC
OBIT1
38
23
NC
CM0
39
22
NC
CM1
40
21
ODIF0
CM2
41
20
ODIF1
NC
42
19
CSN/SMUTE
VSEL
43
18
SCL/CCLK
DV18
44
17
DVSS
45
16
SDA/CDTI/SL
/SD
CDTO
OW
SLOW
DVDD
46
15
PSN
NC
47
14
PDN
NC
48
13
I2C
AK4136
11
12
TEST1
9
IDIF2
TEST0
8
CAD1/IDIF1
F0
10
7
CAD0/IDI
SRCEN
6
4
ILRCK
SDTI
3
NC
5
2
NC
IBICK
1
NC
Top View
Figure 2. Pin Layout
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■ Pin Functions
No.
Pin Name
I/O
9
NC
NC
NC
ILRCK
IBICK
SDTI
CAD0
IDIF0
CAD1
IDIF1
IDIF2
I
I
I
I
I
I
I
I
10
SRCEN
O
11
12
TEST0
TEST1
I
I
13
I2C
I
14
PDN
I
15
PSN
I
16
CDTO
SDA
CDTI
SLOW
SCL
CCLK
SD
CSN
O
I/O
I
I
I
I
I
I
SMUTE
I
ODIF1
ODIF0
NC
NC
I
I
-
1
2
3
4
5
6
7
8
17
18
19
Function
This pin must be connected to DVSS.
This pin must be connected to DVSS.
This pin must be connected to DVSS.
L/R Clock Pin in PCM Mode
Audio Serial Data Clock Pin in PCM Mode
Audio Serial Data Input Pin in PCM Mode
Chip Address 0 Pin in Serial Control Mode
Digital Input Format 0 Pin in Parallel Control Mode
Chip Address 1 Pin in Serial Control Mode
Digital Input Format 1 Pin in Parallel Control Mode
Digital Input Format 2 Pin in Parallel Control Mode
Unlock Status Pin
When the PDN pin= “L”, this pin outputs “H”.
Test pin 0. Must be connected to DVSS in normal use.
Test pin 1. Must be connected to DVSS in normal use.
Select serial mode
“L”: 4-wire serial Mode ,“H”: I2C Mode
Power-Down Mode Pin
“H”: Power up,
“L”: Power down reset and initializes the control register.
The AK4136 should be reset once by bringing PDN pin = “L” upon
power-up.
Parallel/Serial Mode Select
“L”: Serial Mode , “H”: Parallel Mode
I2C= “L”: Control Data Output Pin in Serial Control Mode
I2C= “H”: Control Data In/Out Pin in Serial Control Mode
I2C= “L”: Control Data Input Pin in Serial Control Mode
Digital Filter Select Pin in Parallel Control Mode
I2C= “H”: Control Data Clock Input Pin in Serial Control Mode
I2C= “L”: Control Data Clock Pin in Serial Control Mode
Digital Filter Select Pin in Parallel Control Mode
Chip Select Pin in Serial Control Mode, I2C= “L”
Soft Mute Pin in Parallel Control Mode
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
Audio Interface Format #1 Pin for Output PORT
Audio Interface Format #0 Pin for Output PORT
This pin must be connected to DVSS.
This pin must be connected to DVSS.
NC
This pin must be connected to DVSS.
NC
This pin must be connected to DVSS.
NC
This pin must be connected to DVSS.
Note 1. All input pins must not be allowed to float. DVDD must be connected to the same power supply.
Note 2. PSN, CM2-0, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD1-0 pins must be changed when the
PDN pin = “L”.
20
21
22
23
24
25
26
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No.
Pin Name
I/O
Function
Audio Serial Data Output Pin for Output PORT
When the PDN pin = “L”, the SDTO pin outputs “L”.
Audio Serial Data Clock Pin for Output PORT
28 OBICK
I/O
When the PDN pin = “L” in master mode, the OBICK pin outputs “L”.
Output Channel Clock Pin for Output PORT
29 OLRCK
I/O
When the PDN pin = “L” in master mode, the OLRCK pin outputs “L”.
TDM Format Select Pin
30 TDM
I
“L”(connected to DVSS): Stereo Mode
“H”(connected to DVDD): TDM mode for Output
X’tal Output Pin
31 XTO
When the PDN pin = “L” or CM2-0 pins = “HHL” or “HHH”, XTO outputs
O
“L”.
Master Clock Select Pin
32 CLKMODE
I
“L”(connected to DVSS): X'tal Mode
“H”(connected to DVDD): External Master Clock or TDM pin = “H”
XTI
I
X’tal Input Pin
33 OMCLK
I
External Master Clock Input
TDMI
I
TDMI Daisy-Chain Input Pin
34 DVSS
Digital Ground Pin
35 DVDD
Digital Power Supply Pin, 3.0 3.6V or 1.7 1.9V
36 DVDD
Digital Power Supply Pin, 3.0 3.6V or 1.7 1.9V
37 OBIT0
I
Bit Length Select #0 Pin for Output Data
38 OBIT1
I
Bit Length Select #1 Pin for Output Data
39 CM0
I
Clock Select or Mode Select #0 Pin for Output PORT
40 CM1
I
Clock Select or Mode Select #1 Pin for Output PORT
41 CM2
I
Clock Select or Mode Select #2 Pin for Output PORT
42 NC
This pin must be connected to DVSS.
Digital Power select
43 VSEL
I
“L”: DV18 is Output pin, “H”: DV18 is Power Supply Pin
Digital Power Pin, Typ 1.8V
VSEL= “L”, Output
When the PDN pin= “L”, the DV18 pin outputs “L”. Current must not be
taken from this pin. A 10μF (±30%; including the temperature
44 DV18
I/O
characteristics) capacitor should be connected between this pin and
DVSS. When this capacitor is polarized, the positive polarity pin should
be connected to the DV18 pin.
VSEL= “H”, Input
45 DVSS
Digital Ground Pin
46 DVDD
Digital Power Supply Pin, 3.0 3.6V or 1.7 1.9V
47 NC
This pin must be connected to DVSS.
48 NC
This pin must be connected to DVSS.
Note 1. All input pins must not be allowed to float. DVDD must be connected to the same power supply.
Note 2. PSN, CM2-0, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD1-0 pins must be changed when the
PDN pin = “L”.
27
SDTO
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*Unused Input/Output Pins
Classification
Digital
Pin Name
CSN/SMUTE
XTI/OMCLK/TDMI
SRCEN, XTO, CDTO
Setting
Connect to DVSS
Connect to DVSS (Slave Mode)
Open
* The status of OLRCK and OBICK pins, when the PDN pin = “L”, are shown below. (“L” output in
Master mode)
Setting Pins
CM2
CM1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
CM0
L
H
L
H
L
H
L
H
OLRCK,
OBICK
“L” Output
Input
“L” Output
* The output pin status when the PDN pin = “L” is shown below.
Output Pin
SDTO
SRCEN
XTO
CDTO
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Status
“L” Output
“H” Output
“L” Output
Hi-z
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[AK4136]
6. Absolute Maximum Ratings
(DVSS=0V; Note 3)
Parameter
Power Supplies Digital
(Internal Digital) (Note 4)
Input Current, Any Pin Except Supplies
Digital Input Voltage (Note 5)
Symbol
DVDD
DV18
IIN
Min.
-0.3
-0.3
-
VDIN
-0.3
Max.
4.3
2.5
10
(DVDD+0.3)
or 4.3
105
150
Unit
V
V
mA
V
Ambient Temperature (Power applied) (Note 6)
Ta
-40
C
Storage Temperature
Tstg
-65
C
Note 3. All voltages are with respect to ground.
Note 4. DVSS must be connected to the same ground.
Note 5. ILRCK,IBICK, SDTI, IDIF0/CAD0, IDIF1/CAD1, IDIF2, PDN, PSN, I2C, SLOW/CDTI/SDA,
SD/CCLK/SCL, SMUTE/CSN, OBIT1-0, ODIF1-0,CM2-0, VSEL, TEST1-0 pin
Note 6. In the case that the PCB wiring density is more than 100%
WARING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operation Conditions
(DVSS=0V; Note 3; VSEL= “L”)
Parameter
Symbol
Min.
Typ.
Power Supplies
Digital
DVDD
3.0
3.3
Max.
3.6
Unit
V
(DVSS=0V; Note 3; VSEL= “H”)
Parameter
Power Supplies:
Digital
(Note 7)
Digital
Symbol
DVDD
DV18
DVDD- DV18
Difference
Note 3. All voltages are with respect to ground.
Note 7. DVDD and DV18 should be connected externally.
Min.
1.7
1.7
Typ.
1.8
1.8
Max.
1.9
1.9
Unit
V
V
-
0
-
V
The PDN pin must be “L” when power up the AK4136. Set the PDN pin to “H” after all power supplies
are ON. Writing by a microcontroller should be executed with a 5ms interval after the PDN pin = “H”.
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[AK4136]
8. SRC Characteristics
■ PCMIN → PCMOUT
(Ta=-40 +105C; DVDD=3.03.6V or DVDD=DV18=1.7V1.9V; DVSS=0V; Signal Frequency = 1kHz;
data = 32bit; measurement bandwidth = 20HzFSO/2; unless otherwise specified.)
Parameter
Symbol
Min.
Typ.
Max. Unit
Resolution
32
Bits
Input Sample Rate
FSI
8
384
kHz
Output Sample Rate
FSO
8
384
kHz
THD+N
(Input = 1kHz, 0dBFS)
FSO/FSI = 48kHz/48kHz
-140
dB
FSO/FSI = 48kHz/44.1kHz
-133
dB
FSO/FSI = 48kHz/192kHz
-143
dB
FSO/FSI = 192kHz/48kHz
-134
dB
Worst Case (FSO/FSI=32kHz/176.4kHz)
-100
dB
Dynamic Range (Input = 1kHz, -60dBFS)
FSO/FSI = 48kHz/44.1kHz
170
dB
FSO/FSI = 48kHz/192kHz
174
dB
FSO/FSI = 192kHz/48kHz
170
dB
FSO/FSI = 32kHz/176.4kHz
170
dB
Worst Case (FSO/FSI = 48kHz/48kHz)
168
dB
Dynamic Range (Input = 1kHz, -60dBFS, A-weighted)
FSO/FSI = 8kHz/48kHz
176
dB
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
12
-
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9. Power Consumptions
■ Internal LDO Mode
(Ta=-40 +105C; DVDD=3.03.6V)
Parameter
Symbol
Power Supply Current
Normal operation: (PDN = “H”)
FSI=FSO=48kHz at Master Mode : DVDD=3.3V
FSI=FSO=192kHz at Master Mode: DVDD=3.3V
FSI=FSO=384kHz at Master Mode: DVDD=3.3V
: DVDD=3.6V
Power down: PDN pin = “L” (Note 8)
DVDD=3.6V
Note 8. All digital inputs including clock pins are held to DVSS.
Min.
Typ.
Max.
Unit
-
11
33
40
-
60
mA
mA
mA
mA
10
100
A
■ DV18 External Supply Mode
(Ta=-40 +105C; DVDD=DV18=1.71.9V)
Parameter
Symbol
Power Supply Current
Normal operation:
FSI=FSO=48kHz at Master Mode : DVDD＝DV18=1.8V
FSI=FSO=192kHz at Master Mode: DVDD＝DV18=1.8V
FSI=FSO=384kHz at Master Mode: DVDD＝DV18=1.8V
: DVDD＝DV18=1.9V
Power down: PDN pin = “L” (Note 8)
DVDD=DV18=1.9V
Note 8. All digital inputs including clock pins are held to DVSS.
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Min.
Typ.
Max.
Unit
-
11
28
32
-
50
mA
mA
mA
mA
10
100
A
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[AK4136]
10. Filter Characteristics
■ Sharp Roll-Off Filter Characteristics
(Ta=-40 +105C; DVDD=3.03.6V or DVDD=DV18=1.7V1.9V, DVSS=0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband
0.985 FSO/FSI 12.000
PB
0
kHz
0.4583FSI
0.01dB
0.905 FSO/FSI 0.985
PB
0
kHz
0.4167FSI
0.714 FSO/FSI 0.905
PB
0
kHz
0.3195FSI
0.656 FSO/FSI 0.714
PB
0
kHz
0.2852FSI
0.536 FSO/FSI 0.656
PB
0
kHz
0.2182FSI
0.492 FSO/FSI 0.536
PB
0
kHz
0.2177FSI
0.452 FSO/FSI 0.492
PB
0
kHz
0.1948FSI
0.357 FSO/FSI 0.452
PB
0
kHz
0.1458FSI
0.324 FSO/FSI 0.357
PB
0
kHz
0.1302FSI
0.246 FSO/FSI 0.324
PB
0
kHz
0.0917FSI
0.226 FSO/FSI 0.246
PB
0
kHz
0.0826FSI
0.1667 FSO/FSI 0.226
PB
0
kHz
0.0583FSI
Stopband
0.985 FSO/FSI 12.000
SB
0.5417FSI
kHz
0.905 FSO/FSI 0.985
SB
0.5021FSI
kHz
0.714 FSO/FSI 0.905
SB
0.3965FSI
kHz
0.656 FSO/FSI 0.714
SB
0.3643FSI
kHz
0.536 FSO/FSI 0.656
SB
0.2974FSI
kHz
0.492 FSO/FSI 0.536
SB
0.2813FSI
kHz
0.452 FSO/FSI 0.492
SB
0.2604FSI
kHz
0.357 FSO/FSI 0.452
SB
0.2116FSI
kHz
0.324 FSO/FSI 0.357
SB
0.1969FSI
kHz
0.246 FSO/FSI 0.324
SB
0.1573FSI
kHz
0.226 FSO/FSI 0.246
SB
0.1471FSI
kHz
0.1667 FSO/FSI 0.226
SB
0.1020FSI
kHz
0.226
FSO/FSI
12.000
PR
0.01
dB
Passband
Ripple
0.1667 FSO/FSI 0.226
PR
0.03
dB
Stopband
0.985 FSO/FSI 12.000
SA
140.2
dB
Attenuation
0.905 FSO/FSI 0.985
SA
140.9
dB
0.714 FSO/FSI 0.905
SA
135.2
dB
0.656 FSO/FSI 0.714
SA
135.1
dB
0.536 FSO/FSI 0.656
SA
133.5
dB
0.492 FSO/FSI 0.536
SA
115.3
dB
0.452 FSO/FSI 0.492
SA
118.2
dB
0.357 FSO/FSI 0.452
SA
123.3
dB
0.324 FSO/FSI 0.357
SA
122.9
dB
0.246 FSO/FSI 0.324
SA
117.9
dB
0.226 FSO/FSI 0.246
SA
119.7
dB
0.1667 FSO/FSI 0.226
SA
90.3
dB
Group Delay
GD
64
1/fs
(Note 9)
Note 9. This is the time from a rising edge of ILRCK after L and R channels data is input to a rising edge
of OLRCK before the L and R channels data is output, when there is no phase difference
between input and output data.
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■ Slow Roll-Off Filter Characteristics
(Ta=-40 +105C; DVDD=3.03.6V or DVDD=DV18=1.7V1.9V, DVSS=0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband 0.01dB 0.1667 FSO/FSI 12.000
PB
0
0.0417FSI kHz
Stopband
0.1667 FSO/FSI 12.000
SB
0.4167FSI
kHz
Passband Ripple
PR
0.01
dB
Stopband Attenuation
SA
108.1
dB
Group Delay
(Note 9)
GD
64
1/fs
Note 9. This is the time from a rising edge of ILRCK after L and R channels data is input to a rising edge
of OLRCK before the L and R channels data is output, when there is no phase difference
between input and output data.
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[AK4136]
■ Short Delay Sharp Roll-Off Filter Characteristics
(Ta=-40 +105C; DVDD=3.03.6V or DVDD=DV18=1.7V1.9V, DVSS=0V)
Parameter
Symbol
Min.
Typ.
Digital Filter
Passband
PB
0
0.985 FSO/FSI 12.000
0.01dB
PB
0
0.905 FSO/FSI 0.985
PB
0
0.714 FSO/FSI 0.905
PB
0
0.656 FSO/FSI 0.714
PB
0
0.536 FSO/FSI 0.656
PB
0
0.492 FSO/FSI 0.536
PB
0
0.452 FSO/FSI 0.492
PB
0
0.357 FSO/FSI 0.452
PB
0
0.324 FSO/FSI 0.357
PB
0
0.246 FSO/FSI 0.324
PB
0
0.226 FSO/FSI 0.246
PB
0
0.1667 FSO/FSI 0.226
Stopband
SB
0.5417FSI
0.985 FSO/FSI 12.000
SB
0.5021FSI
0.905 FSO/FSI 0.985
SB
0.3965FSI
0.714 FSO/FSI 0.905
SB
0.3643FSI
0.656 FSO/FSI 0.714
SB
0.2974FSI
0.536 FSO/FSI 0.656
SB
0.2813FSI
0.492 FSO/FSI 0.536
SB
0.2604FSI
0.452 FSO/FSI 0.492
SB
0.2116FSI
0.357 FSO/FSI 0.452
SB
0.1969FSI
0.324 FSO/FSI 0.357
SB
0.1573FSI
0.246 FSO/FSI 0.324
SB
0.1471FSI
0.226 FSO/FSI 0.246
SB
0.1020FSI
0.1667 FSO/FSI 0.226
PR
0.226 FSO/FSI 12.000
Passband
Ripple
PR
0.1667 FSO/FSI 0.226
Stopband
SA
140.2
0.985 FSO/FSI 24.000
Attenuation
SA
140.9
0.905 FSO/FSI 0.985
SA
135.2
0.714 FSO/FSI 0.905
SA
135.1
0.656 FSO/FSI 0.714
SA
133.5
0.536 FSO/FSI 0.656
SA
115.3
0.492 FSO/FSI 0.536
SA
118.2
0.452 FSO/FSI 0.492
SA
123.3
0.357 FSO/FSI 0.452
SA
122.9
0.324 FSO/FSI 0.357
SA
117.9
0.246 FSO/FSI 0.324
SA
119.7
0.226 FSO/FSI 0.246
SA
90.3
0.1667 FSO/FSI 0.226
GD
20
0.905 FSO/FSI 12.000
GD
22
0.656 FSO/FSI 0.905
GD
26
0.536 FSO/FSI 0.656
GD
23
0.492 FSO/FSI 0.536
Group Delay
GD
24
0.452 FSO/FSI 0.492
(Note 9)
GD
26
0.324 FSO/FSI 0.452
GD
29
0.246 FSO/FSI 0.324
GD
30
0.226 FSO/FSI 0.246
GD
32
0.1667 FSO/FSI 0.226
016000098-E-00
- 15 -
Max.
Unit
0.4583FSI
0.4167FSI
0.3195FSI
0.2852FSI
0.2182FSI
0.2177FSI
0.1948FSI
0.1458FSI
0.1302FSI
0.0917FSI
0.0826FSI
0.0583FSI
0.01
0.03
-
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
1/fs
1/fs
1/fs
1/fs
1/fs
1/fs
1/fs
1/fs
1/fs
2016/01
[AK4136]
Note 9. This is the time from a rising edge of ILRCK after L and R channels data is input to a rising edge
of OLRCK before the L and R channels data is output, when there is no phase difference
between input and output data.
■ Short Delay Slow Roll-Off Filter Characteristics
(Ta=-40 +105C; DVDD=3.03.6V or DVDD=DV18=1.7V1.9V, DVSS=0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Passband 0.01dB 0.1667FSO/FSI 12.000
PB
0
kHz
0.0417FSI
Stopband
0.1667FSO/FSI 12.000
SB
0.4167FSI
kHz
Passband Ripple
PR
0.01
dB
Stopband Attenuation
SA
108.1
dB
Group Delay (Note 9)
GD
21
1/fs
Note 9. This is the time from a rising edge of ILRCK after L and R channels data is input to a rising edge
of OLRCK before the L and R channels data is output, when there is no phase difference
between input and output data.
11. Input and Output Examples
Possible Input and Output data combinations are shown below.
Fsi is the sampling rate of input data, and Fso is the sampling rate of output data.
Fsi[kHz]
PCM
8
11.025
16
32
44.1
48
88.2
96
176.4
192
Fso[kHz]
PCM
min
8
8
8
8
8
8
14.7
16
29.6
32
max
96
132.3
192
384
384
384
384
384
384
384
When the input data is 384 kHz and down converted, THD+N may degrade to 80dB.
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2016/01
[AK4136]
12. DC Characteristics
(Ta=-40 +105C; DVDD=3.03.6V: VSEL pin = “L” or DVDD=DV18=1.7V1.9V: VSEL pin = “H”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
High-Level Input Voltage
VIH
70%DVDD
V
Low-Level Input Voltage
VIL
30%DVDD
V
High-Level Output Voltage
Except SDA pin
(Iout=400A)
VOH
DVDD0.4
V
Low-Level Output Voltage
Except SDA pin
(Iout=400A)
VOL
0.4
V
SDA pin
(Iout=3mA)
VOL
0.4
V
Input Leakage Current
Iin
10
A
13.Switching Characteristics
(Ta=-40 +105C; DVDD=3.03.6V: VSEL pin = “L” or DVDD=DV18=1.7V1.9V:
CL=20pF)
Parameter
Symbol
Min.
Typ.
Master Clock Timing
fXTAL
11.2896
Crystal Oscillator Frequency
(256 times of 44.1, 48, 88.2 or 96kHz)
OMCLK Input
128 FSO:
fCLK
1.024
Pulse Width Low
tCLKL
7
Pulse Width High
tCLKH
7
256 FSO:
fCLK
2.048
Pulse Width Low
tCLKL
7
Pulse Width High
tCLKH
7
384 FSO:
fCLK
3.072
Pulse Width Low
tCLKL
10
Pulse Width High
tCLKH
10
512 FSO:
fCLK
4.096
Pulse Width Low
tCLKL
7
Pulse Width High
tCLKH
7
768 FSO:
fCLK
6.144
Pulse Width Low
tCLKL
10
Pulse Width High
tCLKH
10
016000098-E-00
- 17 -
VSEL pin = “H”;
Max.
Unit
24.576
MHz
49.152
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
49.152
36.864
49.152
36.864
2016/01
[AK4136]
Parameter
Input PORT ILRCK
Frequency
Normal speed mode
Double speed mode
Quad speed mode
Oct speed mode
Duty Cycle
Slave Mode
Output PORT OLRCK
Frequency
Slave mode
Normal speed mode
Double speed mode
Quad speed mode
Oct speed mode
Master mode
OMCLK Input, 128FSO mode
OMCLK Input, 256FSO mode
OMCLK Input, 384FSO mode
OMCLK Input, 512FSO mode
OMCLK Input, 768FSO mode
Duty Cycle
Slave Mode
Master Mode
Input PORT ILRCK for TDM256 Mode
Frequency
“H” time (slave mode)
“L” time (slave mode)
Input PORT ILRCK for TDM512 Mode
Frequency
“H” time (slave mode)
“L” time (slave mode)
Output PORT OLRCK for TDM256 Mode
Frequency
“H” time (slave mode)
“L” time (slave mode)
Output PORT OLRCK for TDM512 Mode
Frequency
“H” time (slave mode)
“L” time (slave mode)
016000098-E-00
Symbol
Min.
FSIN
FSID
FSIQ
FSIO
Duty
8
54
108
FSON
FSOD
FSOQ
FSOO
8
54
108
FSO
FSO
FSO
FSO
FSO
8
8
8
8
8
Duty
Duty
48
FSI
tLRH
tLRL
48
Typ.
Max.
54
108
216
384
50
52
Unit
kHz
kHz
kHz
kHz
kHz
%
54
108
216
kHz
kHz
kHz
kHz
384
192
96
96
48
kHz
kHz
kHz
kHz
kHz
52
%
%
8
1/256FSI
1/256FSI
96
kHz
ns
ns
FSI
tLRH
tLRL
8
1/512FSI
1/512FSI
48
kHz
ns
ns
FSO
tLRH
tLRL
8
1/256 FSO
1/256 FSO
96
kHz
ns
ns
FSO
tLRH
tLRL
8
1/512 FSO
1/512 FSO
48
kHz
ns
ns
- 18 -
384
50
50
2016/01
[AK4136]
Parameter
Symbol
Min.
Typ.
Audio Interface Timing
Input PORT (Slave mode)
IBICK Period
Normal speed mode
tBCK
1/256 FSIN
Double speed mode
tBCK
1/128 FSID
Quad speed mode
tBCK
1/64 FSIQ
Oct speed mode
tBCK
1/64 FSIO
IBICK Pulse Width Low
tBCKL
16
IBICK Pulse Width High
tBCKH
16
ILRCK Edge to IBICK “↑”
(Note 10)
tLRB
10
IBICK “↑” to ILRCK Edge
(Note 10)
tBLR
10
SDTI Hold Time from IBICK “↑”
tSDH
10
SDTI Setup Time to IBICK “↑”
tSDS
6
Input PORT (TDM256 slave mode)
IBICK Period
tBCK
40
IBICK Pulse Width Low
tBCKL
16
IBICK Pulse Width High
tBCKH
16
ILRCK Edge to IBICK “↑”
(Note 10)
tLRB
10
IBICK “↑” to ILRCK Edge
(Note 10)
tBLR
10
SDTI Hold Time from IBICK “↑”
tSDH
10
SDTI Setup Time to IBICK “↑”
tSDS
6
Input PORT (TDM512 slave mode)
IBICK Period
tBCK
40
IBICK Pulse Width Low
tBCKL
16
IBICK Pulse Width High
tBCKH
16
ILRCK Edge to IBICK “↑”
(Note 10)
tLRB
10
IBICK “↑” to ILRCK Edge
(Note 10)
tBLR
10
SDTI Hold Time from IBICK “↑”
tSDH
10
SDTI Setup Time to IBICK “↑”
tSDS
6
Note 10. IBICK rising edge must not occur at the same time as ILRCK edge.
Note 11. Maximum frequency of IBICK and OBICK is 24.576MHz.
016000098-E-00
- 19 -
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2016/01
[AK4136]
Parameter
Audio Interface Timing
Output PORT (Slave mode)
OBICK Period
Normal speed mode
Double speed mode
Quad speed mode
Oct speed mode
OBICK Pulse Width Low
OBICK Pulse Width High
OLRCK Edge to OBICK “↑”
OBICK “↑” to OLRCK Edge
(Note 10)
(Note 10)
Symbol
Min.
tBCK
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
1/256 FSON
1/128 FSOD
1/64 FSOQ
1/64 FSOO
16
16
10
10
Typ.
Max.
Unit
ns
ns
ns
ns
DVDD=3.0V~3.6V (VSEL pin= “L”)
OLRCK to SDTO(MSB) (Except I2S mode)
OBICK “↓” to SDTO
tLRS
tBSD
10
10
ns
ns
DVDD=1.7V~1.9V (VSEL pin= “H”)
(Except fso=384kHz)
OLRCK to SDTO(MSB) (Except I2S mode)
OBICK “↓” to SDTO
tLRS
tBSD
20
20
ns
ns
Note 10. IBICK rising edge must not occur at the same time as ILRCK edge.
016000098-E-00
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2016/01
[AK4136]
Parameter
Audio Interface Timing
Output PORT (TDM256 slave mode)
DVDD=3.0V～3.6V (VSEL pin= “L”)
OBICK Period
OBICK Pulse Width Low
OBICK Pulse Width High
OLRCK Edge to OBICK “↑”
(Note 10)
OBICK “↑” to OLRCK Edge
(Note 10)
OBICK “↓” to SDTO
Symbol
Min.
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
40
16
16
10
10
Typ.
DVDD=1.7V～1.9V (VSEL pin= “H”)
OBICK Period
tBCK
80
OBICK Pulse Width Low
tBCKL
32
OBICK Pulse Width High
tBCKH
32
OLRCK Edge to OBICK “↑”
(Note 10)
tLRB
20
OBICK “↑” to OLRCK Edge
(Note 10)
tBLR
20
OBICK “↓” to SDTO
tBSD
Output PORT (TDM512 slave mode)
DVDD=3.0V～3.6V(VSEL pin= “L”)
OBICK Period
tBCK
40
OBICK Pulse Width Low
tBCKL
16
OBICK Pulse Width High
tBCKH
16
OLRCK Edge to OBICK “↑”
(Note 10)
tLRB
10
OBICK “↑” to OLRCK Edge
(Note 10)
tBLR
10
OBICK “↓” to SDTO
tBSD
Output PORT (Master mode)
OBICK Frequency
fBCK
64 FSO
OBICK Duty
dBCK
50
OBICK “↓” to OLRCK Edge
tMBLR
5
OBICK “↓” to SDTO
tBSD
5
Reset Timing
PDN “L” Width after DVDD is on. (Note 13)
tAPD1
150
PDN Accept Pulse Width
(Note 13)
tAPD2
700
PDN pin Pulse Width of Spike Noise
tPDS
0
Suppressed by Input Filter (Note 14)
Note 10. IBICK rising edge must not occur at the same time as ILRCK edge.
Note 12. TDM modes are only supported in slave mode.
Max.
Unit
10
ns
ns
ns
ns
ns
ns
20
ns
ns
ns
ns
ns
sn
10
ns
ns
ns
ns
ns
ns
5
5
Hz
%
ns
ns
50
ns
ms
ns
Note 13. The AK4136 can be reset by bringing the PDN pin = “L”.
Note 14. “L” pulse width of spike noise suppressed by input filter of the PDN pin.
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2016/01
[AK4136]
Parameter
Control Interface Timing
CCLK Period
CCLK Pulse Width High
CCLK Pulse Width Low
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CCLK “↓” to CDTO
CSN “↑” to CDTO “Hi-Z”
Symbol
Min.
tCCK
tCCKH
tCCKL
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
50
50
150
50
50
Typ.
Max.
Unit
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
400
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 15) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
0.3
Fall Time of Both SDA and SCL Lines
tF
0.3
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise
tSP
0
50
Suppressed by Input Filter
Capacitive load on bus
Cb
400
Note 15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
016000098-E-00
- 22 -
kHz
s
s
s
s
s
s
s
s
s
s
ns
pF
2016/01
[AK4136]
■ Timing Diagrams
1/fCLK
VIH
XTI
VIL
tCLKH
tCLKL
1/fCLK
VIH
OMCLK(I)
VIL
tCLKH
tCLKL
dCLK=tCLKH(or fCKL)x fCLKx100
Figure 3. OMCLK, Clock Timing
016000098-E-00
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2016/01
[AK4136]
Slave Mode
1/FSI
VIH
ILRCK(I)
VIL
tLRCH
tLRCL
Duty=tLRCH(or tLRCL)xFSIx100
tBCK
VIH
IBICK(I)
VIL
tBCKH
tBCKL
TDM256 or TDM512 Mode and Slave Mode
1/FSI
VIH
ILRCK(I)
VIL
tLRH
tLRL
tBCK
VIH
IBICK(I)
VIL
tBCKH
tBCKL
Figure 4. ILRCK, IBICK Clock Timing
016000098-E-00
- 24 -
2016/01
[AK4136]
Slave Mode
1/FSO
VIH
OLRCK(I)
VIL
tLRCH
tLRCL
Duty=tLRCH(or tLRCL)xFSOx100
tBCK
VIH
OBICK(I)
VIL
tBCKH
tBCKL
TDM256 or TDM512 Mode and Slave Mode
1/FSO
VIH
OLRCK(I)
VIL
tLRH
tLRL
tBCK
VIH
OBICK(I)
VIL
tBCKH
tBCKL
Figure 5. OLRCK, OBICK Clock Timing (Slave Mode)
Master Mode
1/FSO
50%DVDD
OLRCK(O)
tLRCH
tLRCL
Duty=tLRCH(or tLRCL) x FSO X100
1/fBCK
50%DVDD
OBICK(O)
tBICKH
tBICKL
dBCK=tBICKH(or tBICKL) x fBCK X100
Figure 6. OLRCK, OBICK Clock Timing (Master Mode)
016000098-E-00
- 25 -
2016/01
[AK4136]
Slave mode and TDM256 or TDM512 Slave Mode
VIH
ILRCK
VIL
tBLR
tLRB
VIH
IBICK
VIL
tSDS
tSDH
VIH
SDTI
VIL
Figure 7. Input PORT Audio Interface Timing
Slave mode and TDM256 or TDM512 Slave Mode
VIH
OLRCK
VIL
tBLR
tLRB
VIH
OBICK
VIL
tLRS
tBSD
50%DVDD
SDTO
Figure 8. Output PORT Audio Interface Timing
Master mode and TDM256 or TDM512 Master mode
50%DVDD
OLRCK
tMBLR
50%DVDD
OBICK
tBSD
50%DVDD
SDTO
Figure 9. Output PORT Audio Interface Timing
016000098-E-00
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2016/01
[AK4136]
4-Wire Read
VIH
CSN
tCCLK
tCCKH
tCSS
VIH
1/2 Level of VIH/VIL
VIL
CCLK
tCDS tCDH
CDTI
CAD1
tSCKL
CAD0
R/W
VIH
A4
A0
VIL
Hi-Z
CDTO
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
VIH
D0
VIL
Hi-Z
CDTO
Figure 10. 4-wire Serial Control Mode
016000098-E-00
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2016/01
[AK4136]
4Wire Write
VIL
CSN
CCLK
VIL
CDTI
CDTO
A1
A0
Hi-Z
D7
D6
D5
VOH
VOL
tDCD
tCSW
VIH
CSN
VIL
tCSH
VIH
VIL
CCLK
tCCZ
CDTI
Hi-Z
CDTO
D2
D1
VOH
D0
Figure 11. 4-wire Serial Control Mode
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2016/01
[AK4136]
I2C Bus Control Mode
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
Figure 12. I2C Bus Control Mode
PDN
DVDD
tAPD2
tPDS
tAPD1
VIH
VIL
PDN
“L”
“H”
“L”
“H”
Figure 13. Power Down & Reset Timing
016000098-E-00
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2016/01
[AK4136]
14.Functional Descriptions
■ Power-up Sequence
VSEL pin= “L” (regulator mode)
DVDD (3.3V)
PDN pin
LDO
5ms(max)
Internal reset
XTI
OSC
Figure 14. Power-up Sequence (Regulator Mode)
VSEL pin= “H” (regulator off mode)
DVDD, DV18 (1.8V)
PDN pin
5ms(max)
Internal reset
XTI
OSC
Figure 15. Power-up Sequence (Regulator Off Mode)
016000098-E-00
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2016/01
[AK4136]
■ SRC Bypass Mode
1. SRC Mode Setting
In parallel control mode (PSN pin = “H”), the CM2-0 pins selects SRC bypass mode or SRC mode.
The CM2-0 pins select the master/slave mode and system clock simultaneously. (Table 7)
Table 1. SRC/SRC Bypass Mode Setting (@Parallel Control Mode)
CM2 CM1 CM0
SRC Mode /
Mode
pin
pin
pin
SRC Bypass Mode
0
L
L
L
1
L
L
H
2
L
H
L
SRC Mode
3
L
H
H
4
H
L
L
5
H
L
H
6
H
H
L
SRC Bypass Mode
7
H
H
H
In serial control mode (PSN pin = “L”), BYPS bit selects SRC bypass mode or SRC mode.
The default value of the BYPS bit is “0” (SRC mode).
Table 2. SRC/SRC Bypass Mode Setting (@Serial Control Mode)
BYPS bit
SRC mode
0
SRC
(Default)
1
Bypass
SDTI
ILRCK
IBICK
TDM
ODIF1
ODIF0
OBIT1
OBIT0
SRCEN
2. SRC Bypass Mode
・PCMIN → PCMOUT Mode (Slave Mode)
SDTI input data is clocked in by ILRCK and IBICK according to the audio interface format shown in
Table 3. SDTO output data is clocked out by OLRCK and OBICK according to the audio interface
format shown in Table 9 and Table 10. OBICK must be synchronized with IBICK but the phase is not
critical. OLRCK must be synchronized with ILRCK but the phase is not critical.
PCM
Input
Serial
Audio
I/F
PCM
Output
Serial
Audio
I/F
SMUTE
Dither
Internal
OSC
SDTO
OLRCK
OBICK
TEST1
PDN
REF
DVSS
DVDD
CM2
CM1
Clock
Div.
CM0
XTO
X’tal
OSC
XTI/OMCLK/TDMI
CDTO
SDA/CDTI/SLOW
CSN/SMUTE
SCL/CCLK/SD
CAD0/IDIF0
IDIF2
CAD1/IDIF1
DV18
Internal
Regulator
UP/IF
VSEL
I2C
PSN
TEST0
Figure 16. BYPASS Mode Slave (PCMIN→PCMOUT)
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2016/01
[AK4136]
SDTI
ILRCK
IBICK
TDM
ODIF1
ODIF0
OBIT1
OBIT0
SRCEN
・PCMIN → PCMOUT Mode (Master Mode)
SDTI input data is clocked in by ILRCK and IBICK according to the audio interface format shown in
Table 3. SDTO output data is clocked out by ILRCK and IBICK according to the audio interface format
shown in Table 9 and Table 10. In this case, ILRCK is directly output from the OLRCK pin, and IBICK is
directly output from the OBICK pin.
PCM
Input
Serial
Audio
I/F
PCM
Output
Serial
Audio
I/F
SMUTE
SDTO
OLRCK
OBICK
Dither
Internal
OSC
TEST1
TEST0
REF
DVSS
DVDD
CM2
CM1
Clock
Div.
CM0
XTO
CDTO
SDA/CDTI/SLOW
CSN/SMUTE
SCL/CCLK/SD
CAD0/IDIF0
IDIF2
CAD1/IDIF1
X’tal
OSC
XTI/OMCLK/TDMI
Internal
Regulator
UP/IF
DV18
I2C
PSN
VSEL
PDN
Figure 17. BYPASS Mode Master (PCMIN→PCMOUT)
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[AK4136]
■ System Clock and Audio Interface Format for Input PORT
The input port of the AK4136 only supports slave mode. Both ILRCK and IBICK pins are inputs and
master clock supplies are not necessary. The audio data format of input port is MSB first, 2’s
complement format. The SDTI is latched on the rising edge of IBICK.
In parallel control mode (PSN pin= “H”), IDIF2-0 pins control all audio interface formats of the input port.
IDIF2-0 pins must be set during the PDN pin= “L”.
Table 3. Input PORT Audio Interface Format (@Parallel Control mode)
IDIF2 Pin IDIF1 Pin IDIF0 Pin
ILRCK
Mode
SDTI Format
IBICK Freq
(Note 17) (Note 17) (Note 17)
/ IBICK
0
L
L
L
32bit, LSB justified
256FS or 64FSI
1
L
L
H
24bit, LSB justified
256FSI or 48FSI
2
L
H
L
32bit, MSB justified
256FSI or 64FSI
32 or 16 bit, I2S Compatible
256FSI or 64FSI
3
L
H
H
2
Input
16 bit, I S Compatible
32FSI
4
H
L
L
TDM 32bit, MSB justified
256FSI
5
H
L
H
TDM 32bit, I2S Compatible
6
H
H
L
TDM 32bit, MSB justified
512FSI
7
H
H
H
TDM 32bit, I2S Compatible
Note 16. When IBICK = 32FSI, the AK4136 only supports 16-bit I2S Compatible format.
Note 17. TDMICH2-1 bits select a data channel in TDM input mode.
In serial control mode (PSN pin = “L”), the setting of IDIF2-0 pins is ignored and IDIF2-0 bits setting is
reflected. IDIF2-0 bits should be changed after all SDTO output codes become zero during soft mute by
SMUTE bit = “1” or the SMUTE pin = “H”.
Table 4. Input PORT Audio Interface Format (@Serial Control Mode)
IDIF2 bit IDIF1 bit IDIF0 bit
ILRCK
Mode
SDTI Format
IBICK Freq
(Note 17) (Note 17) (Note 17)
/ IBICK
0
0
0
0
32bit, LSB justified
256FS or 64FSI
1
0
0
1
24bit, LSB justified
256FSI or 48FSI
2
0
1
0
32bit, MSB justified
256FSI or 64FSI
2
32 or 16 bit, I S Compatible
256FSI or 64FSI
3
0
1
1
16 bit, I2S Compatible
Input
32FSI
4
1
0
0
TDM 32bit, MSB justified
256FSI
5
1
0
1
TDM 32bit, I2S Compatible
6
1
1
0
TDM 32bit, MSB justified
512FSI
7
1
1
1
TDM 32bit, I2S Compatible
Note 16. When IBICK = 32FSI, the AK4136 only supports 16-bit I2S Compatible format.
Note 17. TDMICH2-1 bits select a data channel in TDM input mode.
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[AK4136]
ILRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
IBICK(128fs)
SDTI
31
0
1
2
12
13
14
23
1
24
0
31
31
0
1
2
12
13
14
23
1
24
0
31
0
1
IBICK(64fs)
SDTI
31 30
20 19 18
8
9
0
1
31 30
20
19 18
Lch Data
8
9
0
1
31
Rch Data
31: MSB, 0:LSB
Figure 18. Mode0 Timing (32-bit LSB)
ILRCK
0
1
2
20
21
22
40
41
63
0
1
2
20
21
22
40
IBICK(128fs)
41
63
0
1
9
SDTI
23
0
1
2
9
10
11
23
1
24
0
31
23
0
1
2
9
10
11
23
1
24
0
31
0
1
IBICK(64fs)
SDTI
23 19 18
8
9
0
1
23
19 18
Lch Data
8
9
0
1
31
Rch Data
23: MSB, 0:LSB
Figure 19. Mode1 Timing (24-bit LSB)
ILRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
IBICK(128fs)
SDTI
31 30
0
1
12 11 10
2
12
13
0
14
31 30
23
24
31
0
1
12
2
11 10
12
13
0
14
31
23
24
31
0
1
IBICK(64fs)
SDTI
31 30
20 19 18
9
8
1
0
31 30
20
Lch Data
19 18
9
8
1
0
31
Rch Data
31: MSB, 0:LSB
Figure 20. Mode2 timing (32-bit MSB)
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[AK4136]
ILRCK
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
24
25
31
0
1
IBICK(128fs)
SDTI
31
0
13 12 11
1
2
12
13
0
14
31
24
25
31
0
1
13
2
12 11
12
0
13
14
0
1
IBICK(64fs)
SDTI
0
31
21 20 19
8
9
1
2
0
31
21
20 19
Lch Data
8
9
1
2
0
Rch Data
31: MSB, 0:LSB
Figure 21. Mode3 Timing (32-bit I2S)
256 IBICK
ILRCK(I)
IBICK (I: 256FSI)
SDTI(I)
31 30
1
0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
1 0 31 30
L1
R1
L2
R2
L3
R3
L4
R4
32 IBICK
32 I BICK
32 I BICK
32 I BICK
32 IBICK
32 I BICK
32 I BICK
32 I BICK
Figure 22. Mode4 Timing (32-bit MSB TDM256fs)
256 IBICK
ILRCK(I)
IBICK(I: 256FSI)
SDTI(I)
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
L1
R1
L2
R2
L3
R3
L4
R4
32 IBICK
32 I BICK
32 I BICK
32 I BICK
32 IBICK
32 I BICK
32 I BICK
32 I BICK
1
0
Figure 23. Mode5 Timing (32-bit I2S TDM256fs)
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[AK4136]
512BICK
ILRCK
IBICK(I:512fs)
SDTI(i)
31 30
1 0 31 30
L1
1 0 31 30
R1
1 0 31 30
L2
1 0 31 30
R2
1 0 31 30
L3
1 0 31 30
R3
1 0 31 30
1 0 31 30
L4
R4
1 0 31 30
1 0 31 30
R5
L5
1 0 31 30
1 0 31 30
R6
L6
L7
1 0 31 30
1 0 31 30
R7
L8
1 0 31 30
1 0 31 30
R8
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 24. Mode6 Timing (32-bit MSB TDM512fs)
512BICK
ILRCK
IBICK(I:512fs)
SDTI(i)
31 30
L1
1 0 31 30
R1
1 0 31 30
L2
1 0 31 30
R2
1 0 31 30
L3
1 0 31 30
R3
1 0 31 30
L4
1 0 31 30
R4
1 31
0 30
L5
1 0 31 30
1 0 31 30
R5
1 0 31 30
L6
1 0 31 30
R6
L7
1 0 31 30
1 0 31 30
R7
L8
1 0 31 30
1 0 31 30
R8
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 25. Mode7 Timing (32-bit I2S TDM512fs)
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[AK4136]
■ System Clock for Output PORT
The output ports work both in master and slave modes.
1. Slave Mode
Both OLRCK and OBICK pins are input when the AK4136 is in slave mode. Master clock is
unnecessary.
2. Master Mode
Both OLRCK pin and OBICK pin are output when the AK4136 is in master mode. Master clock is
supplied to the XTI/OMCLK pin. The supplying method of Master clock is selected by CLKMODE pin.
Table 5. Master/Slave Mode Setting
OBICK
CLKMODE pin
XTI/OMCLK pin
pin
Mode
OLRCK
pin
Slave Mode
Input
Input
Connect to DVSS
Connect to DVSS
OPEN
Master Mode
Output
Output
L
H
X’tal Input
External Clock Input
X’tal Output
“L” Output
XTO pin
・X’tal Mode
XTI/OMCLK
C
C
XTO
AK4136
Note: Refer to Table 6 for the capacitor and resistance values for the X’tal oscillator.
Figure 26. X’tal (XTI) Mode
Table 6. Equivalent Series Resistor and External Capacitor for External X’tal Oscillator
Normal Frequency [MHz]
11.2896
12.288 22.5792 24.576
Equivalent Series Resistance [Ω] max
60
External Capacitor C[pF] max
15
In X’tal mode at 256FSO mode OMCLK input, FSO ranges from 44.1kHz to 96kHz.
In X’tal mode at 384FSO mode OMCLK input, FSO ranges from 29.4kHz to 64kHz.
In X’tal mode at 512FSO mode OMCLK input, FSO ranges from 22.05kHz to 48kHz.
In X’tal mode at 768FSO mode OMCLK input, FSO ranges from 14.7kHz to 32kHz.
In X’tal mode at 128FSO mode OMCLK input, FSO ranges from 88.2kHz to 192kHz.
・External Clock Mode
XTI/OMCLK
The XTO pin = “L” in External
Clock mode.
External Clock
XTO
AK4136
Figure 27. External Clock (OMCLK) Mode
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[AK4136]
The CM2-0 pins select the master/slave mode and SRC bypass mode.
Table 7. Output PORT Master/Slave/ Bypass Mode Control (@Parallel Control Mode)
FSO
CM2 CM1 CM0
OMCLK Input
Mode
Master / Slave
pin
pin
pin
(Note 18)
PCM
0
L
L
L
Master
256FSO
8k 192kHz
1
L
L
H
Master
384FSO
8k 96kHz
2
L
H
L
Master
512FSO
8k 96kHz
3
L
H
H
Master
768FSO
8k 48kHz
4
H
L
L
Slave
Not used
8k 384kHz
5
H
L
H
Master
128FSO
8k 384kHz
6
H
H
L
Slave (Bypass)
Not used
7
H
H
H
Master (Bypass)
Note 18. Use for a clock input or connect to DVSS.
In Mode 6-7, OMCLK/XTI input is ignored internally.
Table 8. Output PORT Master/Slave/ Bypass Mode Control (@Serial Control Mode)
FSO
CM2 CM1 CM0 BYPS
Master /
OMCLK Input
Mode
pin
pin
pin
bit
Slave
(Note 20)
PCM
0
1
2
3
L
L
L
L
L
L
H
H
L
H
L
H
0
0
0
0
Master
Master
Master
Master
4
H
L
L
0
Slave
5
6
H
H
L
H
H
L
0
0
Master
Slave (Bypass)
7
H
H
H
0
Master (Bypass)
256FSO
384FSO
512FSO
768FSO
Not used.
(Note 19)
128FSO
Not used.
(Note 19)
8k 192kHz
8k 96kHz
8k 96kHz
8k 48kHz
8k 384kHz
8k 384kHz
-
8
L
L
L
1
Master (Bypass)
9
L
L
H
1
Master (Bypass)
10
L
H
L
1
Master (Bypass)
11
L
H
H
1
Master (Bypass)
Not used.
(Note 19)
12
H
L
L
1
Slave (Bypass)
13
H
L
H
1
Master (Bypass)
14
H
H
L
1
Slave (Bypass)
15
H
H
H
1
Master (Bypass)
Note 19. Use for a clock input or connect to DVSS. Mode 6, 7, 8-15, OMCLK/XTI/TDMI input is
ignored internally.
Note 20. In SRC mode, even if input port clocks ILRCK and IBICK are stopped, the AK4136 keeps
outputting divided clock of the XTI/OMCLK inputs if the device is in master mode and a clock
input to the XTI/OMCLK pin is supplied. In SRC bypass mode of master mode, ILRCK is
input through and output from the OLRCK pin, and IBICK is input through and output from
the OBICK pin. Therefore the OLRCK output will be stopped if ILRCK clock at the input port
is stopped, and the OBICK will be stopped if IBICK clock at the input port is stopped.
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[AK4136]
■ Audio Interface Format for Output PORT
The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio
data is MSB first, 2’s complement format. The SDTO is clocked out on a falling edge of OBICK.
Select the audio interface format for output port while the PDN pin = “L”. If the AK4136 is in slave mode
at bypass mode, IBICK and OBICK must be synchronized but the phase is not critical. ILRCK and
OLRCK must be synchronized but the phase is not critical. The audio interface format of SDTO is
controlled by ODIF1-0 pins, OBIT1-0 pins and TDM pin.
Output ports become TDM mode when the TDM pin = “H”. 6 channels or 14 channels serial data should
be input to the XTI/OMCLK/TDMI pin. The SDTO pin outputs serial data for 8 channels or 16 channels.
TDM mode is only available when the AK4136 is in slave mode.
Mode
0
1
2
3
4
5
6
7
Table 9. Output PORT Audio Interface Format 1
TDM ODIF1 ODIF0
SDTO Format
L
L
L
LSB justified
2
L
L
H
I S Compatible
L
H
L
MSB justified
2
L
H
H
I S Compatible
H
L
L
TDM256 mode 32bit MSB justified
H
L
H
TDM256 mode 32bit I2S Compatible
H
H
L
TDM512 mode 32bit MSB justified
H
H
H
TDM512 mode 32bit I2S Compatible
Table 10. Output PORT Audio Interface Format 2
Mode
TDM Master / Slave OBIT1 OBIT0 SDTO
OLRCK
pin
setting
pin
pin
pin
OBICK
OBICK Frequency
MSB
LSB
2
justified, I S
justified
64FSO
48FSO
64FSO
40FSO
32FSO
0
L
L
32bit
Slave
1
L
H
24bit
(CM2-0 =
Input
Input
2
H
L
20bit
“HLL”/“HHL”)
3
H
H
16bit
L
4
L
L
32bit
Master
5
L
H
24bit
(CM2-0 ≠
Output Output
64FSO
6
H
L
20bit
“HLL”/“HHL”)
7
H
H
16bit
8
Slave
TDM
9
256FSO
H
(CM2-0 =
*
*
mode
Input
Input
512FSO
10
“HLL”/“HHL”)
32bit
11
(* The data length is fixed to 32 bits in TDM mode. The OBIT1-0 pin settings are ignored. Connect these
pins to DVSS.)
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[AK4136]
OLRCK
0
1
2
9
10
12
13
16
17
31
0
1
2
9
10
12
13
16
17
31
0
1
OBICK(64fs)
SDTO(O)
15
SDTO(O)
SDTO(O)
SDTO(O)
31 30
1
0
15
1
0
19
15
1
0
19
15
1
0
23 22
19
15
1
0
31 30
23
22
19
15
1
0
23 22
19
15
1
0
31 30
23
22
19
15
1
0 31
Lch Data
Rch Data
31: MSB, 0:LSB @ 32bit
Figure 28. Stereo Mode LSB Justified Timing
(Except when the output port is Master (Bypass) Mode and the audio interface of the input port is TDM
mode (24bit MSB justified or 24bit I2S Compatible))
OLRCK
0
1
2
15
16
19
20
23
24
31
0
1
2
15
16
19
20
23
24
31
0
1
OBICK(64fs)
SDTO(O)
15 14
SDTO(O)
19
SDTO(O)
SDTO(O)
1
0
4
0
23 22
19 18
4
0
31 30
23 22
12
8
18
5
1
Lch Data
0
15 14
1
0
19 18
5
4
23 22
19
18
4
0
31 30
23
22
12
8
0
1
0 31
Rch Data
31: MSB, 0:LSB @ 32bit
Figure 29. TDM 256 mode 32bit MSB Justified Timing at Slave Mode
(Except when the output port is Master (Bypass) Mode and the audio interface of the input port is TDM
mode (24bit MSB justified or 24bit I2S Compatible))
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[AK4136]
OLRCK
0
1
2
16
17
20
21
24
25
31
0
1
2
16
17
20
21
24
25
31
0
1
OBICK(64fs)
SDTO(O)
15
SDTO(O)
19
SDTO(O)
SDTO(O)
0
1
4
0
23
19 18
4
0
0 31
23 22
12
8
5
1
2
15
1
0
19
5
4
23
19
18
4
0
0 31
24
23
12
8
0
2
1
0
31
Lch Data
Rch Data
31: MSB, 0:LSB @ 32bit
Figure 30. Stereo Mode I2S Compatible Timing
(Except when the output port is Master (Bypass) Mode and the audio interface of the input port is TDM
mode (32bit MSB justified or 24bit I2S Compatible))
256 BICK
OLRCK
OBICK(256fs)
#1 SDTO(o)
= #2 TDMIN(i)
#2 SDTO(o)
= #3 TDMIN(i)
#3 SDTO(o)
= #4 TDMIN(i)
#4 SDTO(o)
31 30
1
0 31 30
1
L #1
R #1
32 BICK
32 BICK
31 30
1
0 31 30
1
0
31 30
0 31 30
1
0 31 30
1
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0
31 30
0 31 30
1
0 31 30
1
L #3
R #3
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0
31 30
0 31 30
1
0 31 30
1
L #4
R #4
L #3
R #3
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
Figure 31. TDM 256 Mode 32bit MSB Justified Timing at Slave Mode
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[AK4136]
256 BICK
OLRCK
OBICK(256fs)
#1 SDTO(o)
31
= #4 TDMIN(i)
#4 SDTO(o)
0 31
2
1
L #1
R #1
32 BICK
31
= #3 TDMIN(i)
#3 SDTO(o)
1
32 BICK
= #2 TDMIN(i)
#2 SDTO(o)
2
31
2
1
0 31
2
1
0
31
0 31
2
1
0 31
2
1
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
2
1
0 31
2
1
0 31
2
1
0 31
2
1
0
31
0 31
2
1
0 31
2
L #3
R #3
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0 31
2
1 0
31
2
1
0 31
2
1
0 31
2
1
0 31
2
1
0 31
2
1
0
31
1
0 31
2
1
0 31
2
L #4
R #4
L #3
R #3
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
1
0 31
Figure 32. TDM 256 Mode 32bit I2S Compatible Timing at Slave Mode
512 BICK
OLRCK
OBICK(512fs)
#1 SDTO(o)
= #2 TDMIN(i)
#2 SDTO(o)
= #3 TDMIN(i)
#7 SDTO(o)
= #8 TDMIN(i)
#8 SDTO(o)
31 30
1
0 31 30
1
L #1
R #1
32 BICK
32 BICK
31 30
1
0 31 30
1
0
31 30
0 31 30
1
0 31 30
1
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0
31 30
0 31 30
1
0 31 30
1
L #7
R #7
L #6
R #6
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0
31 30
0 31 30
1
0 31 30
1
L #8
R #8
L #7
R #7
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
Figure 33. TDM 512 Mode 32bit MSB Justified Timing at Slave Mode
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[AK4136]
512 BICK
OLRCK
OBICK(512fs
)
#1 SDTO(o)
31
= #8 TDMIN(i)
#8 SDTO(o)
0 31
2
1
L #1
R #1
32 BICK
31
= #3 TDMIN(i)
#7 SDTO(o)
1
32 BICK
= #2 TDMIN(i)
#2 SDTO(o)
2
31
2
1
0 31
2
1
0
31
0 31
2
1
0 31
2
1
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
2
1
0 31
2
1
0 31
2
1
0 31
2
1
0
31
0 31
2
1
0 31
2
L #7
R #7
L #6
R #6
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0 31
2
1 0
31
2
1
0 31
2
1
0 31
2
1
0 31
2
1
0 31
2
1
0
31
1
0 31
2
1
0 31
2
L #8
R #8
L #7
R #7
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
1
0 31
Figure 34. TDM 512 Mode 32bit I2S Compatible Timing at Slave Mode
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[AK4136]
■ Cascade Connection in TDM Mode
The AK4136 supports cascading of up to four devices (8 channels data) in a daisy chain configuration in
TDM mode. In this mode, SDTO pin of device #1 is connected to OMCLK (TDMIN) pin of device #2.
The SDTO pin of device #2 can output 4 channels of TDM data multiplexed with 2-channel of TDM data
from device #1 and 2-channel of TDM data from device #2. Figure 35 shows a connection example of a
daisy chain.
AK4136 #1
OLRCK
48kHz
OBICK
256fs
OMCLK (TDMIN)
GND
SDTO
AK4136 #2
OLRCK
OBICK
OMCLK (TDMIN)
(TDMIN of
AK4136 #3)
SDTO
Figure 35. Cascade Connection Example
256 BICK
OLRCK
OBICK(256fs)
#1 SDTO(o)
= #2 TDMIN(i)
#2 SDTO(o)
= #3 TDMIN(i)
#3 SDTO(o)
= #4 TDMIN(i)
#4 SDTO(o)
31 30
1
0 31 30
1
L #1
R #1
32 BICK
32 BICK
31 30
1
0 31 30
1
0
31 30
0 31 30
1
0 31 30
1
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0
31 30
0 31 30
1
0 31 30
1
L #3
R #3
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0 31 30
1
0
31 30
0 31 30
1
0 31 30
1
L #4
R #4
L #3
R #3
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0 31 30
Figure 36. TDM Cascade
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[AK4136]
■ Soft Mute Function
1. Manual Mode
The soft mute operation is performed in the digital domain of the SRC output. SRC soft mute is
controlled by the SMUTE pin in parallel control mode (PSN pin = “H”) or SMUTE bit in serial control
mode (PSN pin = “L”). The SRC output data is attenuated to in 1024 OLRCK cycles by setting
SMUTE pin to “H” (or SMUTE bit = “1”). When setting the SMUTE pin to “L” (or SMUTE bit to “0”), the
mute is cancelled and the output attenuation level gradually changes to 0dB in 1024 OLRCK cycles. If
the soft mute is cancelled before attenuating to , the attenuation is discontinued and the attenuation
level returns to 0dB by the same cycle. The soft mute is effective for changing the signal source without
stopping the signal transmission. Soft mute cycle is set by SMT2-0 bits (PSN pin= “L”). The setting of
SMT2-0 bits must not be changed during soft mute transition.
Table 11. Soft Mute Cycle Setting (PCM)
SMT2
bit
0
0
0
0
1
1
1
1
SMT1
bit
0
0
1
1
0
0
1
1
SMT0
bit
0
1
0
1
0
1
0
1
Period
fso=48kHz
fso=96kHz
1024/fso
2048/fso
4096/fso
8192/fso
16384/fso
32768/fso
reserved
reserved
21.3ms
42.7ms
85.3ms
170.7ms
341.3ms
682.7ms
-
10.7ms
21.3ms
42.7ms
85.3ms
170.7ms
341.1ms
-
fso=192kHz fso=384kHz
5.3ms
10.7ms
21.3ms
42.7ms
85.3ms
170.7ms
-
2.7ms
5.3ms
10.7ms
21.3ms
42.7ms
85.3ms
-
SMUTE
0dB
(1)
(1)
(3)
Attenuation
-
SDTO
Figure 37. Soft Mute Manual Mode
1. Soft mute cycle is set by SMT2-0 bits (Table 11). The output data is attenuated to in the soft
mute cycle.
2. If the soft mute is cancelled before attenuating to , the attenuation is discontinued and the
attenuation level returns to 0dB by the same clock cycles.
3. If the soft mute is cancelled within the soft mute cycle after starting soft mute operation, the
attenuation is discontinued and the attenuation level returns to 0dB by the same cycle.
4. The transition time can only be set by registers.
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[AK4136]
2. Semi-Auto Mode
The AK4136 enters Semi-auto Soft Mute mode by detecting reset release (RSTN bit=“0”→“1”) while the
PSN pin=“L” and SMUTE bit = “1”.
The soft mute is cancelled automatically in 4410/FSO=100ms @FSO=44.1kHz after detecting a rising
edge of the RSTN bitn = “0” → “1”. Soft mute will not be cancelled if the SMUTE bit is “1” after reset is
released. The setting of SMSEMI bit must be changed during RSTN bit = “0”.
RSTN bit
“0”
SMUTE Pin
Don’t Care
“L”
(1)
0dB
Attenuation
4410/fso
-
SDTO
Figure 38. Soft Mute Semi-Auto Mode
(1) The output data is attenuated by during the soft mute cycle (Table 11). (only When the SMUTE
pin=“L”. When the SMUTE pin=“H”, the output data is kept muted.)
(2) When the attenuation level is 0dB by a soft mute release after 4410/FSO, the output signal is able to
mute or release mute by the soft mute cycle (Table 11).
■ Dither Circuit
The AK4137 includes a dither circuit. The dither circuit adds a dither signal after the lowest bit of all the
output data set by the OBIT1-0 pins when DITHER bit = “1”, regardless of SRC and SRC bypass
modes. If the output data has 32-bit length in SRC bypass mode, the output code will not be affected by
the DITHER bit setting.
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[AK4136]
■ Digital Filter
The AK4136 has four kinds of digital filters and they are selected by the SD pin and the SLOW pin in
parallel control mode (PSN pin = “H”).
In serial control mode (PSN pin = “L”), the SD pin and the SLOW pin becomes the SCLK/CCLK pin and
the SDA/CDTI pin, respectively and the filter setting by these pins are ignored.
Table 12. Digital Filter Setting (@Parallel Control Mode)
SD pin
SLOW pin
Mode
L
L
Sharp roll-off filter
L
H
Slow roll-off filter
H
L
Short delay Sharp roll-off filter
H
H
Short delay Slow roll-off filter
SD bit
0
0
1
1
Table 13. Digital Filter Setting (@Serial Control Mode)
SLOW bit
Mode
0
Sharp Roll-off Filter
1
Slow Roll-off Filter
0
Short delay Sharp Roll-off Filter
1
Short delay Slow Roll-off Filter
(default)
■ De-emphasis Filter
In serial control mode (PSN pin = “L”), de-emphasis setting of the SRC is controlled by DEM1-0 bits. In
parallel control mode (PSN pin = “H”), DEM1-0 bits setting is invalid and de-emphasis setting of the
SRC is controlled by DEM1-0 pins.
Table 14. De-emphasis Filter Setting
DEM1bit
DEM0 bit
Mode
0
0
44.1kHz
0
1
OFF
1
0
48kHz
1
1
32kHz
■ Regulator
The AK4136 has an internal regulator which suppresses the voltage to 1.8V from DVDD. The generated
1.8V power is used as power supply for internal circuits only. When an over-current flows into the
regulator output, over-current detection circuit will work. When an over-voltage flows into the regulator
output, over-voltage detection circuit will work. The regulator block is powered-down and the AK4136
becomes reset state when over-current detection or over-voltage detection is executed. The AK4136
does not return to normal operation without a reset by the PDN pin when these detection circuits are
worked. When over-current or over-voltage is detected, the PDN pin should be brought into “L” at once,
and set to “H” again to recover normal operation.
The SRCEN pin indicates the internal status of the device. It outputs “L” in SRC normal operation and
outputs “H” when over-current or over-voltage is detected.
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[AK4136]
■ System Reset
Bringing the PDN pin = “L” sets the AK4136 power-down mode and initializes digital filters. The AK4136
should be reset once by bringing the PDN pin = “L” upon power-up. When the PDN pin is “L”, the SDTO
output is “L”. It takes 32ms (max) to output SDTO data after power-down state is released by a clock
input. Until then, the SDTO pin outputs “L”. The internal SRC circuit is powered up on an edge of ILRCK
after the internal regulator is powered up.
Case 1
External clocks
(Input port)
Don’t care
Input Clocks 1
Input Clocks 2
Don’t care
SDTI
Don’t care
Input Data 1
Input Data 2
Don’t care
External clocks
(Output port)
Don’t care
Output Clocks 1
Output Clocks 2
Don’t care
PDN
(Internal state) Power-down
SDTO
(1)
(1)
< 32ms
< 32ms
LDO Up & Ratio
detection & GD
“0” data
Normal
operation
Normal data
PD
LDO Up & Ratio
detection & GD
“0” data
Normal
operation
Power-down
Normal data
“0” data
SRCEN
LDO: Internal Regulator
GD: Group Delay
PD: Power Down
Figure 39. System Reset 1
The setting of the PSN, CM2-0, OBIT1-0, TDM, ODIF1-0, IDIF2-0, CAD1-0 pins must be changed while
the PDN pin is “L”. The SRCEN pin outputs “H” during “L” period of the PDN pin. If the internal regulator
is normal operation and ratio detection is completed, SRC data is output from the SDTO pin after a
rising edge of the PDN pin.
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[AK4136]
Case 2
External clocks
(Input port)
(No Clock)
SDTI
External clocks
(Output port)
Input Clocks
Don’t care
(Don’t care)
Input Data
Don’t care
(Don’t care)
Output Clocks
Don’t care
PDN
(1)
< 27ms
(Internal state) Power-down
ILCK
LDO Up
Ratio detection
& GD
“0” data
SDTO
Normal
operation
Power-down
Normal data
“0” data
SRCEN
LDO: Internal Regulator
GD: Group Delay
PD: Power Down
Figure 40. System Reset 2
■ Internal Reset Function for Clock Change
Clock change timing is shown in Figure 41 and Figure 42. When changing the clock, the AK4136 should
be reset by the PDN pin in parallel control mode and it should be reset by the PDN pin or RSTN bit in
serial control mode.
External clocks
(input port
or output port)
Clocks 1
(Don’t care)
Clock 2
PDN
< 32msec
(interlal state) Normal operation
LDO ON & Ratio
detection & GD
Normal operation
Note 21
SDTO
Normal data
SMUTE (Note 22,
recommended)
Att.Level
Power
down
normal
data
1024/fso
1024/fso
0dB
-dB
LDO: Internal Regulator
GD: Group Delay
Figure 41. Sequence of Changing Clocks (Parallel Control Mode, PSN pin=“H”)
Note 21. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI more than
1024/fs (GD) before the PDN pin changes to “L”. It makes the data on SDTO remain as “0”.
Note 22. SMUTE can also remove the clicking noise (Note 21).
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[AK4136]
External clocks
(input port
or output port)
Clocks 1
(Don’t care)
Clock 2
PDN
< 32msec
(interlal state)
Normal operation
Power
down
LDO ON & Ratio
detection & GD
Normal operation
Note 23
SDTO
Normal data
SMUTE (Note 24,
recommended)
Att.Level
Normal data
1024/fso
1024/fso
0dB
-dB
LDO: Internal Regulator
GD: Group Delay
Figure 42. Sequence of Changing Clocks (Serial Control Mode, PSN pin= “L”)
Note 23. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI more than
1024/fs (GD) before the PDN pin changes to “L”. It makes the data on SDTO remain as “0”.
Note 24. SMUTE can also remove the clicking noise (Note 23).
Note 25. The digital block except serial control interface and registers is powered-down. The internal
oscillator and regulator are not powered-down.
Note 26. It is the total time of “0.5/FSI+8/FSI(O)+204/FSO” or “1.5/FSI+8/FSI(O)+204/FSO”. (FSI(O) is
lower frequency between FSI and FSO)
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[AK4136]
■ When the Frequency of ILRCK at Input Port Is Changed Without A Reset by The PDN Pin
or RSTN Bit
When the difference of internal oscillator clock number in one ILRCK cycle between before ILRCK
frequency is changed (FSO/FSI ratio is stabilized) and after the change is more than 1/16 for 8cycles,
an internal reset is made automatically and sampling frequency ratio detection is executed again. SDTO
outputs “L” when the internal reset is made, and SRC data is output after “214/FSO” (FSI(O) is lower
frequency between FSI and FSO).
If the difference of internal oscillator clock number in one ILRCK cycle between before ILRCK frequency
is changed and after the change is less than 1/16 or more than 1/16 but shorter than 8 cycles, the
internal reset is not executed. In both cases; when ILRCK frequency is changed immediately without
transition time or with transition time which is not long enough for an internal reset, it takes 5148/FSO**
(max. 643.5ms PCM Output @FSO=8kHz) to output normal SRC data. Distorted data may be output
until normal SRC output.
When ILRCK is stopped, an internal reset is executed automatically. It takes “214/FSO” [s] to output
normal SRC data after ILRCK is input again (FSI(O) is lower frequency between FSI and FSO).
■ When the Frequency of OLRCK at Output Port Is Changed Without A Reset by The PDN
Pin or RSTN Bit
When the difference of internal oscillator clock number in one OLRCK cycle between before OLRCK
frequency is changed (FSO/FSI ratio is stabilized) and after the change is more than 1/16 for 8 cycles,
an internal reset is made automatically and sampling frequency ratio detection is executed again. SDTO
outputs “L” when the internal reset is made, and SRC data is output after “214/FSO” (FSI(O) is lower
frequency between FSI and FSO).
If the difference of internal oscillator clock number in one OLRCK cycle between before an OLRCK
frequency change and after the change is less than 1/16 or more than 1/16 but shorter than 8 cycles,
the internal reset is not executed. It takes 5148/FSO** (max. 643.5ms PCM output @FSO=8kHz) to
output normal SRC data. Distorted data may be output until normal SRC output.
When OLRCK is stopped, an internal reset is executed automatically. It takes “214/FSO” [s] to output
normal SRC data after ILRCKx is input again.
** When FSO=8kHz and FSO/FSI ratio is changed from 1/6 to 1/5.99. It is 160.9ms when FSO=32kHz
and FSO/fSI ratio is changed from 1/6 to 1/5.99.
■ Pop Noise Reduction in Sampling Rate Conversion
When ILRCK and OLRCK frequencies of the input port are changed without a reset by the PDN pin or
RSTN bit, the output signal is soft muted automatically if internal reset is executed by ASCHON bit = “1”.
Soft mute time is the setting value shown in Table 11.
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[AK4136]
■ Internal Status Pin
The SRCEN pin indicates internal status of the device. This pin outputs “H” when the PDN pin = “L”.
SRC data is output from the SDTO pin, which corresponds to the each sampling frequency ratio
detected SRC, after a rising edge “↑” of PDN if the internal regulator is in normal operation.
When an over-current/voltage flows into the internal regulator, the SRCEN pin outputs “H”. An OR’ed
result of the flags between over-current/voltage detection at the internal regulator and SRC sampling
frequency detection complete is output from this pin.
Over-Current/Voltage Limit Flag
（“L” Normal, “H” Over-Current（Voltage）detect）
SRC Sampling Frequency Ratio Detection Complete Flag
SRCEN pin
Figure 43. Internal Flags and SRCEN pin Output
In parallel control mode, if the AK4136 is set in SRC bypass mode by CM2-0 pins during the PDN pin =
“L” and powered-up, the SRCEN pin outputs “L” after the power-up time of the internal regulator (max.
5ms) from a rising edge “↑” of the PDN pin.
In serial control mode, if BYPS bit is set to “1” while RSTN bit = “0”, the SRCEN pin immediately outputs
“L” after register writing.
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[AK4136]
■ Serial Control Interface
The AK4136 becomes serial control mode by setting the PSN pin to “L”. The AK4136 supports 4-wire
serial Interface (I2S pin = “L”) and I2C bus (I2S pin = “H”) modes for internal register accessing.
1. 4-wire Serial Control Mode (I2C pin = “L”)
The internal registers may be written by the 4-wire µP interface pins: CSN, CCLK and CDTI. The data
on this interface consists of Chip address (2bits, C1/0), Read/Write (Write= “1”, Read= “0”), Register
address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the
rising edge of CCLK and data is clocked out on the falling edge. Data write becomes available by a
rising edge of CSN pin. For read operations, the CDTO output goes high impedance after a low-to-high
transition of CSN. The maximum speed of CCLK is 5MHz. Internal register values are initialized by
setting the PDN pin to “L”. The internal register timing circuit is reset by setting RSTN bit to “0” in serial
control mode. In this case, the register values are not initialized.
CSN
CCLK
CDTI
C1
C0 R/W
A4
A3
A2
A1
A0
CDTO
D7
D6
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
Hi-z
Figure 44. Write Operation
CSN
CCL
K
CDT
C1
C0 R/W A4
ICDTO
A3
A2
A1
A0
D7
Hi-z
D6
Figure 45. Read Operation
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W: READ/WRITE (Wirte=“1”, Read=”0”)
A4-A0: Register Address
D7-D0: Control Data
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[AK4136]
2. I2C-bus Control Mode (I2C pin = “H”)
The AK4136 supports High speed mode I2C-bus (max: 400kHz)
2-1. WRITE Operation
Figure 46 shows the data transfer sequence of the I2C-bus mode. All commands are preceded by
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates START
condition (Figure 52). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave
address are fixed as “00100”. The next 6th and 7th bits are CAD0/CAD1(device address bit). This bit
identifies the specific device on the bus. The hard-wired input pin (CAD0/CAD1 pin) set these device
address bits. If the slave address matches that of the AK4136, the AK4136 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and
release the SDA line (HIGH) during the acknowledge clock pulse (Figure 53). R/W bit = “1” indicates
that the read operation is to be executed. “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4136. The format is MSB first, and
those most significant 3-bits are fixed to zeros (Figure 48). The data after the second byte contains
control data. The format is MSB first, 8bits (Figure 49). The AK4136 generates an acknowledge after
each byte is received. Data transfer is always terminated by STOP condition generated by the master. A
LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 52).
The AK4136 can execute multiple one byte write operations in a sequence. After receipt of the third
byte the AK4136 generates an acknowledge and awaits the next data. The master can transmit more
than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving
each data packet the internal 6-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 02H prior to generating a stop
condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW
state of the data line can only change when the clock signal on the SCL line is LOW (Figure 54) except
for the START and STOP conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 46. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
A1
A0
D1
D0
Figure 47. The First Byte
0
0
0
A4
A3
A2
Figure 48. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 49. Byte Structure after the second byte
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[AK4136]
2-2. READ Operation
Set the R/W bit = “1” for the READ operation of the AK4136. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 02H prior to generating stop condition, the address counter will “roll over” to 00H and the data
of 00H will be read out.
The AK4136 supports two basic read operations: Current Address Read and Random Address Read.
2-2-1. Current Address Read
The AK4136 contains an internal address counter that maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either a read or write) was to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave
address with R/W bit “1”, the AK4136 generates an acknowledge, transmits 1-byte of data to the
address set by the internal address counter and increments the internal address counter by 1. If the
master does not generate an acknowledge but generates a stop condition instead, the AK4136
discontinues transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
A
C
K
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 50. Current Address Read
2-2-2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to
issuing a slave address with the R/W bit =“1”, the master must execute a “dummy” write operation first.
The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read.
After the register address is acknowledged, the master immediately reissues the start request and the
slave address with the R/W bit =“1”. The AK4136 then generates an acknowledge, 1 byte of data and
increments the internal address counter by 1. If the master does not generate an acknowledge but
generates a stop condition instead, the AK4136 discontinues transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
Slave
S Address
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 51. Random Address Read
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SDA
SCL
S
P
start condition
stop condition
Figure 52. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 53. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 54. Bit Transfer on the I2C-Bus
The pull-up resistance of SCL and SDA pins should be connected below the voltage of DVDD+0.3V.
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■ Register Map
Addr Register Name
00H Reset & Mute
01H
02H
PCMCONT0
PCMCONT1
D7
D6
D5
D4
SMSEMI
SMT2
SMT1
SMT0
SLOW
0
SD
0
DEM1
0
DEM0
0
D3
SMUTE
D2
D1
D0
default
BYPS
FORCE
STB
RSTN
0x01
DITHER
IDIF2
IDIF1
IDIF0
ASCHON TDMICH2 TDMICH1 TDMICH0
0x12
0x00
Note 27. Register values are initialized by setting the PDN pin to “L”.
Note 28. Writing to the address except 00H ~ 02H is prohibited. The bits defined as 0 must contain a “0”
value.
Note 29. µP interface access becomes valid 5ms (max) after from the PDN pin “↑”.
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■ Register Definitions
Addr Register Name
00H
D7
Reset & Mute SMSEMI
R/W
Default
R/W
0
D6
D5
D4
D3
D2
SMT2
SMT1
SMT0
SMUTE
BYPS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D1
FORCE
STB
R/W
0
D0
RSTN
R/W
1
SMSEMI: Semi Auto Soft Mute
0: Semi Auto Soft Mute Off (default)
1: Semi Auto Soft Mute ON
SMT2-0: Soft Mute Period
000: 1024/fso (default)
001: 2048/fso
010: 4096/fso
011: 8192/fso
100: 16384/fso
101: 32768/fso
110: reserved
111: reserved
Soft Mute Cycle is determined.
SMUTE: Soft Mute Control
0: Soft Mute Release (default)
1: Soft Mute
In Serial Control Mode (PSN pin = “L”), the CSN/SMUTE pin functions as the CSN pin, and
SMUTE setting is ignored. In Parallel Control Mode (PSN pin = “H”), the SMUTE pin setting is
valid.
BYPS: Bypass Mode Control (Table 8)
0: SRC Mode (default)
1: SRC Bypass Mode
FORCESTB: CLKSTABLE signal (Checking signal for IRCK and OLRCK changes) is set to “1” forcibly.
0: Normal Operation (default)
1: CLKSTABLE = “1”
RSTN: Digital Reset Control
0: Reset
1: Reset Release (default)
Digital blocks are powered down by setting RSTN bit = “0”. However, I2C serial control interface
and control register blocks are not powered down, and control register values are not initialized. In
this case, control register writing is also available. Internal oscillator that generates internal clock,
regulator and reference voltage generation circuits are not powered down.
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Addr
01H
Register Name
PCMCONT0
R/W
Default
D7
SLOW
R/W
0
D6
SD
R/W
0
D5
DEM1
R/W
0
D4
DEM0
R/W
1
D3
DITHER
R/W
0
D2
IDIF2
R/W
0
D1
IDIF1
R/W
1
D0
IDIF0
R/W
0
SLOW: FIR1 Filter Coefficient Select
0: Sharp Roll OFF Filter (default)
1: Slow Roll OFF Filter
In Serial Control Mode (PSN pin = “L”), the SDA/CDTI/SLOW pin functions as SDA/CDTI pin and
SLOW setting is ignored.
In Parallel Control Mode (PSN pin = “H”), the SLOW pin setting is valid.
SD: FIR1 Filter Coefficient Select
0: Normal Delay Filter（default)
1: Short Delay Filter
In Serial Control Mode (PSN pin = “L”), the SCL/CCLK/SD pin functions as SCL/CCLK pin and SD
setting is ignored.
In Parallel Control Mode (PSN pin = “H”), the SD pin setting is valid.
DEM1, DEM0: De-emphasis Control
00: 44.1kHz
01: OFF
(default)
10: 48kHz
11: 32kHz
DITHER: Dither is added.
0: DITHER OFF (default)
1: DITHER ON
IDIF2, IDIF1, IDIF0: Audio Interface Mode Select for Input Port (Table 3)
000: 32bit, LSB justified
001: 24bit, LSB justified
010: 32bit, MSB justified
(default)
011: 32 or 16bit, I2S justified
100: TDM 32bit, MSB justified
101: TDM 32bit, I2S Compatible
110: TDM 32bit, MSB justified
111: TDM 32bit, I2S Compatible
In Parallel Control Mode (PSN pin = “H”), IDIF2-0 bits settings are valid.
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Addr Register Name
02H
PCMCONT1
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
D2
D1
ASCHON TDMICH2 TDMICH1
R/W
0
R/W
0
R/W
0
D0
TDMICH0
R/W
0
ASCHON: Auto Input Source Change Mode ON
0: Auto Input Source Change Mode OFF (default)
1: Auto Input Source Change Mode ON
TDMICH2, TDMICH1, TDMICH0：TDM Input Mode Channel Sellect
・256fs Mode
000: Ch1 (Lch), Ch2 (Rch) (default)
001: Ch3 (Lch), Ch4 (Rch)
010: Ch5 (Lch), Ch6 (Rch)
011: Ch7 (Lch), Ch8 (Rch)
100: Ch1 (Lch), Ch2 (Rch)
101: Ch3 (Lch), Ch4 (Rch)
110: Ch5 (Lch), Ch6 (Rch)
111: Ch7 (Lch), Ch8 (Rch)
・512fs Mode
000: Ch1 (Lch), Ch2 (Rch) (default)
001: Ch3 (Lch), Ch4 (Rch)
010: Ch5 (Lch), Ch6 (Rch)
011: Ch7 (Lch), Ch8 (Rch)
100: Ch9 (Lch), Ch10 (Rch)
101: Ch11 (Lch), Ch12 (Rch)
110: Ch13 (Lch), Ch14 (Rch)
111: Ch15 (Lch), Ch16 (Rch)
In Parallel Control Mode (PSN pin = “H”), Ch1 (Lch) and Ch2 (Rch) are selected.
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15.Jitter Tolerance
Figure 55 shows the jitter tolerance to ILRCK. The jitter quantity is defined by the jitter frequency and
the jitter amplitude shown in Figure 55. When the jitter amplitude is 0.02UIpp or less, the AK4136
operates normally regardless of the jitter frequency.
AK4136 Jitter Tolerance
Jittter Amplitude [UIpp]
10.00
1.00
0.10
(2)
0.01
(1)
0.00
1
10
100
1000
10000
100000
Jittter Frequency [Hz]
Figure 55. Jitter Tolerance
(1) Normal Operation
(2) There is a possibility that the output data is lost.
Note
▪ Y axis is the jitter amplitude of ILRCK just before THD+N degradation starts.
1UI (Unit Interval) is one cycle of ILRCK. When FSI = 48kHz, 1[UIpp]=1/48kHz
=20.8μs
▪ This data is evaluated by adding jitter to ILRCK and IBICK, and comparing to the
corresponding data input.
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16.Recommended External Circuit
Figure 56 and Figure 57 shows the system connection diagram. An evaluation board (AKD4136)
demonstrates application circuits, the optimum layout, power supply arrangements and measurement
results.
Serial Control mode (PSN pin = “L”)
4-wire serial Control Mode, Chip Address = “00”
XTI/XTO = 256FSO, X’tal is used
Input PORT: Slave mode, 64FSI IBICK
Input audio interface format can be set by registers.
Output PORT: Master mode, 32bit I2S Compatible, 64FSO OBICK.
De-emphasis filter can be switched ON/OFF by the register setting.
Digital 3.3V
+ 10u 10u +
37
OBIT0
CM0 39
OBIT1 38
CM1 40
NC 42
CM2 41
VSEL 43
DV18 44
DVSS 45
NC 47
1
NC
2
NC
DVDD 35
3
NC
DVSS 34
DVDD
4
ILRCK
5
IBICK
6
SDTI
7
CAD0/IDIF0
8
9
36
0.1u
+ 10u
+
0.1u 10u
XTI/OMCLK/TDMI 33
AK4136
Top View
CLKMODE 32
XTO
31
fso
N
CAD1/IDIF1
24.576MHz
TDM 30
OLRCK 29
IDIF2
OBICK 28
10 SRCEN
64fso
DAC
NC 26
23 NC
22 NC
21 ODIF0
NC 25
20 ODIF1
19 CSN/SMUTE
18 SCL/CCLK/SD
16 CDTO
15 PSN
14 PDN
13 I2C
12 TEST1
17 SDA/CDTI/SLOW
SDTO 27
11 TEST0
24 NC
DSP
DVDD 46
NC 48
0.1u 0.1u
Micro-Controller
+
Electrolytic Capacitor
Ceramic Capacitor
Notes:
- DVSS of the AK4136 must be distributed separately from the ground of external controllers.
- All digital input pins should not be allowed to float.
- Refer to Table 6 for the capacitor values near the X’tal.
Figure 56. Typical Connection Diagram (serial control mode)
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Parallel Control Mode (PSN pin = “H”).
XTI/XTO = 256FSO, X’tal is used.
Input PORT: Slave mode, 32 or 16 bit I2S Compatible, 64 FSI IBICK
Input audio interface format can be set by registers.
Output PORT: Master mode, 32 bit I2S Compatible, 64FSO OBICK.
De-emphasis filter is fixed to OFF.
Digital 3.3V
+ 10u 10u +
37
OBIT0
CM0 39
OBIT1 38
CM1 40
NC 42
CM2 41
VSEL 43
DV18 44
DVSS 45
NC 47
1
NC
2
NC
DVDD 35
3
NC
DVSS 34
4
ILRCK
5
IBICK
6
SDTI
7
CAD0/IDIF0
8
CAD1/IDIF1
9
DVDD
36
0.1u
+ 10u
+
0.1u 10u
XTI/OMCLK/TDMI 33
AK4136
Top View
CLKMODE 32
XTO
31
24.576MHz
TDM 30
fso
OLRCK 29
IDIF2
OBICK 28
10 SRCEN
64fso
DAC
NC 26
23 NC
22 NC
21 ODIF0
NC 25
20 ODIF1
19 CSN/SMUTE
16 CDTO
15 PSN
14 PDN
13 I2C
12 TEST1
18 SCL/CCLK/SD
11 TEST0
17 SDA/CDTI/SLOW
SDTO 27
24 NC
DSP
DVDD 46
NC 48
0.1u 0.1u
Micro-Controller
+
Electrolytic Capacitor
Ceramic Capacitor
Notes:
- DVSS of the AK4136 must be distributed separately from the ground of external controllers.
- All digital input pins should not be allowed to float.
- Refer to Table 6 for the capacitor values near the X’tal.
Figure 57. Typical Connection Diagram (parallel control mode)
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17.Package
■ Outline Dimensions
9.0 ± 0.2
C
48
37
1
7.0 ± 0.2
9.0 ± 0.2
36
A
12
25
13
0.08 M S A C
0.50
0.22 ± 0.05
0.10
0.00 ~ 0.2
1.40 ± 0.05
0.05 ~ 0.15
S
1.6 MAX
7.0 ± 0.2
S
0.60 ± 0.15
■ Material & Lead Finish
Package molding compound: Epoxy
Lead frame material: Cu
Pin surface treatment: Solder (Pb free) plate
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■ Marking
AK4136VQ
XXXXXXX
1
XXXXXXX: Date code identifier
18. Ordering Guide
AK4136VQ
AKD4136
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40 +105C
48-pin LQFP (0.5mm pitch)
Evaluation Board for AK4136
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19. Revision History
Date (Y/M/D) Revision Reason
16/01/21
00
First Edition
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Page
Contents
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IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or
application of AKM product stipulated in this document (“Product”), please make inquiries the
sales office of AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third
party with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING
FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR
APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which
may cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the
aerospace industry, medical equipment, equipment used for automobiles, trains, ships and
other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations
in which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the
design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological
weapons or missile technology products (mass destruction weapons). When exporting the
Products or related technology or any information contained in this document, you should
comply with the applicable export control laws and regulations and follow the procedures
required by such laws and regulations. The Products and related technology may not be used
for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including
without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses
occurring as a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without
prior written consent of AKM.
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