[AK4331]
AK4331
Low-Power Advanced 32-bit DAC with HP/SRC
1. General Description
The AK4331 is an advanced 32-bit high sound quality stereo audio DAC with a built-in ground-referenced
headphone amplifier. The AK4331 has four types of 32-bit digital filters for better sound quality, achieving
low distortion characteristics and wide dynamic range. The AK4331 also has a jitter cleaner with a built-in
SRC and a X’tal. The AK4331 is available in a 36-pin CSP package, utilizing less board space than
competitive offerings.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
2. Features
High Sound Quality Low Power Advanced 32-bit Stereo DAC
- 4 types of Digital Filter for Sound Color Selection
- Short Delay Sharp Roll-off, GD = 5.5 / fs
- Short Delay Slow Roll-off, GD = 4.5 / fs
- Sharp Roll-off
- Slow Roll-off
Ground-referenced Class-G Stereo Headphone Amplifier
- Output Power: 70 mW @ 8Ω
- THD+N: 100 dB
- S/N: 109 dB
- Output Noise Level: 114 dBV (Analog Volume = 10 dB)
- Analog Volume: +4 to 10 dB, 2 dB Step
- Ground Loop Noise Cancellation
Low Power Consumption: 4.4 mW (Play back, fs = 48 kHz, External Slave Mode)
5.0 mW (Play back, fs = 48 kHz, PLL Slave Mode)
Headphone Amplifier Output Pins Comply with IEC61000-4-2 ESD Protection
- ±8 kV Contact Discharge
Digital Audio interface
- Master / Slave Mode
- Sampling Frequency (Slave Mode / Master Mode):
8 k, 11.025 k, 12 k, 16 k, 22.05 k, 24 k, 32 k, 44.1 k, 48 k, 64 k, 88.2 k, 96 k, 128 k,
176.4 k, 192 kHz
- Interface Format: 32/24/16-bit I2S/MSB justified
Asynchronous Sample Rate Converter
- Up sample: up to ×6.02
Stereo Digital Microphone Interface
Power Management
PLL
Jitter Cleaner with a built-in SRC and X’tal Oscillator
μP Interface: I2C-bus (400 kHz)
Operation Temperature Range: Ta = 40 to 85 C
Power Supply:
AVDD (DAC, PLL):
1.7 to 1.9 V
CVDD (Headphone Amplifier, Charge Pump): 1.7 to 1.9 V
LVDD (LDO2 for Digital Core):
1.7 to 1.9 V (built-in LDO)
TVDD (Digital Interface):
1.65 to 3.6 V
Pin Compatible and Register Backward Compatible with the AK4375A
Package: 36-pin CSP (2.533 × 2.371 mm, 0.4 mm pitch)
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3. Table of Contents
1. General Description ................................................................................................................................ 1
2. Features.................................................................................................................................................. 1
3. Table of Contents.................................................................................................................................... 2
4. Block Diagram and Functions ................................................................................................................ 4
5. Pin Configurations and Functions .......................................................................................................... 5
5-1. Pin Configurations ........................................................................................................................ 5
5-2. Pin Function Difference with AK4375A ........................................................................................ 6
5-3. Pin Functions ................................................................................................................................ 7
5-4. Handing of Unused Pins ............................................................................................................. 10
6. Absolute Maximum Ratings................................................................................................................... 11
7. Recommended Operating Conditions ................................................................................................... 11
8. Electrical Characteristics ...................................................................................................................... 12
8-1. DAC Analog Characteristics ....................................................................................................... 12
8-2. PLL Characteristics..................................................................................................................... 14
8-3. Charge Pump & LDO Circuit Power-Up Time ............................................................................ 14
8-4. Power Supply Current................................................................................................................. 15
8-5. Power Consumptions for Each Operation Mode ........................................................................ 15
8-6. SRC Characteristics ................................................................................................................... 15
8-7. DAC Sharp Roll-Off Filter Characteristics (SRC Bypass Mode) ................................................ 16
8-8. DAC Slow Roll-Off Filter Characteristics (SRC Bypass Mode) .................................................. 18
8-9. DAC Short Delay Sharp Roll-Off Filter Characteristics (SRC Bypass Mode) ............................ 20
8-10. DAC Short Delay Slow Roll-Off Filter Characteristics (SRC Bypass Mode) .............................. 22
8-11. DAC Sharp Roll-Off Filter Characteristics (SRC Mode) ............................................................. 24
8-12. DAC Slow Roll-Off Filter Characteristics (SRC Mode) ............................................................... 26
8-13. DAC Short Delay Sharp Roll-Off Filter Characteristics (SRC Mode) ......................................... 28
8-14. DAC Short Delay Slow Roll-Off Filter Characteristics (SRC Mode) ........................................... 30
8-15. Digital Microphone Filter Characteristics .................................................................................... 32
8-16. DC Characteristics ...................................................................................................................... 33
8-17. Switching Characteristics............................................................................................................ 34
8-18. Timing Diagram (System Clock) ................................................................................................. 36
8-19. Timing Diagram (Serial Audio Interface) .................................................................................... 37
8-20. Timing Diagram (I2C-bus Interface) ............................................................................................ 38
8-21. Timing Diagram (Reset).............................................................................................................. 38
8-22. Timing Diagram (Digital Microphone Interface) .......................................................................... 39
9. Functional Description .......................................................................................................................... 40
9-1. System Clock .............................................................................................................................. 40
9-2. Master Counter Synchronization Control ................................................................................... 46
9-3. PLL .............................................................................................................................................. 47
9-4. Crystal Oscillator ......................................................................................................................... 52
9-5. Digital Microphone ...................................................................................................................... 53
9-6. Digital Microphone HPF .............................................................................................................. 55
9-7. Digital Microphone Mono/Stereo Mode ...................................................................................... 55
9-8. Digital Microphone Initialization Cycle ........................................................................................ 55
9-9. Side Tone Digital Volume (SVOL) .............................................................................................. 56
9-10. DAC Digital Filter ........................................................................................................................ 57
9-11. Digital Mixing............................................................................................................................... 57
9-12. Digital Volume ............................................................................................................................. 58
9-13. Headphone Amplifier Output (HPL/HPR pins) ........................................................................... 59
9-14. Charge Pump & LDO Circuits..................................................................................................... 64
9-15. Asynchronous Sampling Rate Converter (SRC) ........................................................................ 65
9-16. SRC Selector Function ............................................................................................................... 66
9-17. SRC Clock Change Sequence ................................................................................................... 67
9-18. Soft Mute..................................................................................................................................... 68
9-19. Serial Audio Interface ................................................................................................................. 70
9-20. Serial Control Interface (I2C-bus) ............................................................................................... 71
9-21. Control Sequence ....................................................................................................................... 75
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9-22. Register Map............................................................................................................................... 78
9-23. Register Definitions..................................................................................................................... 79
10. Recommended External Circuits ........................................................................................................ 87
11. Package .............................................................................................................................................. 89
11-1. Outline Dimensions..................................................................................................................... 89
11-2. Material and Lead Finish ............................................................................................................ 89
11-3. Marking ....................................................................................................................................... 90
12. Ordering Guide ................................................................................................................................... 90
13. Revision History .................................................................................................................................. 91
IMPORTANT NOTICE .............................................................................................................................. 91
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LDO2
2
SCL
VCOM
VSS2
VSS1
CVDD
PDN
for Digital Logic
TEST1
Control
Register
IC
Interface
SDA
AVDD
VSS3
VDD12
LVDD
TVDD
4. Block Diagram and Functions
TEST2
SRC Bypass
Mode
32-bit
MIX
Audio
Interface
BCLK
DVOL
LRCK
SDTI
Digital
Filter
Stereo
DAC
SRC
HP
(w/ Vol)
SRC
Mode
SDTO
HPL
HPGND
HPR
SVOL
(0/-6/-12/-18/-24dB)
DMIC
Interface
VEE2
VCC2
CP2B
CN2B
CP2A
CN2A
RVEE
RAVDD
VEE1
for Headphone Amplifier
IFCLK/
(Class-G)
SRCMCLK for DAC
DACCLK
Charge Pump1
Charge
X’tal OSC
& LDO1P/N
Pump2
PLL
XTI/MCKI
BCLK
CP1
CN1
DMDAT
XTO
DMCLK
Figure 1. AK4331 Block Diagram
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5. Pin Configurations and Functions
5-1. Pin Configurations
36-pin CSP
6
5
4
Top View
3
2
1
A
B
C
D
E
F
6
VDD12
LVDD
CN1
CP1
CVDD
CN2B
5
VSS3
SDTI
VEE1
VSS2
CP2B
CN2A
4
TVDD
LRCK
SDA
SCL
CP2A
VEE2
3
MCKI
/XTI
BCLK
PDN
TEST1
VCC2
HPR
2
XTO
DMDAT
TEST2
VSS1
HPL
HPGND
1
SDTO
DMCLK
RVEE
RAVDD
AVDD
VCOM
A
B
C
D
E
F
Top View
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5-2. Pin Function Difference with AK4375A
Pin
No.
AK4375A
Pin Name
A1
XTI
A3
MCKI
B1
TESTO
B2
LDO2E
C2
VSS4
AK4331
Pin Name
Function
X’tal Oscillator Input Pin
SDTO
Left floating when not in use.
External Master Clock Input Pin
Connect to VSS3 when not in
use.
MCKI/XTI
Test Output Pin
Left floating when not in use.
LDO2 Enable pin
This pin must be tied “H”.
Ground4 pin
This pin must be tied “L”.
DMCLK
DMDAT
TEST2
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Function
Audio Serial Data Output Pin
Left floating when not in use.
External Master Clock Input
/ X’tal Oscillator Input Pin
Connect to VSS3 and set
PMOSC bit to “0” when not in
use.
Digital MIC Clock Output Pin
Left floating when not in use.
Digital MIC Data Input Pin
Connect to VSS1 or AVDD
when not in use.
Test Input pin
This pin must be tied “L”.
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5-3. Pin Functions
No.
Pin Name
Power Supply
E1
AVDD
D2
VSS1
I/O
Protection
Diode
Function
Power
Domain
-
Analog Power Supply Pin
AVDD
Ground 1 Pin
Headphone Amplifier / Charge Pump
E6
CVDD
CVDD
Power Supply Pin
D5
VSS2
Ground 2 Pin
B6
LVDD
Digital Core & LDO2 Power Supply Pin
LVDD
A5
VSS3
Ground 3 Pin
A4
TVDD
Digital Interface Power Supply Pin
TVDD
Common Voltage Output Pin
AVDD /
F1
VCOM
O
Connect a 2.2 μF ±50% capacitor between this
VSS1
pin and the VSS1 pin. (Note 2)
LDO2 (1.2 V) Output Power Supply Pin (Note 1)
LVDD /
A6
VDD12
Connect a capacitor between this pin to the VSS3
LVDD
VSS3
pin. (Note 2)
Note 1. Capacitor value connected to the VDD12 pin should be selected from 2.2 µF ±50% to 4.7µF
±50%.
Note 2. Do not connect a load to the VCOM pin and the VDD12 pin.
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No.
Pin Name
I/O
Protection
Diode
Function
Power
Domain
Charge Pump & LDO
Positive Charge Pump Capacitor Terminal 1 Pin
CVDD /
Connect a 2.2 μF ±50% capacitor between this
CVDD
VSS2
pin and the CN1 pin.
Negative Charge Pump Capacitor Terminal 1 Pin
C6 CN1
I
Connect a 2.2 μF ±50% capacitor between this CVDD
CVDD
pin and the CP1 pin.
Charge Pump Circuit Negative Voltage (CVDD)
CVDD /
Output 1 Pin
C5 VEE1
O
Connect a 2.2 μF ±50% capacitor between this VSS2
pin and the VSS2 pin. (Note 3)
LDO1P (1.5 V) Output Pin (Note 4)
AVDD /
D1 RAVDD
O
Connect a capacitor between this pin and the
VSS1
VSS1 pin. (Note 3)
LDO1N (1.5 V) Output Pin (Note 4)
AVDD /
C1 RVEE
O
Connect a capacitor between this pin and the
VSS1
VSS1 pin. (Note 3)
Charge Pump Circuit Positive Voltage
(CVDD or 1/2 × CVDD) Output Pin
CVDD /
E3
VCC2
O
CVDD
Connect a 2.2 μF ±50% capacitor between this VSS2
pin and the VSS2 pin. (Note 3)
Positive Charge Pump Capacitor Terminal 2A Pin
CVDD /
E4
CP2A
O
Connect a 2.2 μF ±50% capacitor between this
CVDD
VSS2
pin and the CN2A pin.
Negative Charge Pump Capacitor Terminal 2A Pin
F5
CN2A
I
Connect a 2.2 μF ±50% capacitor between this CVDD
CVDD
pin and the CP2A pin.
Positive Charge Pump Capacitor Terminal 2B Pin
CVDD /
E5
CP2B
O
Connect a 2.2 μF ±50% capacitor between this
CVDD
VSS2
pin and the CN2B pin.
Negative Charge Pump Capacitor Terminal 2B Pin
F6
CN2B
I
Connect a 2.2 μF ±50% capacitor between this CVDD
CVDD
pin and the CP2B pin.
Charge Pump Circuit Negative Voltage
CVDD /
(CVDD or 1/2 × CVDD) Output 2 Pin
F4
VEE2
O
Connect a 2.2 μF ±50% capacitor between this VSS2
pin and the VSS2 pin. (Note 3)
Note 3. Do not connect a load to the VEE1 pin, VCC2 pin, VEE2 pin, RAVDD pin and the RVEE pin.
Note 4. Capacitor value connected to the RAVDD pin and the RVEE pin should be selected from 1.0
µF ±50% to 4.7 µF ±50%.
D6
CP1
O
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No.
Pin Name
I/O
Protection
Diode
Function
Power
Domain
Control Interface
D4
SCL
I
C4
SDA
I/O
I2C Serial Data Clock Pin
I2C Serial Data Input/Output Pin
TVDD /
VSS3
TVDD /
VSS3
TVDD
TVDD
Audio Interface
External Master Clock Input Pin
(PMOSC bit = “0”)
X’tal Oscillator Input Pin
(PMOSC bit = “1”)
MCKI
I
XTI
I
A1
SDTO
O
Audio Serial Data Output Pin
A2
XTO
O
X’tal Oscillator Output Pin
B3
BCLK
I/O
Audio Serial Data Clock Pin
B4
LRCK
I/O
Frame Sync Clock Pin
B5
SDTI
I
Audio Serial Data Input Pin
A3
TVDD /
VSS3
TVDD /
VSS3
TVDD /
VSS3
TVDD /
VSS3
TVDD /
VSS3
TVDD /
VSS3
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
Analog Output
E2
HPL
O
Lch Headphone Amplifier Output Pin
F3
HPR
O
Rch Headphone Amplifier Output Pin
F2
HPGND
I
Headphone Amplifier Ground Loop Noise
Cancellation Pin
CVDD /
VEE2
CVDD /
VEE2
CVDD /
VEE2
CVDD /
VEE2
-
-
Digital MIC Interface
B1
DMCLK
O
Digital MIC Clock Output Pin
B2
DMDAT
I
Digital MIC Data Input Pin
AVDD /
VSS1
AVDD /
VSS1
AVDD
AVDD
Others
Power down Pin
TVDD /
TVDD
“L”: Power-Down, “H”: Power-Up
VSS3
Test Input 1 Pin
TVDD
D3 TEST1
I
TVDD
It must be tied “L”.
VSS3
Test Input 2 Pin
TVDD /
C2 TEST2
I
TVDD
It must be tied “L”.
VSS3
Note 5. The SCL pin, SDA pin, MCKI/XTI pin, BCLK pin, LRCK pin, SDTI pin, HPGND pin, DMDAT pin,
PDN pin, TEST1 pin and the TEST2 pin must not be allowed to float.
C3
PDN
I
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5-4. Handing of Unused Pins
Unused I/O pins must be connected appropriately.
Classification Pin Name
Analog
HPL, HPR
MCKI/XTI, TEST1, TEST2
Digital
DMCLK, SDTO, XTO
DMDAT
Setting
Open
Connect to VSS3
Open
Connect to VSS1 or AVDD
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6. Absolute Maximum Ratings
(VSS1 = VSS2 = VSS3 = 0 V; Note 7, Note 8)
Parameter
Symbol
Power
Analog
AVDD
Supplies:
Headphone Amplifier / Charge Pump
CVDD
(Note 6)
LDO2 for Digital Core
LVDD
Digital Interface
TVDD
Input Current, Any Pin Except Supplies
IIN
Min.
0.3
0.3
0.3
0.3
-
Max.
Unit
4.3
V
4.3
V
4.3
V
4.3
V
±10
mA
AVDD+0.3
Digital Input Voltage 1 (Note 9)
VIND1
V
0.3
or 4.3
TVDD+0.3
Digital Input Voltage 2 (Note 10)
VIND2
V
0.3
or 4.3
Ambient Temperature (powered applied)
Ta
85
40
C
Storage Temperature
Tstg
150
65
C
Note 6. Charge pump 1 & 2 are not in operation. In the case that charge pump 1 & 2 are in operation,
the maximum values of AVDD and CVDD become 2.15 V.
Note 7. All voltages with respect to ground.
Note 8. VSS1, VSS2 and VSS3 must be connected to the same analog plane.
Note 9. DMDAT pin
The maximum value of input voltage is lower value between (AVDD+0.3) V and 4.3 V.
Note 10. MCKI/XTI, BCLK, LRCK, SDTI, SCL, SDA, PDN, TEST1, TEST2 pins
The maximum value of input voltage is lower value between (TVDD+0.3) V and 4.3 V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal Operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(VSS1 = VSS2 = VSS3 ＝ 0 V; Note 11)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power
Analog
AVDD
1.7
1.8
1.9
V
Supplies:
Headphone Amplifier / Charge Pump
CVDD
1.7
1.8
1.9
V
(Note 12)
LDO2 for Digital Core
LVDD
1.7
1.8
1.9
V
Digital Interface
TVDD
1.65
1.8
3.6
V
Note 11. All voltages with respect to ground.
Note 12. Each power up/down sequence is shown below.
1. PDN pin = “L”
2. TVDD, AVDD, LVDD and CVDD are powered up.
(AVDD must be powered up before or at the same time of CVDD. The power-up sequence of
TVDD and LVDD is not critical.)
3. The PDN pin is allowed to be “H” after all power supplies are applied and settled.
1. PDN pin = “L”
2. TVDD, AVDD, LVDD and CVDD are powered down.
(CVDD must be powered down before or at the same time of AVDD. The power-down
sequence of TVDD and LVDD is not critical.)
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8. Electrical Characteristics
8-1. DAC Analog Characteristics
(Ta = 25C; AVDD = CVDD = LVDD = TVDD = 1.8 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; Signal
Frequency = 1 kHz; 24-bit Data; fs = 48 kHz, BCLK = 64fs; Measurement Bandwidth = 20 Hz to 20 kHz,
OVL/R = 0 dB, RL = 32Ω, SELDAIN bit = “0”; unless otherwise specified)
Parameter
Min.
Typ.
Max.
Unit
Stereo DAC Characteristics:
Resolution
32
Bits
Headphone Amplifier Characteristics: DAC (Stereo) → HPL/HPR pins
Output Power
0 dBFS, RL = 32Ω, HPG = 0 dB
25
mW
10
mW
0 dBFS, RL = 32Ω, HPG = 4 dB
45
mW
RL = 16Ω, HPG = 0 dB, THD+N < 60 dB
70
mW
RL = 8Ω, HPG = +2 dB, THD+N < 20 dB
0.52
0.57
0.61
Vrms
Output Level (0 dBFS, RL = 32Ω, HPG = 4 dB) (Note 13)
THD+N
fs = 48 kHz
0 dBFS, RL = 32Ω, HPG = 4 dB
dB
100
90
BW = 20 kHz
(Po = 10 mW)
fs = 96 kHz
dB
97
BW = 40 kHz
fs = 192 kHz
dB
97
BW = 40 kHz
fs = 48 kHz
60 dBFS, RL = 32Ω, HPG = 4 dB
dB
44
BW = 20 kHz
fs = 96 kHz
dB
40
BW = 40 kHz
fs = 192 kHz
dB
40
BW = 40 kHz
Dynamic Range
107
dB
60 dBFS, A-weighted, HPG = 4 dB
S/N (A-weighted)
Po = 25 mW, HPG = 0 dB (Data = 0 dBFS / “0” Data)
109
dB
99
107
dB
Po = 10 mW, HPG = 4 dB (Data = 0 dBFS / “0” Data)
Output Noise Level
dBV
114
106
(A-weighted, HPG = 10 dB)
Note 13. Output level is proportional to AVDD. Typ. 0.57 Vrms × AVDD / 1.8 V @headphone amplifier
gain = 4 dB.
Headphone Amplifier
AK4331
0.1 μF
RL
15Ω
Figure 2. External Circuit for Headphone Amplifier
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Parameter
Min.
Typ.
Max.
Unit
Interchannel Isolation
0 dBFS, HPG = 4 dB (Po = 10 mW)
80
100
dB
External Impedance = 0.09Ω (Note 14)
Interchannel Gain Mismatch
0
0.8
dB
Load Resistance
7.2
32
Ω
Load Capacitance
500
pF
Load Inductance
0.375
µH
PSRR (HPG = 4 dB) (Note 15)
217 Hz
85
dB
1 kHz
85
dB
DC-offset (Note 16)
HPG = 0 dB
0
+0.15
mV
0.15
HPG = All gain
0
+0.2
mV
0.2
Headphone Output Volume Characteristics:
Gain Setting
+4
dB
10
Step Width
1
2
3
dB
Gain: +4 to 10 dB
Note 14. Impedance between the HPGND pin and the system ground.
Note 15. PSRR is referred to all power supplies with 100 mVpp sine wave.
Note 16. When there is no gain change and temperature drift after headphone amplifier is powered up.
Parameter
Value
Unit
ESD Immunity
±8
kV
IEC61000-4-2 Level4, Contact (Note 17)
Note 17. It is measured at the HPL and HPR pins on an evaluation board (AKD4331-SA Rev.1).
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8-2. PLL Characteristics
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; unless otherwise specified)
Parameter
Min.
Typ.
Max.
Unit
PLL Characteristics
Reference Clock (Note 15)
76.8
768
kHz
PLLCLK Frequency (Note 15)
44.1 kHz × 256fs × 2
22.5792
MHz
48.0 kHz × 256fs × 2
24.576
MHz
Lock Time
2
msec
8-3. Charge Pump & LDO Circuit Power-Up Time
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; unless otherwise specified)
Parameter
Capacitor
Min.
Typ.
Max.
Unit
Block Power-Up Time
CP1 (Note 18)
6.5
msec
CP2 (Class-G) (Note 18, Note 19) 4.5
msec
LDO1P (Note 20)
1 μF @RAVDD
0.5
msec
LDO1N (Note 20)
1 μF @RVEE
0.5
msec
LDO2 (Note 18)
1
msec
Note 18. Power-up time is a fixed value that is not affected by a capacitor.
Note 19. Power-up time is a value to 1/2 × CVDD, since CP2 starts with 1/2VDD Mode as part of
Class-G operation.
Note 20. Power-up time is proportional to a capacitor value. For instance, if a 2.2 μF capacitor is
connected to the RAVDD pin, LDO1P power-up time is 1.1 msec at maximum.
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8-4. Power Supply Current
(Ta = 25C; AVDD = CVDD = LVDD = TVDD = 1.8 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; unless
otherwise specified)
Parameter
Min.
Typ.
Max.
Unit
Power Supply Current:
Power Up (PDN pin = “H”, All Circuits Power-Up) (Note 21)
AVDD + CVDD + LVDD + TVDD
4.1
6.1
mA
Power Down (PDN pin = “L”) (Note 22)
AVDD + CVDD + LVDD + TVDD
0
10
μA
Note 21. fso/fsi = 48 kHz/48 kHz, MCKI = 256fs, BCLK = 64fs; No data input, RL = 32Ω, DAC,
Headphone Amplifier, PLL & X’tal & SRC & DMIC Power-Up
Note 22. The DMDAT pin is fixed to AVDD or VSS1 and other digital input pins are fixed to TVDD or
VSS3.
8-5. Power Consumptions for Each Operation Mode
(Ta = 25C; AVDD = CVDD = LVDD = TVDD = 1.8 V; VSS1 = VSS2 = VSS3 = HPGND = 0 V; SRC
Bypass Mode, MCKI = 256fs, BCLK = 64fs; No data input, RL = 32Ω, X’tal & DMIC OFF)
Table 1. Power Consumption (Typ.) for Each Operation Mode
Typical Current [mA]
Mode
AVDD
CVDD
LVDD
TVDD
DAC → Headphone (fs = 48 kHz),
0.79
1.37
0.27
0.01
External Slave Mode
DAC → Headphone (fs = 96 kHz),
0.87
1.69
0.36
0.01
External Slave Mode
DAC → Headphone (fs = 192 kHz),
0.87
1.69
0.44
0.01
External Slave Mode, MCKI = 128fs
DAC → Headphone (fs = 48 kHz),
0.79
1.37
0.69
0.01
External Slave Mode, DMIC enable
DAC → Headphone (fs = 96 kHz),
0.87
1.69
1.16
0.01
External Slave Mode, DMIC enable
DAC → Headphone (fs = 48 kHz),
1.06
1.37
0.31
0.01
PLL Slave Mode
DAC → Headphone (fs = 96 kHz),
1.14
1.69
0.41
0.01
PLL Slave Mode
DAC → Headphone (fs = 192 kHz),
1.14
1.69
0.49
0.01
PLL Slave Mode
Total Power
[mW]
4.4
5.3
5.4
5.1
6.7
5.0
5.9
6.0
8-6. SRC Characteristics
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
0 V; unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Resolution
32
Bits
Input Sample Rate
FSI
8
192
kHz
Output Sample Rate
FSO
8
192
kHz
Ratio between Input and Output Sample Rate
FSO/FSI
0.98
6.02
-
018006903-E-00
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[AK4331]
8-7. DAC Sharp Roll-Off Filter Characteristics (SRC Bypass Mode)
8-7-1. Sharp Roll-Off Filter (SRC Bypass Mode, fs = 48 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 48 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
22.42
kHz
0.006 to +0.23 dB
(Note 23)
24.02
kHz
6.0 dB
Stopband (Note 23)
SB
26.2
kHz
Passband Ripple
PR
+0.23
dB
0.006
Stopband Attenuation (Note 24)
SA
69.8
dB
Group Delay (Note 25)
GD
25.8
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 20.0 kHz
FR
+0.10
dB
0.12
Note 23. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.467 × fs (@0.006/+0.23 dB), SB = 0.5465 × fs. Each frequency response refers to that
of 1 kHz.
Note 24. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 25. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
8-7-2. Sharp Roll-Off Filter (SRC Bypass Mode, fs = 96 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 96 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
44.85
kHz
0.003 to +0.24 dB
(Note 26)
48.04
kHz
6.0 dB
Stopband (Note 26)
SB
52.5
kHz
Passband Ripple
PR
+0.24
dB
0.003
Stopband Attenuation (Note 27)
SA
69.8
dB
Group Delay (Note 28)
GD
25.8
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 40.0 kHz
FR
+0.11
dB
1.69
Note 26. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4672 × fs (@0.003/+0.24 dB), SB = 0.547 × fs. Each frequency response refers to that
of 1 kHz.
Note 27. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 28. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
018006903-E-00
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- 16 -
[AK4331]
8-7-3. Sharp Roll-Off Filter (SRC Bypass Mode, fs = 192 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 192 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
89.74
kHz
0.002 to +0.24 dB
(Note 29)
96.08
kHz
6.0 dB
Stopband (Note 29)
SB
104.9
kHz
Passband Ripple
PR
+0.24
dB
0.002
Stopband Attenuation (Note 30)
SA
69.8
dB
Group Delay (Note 31)
GD
25.8
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 80.0 kHz
FR
+0.35
dB
8.23
Note 29. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4674 × fs (@0.002/+0.24 dB), SB = 0.5465 × fs. Each frequency response refers to
that of 1 kHz.
Note 30. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 31. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
018006903-E-00
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- 17 -
[AK4331]
8-8. DAC Slow Roll-Off Filter Characteristics (SRC Bypass Mode)
8-8-1. Slow Roll-Off Filter (SRC Bypass Mode, fs = 48 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 48 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
8.49
kHz
0.07 to +0.005 dB
(Note 32)
20.15
kHz
3.0 dB
Stopband (Note 32)
SB
42.59
kHz
Passband Ripple
PR
+0.005
dB
0.07
Stopband Attenuation (Note 33)
SA
72.8
dB
Group Delay (Note 34)
GD
25.8
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 20.0 kHz
FR
+0.03
dB
3.21
Note 32. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.1769 × fs (@0.07/+0.005 dB), SB = 0.887 × fs. Each frequency response refers to that
of 1 kHz.
Note 33. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 34. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
8-8-2. Slow Roll-Off Filter (SRC Bypass Mode, fs = 96 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 96 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
17.02
kHz
0.07 to +0.006 dB
(Note 35)
40.3
kHz
3.0 dB
Stopband (Note 35)
SB
85.15
kHz
Passband Ripple
PR
+0.006
dB
0.07
Stopband Attenuation (Note 36)
SA
72.8
dB
Group Delay (Note 37)
GD
25.8
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 40.0 kHz
FR
+0.10
dB
4.84
Note 35. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.1773 × fs (@0.07/+0.006 dB), SB = 0.887 × fs. Each frequency response refers to that
of 1 kHz.
Note 36. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 37. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
018006903-E-00
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- 18 -
[AK4331]
8-8-3. Slow Roll-Off Filter (SRC Bypass Mode, fs = 192 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 192 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
34.17
kHz
0.07 to +0.006 dB
(Note 38)
80.65
kHz
3.0 dB
Stopband (Note 38)
SB
170.3
kHz
Passband Ripple
PR
+0.006
dB
0.07
Stopband Attenuation (Note 39)
SA
72.8
dB
Group Delay (Note 40)
GD
25.8
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 80.0 kHz
FR
+0.35
dB
11.38
Note 38. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.178 × fs (@0.07/+0.006 dB), SB = 0.887 × fs. Each frequency response refers to that
of 1 kHz.
Note 39. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 40. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
018006903-E-00
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- 19 -
[AK4331]
8-9. DAC Short Delay Sharp Roll-Off Filter Characteristics (SRC Bypass Mode)
8-9-1. Short Delay Sharp Roll-Off Filter (SRC Bypass Mode, fs = 48 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 48 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
22.41
kHz
0.009 to +0.232 dB
(Note 41)
24.15
kHz
6.0 dB
Stopband (Note 41)
SB
26.23
kHz
Passband Ripple
PR
+0.232
dB
0.009
Stopband Attenuation (Note 42)
SA
69.8
dB
Group Delay (Note 43)
GD
5.5
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 20.0 kHz
FR
+0.10
dB
0.12
Note 41. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4669 × fs (@0.009/+0.232 dB), SB = 0.5465 × fs. Each frequency response refers to
that of 1 kHz.
Note 42. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 43. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
8-9-2. Short Delay Sharp Roll-Off Filter (SRC Bypass Mode, fs = 96 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 96 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
44.82
kHz
0.004 to +0.238 dB
(Note 44)
48.32
kHz
6.0 dB
Stopband (Note 44)
SB
52.5
kHz
Passband Ripple
PR
+0.238
dB
0.004
Stopband Attenuation (Note 45)
SA
69.8
dB
Group Delay (Note 46)
GD
5.5
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 40.0 kHz
FR
+0.11
dB
1.69
Note 44. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4669 × fs (@0.004/+0.238 dB), SB = 0.5465 × fs. Each frequency response refers to
that of 1 kHz.
Note 45. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 46. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
018006903-E-00
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- 20 -
[AK4331]
8-9-3. Short Delay Sharp Roll-Off Filter (SRC Bypass Mode, fs = 192 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 192 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
89.68
kHz
0.002 to +0.247 dB
(Note 47)
96.64
kHz
6.0 dB
Stopband (Note 47)
SB
104.9
kHz
Passband Ripple
PR
+0.247
dB
0.002
Stopband Attenuation (Note 48)
SA
69.8
dB
Group Delay (Note 49)
GD
5.5
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 80.0 kHz
FR
+0.36
dB
8.23
Note 47. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4671 × fs (@0.002/+0.247 dB), SB = 0.5465 × fs. Each frequency response refers to
that of 1 kHz.
Note 48. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 49. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
018006903-E-00
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- 21 -
[AK4331]
8-10. DAC Short Delay Slow Roll-Off Filter Characteristics (SRC Bypass Mode)
8-10-1. Short Delay Slow Roll-Off Filter (SRC Bypass Mode, fs = 48 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 48 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
9.82
kHz
0.07 to +0.025 dB
(Note 50)
20.57
kHz
3.0 dB
Stopband (Note 50)
SB
42.98
kHz
Passband Ripple
PR
+0.025
dB
0.07
Stopband Attenuation (Note 51)
SA
75.1
dB
Group Delay (Note 52)
GD
4.5
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 20.0 kHz
FR
+0.04
dB
2.96
Note 50. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.2045 × fs (@0.07/+0.025 dB), SB = 0.8955 × fs. Each frequency response refers to
that of 1 kHz.
Note 51. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 52. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
8-10-2. Short Delay Slow Roll-Off Filter (SRC Bypass Mode, fs = 96 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 96 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
19.7
kHz
0.07 to +0.027 dB
(Note 53)
41.16
kHz
3.0 dB
Stopband (Note 53)
SB
85.97
kHz
Passband Ripple
PR
+0.027
dB
0.07
Stopband Attenuation (Note 54)
SA
75.1
dB
Group Delay (Note 55)
GD
4.5
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 40.0 kHz
FR
+0.10
dB
4.59
Note 53. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.2052 × fs (@0.07/+0.027 dB), SB = 0.8955 × fs. Each frequency response refers to
that of 1 kHz.
Note 54. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 55. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
018006903-E-00
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[AK4331]
8-10-3. Short Delay Slow Roll-Off Filter (SRC Bypass Mode, fs = 192 kHz)
(Ta = -40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 192 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “0”, DADFSEL bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
39.54
kHz
0.07 to +0.028 dB
(Note 56)
82.37
kHz
3.0 dB
Stopband (Note 56)
SB
172
kHz
Passband Ripple
PR
+0.028
dB
0.07
Stopband Attenuation (Note 57)
SA
75.1
dB
Group Delay (Note 58)
GD
4.5
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 80.0 kHz
FR
+0.35
dB
11.13
Note 56. The passband and stopband frequencies scale with fs (system sampling rate)
PB = 0.2059 × fs (@0.07/+0.028 dB), SB = 0.8958 × fs. Each frequency response refers to
that of 1 kHz.
Note 57. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 58. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
018006903-E-00
2018/07
- 23 -
[AK4331]
8-11. DAC Sharp Roll-Off Filter Characteristics (SRC Mode)
8-11-1. Sharp Roll-Off Filter (SRC Mode, fs = 48 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 48 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
22.28
kHz
0.004 to +0.199 dB
(Note 59)
24.00
kHz
6.0 dB
Stopband (Note 59)
SB
26.21
kHz
Passband Ripple
PR
+0.199
dB
0.004
Stopband Attenuation (Note 60)
SA
70.4
dB
Group Delay (Note 61)
GD
27.6
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 20.0 kHz
FR
+0.10
dB
0.12
Note 59. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4642 × fs (@0.004/+0.199 dB), SB = 0.546 × fs. Each frequency response refers to
that of 1 kHz.
Note 60. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 61. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
8-11-2. Sharp Roll-Off Filter (SRC Mode, fs = 96 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 96 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
44.58
kHz
0.001 to +0.202 dB
(Note 62)
48.01
kHz
6.0 dB
Stopband (Note 62)
SB
52.45
kHz
Passband Ripple
PR
+0.202
dB
0.001
Stopband Attenuation (Note 63)
SA
70.2
dB
Group Delay (Note 64)
GD
27.6
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 40.0 kHz
FR
+0.11
dB
1.72
Note 62. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4644 × fs (@0.001/+0.202 dB), SB = 0.5464 × fs. Each frequency response refers to
that of 1 kHz.
Note 63. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 64. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
018006903-E-00
2018/07
- 24 -
[AK4331]
8-11-3. Sharp Roll-Off Filter (SRC Mode, fs = 192 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 192 kHz; DASD bit = “0”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
0.000 to +0.210 dB
PB
0
89.22
kHz
(Note 65)
96.02
kHz
6.0 dB
Stopband (Note 65)
SB
104.92
kHz
Passband Ripple
PR
0.000
+0.210
dB
Stopband Attenuation (Note 66)
SA
70.1
dB
Group Delay (Note 67)
GD
27.6
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 80.0 kHz
FR
+0.35
dB
8.27
Note 65. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4647 × fs (@0.000/+0.210 dB), SB = 0.5465 × fs. Each frequency response refers to
that of 1 kHz.
Note 66. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 67. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
018006903-E-00
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[AK4331]
8-12. DAC Slow Roll-Off Filter Characteristics (SRC Mode)
8-12-1. Slow Roll-Off Filter (SRC Mode, fs = 48 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 48 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
8.91
kHz
0.07 to +0.011 dB
(Note 68)
20.06
kHz
3.0 dB
Stopband (Note 68)
SB
42.57
kHz
Passband Ripple
PR
+0.011
dB
0.07
Stopband Attenuation (Note 69)
SA
73.9
dB
Group Delay (Note 70)
GD
27.6
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 20.0 kHz
FR
+0.03
dB
3.21
Note 68. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.1856 × fs (@0.07/+0.011 dB), SB = 0.887 × fs. Each frequency response refers to that
of 1 kHz.
Note 69. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 70. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
8-12-2. Slow Roll-Off Filter (SRC Mode, fs = 96 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 96 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
17.88
kHz
0.07 to +0.012 dB
(Note 71)
40.15
kHz
3.0 dB
Stopband (Note 71)
SB
85.15
kHz
Passband Ripple
PR
+0.012
dB
0.07
Stopband Attenuation (Note 72)
SA
73.9
dB
Group Delay (Note 73)
GD
27.6
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 40.0 kHz
FR
+0.10
dB
4.87
Note 71. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.1863 × fs (@0.07/+0.012 dB), SB = 0.887 × fs. Each frequency response refers to that
of 1 kHz.
Note 72. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 73. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
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[AK4331]
8-12-3. Slow Roll-Off Filter (SRC Mode, fs = 192 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 192 kHz; DASD bit = “0”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
35.89
kHz
0.07 to +0.013 dB
(Note 74)
80.34
kHz
3.0 dB
Stopband (Note 74)
SB
170.30
kHz
Passband Ripple
PR
+0.013
dB
0.07
Stopband Attenuation (Note 75)
SA
73.9
dB
Group Delay (Note 76)
GD
27.6
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 80.0 kHz
FR
+0.35
dB
11.42
Note 74. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.1869 × fs (@0.07/+0.013 dB), SB = 0.887 × fs. Each frequency response refers to that
of 1 kHz.
Note 75. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 76. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
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[AK4331]
8-13. DAC Short Delay Sharp Roll-Off Filter Characteristics (SRC Mode)
8-13-1. Short Delay Sharp Roll-Off Filter (SRC Mode, fs = 48 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 48 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
22.28
kHz
0.004 to +0.198 dB
(Note 77)
24.00
kHz
6.0 dB
Stopband (Note 77)
SB
26.21
kHz
Passband Ripple
PR
+0.198
dB
0.004
Stopband Attenuation (Note 78)
SA
70.4
dB
Group Delay (Note 79)
GD
7.3
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 20.0 kHz
FR
+0.10
dB
0.12
Note 77. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4642 × fs (@0.004/+0.198 dB), SB = 0.546 × fs. Each frequency response refers to
that of 1 kHz.
Note 78. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 79. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
8-13-2. Short Delay Sharp Roll-Off Filter (SRC Mode, fs = 96 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 96 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
44.58
kHz
0.001 to +0.202 dB
(Note 80)
48.01
kHz
6.0 dB
Stopband (Note 80)
SB
52.44
kHz
Passband Ripple
PR
+0.202
dB
0.001
Stopband Attenuation (Note 81)
SA
70.4
dB
Group Delay (Note 81)
GD
7.3
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 40.0 kHz
FR
+0.11
dB
1.72
Note 80. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4644 × fs (@0.001/+0.202 dB), SB = 0.5463 × fs. Each frequency response refers to
that of 1 kHz.
Note 81. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 82. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
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[AK4331]
8-13-3. Short Delay Sharp Roll-Off Filter (SRC Mode, fs = 192 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 192 kHz; DASD bit = “1”, DASL bit = “0”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
0.000 to +0.210 dB
PB
0
89.22
kHz
(Note 83)
96.02
kHz
6.0 dB
Stopband (Note 83)
SB
104.90
kHz
Passband Ripple
PR
0.000
+0.210
dB
Stopband Attenuation (Note 84)
SA
70.4
dB
Group Delay (Note 85)
GD
7.3
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 80.0 kHz
FR
+0.36
dB
8.27
Note 83. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.4647 × fs (@0.000/+0.210 dB), SB = 0.5464 × fs. Each frequency response refers to
that of 1 kHz.
Note 84. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 85. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
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[AK4331]
8-14. DAC Short Delay Slow Roll-Off Filter Characteristics (SRC Mode)
8-14-1. Short Delay Slow Roll-Off Filter (SRC Mode, fs = 48 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 48 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
10.19
kHz
0.07 to +0.036 dB
(Note 86)
20.48
kHz
3.0 dB
Stopband (Note 86)
SB
42.98
kHz
Passband Ripple
PR
+0.036
dB
0.07
Stopband Attenuation (Note 87)
SA
76.3
dB
Group Delay (Note 88)
GD
6.3
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 20.0 kHz
FR
+0.04
dB
2.97
Note 86. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.2123 × fs (@0.07/+0.036 dB), SB = 0.8954 × fs. Each frequency response refers to
that of 1 kHz.
Note 87. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 88. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
8-14-2. Short Delay Slow Roll-Off Filter (SRC Mode, fs = 96 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 96 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
20.45
kHz
0.07 to +0.038 dB
(Note 89)
40.98
kHz
3.0 dB
Stopband (Note 89)
SB
85.80
kHz
Passband Ripple
PR
+0.038
dB
0.07
Stopband Attenuation (Note 90)
SA
73.9
dB
Group Delay (Note 91)
GD
6.3
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 40.0 kHz
FR
+0.10
dB
4.63
Note 89. The passband and stopband frequencies scale with fs (system sampling rate).
PB = 0.2130 × fs (@0.07/+0.038 dB), SB = 0.8938 × fs. Each frequency response refers to
that of 1 kHz.
Note 90. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 91. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
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[AK4331]
8-14-3. Short Delay Slow Roll-Off Filter (SRC Mode, fs = 192 kHz)
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 192 kHz; DASD bit = “1”, DASL bit = “1”, SELDAIN bit = “1”, DADFSEL bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
DAC Digital Filter (LPF):
Passband
PB
0
41.05
kHz
0.07 to +0.039 dB
(Note 92)
82.02
kHz
3.0 dB
Stopband (Note 92)
SB
171.96
kHz
Passband Ripple
PR
+0.039
dB
0.07
Stopband Attenuation (Note 93)
SA
76.2
dB
Group Delay (Note 94)
GD
6.3
1/fs
DAC Digital Filter (LPF) + DACANA (Headphone Amplifier):
Frequency Response: 0 to 80.0 kHz
FR
+0.35
dB
11.17
Note 92. The passband and stopband frequencies scale with fs (system sampling rate)
PB = 0.2138 × fs (@0.07/+0.039 dB), SB = 0.8956 × fs. Each frequency response refers to
that of 1 kHz.
Note 93. The bandwidth of the stopband attenuation value is from stopband to fs (system sampling
rate).
Note 94. The calculated delay time is resulting from digital filtering. This is the time from the input of
MSB for L channel of SDTI to the output of an analog signal. The error of the delay at audio
interface is within +1 [1/fs].
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[AK4331]
8-15. Digital Microphone Filter Characteristics
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V; TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; fs = 48 kHz)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Passband
PB
0
20.7
kHz
+0.18 to 0.09 dB
(Note 95)
21.6
kHz
0.87 dB
22.8
kHz
3.0 dB
Stopband (Note 95)
SB
28.4
kHz
Passband Ripple
PR
0.18
dB
0.09
Stopband Attenuation
SA
65
dB
Group Delay Distortion
ΔGD
0
μsec
Group Delay (Ts = 1/fs) (Note 96)
GD
12.5
1/fs
Digital MIC HPF: HPFC[1:0] bits = “00”
Frequency Response
FR
29.8
Hz
3.0 dB
(Note 95)
Note 95. The passband and stopband frequencies scale with “fs” (system sampling rate). Each
frequency response refers to that of 1 kHz.
Note 96. The calculated delay time is resulting from digital filtering. This is the time from the 16/24/32-bit
data is set to input register to the output of SDTO digital data.
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[AK4331]
8-16. DC Characteristics
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V, TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V, PMOSC bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
I/O Pins (Note 97)
High-Level Input Voltage
Except for DMDAT pin
VIH1
70%TVDD
V
DMDAT pin
VIH2
65%AVDD
V
Low-Level Input Voltage
Except for DMDAT pin
VIL1
30%TVDD
V
DMDAT pin
VIL2
35%AVDD
V
High-Level Output Voltage
VOH1
V
Except for DMCLK pin (Iout = 200 μA)
TVDD 0.2
VOH2
V
DMCLK pin (Iout = 80 μA)
AVDD 0.4
Low-Level Output Voltage
Except for SDA pin, DMCLK pin
VOL1
0.2
V
(Iout = 200 μA)
DMCLK pin (Iout = 80 μA)
VOL2
0.4
V
SDA pin
2 V < TVDD ≤ 3.6 V (Iout = 3 mA)
VOL3
0.4
V
1.65 V ≤ TVDD ≤ 2 V (Iout = 2 mA)
VOL3
20%TVDD
V
Input Leakage Current (Note 98)
Iin
+5
μA
5
Note 97. MCKI/XTI, BCLK, LRCK, SDTI, SDTO, SCL, SDA, PDN, TEST1, TEST2, DMCLK, DMDAT
pins.
Note 98. Except for MCKI/XTI pin.
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[AK4331]
8-17. Switching Characteristics
(Ta = 40 to 85C; AVDD = CVDD = LVDD = 1.7 to 1.9 V, TVDD = 1.65 to 3.6 V; VSS1 = VSS2 = VSS3 =
HPGND = 0 V; CL = 80 pF; unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Max.
Unit
MCKI
Input Frequency
fMCK
0.256
24.576
MHz
Pulse Width Low
tMCKL
0.4 / fMCK
nsec
Pulse Width High
tMCKH
0.4 / fMCK
nsec
X’tal Oscillator (XTI pin)
Input Frequency
fMCK
11.2896
24.576
MHz
Audio Interface Timing
Master Mode
LRCK Output Timing
Frequency (When not use Digital MIC)
fs
8
192
kHz
(Note 99)
Frequency (When use Digital MIC)
fs
8
96
kHz
(Note 100)
Duty
LRDuty
50
%
BCLK Output Timing
Period (BCKO bit = “0”)
tBCK
1/(64fs)
nsec
(BCKO bit = “1”)
tBCK
1/(32fs)
nsec
Duty
BCKDuty
50
%
BCLK “↓” to LRCK Edge
tBLR
20
nsec
20
SDTI Setup Time
tBDS
10
nsec
SDTI Hold Time
tBDH
10
nsec
Delay time from BCLK Falling to SDTO
tBOD
40
nsec
40
Slave Mode
LRCK Input Timing
Frequency (When not use Digital MIC)
fs
8
192
kHz
(Note 99)
Frequency (When use Digital MIC)
fs
8
96
kHz
(Note 100)
Duty
LRDuty
45
50
55
%
BCLK Input Timing
Frequency (When not use Digital MIC)
12.288
fBCK
0.256
MHz
(Note 101)
or 512fs
Frequency (When use Digital MIC)
6.144
fBCK
0.256
MHz
(Note 102)
or 512fs
Pulse Width Low
tBCKL
0.4 / tBCK
nsec
Pulse Width High
tBCKH
0.4 / tBCK
nsec
BCLK “↑” to LRCK Edge
tBLR
20
nsec
LRCK Edge to BCLK “↑”
tLRB
20
nsec
SDTI Setup Time
tBDS
10
nsec
SDTI Hold Time
tBDH
10
nsec
Delay time from BCLK Falling to SDTO
tBOD
40
nsec
Note 99. Supported sampling rate are 8 k, 11.025 k, 12 k, 16 k, 22.05 k, 24 k, 32 k, 44.1 k, 48 k, 64 k,
88.2 k, 96 k, 128 k, 176.4 k and 192 kHz.
Note 100. Supported sampling rate are 8 k, 11.025 k, 12 k, 16 k, 22.05 k, 24 k, 32 k, 44.1 k, 48 k, 64 k,
88.2 k and 96 kHz.
Note 101. The maximum value is lower frequency between “12.288 MHz” and “512fs”.
Note 102. The maximum value is lower frequency between “6.144 MHz” and “512fs”.
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[AK4331]
Parameter
Symbol
Min.
Typ.
Max. Unit
Digital MIC Interface Timing: CL = 100 pF
DMCLK Output Timing
Period
tSCK
1/(64fs)
nsec
Rising Time
tSRise
10
nsec
Falling Time
tSFall
10
nsec
Duty Cycle
dSCK
45
50
55
%
Audio Interface Timing (DMCLK, DMDAT pins)
DMDAT Setup Time
tDMS
50
nsec
DMDAT Hold Time
tDMH
0
nsec
2
Control Interface Timing (I C-bus mode): (Note 103)
SCL Clock Frequency
fSCL
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
μsec
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
μsec
Clock Low Time
tLOW
1.3
μsec
Clock High Time
tHIGH
0.6
μsec
Setup Time for Repeated Start Condition
tSU:STA
0.6
μsec
SDA Hold Time from SCL Falling (Note 104)
tHD:DAT
0
μsec
SDA Setup Time from SCL Rising
tSU:DAT
0.1
μsec
Rise Time of Both SDA and SCL Lines
tR
0.3
μsec
Fall Time of Both SDA and SCL Lines
tF
0.3
μsec
Setup Time for Stop Condition
tSU:STO
0.6
μsec
Capacitive Load on Bus
Cb
400
pF
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
50
nsec
Power-Down & Reset Timing
PDN Accept Pulse Width (Note 105)
tPDN
1
msec
PDN Reject Pulse Width (Note 105)
tRPD
50
nsec
PMDMx bit = “1” to SDTO Valid (Note 106)
ADRST[1:0] bits = “00”
tPDV
1059
1/fs
ADRST[1:0] bits = “01”
tPDV
267
1/fs
ADRST[1:0] bits = “10”
tPDV
2115
1/fs
ADRST[1:0] bits = “11”
tPDV
531
1/fs
Note 103. I2C-bus is a registered trademark of NXP B.V.
Note 104. Data must be held long enough to bridge the 300 nsec-transition time of SCL.
Note 105. The AK4331 will be reset by bringing the PDN pin = “L”. The PDN pin must held “L” for longer
period than or equal to tPDN (Min.). The AK4331 will not be reset by the “L” pulse shorter than
or equal to tRPD (Max.).
Note 106. This is the time from PMDMx bit = “1” to the output of SDTO digital data.
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[AK4331]
8-18. Timing Diagram (System Clock)
1/fMCK
1/fMCK
VIH1
MCKI
VIL1
tMCKH
tMCKL
1/fs
1/fs
VIH1
LRCK
VIL1
tLRCKH
tLRCKL
LRDuty = tLRCKH × fs × 100
1/fBCK
1/fBCK
VIH1
BCLK
VIL1
tBCKH
tBCKL
Figure 3. System Clock (Slave Mode)
1/fs
50%TVDD
LRCK
tLRCKH
tLRCKL
LRDuty = tLRCKH × fs × 100
tBCK
50%TVDD
BCLK
tBCKH
tBCKL
BCKDuty = tBCKH / tBCK × 100
Figure 4. System Clock (Master Mode)
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[AK4331]
8-19. Timing Diagram (Serial Audio Interface)
VIH1
VIL1
LRCK
tBLR
tLRB
VIH1
VIL1
BCLK
tBDS
tBDH
VIH1
VIL1
SDTI
tBOD
50%TVDD
SDTO
Figure 5. Serial Data Interface (Slave Mode)
50%TVDD
LRCK
tBLR
50%TVDD
BCLK
tBDS
tBDH
VIH1
VIL1
SDTI
tBOD
50%TVDD
SDTO
Figure 6. Serial Data Interface (Master Mode)
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[AK4331]
8-20. Timing Diagram (I2C-bus Interface)
VIH1
SDA
VIL1
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH1
SCL
VIL1
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
2
Figure 7. I C-bus Mode Timing
8-21. Timing Diagram (Reset)
tPDN
tRPD
PDN
VIL 1
Figure 8. Power Down and Standby
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[AK4331]
8-22. Timing Diagram (Digital Microphone Interface)
tSCK
65%AVDD
50%AVDD
35%AVDD
DMCLK
tSCKL
tSFall
tSRise
tSCKL = tSCK x (1 – dSCK / 100)
50%AVDD
DMCLK
tDMS
tDMH
VIH2
DMDAT
Lch
@DCLKP bit = “0”
VIL2
tDMS
tDMH
VIH2
DMDAT
VIL2
Rch
@DCLKP bit = “0”
Figure 9. Digital Microphone Interface Timing
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[AK4331]
9. Functional Description
9-1. System Clock
The SRC, DAC, Headphone Amplifier and Audio Interface blocks are operated by a clock generated by
PLL, an external MCKI or a clock generated by X’tal oscillator. The sampling frequency and master clock
frequency are set by registers shown in Table 2.
Table 2. Setting Registers for Master Clock Frequency and Sampling Frequency
SRC Path Mode
System Clock
SRC Mode
SRC Bypass
Mode
FSI
FSO
HPMD[1:0] bits,
HPMD[1:0] bits,
Master Clock
CM[1:0] bits
CM[1:0] bits
CM2[1:0] bits
Frequency
(Table 7)
(Table 5)
(Table 9)
Sampling
FS[4:0] bits
FS[4:0] bits
FS2[4:0] bits
Frequency
(Table 6)
(Table 8)
(Table 10)
The AK4331 can be operated in both master and slave modes. Clock mode of the LRCK pin and the
BLCK pin can be selected by MS bit. When using master mode, the LRCK pin and the BCLK pin should
be pulled down or pulled up with an external resistor (about 100 kΩ) because both pins are floating state
until MS bit becomes “1”.
Table 3. Master / Slave Mode Select
MS bit
LRCK pin, BCLK pin
0
Slave Mode
1
Master Mode
(default)
Master / slave mode switching is not allowed while the AK4331 is in normal operation. The SRC, DAC and
headphone amplifier must be powered down and PMTIM bit must be “0” before master / slave mode is
switched. Furthermore, PLL and charge pump must also be powered down in case that sampling
frequency is changed or SRCMCLK / DACCLK is stopped.
1. SRC, DAC, Headphone Amplifier (PLL, Charge Pump) Power-Down
2. Clock Mode of ACPU Setting (In case clock mode of ACPU is master, switch to slave.)
3. MS bit Selection
4. Clock Mode of ACPU Setting (In case clock mode of ACPU is slave, switch to master.)
5. SRC, DAC, Headphone Amplifier (PLL, Charge Pump) Power-Up
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[AK4331]
32-bit
MIX
Audio
Interface
BCLK
DVOL
LRCK
SDTI
Digital
Filter
HP
(w/ Vol)
Stereo
DAC
SRC
HPL
HPGND
HPR
SDTO
SVOL
DMCLK
D-MIC
Interface
(0/-6/-12/-18/-24dB)
PLLO: PLS bit (MCKI/XTI pin or BCLK pin)
PLD[15:0], PLM[15:0], PLLMD, MDIV[3:0] bits
DMDAT
BCLK
IFCLK/
SRCMCLK
DACCLK
PLL
DACCLK: XCKSEL bit (PLLO or MCKI/XTI pin)
with X’tal: CM2[1:0], FS2[4:0] bits
XTO
MCKI/XTI
X’tal OSC
IFCLK/SRCMCLK: SRCCKS bit (PLLO or MCKI/XTI pin)
CM[1:0], FS[4:0] bits
Figure 10. Internal configure diagram of AK4331
Table 4. Setting of Clock Select (x: Do not Care, S: Slave, M: Master)
Mode
1
2
PMSRC /
MCKI LRCK
MS PMOSC PMPLL PLS
SRCCKS XCKSEL
PLL Clock
SRC
DAC
SELDAIN
M/S /XTI BCLK
bit
bit
bit
bit
bit
bit
Source
CLK
CLK
bits
pin
pins
0
0
0
x
0
1
1
S MCLK
In
(PLL Disable) (Bypass) MCKI
0
0
1
0
0
0
0
S MCLK
In
MCKI
(Bypass) PLLO
3
0
0
1
1
0
0
0
S
VSS3
In
BCLK
(Bypass) PLLO
4
0
0
1
1
1
0
0
S
VSS3
In
BCLK
PLLO
PLLO
5
0
1
1
1
1
0
1
S
X’tal
In
BCLK
PLLO
XTI
6
0
1
0
x
1
1
1
S
X’tal
In
(PLL Disable)
XTI
XTI
7
1
0
0
x
0
1
1
M
MCLK
Out
8
1
0
1
0
0
0
0
M
MCLK
Out
9
1
1
0
x
0
1
1
M
X’tal
Out
10
1
1
1
0
0
0
0
M
X’tal
Out
XTI
11
1
0
0
x
1
1
1
M
MCLK
Out
(PLL Disable)
MCKI
MCKI
12
1
0
1
0
1
0
0
M
MCLK
Out
MCKI
PLLO
PLLO
13
1
1
0
x
1
1
1
M
X’tal
Out
(PLL Disable)
XTI
XTI
14
1
1
1
0
1
0
0
M
X’tal
Out
XTI
PLLO
PLLO
(PLL Disable) (Bypass) MCKI
MCKI
(Bypass) PLLO
(PLL Disable) (Bypass)
XTI
(Bypass) PLLO
Note 107. Operation is only guaranteed with clock combinations in Table 4.
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[AK4331]
1. SRC Bypass Mode (SELDAIN bit = “0”)
DAC, Charge Pump, Headphone Amplifier: HPMD[1:0] bits, CM[1:0] bits, FS[4:0] bits
2. SRC Mode (SELDAIN bit = “1”)
SRC (FSI): CM[1:0] bits, FS[4:0] bits
SRC (FSO), DAC, Charge Pump, Headphone Amplifier: HPMD[1:0] bits, CM2[1:0] bits, FS2[4:0] bits
(DAC and Headphone Amplifier are operated by a X’tal)
32-bit
SDTI
MIX
Audio
Interface
BCLK
DVOL
LRCK
Digital
Filter
SRC
Stereo
DAC
HP
(w/ Vol)
HPL
HPGND
HPR
SDTO
DACCLK
SVOL
DMCLK
DMIC
Interface
DMDAT
BCLK
(0/-6/-12/-18/-24dB)
PLLO: PLS bit = “0” (MCKI/XTI pin)
PLD[15:0], PLM[15:0], PLLMD, MDIV[3:0] bits
IFCLK/
SRCMCLK
DACCLK
PLL
DACCLK: XCKSEL bit = “0” (PLLO)
CM[1:0], FS[4:0] bits
XTO
XTI/MCKI
X’tal OSC
IFCLK/SRCMCLK: SRCCKS bit = “0” (PLLO)
CM[1:0], FS[4:0] bits
Figure 11. Example of Clock and Data Flow (Mode 2)
32-bit
SDTI
MIX
Audio
Interface
BCLK
DVOL
LRCK
Digital
Filter
SRC
Stereo
DAC
HP
(w/ Vol)
HPL
HPGND
HPR
SDTO
DACCLK
SVOL
DMCLK
DMIC
Interface
DMDAT
BCLK
(0/-6/-12/-18/-24dB)
PLLO: PLS bit = “1” (BCLK pin)
PLD[15:0], PLM[15:0], PLLMD, MDIV[3:0] bits
IFCLK/
SRCMCLK
DACCLK
PLL
DACCLK: XCKSEL bit = “1” (MCKI/XTI pin)
CM2[1:0], FS2[4:0] bits
XTO
XTI/MCKI
X’tal OSC
IFCLK/SRCMCLK: SRCCKS bit = “0” (PLLO)
CM[1:0], FS[4:0] bits
Figure 12. Example of Clock and Data Flow (Mode 5)
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1. SRC Bypass Mode (SELDAIN bit = “0”)
DAC, Charge Pump, Headphone Amplifier: HPMD[1:0] bits, CM[1:0] bits, FS[4:0] bits
2. SRC Mode (SELDAIN bit = “1”)
SRC (FSI): CM[1:0] bits, FS[4:0] bits
SRC (FSO), DAC, Charge Pump, Headphone Amplifier: HPMD[1:0] bits, CM2[1:0] bits, FS2[4:0] bits
(DAC and Headphone Amplifier are operated by a X’tal)
32-bit
SDTI
MIX
Audio
Interface
BCLK
DVOL
LRCK
Digital
Filter
SRC
Stereo
DAC
HP
(w/ Vol)
HPL
HPGND
HPR
SDTO
DACCLK
SVOL
DMCLK
DMIC
Interface
DMDAT
BCLK
(0/-6/-12/-18/-24dB)
PLLO: PLS bit = “0” (MCKI/XTI pin)
PLD[15:0], PLM[15:0], PLLMD, MDIV[3:0] bits
IFCLK/
SRCMCLK
DACCLK
PLL
DACCLK: XCKSEL bit = “0” (PLLO)
CM[1:0], FS[4:0] bits
XTO
XTI/MCKI
X’tal OSC
IFCLK/SRCMCLK: SRCCKS bit = “0” (PLLO)
CM[1:0], FS[4:0] bits
Figure 13. Example of Clock and Data Flow (Mode 8)
32-bit
SDTI
MIX
Audio
Interface
BCLK
DVOL
LRCK
Digital
Filter
SRC
Stereo
DAC
HP
(w/ Vol)
HPL
HPGND
HPR
SDTO
DACCLK
SVOL
DMCLK
DMIC
Interface
DMDAT
BCLK
(0/-6/-12/-18/-24dB)
IFCLK/
SRCMCLK
DACCLK
PLL
DACCLK: XCKSEL bit = “1” (MCKI/XTI pin)
CM2[1:0], FS2[4:0] bits
XTO
XTI/MCKI
X’tal OSC
IFCLK/SRCMCLK: SRCCKS bit = “1” (MCKI/XTI pin)
CM[1:0], FS[4:0] bits
Figure 14. Example of Clock and Data Flow (Mode 11)
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[AK4331]
< Master Clock Frequency and Sampling Frequency Setting (SRC Bypass Mode) >
HPMD1
bit
0
1
0
0
1
Table 5. Setting of Master Clock Frequency (SRC Bypass Mode)
HPMD0
Master Clock
Sampling Frequency
CM1 bit CM0 bit
bit
Frequency
Range
0
0
0
256fs
8 to 48 kHz
(default)
1
0
0
256fs
64 to 96 kHz
0
0
1
512fs
8 to 48 kHz
0
1
0
1024fs
8 to 24 kHz
1
1
1
128fs
128 to 192 kHz
Table 6. Setting of Sampling Frequency (SRC Bypass Mode, N/A: Not available)
FS4 bit
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8 kHz
(default)
0
0
0
0
1
11.025 kHz
0
0
0
1
0
12 kHz
0
0
1
0
0
16 kHz
0
0
1
0
1
22.05 kHz
0
0
1
1
0
24 kHz
0
1
0
0
0
32 kHz
0
1
0
0
1
44.1 kHz
0
1
0
1
0
48 kHz
0
1
1
0
0
64 kHz
0
1
1
0
1
88.2 kHz
0
1
1
1
0
96 kHz
1
0
0
0
0
128 kHz
1
0
0
0
1
176.4 kHz
1
0
0
1
0
192 kHz
Others
N/A
* Depending on setting of PLL’s divider, the sampling frequency may differ.
Please set PLD[15:0] and PLM[15:0] bits precisely.
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< Master Clock Frequency and Sampling Frequency Setting (SRC Mode) >
Table 7. Setting of Master Clock Frequency (SRC Mode: FSI)
Master Clock
Sampling Frequency
CM1 bit CM0 bit
Frequency
Range
0
0
256fs
8 to 96 kHz
(default)
0
1
512fs
8 to 48 kHz
1
0
1024fs
8 to 24 kHz
1
1
128fs
128 to 192 kHz
Table 8. Setting of Sampling Frequency (SRC Mode, N/A: Not available)
FS4 bit
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8 kHz
(default)
0
0
0
0
1
11.025 kHz
0
0
0
1
0
12 kHz
0
0
1
0
0
16 kHz
0
0
1
0
1
22.05 kHz
0
0
1
1
0
24 kHz
0
1
0
0
0
32 kHz
0
1
0
0
1
44.1 kHz
0
1
0
1
0
48 kHz
0
1
1
0
0
64 kHz
0
1
1
0
1
88.2 kHz
0
1
1
1
0
96 kHz
1
0
0
0
0
128 kHz
1
0
0
0
1
176.4 kHz
1
0
0
1
0
192 kHz
Others
N/A
* Depending on setting of PLL’s divider, the sampling frequency may differ.
Please set PLD[15:0] and PLM[15:0] bits precisely.
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[AK4331]
HPMD1
bit
0
1
0
0
1
Table 9. Setting of Master Clock Frequency (SRC Mode: FSO)
HPMD0
CM21
CM20
Master Clock
Sampling Frequency
bit
bit
bit
Frequency
Range
0
0
0
256fs
8 to 48 kHz
(default)
1
0
0
256fs
64 to 96 kHz
0
0
1
512fs
8 to 48 kHz
0
1
0
1024fs
8 to 24 kHz
1
1
1
128fs
128 to 192 kHz
Table 10. Setting of Sampling Frequency (SRC Mode: FSO, N/A: Not available)
FS24 bit FS23 bit FS22 bit FS21 bit FS20 bit Sampling Frequency
0
0
0
0
0
8 kHz
(default)
0
0
0
0
1
11.025 kHz
0
0
0
1
0
12 kHz
0
0
1
0
0
16 kHz
0
0
1
0
1
22.05 kHz
0
0
1
1
0
24 kHz
0
1
0
0
0
32 kHz
0
1
0
0
1
44.1 kHz
0
1
0
1
0
48 kHz
0
1
1
0
0
64 kHz
0
1
1
0
1
88.2 kHz
0
1
1
1
0
96 kHz
1
0
0
0
0
128 kHz
1
0
0
0
1
176.4 kHz
1
0
0
1
0
192 kHz
Others
N/A
* Depending on setting of PLL’s divider, the sampling frequency may differ.
Please set PLD[15:0] and PLM[15:0] bits precisely.
9-2. Master Counter Synchronization Control
Internal master counter starts when setting PMTIM bit = “1”. Phase difference can be controlled within
4/64fs by asserting PMTIM bit when using multiple AK4331’s. In case of using PLL output (PLLO) as
system clock, set PMTIM bit to “1” in 2 msec or more after setting PMPLL bit to "1". In case of using
external clock as system clock, supply a stable clock and set PMTIM bit to "1". All power management bits
except for PMOSC and PMPLL bits (PMCP1, PMCP2, PMLDO1P, PMLDO1N, PMSRC, PMSM, PMDA,
PMHPL, PMHPR, PMDML and PMDMR bits) must be “0” when PMTIM bit = “0”.
Table 11. Master Counter Power Control
PMTIM bit
Master Counter Status
0
Disable
(default)
1
Enable
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9-3. PLL
The PLL generates a PLLO which can be used as operation clock for the Digital Interface (IFCLK), the
SRC (SRCMCLK) and the DAC (DACCLK). The oscillation frequency PLLCLK should be set in the range
from 22.5792 to 24.576 MHz (Table 12 shows setting of 48 kHz, 44.1 kHz and 32 kHz base rates). Refer
to Table 19 and Table 20 for PLL setting examples. Reference clock of PLL (REFCLK) should be set in
the range from 76.8 kHz to 768 kHz.
MCKI/XTI
BCLK
76.8 kHz to
768 kHz
PLL ANA
REFCLK
Feedback
1
------------(MDIV+1)
PLLO
1
------------(PLD+1)
PLLCLK
PLLCLK
Table 12. PLLCLK Setting
48 kHz base rate /
44.1 kHz base rate
32 kHz base rate
24.576 MHz
22.5792 MHz
PLS bit
1
------------(PLM+1)
REFCLK = PLL Source / (PLD+1)
PLLCLK = REFCLK × (PLM+1)
PLLO= PLLCLK / (MDIV+1)
Figure 15. PLL Block Diagram
9-3-1. Power Management (PMPLL)
PLL can be powered down by a control register setting.
Table 13. PLL Power Control
PMPLL bit
PLL Status
0
Power-Down
(default)
1
Power-Up
9-3-2. Input Clock Select Function
The PLL has a function that selects the input clock. The clock source pin is selected by PLS bit. PLS bit
must be set at PMTIM bit = “0”.
Table 14. PLL Clock Source Select
PLS bit
Clock Source
0
MCKI/XTI pin
(default)
1
BCLK pin
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9-3-3. PLL Reference Clock Divider
The PLL can set the dividing number of the reference clock in 16-bit. The input clock is used as PLL
reference clock by dividing by (PLD + 1). PLD[15:0] bits must be set at PMTIM bit = “0”.
Table 15. PLL Reference Clock Divider
PLD[15:0] bits
Dividing Number
0000H
1
(default)
0001H to FFFFH
1 / (PLD + 1)
Note 108. The reference clock divided by PLD should be set in the range from 76.8 kHz to 768 kHz.
9-3-4. PLL Feedback Clock Divider
The dividing number of feedback clock can be set freely in 16-bit. PLLCLK is divided by (PLM +1) and
used as PLL feedback clock. PLM[15:0] bits must be set at PMTIM bit = “0”.
Table 16. PLL Feedback Clock Divider
PLM[15:0] bits
Dividing Number
0000H
Clock Stop
(default)
0001H to FFFFH
1 / (PLM + 1)
9-3-5. PLL Internal Mode Setting
PLLMD bit controls PLL internal mode. Set PLLMD bit by referring to Table 19 and Table 20. PLLMD bit
must be set at PMPLL bit = “0”.
Table 17. PLL Internal Mode Setting
PLLMD bit
Reference Clock
0
≥ 256 kHz
(default)
1
< 256 kHz
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9-3-6. PLLCLK Divider Setting
MDIV[3:0] bits control PLLCLK divider.
MDIV[3:0] bits must be set at PMTIM bit = “0”.
Table 18. PLLCLK Divider Setting
MDIV[3:0] bits
Divide by
0H
1
(default)
1H to FH
1 / (MDIV + 1)
Note 109. When set each registers as following, divider value is set to 1.5 at MDIV[3:0] bits = 0H.
< SRC Bypass Mode (SELDAIN bit = “0”), SRCCKS bit = “0” and XCKSEL bit = “0” >
・CM[1:0] bits = “10”, FS[4:0] bits = “00100” (1024fs, fs = 16 kHz)
・CM[1:0] bits = “01”, FS[4:0] bits = “01000” (512fs, fs = 32 kHz)
・CM[1:0] bits = “00”, FS[4:0] bits = “01100” (256fs, fs = 64 kHz)
・CM[1:0] bits = “11”, FS[4:0] bits = “10000” (128fs, fs = 128 kHz)
< SRC Mode (SELDAIN bit = “1”) and SRCCKS bit = “0” >
・CM[1:0] bits = “10”, FS[4:0] bits = “00100” (1024fs, fs = 16 kHz)
・CM[1:0] bits = “01”, FS[4:0] bits = “01000” (512fs, fs = 32 kHz)
・CM[1:0] bits = “00”, FS[4:0] bits = “01100” (256fs, fs = 64 kHz)
・CM[1:0] bits = “11”, FS[4:0] bits = “10000” (128fs, fs = 128 kHz)
< SRC Mode (SELDAIN bit = “1”) and XCKSEL bit = “0” >
・CM2[1:0] bits = “10”, FS2[4:0] bits = “00100” (1024fs, fs = 16 kHz)
・CM2[1:0] bits = “01”, FS2[4:0] bits = “01000” (512fs, fs = 32 kHz)
・CM2[1:0] bits = “00”, FS2[4:0] bits = “01100” (256fs, fs = 64 kHz)
・CM2[1:0] bits = “11”, FS2[4:0] bits = “10000” (128fs, fs = 128 kHz)
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[AK4331]
9-3-7. PLL Setting Examples
Table 19. PLL Setting Example (PLL reference source: MCKI)
CLKIN
PLL Condition
Sampling
Source Frequency PLD+1 REFCLK PLM+1 PLLMD
PLLCLK
MDIV+1 Frequency
[Hz]
[Hz]
bit
[Hz]
(Note 110)
[Hz]
48,000
MCKI
9,600,000
25
384,000
64
0
24,576,000
0
32,000
48,000
19,200,000
25
768,000
32
0
24,576,000
0
32,000
48,000
12,288,000
16
768,000
32
0
24,576,000
0
32,000
48,000
24,576,000
32
768,000
32
0
24,576,000
0
32,000
48,000
12,000,000
125
96,000
256
1
24,576,000
0
32,000
48,000
24,000,000
125
192,000
128
1
24,576,000
0
32,000
9,600,000
125
76,800
294
1
22,579,200
0
44,100
19,200,000
125
153,600
147
1
22,579,200
0
44,100
11,289,600
16
705,600
32
0
22,579,200
0
44,100
22,579,200
32
705,600
32
0
22,579,200
0
44,100
Note 110. At the case of CM[1:0] bits and CM2[1:0] bits are set to “01” (512fs).
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Table 20. PLL Setting Example (PLL reference source: BCLK)
CLKIN
PLL Condition
Source Frequency PLD+1 REFCLK PLM+1 PLLMD
PLLCLK
MDIV+1
[Hz]
[Hz]
bit
[Hz]
(Note 110)
BCLK
256,000
1
256,000
96
0
24,576,000
5
(32fs)
352,800
1
352,800
64
0
22,579,200
3
512,000
1
512,000
48
0
24,576,000
2
705,600
1
705,600
32
0
22,579,200
1
768,000
1
768,000
32
0
24,576,000
1
1,024,000
2
512,000
48
0
24,576,000
0
1,411,200
2
705,600
32
0
22,579,200
0
1,536,000
2
768,000
32
0
24,576,000
0
BCLK
384,000
1
384,000
64
0
24,576,000
5
(48fs)
529,200
3
176,400
128
1
22,579,200
3
768,000
1
768,000
32
0
24,576,000
2
1,058,400
3
352,800
64
0
22,579,200
1
1,152,000
3
384,000
64
0
24,576,000
1
1,536,000
2
768,000
32
0
24,576,000
0
2,116,800
3
705,600
32
0
22,579,200
0
2,304,000
3
768,000
32
0
24,576,000
0
BCLK
512,000
1
512,000
48
0
24,576,000
5
(64fs)
705,600
1
705,600
32
0
22,579,200
3
1,024,000
2
512,000
48
0
24,576,000
2
1,411,200
2
705,600
32
0
22,579,200
1
1,536,000
2
768,000
32
0
24,576,000
1
2,048,000
4
512,000
48
0
24,576,000
0
2,822,400
4
705,600
32
0
22,579,200
0
3,072,000
4
768,000
32
0
24,576,000
0
018006903-E-00
Sampling
Frequency
[Hz]
8,000
11,025
16,000
22,050
24,000
32,000
44,100
48,000
8,000
11,025
16,000
22,050
24,000
32,000
44,100
48,000
8,000
11,025
16,000
22,050
24,000
32,000
44,100
48,000
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[AK4331]
9-4. Crystal Oscillator
The clock for the MCKI/XTI pin can be generated by two methods. PMOSC bit must be set to “1” when
using a crystal oscillator.
1) X’tal Mode (PMOSC bit = “1”)
MCKI/XTI
Cg
XTO
Cd
AK4331
Figure 16. X’tal Mode
Note 111. The capacitor value is dependent on the crystal oscillator.
Cd = Cg = 20.0 pF (Max.), Rl (Equivalent Series Resistance) = 80Ω (Max.) @ 24.576 MHz
Cd = Cg = 21.5 pF (Max.), Rl (Equivalent Series Resistance) = 60Ω (Max.) @ 19.2 MHz
Cd = Cg = 30.6 pF (Max.), Rl (Equivalent Series Resistance) = 200Ω (Max.) @ 11.2896 MHz
2) External Clock Mode (PMOSC bit = “0”)
MCKI/XTI
External Clock
XTO
AK4331
Figure 17. External Clock Mode
External
Note 112. Do not input
a clockClock
more than TVDD.
3) OFF Mode (Not Using the MCKI/XTI pin and the XTO pin (PMOSC bit = “0”))
MCKI/XTI
XTO
AK4331
Figure 18. OFF Mode
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[AK4331]
9-5. Digital Microphone
1. Connection to Digital Microphone
The same power supply as AVDD must be provided to the digital microphone. The Figure 19 and Figure
20 show mono/stereo connection examples. The AK4331 provides DMCLK to a digital microphone by
converting IFCLK to 64fs with a built-in decimation filter. Accordingly, the digital microphone generates
1-bit data by ΔΣ Modulators and transmits to the DMDAT pin of the AK4331. PMDML/R bits control
power-up/down of the digital block (Decimation Filter and HPF). The DCLKE bit controls ON/OFF of the
output clock from the DMCLK pin. When the AK4331 is powered up (PDN pin = “H”), external pull-down
resistor (R) should be connected to the DMDAT pin to avoid floating state.
Note that the digital microphone sampling frequency is 96 kHz at maximum and interface does
not support quad speed mode (fs ≥ 128 kHz).
AVDD
AK4331
PMDML/R bits
VDD
AMP
ΔΣ
Modulator
IFCLK
DMCLK (64fs)
Divider
100 kΩ
Decimation
Filter
SDTO Data
HPF
SVE bit
SVOL
DMDAT
Lch
R
VDD
AMP
ΔΣ
Modulator
Rch
Figure 19. Connection Example of Stereo Digital Microphone
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[AK4331]
AVDD
AK4331
PMDML/R bits
VDD
AMP
DMCLK (64fs)
IFCLK
Divider
100 kΩ
ΔΣ
Modulator
Decimation
Filter
SDTO Data
HPF
SVE bit
SVOL
DMDAT
R
Figure 20. Connection Example of Mono Digital Microphone
2. Interface
The input data channel of the DMDAT pin is set by DCLKP bit. When DCLKP bit = “1”, L channel data is
input to the Decimation Filter if DMCLK signal = “H”, R channel data is input if DMCLK signal = “L”. When
DCLKP bit = “0”, R channel data is input to the Decimation Filter if DMCLK signal = “H”, L channel data is
input if DMCLK signal = “L”. The DMCLK pin outputs “L” when DCLKE bit = “0”, and only supports 64fs.
The output data through “the Decimation and Digital Filters” is the negative full-scale with the 0% 1’s
density of 1-bit output data and positive full-scale with the 100% 1’s density of 1-bit output data. DCLKP
bit must be set at PMDML/R bits = “0”.
Table 21. Data Input/Output Timing with Digital Microphone
DCLKP bit
DMCLK pin = “H”
DMCLK pin = “L”
0
Rch
Lch
(default)
1
Lch
Rch
DMCLK (64fs)
DMDAT (Lch)
Valid
Data
Valid
Data
Valid
Data
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 21. Data Input/Output Timing with Digital Microphone (DCLKP bit = “0”)
DMCLK (64fs)
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 22. Data Input/Output Timing with Digital Microphone (DCLKP bit = “1”)
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[AK4331]
9-6. Digital Microphone HPF
A digital High Pass Filter (HPF) is integrated for DC offset cancellation of the digital microphone input.
The cut-off frequencies are set by HPFC[1:0] bits (Table 22). It is proportional to the sampling frequency
(fs) and default is 29.8 Hz (@fs = 48 kHz). HPFADN bit controls the ON/OFF of the HPF (Recommend
HPF enable). HPFC[1:0] bits must be set at PMDML/R bits = “0”.
Table 22. Digital Microphone HPF Cut-Off Frequency
Cut-Off Frequency
HPFC1 bit HPFC0 bit
fs = 8 kHz fs = 48 kHz fs = 96 kHz
0
0
4.97 Hz
29.8 Hz
59.9 Hz
(default)
0
1
2.49 Hz
14.9 Hz
29.8 Hz
1
0
19.9 Hz
119.4 Hz
238.7 Hz
1
1
39.8 Hz
238.7 Hz
477.5 Hz
9-7. Digital Microphone Mono/Stereo Mode
PMDML and PMDMR bits set On/Off and mono/stereo operation of the digital microphone.
PMDMR bit
0
0
1
1
Table 23. Digital Microphone Mono/Stereo Select
PMDML bit
SDTO Rch data
SDTO Lch data
0
All “0”
All “0”
1
DMIC Lch Input Signal
DMIC Lch Input Signal
0
DMIC Rch Input Signal
DMIC Rch Input Signal
1
DMIC Rch Input Signal
DMIC Lch Input Signal
(default)
9-8. Digital Microphone Initialization Cycle
Initialization cycle of the digital microphone starts by setting PMDML and PMDMR bits to “1” from “0”. The
initialization cycle is set by ADRST[1:0] bits (Table 24). The outputs data of the DMDAT pin will become a
data corresponds to analog input signal and settle after the initialization cycle is finished. ADRST[1:0] bits
must be set at PMDML/R bits = “0”.
Note 113. The initial data of the digital microphone has an offset that depends on the usage environment
such as microphone, and the cut-off frequency of HPF. Set the initialization cycle longer or
discard the initial data of the digital microphone if this offset causes a problem.
ADRST1 bit
0
0
1
1
Table 24. Digital Microphone Initialization Cycle
Digital MIC Initialization Cycle
ADRST0 bit
Cycle
fs = 8 kHz
fs = 48 kHz fs = 96 kHz
0
1059/fs
132.4 msec
22 msec
11 msec
1
267/fs
33.4 msec
5.6 msec
2.8 msec
0
2115/fs
264.4 msec 44.1 msec
22 msec
1
531/fs
66.4 msec
11.1 msec
5.5 msec
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[AK4331]
9-9. Side Tone Digital Volume (SVOL)
The AK4331 has a side tone volume control (5 levels, 6 dB step, L/R channels common). The volume can
be set by SV[2:0] bits and the attenuation range of the output data is from 0 to 24 dB. The volume is
changed immediately by setting these bits. SVE bit can control whether adding a signal of the side tone
block or not. SV[2:0] bits and SVE bit must be set when PMDML/R bits = “0”.
Table 25. Side Tone Control
SVE bit
Side Tone Addition
0
Disable
(default)
1
Enable
Table 26. Side Tone Volume Setting (N/A: Not available)
SV[2:0] bits
Gain
000
0 dB
(default)
001
6 dB
010
12 dB
011
18 dB
100
24 dB
Others
N/A
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[AK4331]
9-10. DAC Digital Filter
DAC has four types of digital filter. The filter mode of DAC can be selected by DASD and DASL bits. The
default setting is DASL = DASD bits = “0” (Sharp Roll-Off Filter). DASD bit and DASL bit must be set at
PMSRC bit = “0” and PMDA bit = “0”. And DADFSEL bit coordinate digital filter. In case of SRC Bypass
Mode, DADFSEL bit must be set to “0” . In case of SRC Mode, DADFSEL bit must be set to “1”.
Table 27. DAC Digital Filter Setting (SRC Bypass Mode)
DADFSEL bit
DASD bit
DASL bit
DAC Filter Mode Setting
0
0
0
Sharp Roll-Off Filter
0
0
1
Slow Roll-Off Filter
0
1
0
Short Delay Sharp Roll-Off Filter
0
1
1
Short Delay Slow Roll-Off Filter
DADFSEL bit
1
1
1
1
(default)
Table 28. DAC Digital Filter Setting (SRC Mode)
DASD bit
DASL bit
DAC Filter Mode Setting
0
0
Sharp Roll-Off Filter
0
1
Slow Roll-Off Filter
1
0
Short Delay Sharp Roll-Off Filter
1
1
Short Delay Slow Roll-Off Filter
9-11. Digital Mixing
The AK4331 has digital mixing circuits for each L channel and R channel. They can mix the data digitally
and convert the polarity. The inverted data by this polarity conversion is calculated in 2’s complement
format. MDACL/R bits, RDACL/R bits, LDACL/R bits and INVL/R bits must be set at PMSRC bits = “0”
and PMDA bit = “0”.
MDACL bit
MDACR bit
0
0
0
0
1
1
1
1
Table 29. DAC L/R Channel Input Signal Select
RDACL bit
LDACL bit
DAC Lch Input Data
RDACR bit
LDACR bit
DAC Rch Input Data
0
0
MUTE
0
1
Lch
1
0
Rch
1
1
Lch + Rch
0
0
MUTE
0
1
Lch / 2
1
0
Rch / 2
1
1
(Lch + Rch) / 2
(default)
Table 30. DAC L/R Channel Input Signal Polarity Select
INVL bit
Output Data
INVR bit
0
Normal
(default)
1
Inverting
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[AK4331]
9-12. Digital Volume
The AK4331 has a 32-level digital volume in front of DAC for each L and R channel. The volume is
changed from +3 dB to 12 dB in 0.5 dB step including Mute. The volume change is executed
immediately by setting registers.
When OVOLCN bit is “1”, the OVL[4:0] bits control L channel level and OVR[4:0] bits control R channel
level. When OVOLCN bit = “0”, the OVL[4:0] bits control both L channel and R channel attenuation levels.
In this case, the setting of OVR[4:0] bits is ignored. OVL/R[4:0] bits must be set at PMSRC bits = “0” and
PMDA bit = “0”.
Table 31. Digital Volume Setting
OVL[4:0] bits
Volume (dB)
OVR[4:0] bits
1FH
+3.0
1EH
+2.5
1DH
+2.0
1CH
+1.5
1BH
+1.0
1AH
+0.5
19H
0.0
(default)
18H
0.5
17H
1.0
16H
1.5
15H
2.0
14H
2.5
13H
3.0
12H
3.5
11H
4.0
10H
4.5
0FH
5.0
0EH
5.5
0DH
6.0
0CH
6.5
0BH
7.0
0AH
7.5
09H
8.0
08H
8.5
07H
9.0
06H
9.5
05H
10.0
04H
10.5
03H
11.0
02H
11.5
01H
12.0
00H
MUTE
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[AK4331]
9-13. Headphone Amplifier Output (HPL/HPR pins)
Headphone amplifiers are operated by positive and negative power that is supplied from internal charge
pump circuit. The VEE2 pin output the negative voltage generated by the internal charge pump circuit
from CVDD. This charge pump circuit is switched between VDD mode and 1/2VDD mode by the output
level of the headphone amplifiers. The headphone amplifier output is single-ended and centered on
HPGND (0 V). Therefore, a capacitor for AC-coupling is not necessary. The minimum load resistance is
7.2Ω. The output power is 10 mW (@ 0 dBFS, RL = 32Ω, AVDD = CVDD = 1.8 V and HPG = 4 dB) and
25 mW (@ 0 dBFS, RL = 32Ω, AVDD = CVDD = 1.8 V and HPG = 0 dB). Ground loop noise cancelling
function for headphone amplifier is available by connecting the HPGND pin to the ground of the jack.
PMDA bit
PMHPL bit
MDACL bit,
LDACL bit,
RDACL bit
SDTI
Lch Data
MIX
Digital
Filter
Volume
Invert
MDACR bit,
LDACR bit,
RDACR bit
SDTI
Rch Data
OVL[4:0] bits
INVL bit
MIX
PMSM bit
SELSM bit
SMUTE
HPG[2:0] bits
DAC
Lch
HPL pin
HPGND pin
PMSM bit
SELSM bit
OVR[4:0] bits
INVR bit
Invert
Volume
Digital
Filter
SMUTE
DAC
Rch
HPR pin
HPG[2:0] bits
PMHPR bit
Figure 23. DAC & Headphone Amplifier Block Diagram (SRC Bypass Mode)
PMDA bit
MDACL bit,
LDACL bit,
RDACL bit
SDTI
Lch Data
MIX
MDACR bit,
LDACR bit,
RDACR bit
SDTI
Rch Data
MIX
PMHPL bit
INVL bit
Invert
OVL[4:0] bits
Volume
Digital
Filter
PMSRC bit
PMSM bit
SELSM bit
SRC
SMUTE
PMSRC bit
PMSM bit
SELSM bit
SRC
SMUTE
DAC
Lch
HPG[2:0] bits
HPL pin
HPGND pin
INVR bit
Invert
OVR[4:0] bits
Volume
Digital
Filter
DAC
Rch
HPR pin
HPG[2:0] bits
PMHPR bit
Figure 24. DAC & Headphone Amplifier Block Diagram (SRC Mode)
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[AK4331]
CPMODE1 bit
0
0
1
1
Table 32. Charge Pump Mode Setting (N/A: Not available)
CPMODE0 bit
Mode
Operation Voltage
0
Class-G Operation Mode
Automatic Switching
1
VDD Operation Mode
±VDD
0
1/2VDD Operation Mode
±1/2VDD
1
N/A
N/A
(default)
< Class-G Mode Switching Level >
A switching threshold level of VDD and 1/2VDD modes can be set by LVDSEL[1:0] bits. LVDSEL[1:0] bits
should be set before PMHPL bit or PMHPR bit is set to “1”.
LVDSEL bits = “00” (default: Assuming connecting a 16Ω headphone)
VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 16Ω)
1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 16Ω)
LVDSEL bits = “01” (Assuming connecting a 32Ω headphone or more)
VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 32Ω)
1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 32Ω)
LVDSEL bits = “10” (Assuming connecting a 11Ω headphone)
VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 11Ω)
1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 11Ω)
LVDSEL bits = “11” (Assuming connecting a 8Ω headphone)
VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 8Ω)
1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 8Ω)
When the charge pump operation mode is changed to VDD mode from 1/2VDD mode, an internal counter
for holding VDD mode starts (Table 33). The charge pump changes to 1/2VDD mode if the output signal
level is lower than the switching level and 1/2VDD mode detection time that is set by LVDTM[2:0] bits is
passed after VDD mode hold time is finished.
Table 33. VDD Mode Holding Period Setting (x: Do not Care)
VDD Mode Holding Period
VDDTM[3:0]
bits
8 kHz
48 kHz
96 kHz
192 kHz
0000
1024/fs
128 msec
21.3 msec
10.7 msec
5.3 msec
0001
2048/fs
256 msec
42.7 msec
21.3 msec
10.7 msec
0010
4096/fs
512 msec
85.3 msec
42.7 msec
21.3 msec
0011
8192/fs
1024 msec
170.7 msec
85.3 msec
42.7 msec
0100
16384/fs
2048 msec
341.3 msec
170.7 msec
85.3 msec
0101
32768/fs
4096 msec
682.7 msec
341.3 msec
170.7 msec
0110
65536/fs
8192 msec 1365.3 msec 682.7 msec
341.3 msec
0111
131072/fs 16384 msec 2730.7 msec 1365.3 msec 682.7 msec
1xxx
262144/fs 32768 msec 5461.3 msec 2730.7 msec 1365.3 msec
(default)
When the output voltage becomes less than class-G mode switching level, the internal detection counter
for 1/2VDD mode which is set by LVDTM[2:0] bits starts. This counter is reset when the output voltage
exceeds class-G mode switching level. The charge pump operation mode is changed to 1/2VDD from
VDD if the detection counter of 1/2VDD mode is finished and also the VDD mode hold period is passed.
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[AK4331]
Under 1/2VDD Level
Class-G Mode Switching Level
Class-G Mode Switching Level
Detection Time (LVTDM[2:0]bits)
1) Detection Time < 1/2VDD Level
Class-G Mode
VDD
1/2VDD
VDD (Start)
2) Detection Time > 1/2VDD Level
VDD
Class-G Mode
Figure 25. Transition to 1/2VDD Mode from VDD Mode
Table 34. 1/2VDD Detection Period (Minimum frequency that is not detected)
1/2VDD Mode Detection Time /
LVDTM[2:0]
Minimum Frequency that is Not Detected
bits
8 kHz
48 kHz
96 kHz
192 kHz
8 msec
1.3 msec
0.67 msec 0.33 msec
000
64/fs
(default)
62.5 Hz
375 Hz
750 Hz
1500 Hz
16 msec
2.7 msec
1.3 msec
0.67 msec
001
128/fs
31.3 Hz
187.5 Hz
375 Hz
750 Hz
32 msec
5.3 msec
2.7 msec
1.3 msec
010
256/fs
15.6 Hz
93.8 Hz
187.5 Hz
375 Hz
64 msec
10.7 msec
5.3 msec
2.7 msec
011
512/fs
7.8 Hz
46.9 Hz
93.8 Hz
187.5 Hz
128 msec
21.3 msec 10.7 msec
5.3 msec
100
1024/fs
3.9 Hz
23.4 Hz
46.9 Hz
93.8 Hz
256 msec
42.7 msec 21.3 msec 10.7 msec
101
2048/fs
2.0 Hz
11.7 Hz
23.4 Hz
46.9 Hz
512 msec
85.3 msec 42.7 msec 21.3 msec
110
4096/fs
1.0 Hz
5.9 Hz
11.7 Hz
23.4 Hz
1024 msec 170.7 msec 85.3 msec 42.7 msec
111
8192/fs
0.5 Hz
2.8 Hz
5.9 Hz
11.7 Hz
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[AK4331]
< Headphone Amplifier Volume Circuit >
The output level of the headphone amplifier can be controlled by HPG[2:0] bits. The volume setting is
common for both L and R channels and ranges from +4 dB to 10 dB in 2 dB step (Table 35). When the
volume is changed, zero cross detection is executed independently for L and R channels. Zero cross
timeout period is set by HPTM[2:0] bits (Table 36).
The headphone amplifier volume should be changed with an interval of zero cross timeout period after
setting HPG[2:0] bits once. If the volume is changed continuously without the interval, the gain setting at
the next zero crossing point will be applied.
Table 35. Headphone Amplifier Volume Setting
HPG[2:0] bits
Volume (dB)
111
+4
110
+2
101
0
(default)
100
2
011
4
010
6
001
8
000
10
Table 36. Headphone Volume Zero Cross Timeout Setting (x: Do not care)
Zero Crossing Timeout Period
HPTM[2:0]
bits
8 kHz
48 kHz
96 kHz
192 kHz
000
128/fs
16 msec
2.7 msec
1.3 msec
0.67 msec
001
256/fs
32 msec
5.3 msec
2.7 msec
1.3 msec
010
512/fs
64 msec
10.7 msec
5.3 msec
2.7 msec
011
1024/fs
128 msec
21.4 msec
10.7 msec
5.3 msec
(default)
1xx
2048/fs
256 msec
42.7 msec
21.4 msec
10.7 msec
< Headphone Amplifier External Circuit >
It is necessary to put an oscillation prevention circuit (0.1 µF ±20% capacitor and 15Ω ±20% resistor)
because there is a possibility that the headphone amplifier oscillates.
Headphone Amplifier
Headphone
AK4331
0.1 μF
32Ω
15Ω
Figure 26. Example of Headphone Amplifier Oscillation Prevention Circuit
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[AK4331]
< Power-Up/Down Sequence of Headphone Amplifier >
After releasing DAC power-down state by PMDA bit, the headphone amplifier should be powered up by
PMHPL/R bits. A wait time from DAC power-up to headphone power-up is not necessary.
PMDA bit releases a power-down of the digital block of DAC, PMHPL or PMHPR bit powers up the analog
block of the DAC and the headphone amplifier. Then, initialization cycle of the headphone amplifier is
executed. The gain setting (HPG[2:0] bits) should be made before PMHPL bit or PMHPR bit is set to “1”.
Do not change the gain setting (HPG[2:0] bits) during the headphone initialization cycle. The gain setting
can be changed after the headphone initialization cycle is finished. A wait time from the gain setting to
PMHPL bit or PMHPR bit = “1” is not necessary.
When the AK4331 is powered down, the headphone amplifier should be powered down first. The DAC
should be powered down next. A wait time from a headphone power-down to a DAC power-down is not
necessary.
When the headphone amplifier is powered down, the HPL pin and the HPR pin are pulled down to
HPGND via the internal pull-down register. The pulled-down resistor is 4Ω (Typ.) @ HPLHZ = HPRHZ bits
= “0”. The HPL pin and the HPR pin are also pulled down to HPGND via 95 kΩ (Typ.) if HPLHZ bit and
HPRHZ bit are set to “1”.
Table 37. Headphone Output Status (x: Do not Care)
PMHPL bit HPLHZ bit
Headphone Amplifier Status
PMHPR bit HPRHZ bit
0
0
Pull-down by 4Ω (Typ.)
0
1
Pull-down by 95 kΩ (Typ.)
1
x
Normal Operation
When the HPL pin and the HPR pin are connected to analog signal pins of an external device by
Wire-OR, CP1, CP2, LDO1P and LDO1N should be powered up. Do not input a negative voltage to the
HPL pin and the HPR pin when CP1, CP2, LDO1P and LDO1N are powered down.
To avoid pop noise, HPG[2:0] bits setting should be same at power-up and power-down of headphone.
The power-up time of headphone amplifier is shown in Table 38. The HPL and HPR pins output 0 V
(HPGND) when the headphone amplifier is powered up. The power-down is executed immediately.
Table 38. Headphone Power-Up Time
Sampling Frequency [kHz]
Power-Up Time (Max)
8/12/16/24/32/48/64/96/128/192
23.9 msec
11.025/22.05/44.1/88.2/176.4
25.9 msec
< Over Current Protection Circuit >
If the headphone amplifier is in an overcurrent state, such as when output pins are shorted, the
headphone amplifier limits the operation current. The headphone amplifier returns to a normal operation
state if all causes are cleared.
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9-14. Charge Pump & LDO Circuits
The charge pump circuits are operated by CVDD power supply voltage. CVDD is used to generate
positive and negative voltage. The power-up/down sequence of charge pump and LDO circuits are as
follows. CP1 should be powered up before LDO1P/N are powered up. CP2 should be powered up after
LDO1P/N are powered up.
Power-Up Sequence: CP1 → LDO1P, LDO1N → CP2
Power-Down Sequence: CP2 → LDO1P, LDO1N → CP1
LDO1P and LDO1N have an overcurrent protection circuit. When overcurrent flows in a normal operation,
the LDO1P and LDO1N circuits limit the operation current. If the overcurrent state is cleared, the
overcurrent protection will be off and the LDO1P and LDO1N circuits will return to normal operation.
LDO2 has an overvoltage protection circuit. This overvoltage protection circuit powers the LDO2 down
when the power supply becomes unstable by an instantaneous power failure, etc. during operation. The
LDO2 circuit will not return to a normal operation until being reset by the PDN pin (“L” → “H”) after
removing the problems.
The charge pump and the LDO1 circuits, except for the LDO2, can be powered up again while they are in
power-down state.
Table 39. Input/Output Voltage and Operation Block of the Charge Pump
Charge Pump Power Management bit Input Voltage Output Voltage (Typ.) Operation Block
CP1
PMCP1
CVDD
LDO1N, DAC
1.8 V
CP2 (Class-G)
PMCP2
CVDD
±1.8 V / ±0.9 V
Headphone
LDO
LDO1P
LDO1N
LDO2
Table 40. Input/Output Voltage and Operation Block of the LDO
Power
Output Voltage
Power Supply
Operation Block
Management bit
(Typ.)
PMLDO1P
AVDD / VSS1
+1.5 V
VREF+ for DAC, Headphone
VSS1
PMLDO1N
1.5 V
VREF for DAC, Headphone
/ CP1 Output
LVDD / VSS3
+1.2 V
Digital Core
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[AK4331]
9-15. Asynchronous Sampling Rate Converter (SRC)
The AK4331 has a stereo asynchronous SRC before the DAC block. The SRC supports an 8 kHz to 192
kHz audio source (FSI) and an 8 kHz to 192 kHz sampling rate output (FSO). Available sample rate ratio
(FSO/FSI) is 0.98 to 6.02. PMSRC bit controls power up/down of the SRC.
Examples of supported sampling rate are shown below.
Table 41. Up-Sampling Examples
FSO
FSI
FSO/FSI
192 kHz
48 kHz
4.00
96 kHz
48 kHz
2.00
48 kHz
48 kHz
1.00
48 kHz
44.1 kHz
1.09
48 kHz
32 kHz
1.50
48 kHz
24 kHz
2.00
48 kHz
16 kHz
3.00
48 kHz
12 kHz
4.00
48 kHz
8 kHz
6.00
192 kHz
44.1 kHz
4.35
44.1 kHz
44.1 kHz
1.00
44.1 kHz
32 kHz
1.38
44.1 kHz
24 kHz
1.84
44.1 kHz
16 kHz
2.76
44.1 kHz
12 kHz
3.68
44.1 kHz
8 kHz
5.51
16 kHz
16 kHz
1.00
16 kHz
8 kHz
2.00
8 kHz
8 kHz
1.00
SRC input clock (SRCMCLK) is 128fs, 256fs, 512fs or 1024fs. SRCCKS bit selects SRC clock source
between the MCKI/XTI pin and PLLO, and XCKSEL bit selects output clock for SRC (DACCLK) between
the MCKI/XTI pin and PLLO. The SRC can be bypassed by setting SELDAIN bit = “0”.
Table 42. SRC Power Management
PMSRC bit
SRC Status
0
Power-Down (default)
1
Power-Up
Table 43. DAC and Charge Pump Clock Mode Setting
XCKSEL bit
DAC and Charge Pump Clock Mode
0
PLLO
(default)
1
MCKI/XTI pin
Table 44. SRC Clock Mode Setting
SRCCKS bit
SRC Clock Mode
0
PLLO
1
MCKI/XTI pin
(default)
Note 114. SRCCKS bit and XCKSEL bit must be same value at SRC Bypass Mode (SELDAIN bit = “0”).
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[AK4331]
< Jitter Cleaner Function >
The sound quality and characteristics may degrade if a clock with large jitter is input to the DAC from the
host processor. The AK4331 maximizes DAC performance and the sound quality by the internal SRC with
an external low jitter crystal oscillator. When the AK4331 is operated by a clock from the external crystal
oscillator, the master clock is set by CM2[1:0] bits and the sampling frequency is set by FS2[4:0] bits.
9-16. SRC Selector Function
The DAC input data can be selected between the input data of the SDTI pin and the SRC output data by
SELDAIN bit. SELDAIN bit must be set at PMSRC bit = “0”.
SDTI Data
SRC
SELDAIN
DAC
Figure 27. Input Selector for DAC
Table 45. DAC Data Path Setting
SELDAIN bit
DAC
0
SRC Bypass Mode
(default)
1
SRC Mode
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9-17. SRC Clock Change Sequence
When changing the system clock of SRC, the SRC should be reset by setting PMSRC bit to “0”. The SRC
output is “0” while PMSRC bit = “0”. A data output becomes available within 20 msec from setting PMSRC
bit to “1” (up to 156/fso, when the input clock is stabilized) after changing the system clock. Until then the
SRC outputs “0”. Set PMTIM bit to “1” and SRC settings should be finished before setting PMSRC bit to
“1”.
Input Clock
Do not care
Input Clocks 1
Input Clocks 2
Do not care
Input Data
Do not care
Input Data 1
Input Data 2
Do not care
Output Clock
Do not care
Output Clocks 1
Output Clocks 2
Do not care
PMPLL bit
≥ 2 msec
≥ 2 msec
PMTIM bit
PMSRC bit
≤ 20 msec
SRC Output Data
“0” data
Normal data
≤ 20 msec
“0” data
Normal data
“0” data
Figure 28. Sequence of Changing SRC System Clock
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9-18. Soft Mute
AK4331 has a soft mute operation block. PMSM bit and SELSM bit must be set to “1” when using a soft
mute block.
Table 46. Soft Mute Block Power Management (N/A: Not available)
PMSM bit
SELSM bit
Soft Mute Block
0
0
Power-Down
(default)
1
1
Power-Up
Others
N/A
1. Manual Mode
When SMUTE bit is changed to “1”, the output signal is attenuated to ∞ (“0”) in 1024/FSO cycle
(SMT[1:0] bits = “00”). When the SMUTE bit is returned to “0”, the mute is cancelled and the output
attenuation gradually changes to 0 dB in 1024/FSO cycle. If the soft mute is cancelled within 1024/FSO,
the attenuation is discontinued and the attenuation level returns to 0 dB by the same cycle. The soft mute
is effective for changing the signal source without stopping the signal transmission.
SMUTE bit
0 dB
Attenuation Level
dB
(3)
(1)
(2)
Figure 29. Soft Mute Manual Mode
(1) SMUTE bit = “0” → “1”: The output signal is attenuated to ∞ (“0”) in 1024/FSO cycle (SMT[1:0] bits
= “00”)
(2) SMUTE bit = “1” → “0”: The attenuation level of the output signal returns to 0 dB from ∞ (“0”) in
1024/FSO cycle (SMT[1:0] bits = “00”)
(3) If the soft mute is cancelled within 1024/FSO, the attenuation is discontinued and the attenuation
level returns to 0 dB by the same cycle.
SMT1 bit
0
0
1
1
SMT0 bit
0
1
0
1
Table 47. Soft Mute Cycle Setting
Period
FSO = 48 kHz
FSO = 96 kHz
1024/FSO
21.3 msec
10.7 msec
2048/FSO
42.7 msec
21.3 msec
4096/FSO
85.3 msec
42.7 msec
8192/FSO
170.7 msec
85.3 msec
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FSO = 192 kHz
5.3 msec
(default)
10.7 msec
21.3 msec
42.7 msec
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[AK4331]
2. Semi-Auto Mode
The AK4331 enters Semi-Auto mode by setting SAUTO bit to “1”. In this mode, the soft mute is cancelled
automatically in 160/fso after setting PMSM bit and SELSM bit to “1” and the AK4331 will be able to output
the data. When power-down state is released (PMSM bit = SELSM bit = “0” → “1”), the soft mute function
is ON if the SMUTE bit is “1”.
PMSM bit
SELSM bit
“1”
“0”
SMUTE bit
Do not Care
“0”
(1)
0 dB
Attenuation
dB
160/fso
DAC Input Data
Figure 30. Soft Mute Semi-Auto Mode (SRC Bypass Mode)
PMSRC bit
“1”
“0”
PMSM bit
SELSM bit
“1”
“0”
SMUTE bit
Do not Care
“0”
(1)
0 dB
Attenuation
dB
160/fso
DAC Input Data
Figure 31. Soft Mute Semi-Auto Mode (SRC Mode)
(1) The attenuation level is returns to 0 dB in 1024/fso cycle (SMT[1:0] bits = “00”).
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9-19. Serial Audio Interface
The serial audio interface format is set by DIF bit and its data length is controlled by DL[1:0] bits. In case
that the input data length is less than the value which set by DL[1:0] bits, unused lower bits are filled with
“0”. When using master mode, DL[1:0] bits is set in accordance with the setting of BCKO bit. DIF bit and
DL[1:0] bits must be set at PMTIM bit = “0”.
Table 48. Digital Audio Interface Format Setting
DIF bit
Digital Interface Format
0
I2S Compatible
(default)
1
MSB justified
Table 49. Data Length Setting (x: Do not Care, N/A: Not available)
BCLK Frequency
DL1 bit DL0 bit Data Length
Slave Mode
Master Mode
0
0
24-bit linear
≥ 48fs
N/A
(default)
32fs
0
1
16-bit linear
≥ 32fs
(BCKO bit = “1”)
64fs
1
x
32-bit linear
≥ 64fs
(BCKO bit = “0”)
LRCK
BCLK
SDTI
“H” or “L” Lch Data (MSB First)
SDTO
Lch Data (MSB First)
“H” or “L” Rch Data (MSB First) “H” or “L” Next Lch Data
Rch Data (MSB First)
Next Lch Data
Figure 32. I2S Compatible Format (DIF bit = “0”)
LRCK
BCLK
SDTI
“H” or “L” Lch Data (MSB First)
SDTO
Lch Data (MSB First)
“H” or “L” Rch Data (MSB First) “H” or “L” Next Lch Data
Rch Data (MSB First)
Next Lch Data
Figure 33. MSB justified format (DIF bit= “1”)
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[AK4331]
9-20. Serial Control Interface (I2C-bus)
The AK4331 supports the fast-mode I2C-bus (Max: 400 kHz). Pull-up resistors at the SDA and SCL pins
must be connected to (TVDD + 0.3) V or less voltage.
1. WRITE Operation
Figure 34 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 40). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant seven bits of the slave
address are fixed as “0010000”. If the slave address matches that of the AK4331, the AK4331 generates
an acknowledge and the operation is executed. The master must generate the acknowledge-related clock
pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 41). A R/W bit value
of “1” indicates that the read operation is to be executed, and “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4331. The format is MSB first 8 bits
(Figure 36). The data after the second byte contains control data. The format is MSB first, 8 bits (Figure
37). The AK4331 generates an acknowledge after each byte is received. Data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line
while SCL is HIGH defines a STOP condition (Figure 40).
The AK4331 can perform more than one byte write operation per sequence at address from 00H to 17H.
After receipt of the third byte the AK4331 generates an acknowledge and awaits the next data. The
master can transmit more than one byte instead of terminating the write cycle after the first data byte is
transferred. After receiving each data packet the internal address counter is incremented by one, and the
next data is automatically taken into the next address. If the address exceeds 17H prior to generating a
stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (Figure 42) except for the
START and STOP conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W = "0"
Slave
S Address
Sub
Address(n)
A
C
K
Data(n)
A
C
K
Data(n+ 1)
A
C
K
Data(n+ x)
A
C
K
A
C
K
P
A
C
K
Figure 34. Data Transfer Sequence in I2C-bus Mode
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[AK4331]
0
0
1
0
0
0
0
R/W
A2
A1
A0
D1
D0
Figure 35. The First Byte
A7
A6
A5
A4
A3
Figure 36. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 37. The Third Byte
2. READ Operation
Set the R/W bit = “1” for the READ operation of the AK4331. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 17H prior to generating stop condition, the address counter will “roll over” to 00H and the data of
00H will be read out.
The AK4331 supports two basic read operations: Current Address READ and Random Address READ.
2-1. Current Address READ
The AK4331 has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
Current READ operation would access data from the address “n+1”. After receipt of the slave address
with R/W bit “1”, the AK4331 generates an acknowledge, transmits 1-byte of data to the address set by
the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates a stop condition instead, the AK4331 ceases the transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
MA
AC
SK
T
E
R
Data(n+2)
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 38. Current Address READ
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[AK4331]
2-2. Random Address READ
The random read operation allows the master to access any memory location at random. Prior to issuing
the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit “1”. The AK4331 then generates an acknowledge, 1 byte of data and increments
the internal address counter by 1. If the master does not generate an acknowledge but generates a stop
condition instead, the AK4331 ceases the transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
Slave
S Address
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 39. Random Address READ
SDA
SCL
S
P
start condition
stop condition
Figure 40. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 41. Acknowledge (I2C-bus)
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[AK4331]
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 42. Bit Transfer (I2C-bus)
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[AK4331]
9-21. Control Sequence
Figure 43 shows power-up sequence of DAC and headphone amplifier.
Power Supply
(2)
MCKI, BCLK, LRCK
(1) ≥ 1 msec
PDN pin
(3) ≥ 2 msec
Analog Circuit Power
DAC Initial Setting
FS[4:0] bits
(Addr:05H, D4 - D0)
(3) ≥ 1 msec
Addr.26H = 6CH
Addr.27H = 40H
"00000"
LDACL bit
RDACR bit
(Addr:07H, D5, D0)
HPG[2:0] bits
(Addr.26H) = 02H
(Addr.27H) = C0H
(4)
(5)
"01010"
(5)
"101"
(6)
"011"
(Addr:0DH, D2-D0)
PMPLL bit
(Addr:00H, D0)
PMTIM bit
(7)
≥ 2 msec
(8)
(Addr:00H, D1)
PMCP1 bit
(Addr:01H, D0)
(9)
≥ 6.5 msec
PMLDO1P bit
PMLDO1N bit
(Addr:01H, D5, D4)
(10)
≥ 0.5 msec
(11)
PMDA bit
(Addr:02H, D0)
PMCP2 bit
(12)
(Addr:01H, D1)
≥ 4.5 msec
PMHPL bit
PMHPR bit
(Addr:03H, D1, D0)
(13)
23.9 msec
HPL pin
HPR pin
Normal Operation
Figure 43. Power-Up Sequence Example of DAC and Headphone Amplifier
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< Power-Up Sequence Example >
(1) Set the PDN pin from “L” to “H” after turning on all power supplies. In this case, 1 msec or more “L”
time is needed for a certain reset.
(2) After all power supplies are On, MCKI, BCLK and LRCK should be input before powering up PLL or
CP1.
(3) Set the PDN pin = “H” to release the power-down. Register access will be valid in 1 msec at
maximum. However, a wait time of 2 msec is needed to access PMTIM bit and power management
bits of the analog circuit (PMCP1 bit, PMCP2 bit, PMLDO1P bit, PMLDO1N bit, PMDA bit, PMHPL
bit, PMHPR bit and PMPLL bit) until the analog circuit is powered up.
(4) Set DAC initial settings. (Write 02H data into Address 26H and write C0H data into Address 27H)
(5) Set sampling frequency (FS[4:0] bits) and the input signal path of the DAC.
(LDACL bit = RDACR bit = “0” → “1”)
(6) Set headphone amplifier volume by HPG[2:0] bits.
(7) In case of using PLL, power-up PLL (PMPLL bit = “0” → “1”) and wait 2 msec for PLL output
stabilization.
(8) Start internal master counter. (PMTIM bit = “0” → “1”)
PMCP1 bit, PMCP2 bit, PMLDO1P bit, PMLDO1N bit, PMDA bit, PMHPL bit and PMHPR bit must
be powered up after PMTIM bit = “1”.
(9) Power-up CP1 (PMCP1 bit = “0” → “1”) and wait 6.5 msec (Note 115) for CP1 output voltage
stabilization.
(10) Power-up LDO1P and LDO1N (PMLDO1P bit = PMLDO1N bit = “0” → “1”) and wait 0.5 msec (Note
115) for each LDO output voltage stabilization.
(11) Power-up DAC (PMDA bit = “0” → “1”)
(12) Power-up CP2 (PMCP2 bit = “0” → “1”) and wait 4.5 msec (Note 115) for CP2 output voltage
stabilization.
(13) Power-up headphone amplifier (PMHPL bit = PMHPR bit = “0” → “1”)
The power-up time of headphone amplifier is 23.9 msec (@ fs = 48 kHz). The HPL pin and the HPR
pin output 0 V until the headphone amplifier is powered up.
Note 115. Refer to “8-3. Charge Pump & LDO Circuit Power-Up Time”
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[AK4331]
Figure 44 shows power-down sequence of headphone amplifier and DAC.
PMHPL bit
PMHPR bit
(Addr:03H, D1, D0)
HPL pin
HPR pin
PMCP2 bit
(Addr:01H, D1)
PMDA bit
(Addr:02H, D0)
(1)
Norm al
Operation
(2)
(3)
PMLDO1P bit
PMLDO1N bit
(Addr:01H, D5, D4)
(4)
PMCP1 bit
(Addr:01H, D0)
(5)
PMTIM bit
(Addr:00H, D1)
(6)
PMPLL bit
(Addr:00H, D0)
(7)
(8)
MCKI, BCLK, LRCK
(9)
PDN pin
(10)
Pow er Supply
Figure 44. Power-Down Sequence Example of Headphone Amplifier and DAC
< Power-Down Sequence Example >
(1) Power-down headphone amplifier (PMHPL bit = PMHPR bit = “1” → “0”).
When the headphone amplifier is powered down, the HPL pin and the HPR pin are pulled down to
HPGND via the internal pull-down register.
(2) Power-down CP2 (PMCP2 bit = “1” → “0”).
(3) Power-down DAC (PMDA bit = “1” → “0”).
(4) Power-down LDO1P, LDO1N (PMLDO1P bit = PMLDO1N bit = “1” → “0”).
(5) Power-down CP1 (PMCP1 bit = “1” → “0”).
(6) Stop internal master counter. (PMTIM bit = “1” → “0”)
PMCP1 bit, PMCP2 bit, PMLDO1P bit, PMLDO1N bit, PMDA bit, PMHPL bit and PMHPR bit must
be powered off before PMTIM bit = “0”.
(7) In case of using PLL, power-down PLL. (PMPLL bit = “1” → “0”)
(8) Stop MCKI, BCLK and LRCK supply before turning off each of power supplies.
(9) Set the PDN pin from “H” to “L”.
(10) Turn off each of power supplies.
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[AK4331]
9-22. Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
26H
27H
29H
D7
D6
D5
D4
D3
D2
D1
D0
Register Name
0
0
0
PMOSC
0
0
PMTIM
PMPLL
Power Management 1
0
0
PMLDO1N PMLDO1P
0
0
PMCP2
PMCP1
Power Management 2
PMSRC
0
PMSM
SELSM
0
0
0
PMDA
Power Management 3
0
LVDTM[2:0]
CPMODE[1:0]
PMHPR
PMHPL
Power Management 4
LVDSEL[1:0]
VDDTM[3:0]
HPRHZ
HPLHZ
Output Mode Setting
0
CM[1:0]
FS[4:0]
Clock Mode Select
DASD
DASL
DADFSEL
0
0
0
0
0
Digital Filter Select
INVR
MDACR
RDACR
LDACR
INVL
MDACL
RDACL
LDACL
DAC Mono Mixing
0
CM2[1:0]
FS2[4:0]
SRC Clock Select
0
0
0
0
SMT[1:0]
SAUTO
SMUTE
Soft Mute Setting
0
XCKSEL
0
0
0
0
SELDAIN
0
SRC Setting
OVOLCN
0
0
OVL[4:0]
Lch Output Volume
0
0
0
OVR[4:0]
Rch Output Volume
HPTM[2:0]
1
0
HPG[2:0]
HP Volume Control
0
0
0
PLLMD
0
0
0
PLS
PLL CLK Source Select
PLD[15:8]
PLL Ref CLK Divider 1
PLD[7:0]
PLL Ref CLK Divider 2
PLM[15:8]
PLL FB CLK Divider 1
PLM[7:0]
PLL FB CLK Divider 2
0
0
0
0
0
0
0
SRCCKS
SRC CLK Source Select
0
0
0
0
MDIV[3:0]
PLLCLK Divider
DEVICEID[2:0]
MS
BCKO
DIF
DL[1:0]
Audio Interface Format
PMDMR
PMDML
DCLKE
DCLKP
0
0
ADRST[1:0]
Digital MIC
SV[2:0]
SVE
0
HPFC[1:0]
HPFADN
Side Tone Volume Control
T8
T7
T6
T5
T4
T3
T2
T1
DAC Adjustment 1
T16
T15
T14
T13
T12
T11
T10
T9
DAC Adjustment 2
0
0
0
0
0
0
HPMD[1:0]
Mode Control
Note 116.
Note 117.
Note 118.
Note 119.
PDN pin = “L” resets the registers to their default values.
The bits defined as “0” must contain a “0” value.
The bits defined as “1” must contain a “1” value.
Writing access to 18H to 25H, 28H, 2AH to FFH is prohibited.
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9-23. Register Definitions
Addr Register Name
00H Power Management 1
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
PMOSC
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
PMTIM
R/W
0
D0
PMPLL
R/W
0
D4
D3
0
R/W
0
D2
0
R/W
0
D1
PMCP2
R/W
0
D0
PMCP1
R/W
0
PMPLL: PLL Power Management
0: Power-Down (default)
1: Power-Up
PMTIM: Synchronization Control Power Management
0: Disable (default)
1: Enable
PMOSC: Crystal Oscillator Power Management
0: Power-Down (default)
1: Power-Up
Addr Register Name
01H Power Management 2
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
PMLDO1N PMLDO1P
R/W
0
R/W
0
PMCP1: Charge Pump 1 Power Management
0: Power-Down (default)
1: Power-Up
PMCP2: Charge Pump 2 Power Management
0: Power-Down (default)
1: Power-Up
PMLDO1P: LDO1P Power Management
0: Power-Down (default)
1: Power-Up
PMLDO1N: LDO1N Power Management
0: Power-Down (default)
1: Power-Up
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Addr Register Name
02H Power Management 3
R/W
Default
D7
PMSRC
R/W
0
D6
0
R/W
0
D5
PMSM
R/W
0
D4
SELSM
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
0
R/W
0
D0
PMDA
R/W
0
D1
PMHPR
R/W
0
D0
PMHPL
R/W
0
PMDA: DAC Power Management
0: Power-Down (default)
1: Power-Up
PMSM, SELSM: Soft Mute Power Management (Table 46)
“0, 0”: Power-Down (default)
“1, 1”: Power-Up
PMSRC: SRC Power Management
0: Power-Down (default)
1: Power-Up
Addr Register Name
03H Power Management 4
R/W
Default
D7
0
R/W
0
D6
D5
LVDTM[2:0]
R/W
000
D4
D3
D2
CPMODE[1:0]
R/W
00
PMHPL/R: Headphone Amplifier L/R Channel Power Management
0: Power-Down (default)
1: Power-Up
CPMODE[1:0]: Charge Pump Mode Control (Table 32)
Default: “00” (Automatic Switching Mode)
LVDTM[2:0]: Class-G 1/2VDD Mode Detection Time Setting (Table 34)
Default: “000” (64/fs)
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Addr Register Name
04H Output Mode Setting
R/W
Default
D7
D6
LVDSEL[1:0]
R/W
00
D5
D4
D3
VDDTM[3:0]
R/W
0000
D2
D1
HPRHZ
R/W
0
D0
HPLHZ
R/W
0
D1
D0
HPRHZ/HPLHZ: GND Switch Setting for Headphone Amplifier Output
0: Pull-Down by 4Ω (Typ.) (default)
1: Pull-Down by 95 kΩ (Typ.)
VDDTM[3:0]: Class-G VDD Hold Time Setting (Table 33)
Default: “0000” (1024/fs)
LVDSEL[1:0]: Switching Threshold between VDD Mode and 1/2VDD Mode of CP2
00: VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 16Ω)
1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 16Ω)
(Default: Assuming when connecting a 16Ω Headphone)
01: VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 32Ω)
1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 32Ω)
(Assuming when connecting a 32Ω Headphone or more)
10: VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 11Ω)
1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 11Ω)
(Assuming when connecting a 11Ω Headphone)
11: VDD → 1/2VDD: < 1.05 mW at both channels (@CVDD = 1.8 V, RL = 8Ω)
1/2VDD → VDD: ≥ 1.05 mW at either channel (@CVDD = 1.8 V, RL = 8Ω)
(Assuming when connecting a 8Ω Headphone)
Addr Register Name
05H Clock Mode Select
R/W
Default
D7
0
R/W
0
D6
D5
D4
D3
CM[1:0]
R/W
00
D2
FS[4:0]
R/W
00000
FS[4:0]: Sampling Frequency Setting (Table 6 @SRC Bypass Mode, Table 8 @SRC Mode)
Default: “00000” (fs = 8 kHz)
CM[1:0]: Master Clock Frequency Setting (Table 5 @SRC Bypass Mode, Table 7 @SRC Mode)
Default: “00” (256fs)
Addr Register Name
06H Digital Filter Select
R/W
Default
D7
DASD
R/W
0
D6
DASL
R/W
0
D5
DADFSEL
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
0
R/W
0
D0
0
R/W
0
DADFSEL: Digital Filter Setting for DAC Compensation (Table 27, Table 28)
0: In case of SRC Bypass Mode (default)
1: In case of SRC Mode
DASD, DASL: DAC Digital Filter Mode Setting (Table 27, Table 28)
Default: “0, 0” (Sharp Roll-Off Filter)
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Addr Register Name
07H DAC Mono Mixing
R/W
Default
D7
INVR
R/W
0
D6
MDACR
R/W
0
D5
RDACR
R/W
0
D4
LDACR
R/W
0
D3
INVL
R/W
0
D2
MDACL
R/W
0
D1
RDACL
R/W
0
D0
LDACL
R/W
0
D1
D0
D1
SAUTO
R/W
0
D0
SMUTE
R/W
0
MDACL, RDACL, LDACL: DAC L Channel Input Signal Select (Table 29)
Default: “0, 0, 0” (MUTE)
MDACR, RDACR, LDACR: DAC R Channel Input Signal Select (Table 29)
Default: “0, 0, 0” (MUTE)
INVL/R: DAC Input Signal Polarity Select
0: Normal (default)
1: Inverting
Addr Register Name
08H SRC Clock Select
R/W
Default
D7
0
R/W
0
D6
D5
CM2[1:0]
R/W
00
D4
D3
D2
FS2[4:0]
R/W
00000
FS2[4:0]: Sampling Frequency Setting for SRC Output (Table 10)
Default: “00000” (fs = 8 kHz)
CM2[1:0]: Master Clock Frequency Setting for SRC Output (Table 9)
Default: “00” (256fs)
Addr Register Name
09H Soft Mute Setting
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
D2
SMT[1:0]
R/W
00
SMUTE: Soft Mute Enable
0: Disable (default)
1: Enable
SAUTO: Semi-Auto Mode Enable
0: Disable (default)
1: Enable
SMT[1:0]: Soft Mute Cycle Setting (Table 47)
Default: “00”, 1024/FSO
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Addr Register Name
0AH SRC Setting
R/W
Default
D7
0
R/W
0
D6
XCKSEL
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
SELDAIN
R/W
0
D0
0
R/W
0
D3
D2
OVL[4:0]
OVR[4:0]
R/W
19H
D1
D0
SELDAIN: DAC Input Data Select (Table 45)
Default: “0” (SDTI pin; SRC Bypass Mode)
XCKSEL: DAC and Charge Pump Operation Clock (Table 43)
0: PLLO (default)
1: MCKI/XTI pin
Addr Register Name
0BH Lch Output Volume
0CH Rch Output Volume
R/W
Default
D7
OVOLCN
0
R/W
0
D6
0
0
R/W
0
D5
0
0
R/W
0
D4
OVL[4:0]: DAC L Channel Digital Volume Control; +3 dB to 12 dB & Mute, 0.5 dB step (Table 31)
OVR[4:0]: DAC R Channel Digital Volume Control; +3 dB to 12 dB & Mute, 0.5 dB step (Table 31)
Default: 19H (0 dB)
OVOLCN: Digital Volume Control
0: Dependent (default)
1: Independent
OVL[4:0] bits control digital volume of both L and R channels when OVOLCN bit = “0”. In this
case, the value of OVL[4:0] bits will not be written to OVR[4:0] bits.
Addr Register Name
0DH HP Volume Control
R/W
Default
D7
D6
HPTM[2:0]
R/W
011
D5
D4
1
R/W
1
D3
0
R/W
0
D2
D1
HPG[2:0]
R/W
101
D0
HPG[2:0]: Headphone Amplifier Analog Volume Control; +4 dB to 10 dB, 2 dB step (Table 35)
Default: “101” (0 dB)
HPTM[2:0]: Zero Cross Time Output Period Setting for Analog Volume of Headphone Amplifier
(Table 36)
Default: “011” (1024/fs)
Addr Register Name
0EH PLL CLK Source Select
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
PLLMD
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
0
R/W
0
D0
PLS
R/W
0
PLS: PLL Clock Source Select (Table 14)
Default: “0” (MCKI/XTI pin)
PLLMD: PLL Internal Mode Setting (Table 17)
Default: “0”
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Addr Register Name
0FH PLL Ref CLK Divider 1
10H PLL Ref CLK Divider 2
R/W
Default
D7
D6
D5
D4
D3
PLD[15:8]
PLD[7:0]
R/W
0000H
D2
D1
D0
D2
D1
D0
D2
0
R/W
0
D1
0
R/W
0
D0
SRCCKS
R/W
0
PLD[15:0]: PLL Reference Clock Divider Setting (Table 15)
Default: 0000H
Addr Register Name
11H PLL FB CLK Divider 1
12H PLL FB CLK Divider 2
R/W
Default
D7
D6
D5
D4
D3
PLM[15:8]
PLM[7:0]
R/W
0000H
PLM[15:0]: PLL Feedback Clock Divider Setting (Table 16)
Default: 0000H
Addr Register Name
13H SRC CLK Source Select
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D4
0
R/W
0
D3
SRCCKS: SRC Clock Source Select (Table 44)
0: PLLO (default)
1: MCKI/XTI pin
Addr Register Name
14H PLLCLK Divider
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D2
D1
MDIV[3:0]
R/W
0H
D0
MDIV[3:0]: PLLCLK Divider Setting (Table 18)
Default: 0H (Divided by 1)
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Addr Register Name
15H Audio Interface Format
R/W
Default
D7
D6
D5
DEVICEID[2:0]
R
111
D4
MS
R/W
0
D3
BCKO
R/W
0
D2
DIF
R/W
0
D1
D0
DL[1:0]
R/W
00
DL[1:0]: Data Length Setting (Table 49)
Default: “00” (24-bit linear)
DIF: Digital Audio Interface Format Setting (Table 48)
0: I2S Compatible (default)
1: MSB justified
BCKO: BCLK Output Frequency
0: 64fs (Default)
1: 32fs
MS: Master/Slave Mode Setting (Table 3)
0: Slave Mode (default)
1: Master Mode
DEVICEID[2:0]: Device ID
Default: “111” (AK4375: “000”, AK4375A: “001”, AK4376/A: “010”, AK4377: “011”, AK4331: “111”)
Addr Register Name
16H Digital MIC
R/W
Default
D7
PMDMR
R/W
0
D6
PMDML
R/W
0
D5
DCLKE
R/W
0
D4
DCLKP
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
D0
ADRST[1:0]
R/W
00
ADRST[1:0]: Digital Microphone Initialization Cycle Setting (Table 24)
Default: “00” (1059/fs)
DCLKP: Data Latching Edge Select (Table 21)
0: L channel data is latched on the DMCLK rising edge (“↑”). (default)
1: L channel data is latched on the DMCLK falling edge (“↓”).
DCLKE: DMCLK pin Output Clock Control
0: “L” Output (default)
1: 64fs Output
PMDML/R: Input Signal Select with Digital Microphone Power Management (Table 23)
0: Power-Down (default)
1: Power-Up
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Addr Register Name
17H Side Tone Volume Control
R/W
Default
D7
D6
SV[2:0]
R/W
000
D5
D4
SVE
R/W
0
D3
0
R/W
0
D2
D1
HPFC[1:0]
R/W
00
D0
HPFADN
R/W
0
HPFADN: Digital Microphone HPF Control
0: On (default)
1: Off
HPFC[1:0]: Cut-off frequency of Digital Microphone HPF (Table 22)
Default: “00” (29.8 Hz @fs = 48 kHz)
SVE: Side Tone Additional Control (Table 25)
0: Disable (default)
1: Enable
SV[2:0]: Side Tone Volume Control; 0 dB to 24 dB, 6 dB step (Table 26)
Default: “000” (0 dB)
Addr Register Name
26H DAC Adjustment 1
R/W
Default
D7
T8
R/W
0
D6
T7
R/W
1
D5
T6
R/W
1
D4
T5
R/W
0
D3
T4
R/W
1
D2
T3
R/W
1
D1
T2
R/W
0
D0
T1
R/W
0
* 02H data must be written to DAC Adjustment 1 (Addr. 26H) before analog blocks (CP1, CP2, LDO1,
DAC, headphone amplifier and PLL) are powered up.
Addr Register Name
27H DAC Adjustment 2
R/W
Default
D7
T16
R/W
0
D6
T15
R/W
1
D5
T14
R/W
0
D4
T13
R/W
0
D3
T12
R/W
0
D2
T11
R/W
0
D1
T10
R/W
0
D0
T9
R/W
0
* C0H data must be written to DAC Adjustment 2 (Addr. 27H) before analog blocks (CP1, CP2, LDO1,
DAC, headphone amplifier and PLL) are powered up.
Addr Register Name
29H Mode Control
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
D0
HPMD[1:0]
R/W
00
HPMD[1:0]: Headphone Amplifier Operation Mode Setting (N/A: Not available) (Table 5, Table 9)
00: In case of fs = 8 to 48 kHz (SRC Bypass Mode) / FSO = 8 to 48 kHz (SRC Mode) (default)
01: N/A
10: N/A
11: In case of fs = 64 to 192 kHz (SRC Bypass Mode) / FSO = 64 to 192 kHz (SRC Mode)
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10. Recommended External Circuits
1.7 ~1.9 V Power Supply
10 μ
0.1 μ
AVDD
LVDD
VSS1
VDD
VSS3
0.1 μ
VSS3
VCOM
2.2 μ
VSS1
RVEE
1.0 μ
TVDD
VSS3
RAVDD
1.0 μ
VDD12
CVDD
0.1 μ
1.65 to 3.6 V Power Supply
0.1 μ
VDD
VSS2
2.2 μ
VSS3
DMDAT
VSS2
CP1
2.2 μ
DMIC1
DMCLK
CN1
DMIC2
VSS1
VEE1
2.2 μ
2.2 μ
VCC2
SCL
VEE2
2.2 μ
2.2 μ
2.2 μ
SDA
CP2A
SDTO
CN2A
BCLK
CP2B
LRCK
CN2B
SDTI
ACPU
PDN
Headphone
TEST1
HPL
0.1 μ
0.1 μ
15
15
100 k(*1)
100 k(*1)
TEST2
HPR
VSS3
MCKI/XTI
VSS
VSS1V
SS
VSS
Cg
VSS
HPGND
XTO
Cd
VSS1
VSS2
VSS3
VSS3
Cd = Cg = 20.0 pF (Max.) @ f = 24.576 MHz
Cd = Cg = 21.5 pF (Max.) @ f = 19.2 MHz
Cd = Cg = 30.6 pF (Max.) @ f = 11.2896 MHz
VSS
Figure 45. System Connection Diagram (When using X’tal Oscillator and Digital Microphone)
*1: When the AK4331 is in master mode, a pull-down resistor (e.g. 100 kΩ) is needed.
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1. Grounding and Power Supply Decoupling
The AK4331 requires careful attention to power supply and grounding arrangements. The PDN pin
should be held “L” when power supplies are tuning on. AVDD should be powered up before or at the same
time of CVDD. Power-up sequence of TVDD and LVDD is not critical. The PDN pin is allowed to be “H”
after all power supplies are applied and settled. To power down the AK4331, set the PDN pin to “L” and
power down CVDD before or at the same time of AVDD. Power-down sequence of LVDD and TVDD is
not critical.
To avoid pop noise on analog output when power-up/down, the AK4331 should be operated along the
following recommended power-up/down sequence.
1) Power-up
- The PDN pin should be held “L” when power supplies are turning on. The AK4331 can be reset by
keeping the PDN pin “L” for 1 msec or longer after all power supplies are applied and settled. Then
release the reset by setting the PDN pin to “H”.
2) Power-down
- Each of power supplies can be powered OFF after the PDN pin is set to “L”.
VSS1, VSS2 and VSS3 of the AK4331 should be connected to the analog ground plane. System analog
ground and digital ground should be connected together near where the supplies are brought onto the
printed circuit board. Decoupling capacitors should be as close the power supply pins as possible.
Especially, the small value ceramic capacitor is to be closest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2 μF ceramic capacitor attached between the VCOM pin
eliminates the effects of high frequency noise. No load current is allowed to be drawn from the VCOM pin.
All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted
coupling into the AK4331.
3. Charge Pump and LDO Circuits
Capacitors for CP1 block (connected between the CP1 pin and the CN1 pin, between the VEE1 pin and
the VSS2 pin) and for CP2 block (connected between the CP2A pin and the CN2A pin, between the CP2B
pin and the CN2B pin, between the VCC2 pin and the VSS2 pin, between the VEE2 pin and the VSS2 pin)
should be low ESR 2.2 μF ±50%.
Capacitors for LDO1P block (connected between the RAVDD pin and the VSS1 pin) and for LDO1N block
(connected between the RVEE pin and the VSS1 pin) should be low ESR from 1.0 μF ±50% to 4.7 μF
±50%.
These capacitors must be connected as close as possible to the pins. No load current may be drawn from
the Positive / Negative Power Output pin (VEE1, RAVDD, RVEE, VCC2 and VEE2 pins).
4. Analog Outputs
Headphone outputs are single-ended and centered at HPGND (0 V). They should be directly connected
to a headphone without AC coupling.
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11. Package
11-1. Outline Dimensions
36-pin CSP (Unit: mm)
Top View
Bottom View
(0.025 ±0.004)
2.533 ±0.025
A
0.4
B
0.2
6
2.371 ±0.025
0.4
5
4
0.2
3
2
1
1
A
C
0.03
E
D
C
B
36 x (0.204 ~ 0.264)
0.519 0.046
0.382 0.016
0.107 ~ 0.167
F
A
0.015 M C A B
C
11-2. Material and Lead Finish
Package molding compound: Epoxy Resign, Halogen Free
Solder ball material:
SnAgCu
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11-3. Marking
4331
XXXX
1
A
XXXX: Date code (4 digits)
Pin #A1 indication
12. Ordering Guide
AK4331ECB
AKD4331
40 to 85C
36-pin CSP (0.4 mm pitch)
Evaluation board for AK4331
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13. Revision History
Date (Y/M/D)
18/07/12
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third party
with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the
aerospace industry, medical equipment, equipment used for automobiles, trains, ships and
other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations in
which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or
related technology or any information contained in this document, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws
and regulations. The Products and related technology may not be used for or incorporated into
any products or systems whose manufacture, use, or sale is prohibited under any applicable
domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws
and regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as
a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without
prior written consent of AKM.
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2018/07
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