[AK4385]
AK4385
108dB 192kHz 24-Bit 2ch ΔΣ DAC
GENERAL DESCRIPTION
The AK4385 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit
architecture for its modulator the AK4385 delivers a wide dynamic range while preserving linearity for
improved THD+N performance. The AK4385 has full differential SCF outputs, removing the need for AC
coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit word
length and 192kHz sampling rate make this part ideal for a wide range of applications including
DVD-Audio. The AK4385 is offered in a space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
On chip SCF
Digital de-emphasis for 32k, 44.1k and 48kHz sampling
Soft mute
Digital Attenuator (Linear 256 steps)
I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S
Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -94dB
Dynamic Range: 108dB
High Tolerance to Clock Jitter
Power supply: 4.75 to 5.25V
Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
AK4381 Pin Compatible
MCLK
VDD
CSN
CCLK
µP
Interface
De-emphasis
Control
VSS
Clock
Divider
DZFL
CDTI
DZFR
LRCK
BICK
SDTI
Audio
Data
Interface
8X
Interpolator
ΔΣ
Modulator
SCF
8X
Interpolator
ΔΣ
Modulator
SCF
AOUTL+
AOUTLAOUTR+
AOUTR-
PDN
MS0246-E-02
2010/09
-1-
[AK4385]
■ Ordering Guide
-20 ∼ +85°C
16pin TSSOP (0.65mm pitch)
-40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4385
AK4385ET
AK4385VT
AKD4385
■ Pin Layout
MCLK
1
16
DZFL
BICK
2
15
DZFR
SDTI
3
14
VDD
LRCK
4
13
VSS
PDN
5
12
AOUTL+
CSN
6
11
AOUTL-
CCLK
7
10
AOUTR+
CDTI
8
9
AOUTR-
Top
View
PIN/FUNCTION
No.
1
Pin Name
MCLK
I/O
I
Function
Master Clock Input Pin
An external TTL clock should be input on this pin.
2
BICK
I
Audio Serial Data Clock Pin
3
SDTI
I
Audio Serial Data Input Pin
4
LRCK
I
L/R Clock Pin
5
PDN
I
Power-Down Mode Pin
When at “L”, the AK4385 is in the power-down mode and is held in reset.
The AK4385 must be reset once upon power-up.
6
CSN
I
Chip Select Pin
7
CCLK
I
Control Data Input Pin
8
CDTI
I
Control Data Input Pin in serial mode
9
AOUTRO
Rch Negative Analog Output Pin
10
AOUTR+
O
Rch Positive Analog Output Pin
11
AOUTLO
Lch Negative Analog Output Pin
12
AOUTL+
O
Lch Positive Analog Output Pin
13
VSS
Ground Pin
14
VDD
Power Supply Pin
15
DZFR
O
Rch Data Zero Input Detect Pin
16
DZFL
O
Lch Data Zero Input Detect Pin
Note: All input pins should not be left floating.
MS0246-E-02
2010/09
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[AK4385]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supply
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
AK4385ET
(Powered applied)
AK4385VT
Storage Temperature
Note: 1. All voltages with respect to ground.
Symbol
VDD
IIN
VIND
Ta
Ta
Tstg
min
-0.3
-0.3
-20
-40
-65
max
6.0
±10
VDD+0.3
85
85
150
Units
V
mA
V
°C
°C
°C
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
min
4.75
typ
5.0
max
5.25
Units
V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0246-E-02
2010/09
-3-
[AK4385]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL ≥4kΩ; unless otherwise specified)
Parameter
min
typ
max
Resolution
24
Dynamic Characteristics
(Note 3)
THD+N
fs=44.1kHz
0dBFS
-94
-84
BW=20kHz
-60dBFS
-44
fs=96kHz
0dBFS
-92
BW=40kHz
-60dBFS
-41
fs=192kHz
0dBFS
-92
BW=40kHz
-60dBFS
-41
Dynamic Range (-60dBFS with A-weighted)
(Note 4)
100
108
S/N
(A-weighted)
(Note 5)
100
108
Interchannel Isolation (1kHz)
90
110
Interchannel Gain Mismatch
0.2
0.5
DC Accuracy
Gain Drift
100
Output Voltage
(Note 6)
±2.55
±2.75
±2.95
Load Resistance
(Note 7)
4
Power Supplies
Power Supply Current (VDD)
17
27
Normal Operation (PDN = “H”, fs≤96kHz)
20
32
Normal Operation (PDN = “H”, fs=192kHz)
10
100
Power-Down Mode (PDN = “L”)
(Note 8)
Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
4. 100dB at 16bit data.
5. S/N does not depend on input bit length.
6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF,
AOUT (typ.@0dB)=(AOUT+)-(AOUT-)=±2.75Vpp × VREF/5.
7. For AC-load. 4kΩ for DC-load.
8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS.
MS0246-E-02
Units
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
Vpp
kΩ
mA
mA
μA
2010/09
-4-
[AK4385]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD = 4.75 ∼ 5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “0”)
Parameter
Symbol
min
typ
max
Units
Digital filter
PB
0
20.0
kHz
Passband
±0.05dB (Note 9)
22.05
kHz
-6.0dB
Stopband
(Note 9)
SB
24.1
kHz
Passband Ripple
PR
dB
± 0.02
Stopband Attenuation
SA
54
dB
Group Delay
(Note 10)
GD
19.3
1/fs
Digital Filter + SCF
Frequency Response 20.0kHz fs=44.1kHz
FR
dB
± 0.2
40.0kHz fs=96kHz
FR
dB
± 0.3
80.0kHz fs=192kHz
FR
dB
+0.1/-0.6
Notes: 9. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)
Parameter
Symbol
min
(Note 11)
PB
(Note 11)
SB
PR
SA
GD
0
39.2
typ
max
Units
18.2
8.1
-
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 10)
72
-
19.3
-
kHz
kHz
kHz
dB
dB
1/fs
-
+0/-5
+0/-4
+0.1/-5
-
dB
dB
dB
typ
-
max
0.8
0.4
± 10
Units
V
V
V
V
µA
± 0.005
Digital Filter + SCF
FR
20.0kHz fs=44.kHz
40.0kHz fs=96kHz
FR
80.0kHz fs=192kHz
FR
Note: 11. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
Frequency Response
DC CHARACTERISTICS
(Ta=25°C; VDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout=-80µA)
VOH
VDD-0.4
Low-Level Output Voltage
(Iout=80µA)
VOL
Input Leakage Current
Iin
-
MS0246-E-02
-
2010/09
-5-
[AK4385]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
fCLK
2.048
Master Clock Frequency
dCLK
40
Duty Cycle
LRCK Frequency
8
fsn
Normal Speed Mode
60
fsd
Double Speed Mode
120
fsq
Quad Speed Mode
45
Duty
Duty Cycle
Audio Interface Timing
BICK Period
tBCK
Normal Speed Mode
1/128fs
tBCK
Double/Quad Speed Mode
1/64fs
tBCKL
BICK Pulse Width Low
30
tBCKH
Pulse Width High
30
tBLR
BICK rising to LRCK Edge
(Note 12)
20
tLRB
LRCK Edge to BICK rising
(Note 12)
20
tSDH
SDTI Hold Time
20
tSDS
SDTI Setup Time
20
Control Interface Timing
tCCK
200
CCLK Period
tCCKL
80
CCLK Pulse Width Low
tCCKH
80
Pulse Width High
tCDS
40
CDTI Setup Time
tCDH
40
CDTI Hold Time
tCSW
150
CSN “H” Time
tCSS
50
CSN “↓” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
Reset Timing
tPD
150
PDN Pulse Width
(Note 13)
Notes: 12. BICK rising edge must not occur at the same time as LRCK edge.
13. The AK4385 can be reset by bringing PDN= “L”.
MS0246-E-02
typ
11.2896
max
36.864
60
Units
MHz
%
48
96
192
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2010/09
-6-
[AK4385]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Serial Interface Timing
MS0246-E-02
2010/09
-7-
[AK4385]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power-down Timing
MS0246-E-02
2010/09
-8-
[AK4385]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4385, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~4).After exiting reset (PDN = “↑”), the AK4385 is in Auto Setting Mode. In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes
the appropriate frequency (Table 6), it is not necessary to set DFS0/1.
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4385 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4385 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4385 should be reset by PDN=
“L” after threse clocks are provided. If the external clocks are not present, the AK4385 should be in the power-down
mode (PDN= “L”). After exiting reset at power-up etc., the AK4385 is in the power-down mode until MCLK and LRCK
are input.
DFS1
DFS0
Sampling Rate (fs)
0
0
Normal Speed Mode
8kHz~48kHz
0
1
Double Speed Mode
60kHz~96kHz
1
0
Quad Speed Mode
Default
120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
384fs
12.2880MHz
16.9344MHz
18.4320MHz
MCLK
512fs
16.3840MHz
22.5792MHz
24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
1152fs
36.8640MHz
N/A
N/A
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
fs
88.2kHz
96.0kHz
128fs
11.2896MHz
12.2880MHz
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
384fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
fs
176.4kHz
192.0kHz
MCLK
128fs
192fs
22.5792MHz 33.8688MHz
24.5760MHz 36.8640MHz
BICK
64fs
11.2896MHz
12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MS0246-E-02
2010/09
-9-
[AK4385]
MCLK
512fs
768fs
256fs
384fs
128fs
192fs
Sampling Speed
Normal
Double
Quad
Table 5. Sampling Speed (Auto Setting Mode: Default)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
192fs
33.8688
36.8640
MCLK (MHz)
256fs
384fs
22.5792
33.8688
24.5760
36.8640
-
512fs
16.3840
22.5792
24.5760
-
768fs
24.5760
33.8688
36.8640
-
Sampling Speed
Normal
Double
Quad
Table 6. System Clock Example (Auto Setting Mode)
■ Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial
data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK.
Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I2S Compatible
24bit LSB Justified
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Default
Table 7. Audio Data Formats
MS0246-E-02
2010/09
- 10 -
[AK4385]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
14
6
1
0
5
14
4
15
3
2
16
1
17
0
31
15
0
14
6
5
14
1
4
15
3
16
2
1
17
0
31
15
14
0
1
0
1
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
Don’t care
0
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1,4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
MS0246-E-02
2010/09
- 11 -
[AK4385]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
0
1
23 22
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
■ De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled
with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
Default
Table 8. De-emphasis Filter Control (Normal Speed Mode)
■ Output Volume
The AK4385 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition
time of 1 level and all 256 levels is shown in Table 9.
Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Transition Time
1 Level
255 to 0
4LRCK
1020LRCK
8LRCK
2040LRCK
16LRCK
4080LRCK
Table 9. ATT Transition Time
MS0246-E-02
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[AK4385]
■ Zero Detection
The AK4385 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin
of both channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go
to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can
be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF
pin.
■ Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
-∞ during ATT_DATA×ATT transition time (Table 9) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
ATT Level
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA×ATT transition time (Table 9). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft Mute and Zero Detection
MS0246-E-02
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[AK4385]
■ System Reset
The AK4385 should be reset once by bringing PDN= ”L” upon power-up. The AK4385 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4385 is in the
power-down mode until MCLK and LRCK are input.
■ Power-down
The AK4385 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 6 shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
Normal Operation
“0” data
GD
D/A Out
(Analog)
(1)
GD
(2)
(3)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, LRCK, BICK
DZFL/DZFR
External
MUTE
(6)
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up Sequence Example
MS0246-E-02
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[AK4385]
■ Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to
VCOM voltage and DZF pin goes to “H”. Figure 7 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN bit
Internal
State
Normal Operation
D/A In
(Digital)
“0” data
(1)
D/A Out
(Analog)
Normal Operation
Digital Block Power-down
GD
GD
(2)
(3)
(3)
(1)
(4)
Clock In
Don’t care
MCLK,LRCK,BICK
2/fs(5)
DZF
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage (VDD/2).
(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN “1”.
Figure 7. Reset Sequence Example
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[AK4385]
■ Mode Control Interface
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists
of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first,
5bits) and Control Data (MSB first, 8bits). AK4385 latches the data on the rising edge of CCLK, so data should clocked
in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max).
PDN = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are
not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
Chip Address (Fixed to “01”)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 8. Control I/F Timing
*AK4385 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4385 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
■ Register Map
Addr
00H
01H
02H
03H
04H
Notes:
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
D7
D6
D5
D4
D3
D2
D1
D0
ACKS
DZFE
0
ATT7
ATT7
0
DZFM
0
ATT6
ATT6
0
SLOW
0
ATT5
ATT5
DIF2
DFS1
0
ATT4
ATT4
DIF1
DFS0
0
ATT3
ATT3
DIF0
DEM1
DZFB
ATT2
ATT2
PW
DEM0
0
ATT1
ATT1
RSTN
SMUTE
0
ATT0
ATT0
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values.
All data can be written to the register even if PW or RSTN bit is “0”.
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[AK4385]
■ Register Definitions
Addr
00H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 1
ACKS
0
0
DIF2
DIF1
DIF0
PW
RSTN
default
1
0
0
0
1
0
1
1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (see Table 7)
Initial: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0
are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr
01H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 2
DZFE
DZFM
SLOW
DFS1
DFS0
DEM1
DEM0
SMUTE
default
0
0
0
0
0
0
1
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (see Table 8)
Initial: “01”, OFF
DFS1-0: Sampling speed control
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise
occurs.
SLOW: Slow Roll-off Filter Enable
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.
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[AK4385]
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
Addr
02H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 3
0
0
0
0
0
DZFB
0
0
default
0
0
0
0
0
0
0
0
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
Addr
03H
04H
Register Name
Lch ATT
Rch ATT
default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
ATT = 20 log10 (ATT_DATA / 255) [dB]
00H: Mute
SYSTEM DESIGN
Figure 9 shows the system connection diagram. An evaluation board (AKD4385) is available in order to allow an easy
study on the layout of a surrounding circuit.
Master Clock
1
MCLK
DZFL
64fs
2
BICK
DZFR
15
24bit Audio Data
3
SDTI
VDD
14
fs
Reset & Power down
Microcontroller
Digital Ground
16
0.1u
4
LRCK
VSS
13
5
PDN
AOUTL+
12
6
CSN
AOUTL-
11
7
CCLK
AOUTR+
10
8
CDTI
AOUTR-
9
AK4385
+
Analog
Supply 5V
10u
Lch
LPF
Lch
MUTE
Lch Out
Rch
LPF
Rch
MUTE
Rch Out
Analog Ground
Figure 9. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins should not be left floating.
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[AK4385]
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling
capacitor, especially 0.1μF ceramic capacitor for high frequency should be placed as near to VDD as possible. The
differential Voltage between VDD and VSS pins set the analog output range.
2. Analog Outputs
The analog outputs are full-differential outputs and 0.55 x VDD Vpp (typ) centered around the internal common voltage
(about AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and
AOUT-. If the summing gain is 1, the output range is 5.5Vpp (typ @VREFH=5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2’s complement. The output voltage (VAOUT) is a positive
full scale for 7FFFFF (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H
(@24bit).
The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma
modulator beyond the audio passband. DC offset on AOUT+/- is eliminated without AC coupling since the analog
outputs are differential. Figure 10 and 11 show the example of external op-amp circuit summing the differential outputs.
4.7k
4.7k
AOUTR1
470p
Vop
3300p
4.7k
AOUT+
Vop
Analog
Out
R1
4.7k
470p
1k
BIAS
47u
0.1u
When R1=200Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180Ω
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
1k
Figure 10. External 2nd order LPF Circuit Example (using op-amp with single power supply)
4.7k
4.7k
AOUTR1
470p
+Vop
3300p
AOUT+
4.7k
Analog
Out
R1
4.7k
470p
-Vop
When R1=200Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180Ω
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
MS0246-E-02
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[AK4385]
PACKAGE
16pin TSSOP (Unit: mm)
1.1 (max)
*5.0±0.1
16
9
8
1
0.13
M
6.4±0.2
*4.4±0.1
A
0.65
0.22±0.1
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder(Pb free) plate
MS0246-E-02
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- 20 -
[AK4385]
MARKING (AK4385VT)
AKM
4385VT
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4385VT
Asahi Kasei Logo
MS0246-E-02
2010/09
- 21 -
[AK4385]
MARKING (AK4385ET)
AKM
4385ET
XXYYY
5)
6)
7)
8)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4385ET
Asahi Kasei Logo
MS0246-E-02
2010/09
- 22 -
[AK4385]
REVISION HISTORY
Date (YY/MM/DD)
03/07/02
06/01/11
Revision
00
01
Reason
First Edition
Spec Addition
Page
Contents
2
Ordering Guide
AK4385ET was added.
MARKING
AK4385ET was added.
PACKAGE
The package dimension was changed.
22
10/09/28
02
Specification
Change
20
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS0246-E-02
2010/09
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工商网监
湘ICP备2023018690号
