[AK4399]
AK4399
High Performance 123dB Premium 32-Bit DAC
GENERAL DESCRIPTION
AK4399 is a 32-bit DAC, which corresponds to DVD-Audio systems. An internal circuit includes newly
developed 32bit Digital Filter for better sound quality achieving low distortion characteristics and wide
dynamic range. The AK4399 has full differential SCF outputs, removing the need for AC coupling
capacitors and increasing performance for systems with excessive clock jitter. The AK4399 accepts
192kHz PCM data and 1-bit DSD data, ideal for a wide range of applications including DVD-Audio and
SACD.
FEATURES
• 128x Over sampling
• Sampling Rate: 30kHz ∼ 216kHz
• 32Bit 8x Digital Filter (Short delay option GD=7/fs)
- Ripple: ±0.005dB, Attenuation: 100dB
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• DSD data input
• Digital De-emphasis for 32, 44.1, 48kHz sampling
• Soft Mute
• Digital Attenuator (255 levels and 0.5dB step)
• Mono Mode
• External Digital Filter Mode
• THD+N: -105dB
• DR, S/N: 123dB
• I/F Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S, DSD
• Master Clock:
30kHz ~ 32kHz: 1152fs
30kHz ~ 54kHz: 512fs or 768fs
30kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
• Power Supply: 4.75 ∼ 5.25V
• Digital Input Level: TTL
• Package: 44pin LQFP
MS1005-E-00
2008/10
-1-
[AK4399]
■ Block Diagram
DVDD
VSS3
PDN
AVDD
VSS4
VSS2
BICK/DCLK
LRCK/DSDR/WCK
SDATA/DSDL
VDDL
PCM
Data
Interface
8X
Interpolator
SCF
AOUTLN
DSD
Data
Interface
BCK
DINL
AOUTLP
DATT
Soft Mute
ΔΣ
Modulator
Bias
Vref
External
DF
Interface
SCF
VCML
VREFHL
VREFLL
VREFLR
VREFLL
VCMR
AOUTRP
AOUTRN
DINR
CSN/SMUTE
CCLK/DEM0
Control
Register
VDDR
Clock
Divider
CDTI/DEM1
VSS1
CAD0 CAD1/DIF0 PSN
DZFL/DIF1 DIF2
MCLK
DZFR
Block Diagram
MS1005-E-00
2008/10
-2-
[AK4399]
■ Ordering Guide
−10 ∼ +70°C
44pin LQFP (0.8mm pitch)
Evaluation Board for AK4399
AK4399EQ
AKD4399
AOUTLN
VSS2
VDDL
VREFHL
VREFLL
NC
VREFLR
VREFHR
VDDR
VSS1
AOUTRN
33
32
31
30
29
28
27
26
25
24
23
■ Pin Layout
AOUTLP
34
22
AOUTRP
VCML
35
21
VCMR
NC
36
20
NC
NC
37
19
DINL
NC
38
18
DINR
NC
39
17
NC
VSS3
40
16
BCK
AK4399
Top View
10
11
DIF0/CAD1
DIF1/DZFL
9
8
DEM0/CCLK
MS1005-E-00
DEM1/CDTI
7
TST1/CAD0
DIF2
6
12
SMUTE/CSN
44
LRCK/DSDR/WCK
NC
5
NC
4
13
SDATA/DSDL
43
3
VSS4
BICK/DCLK
PSN
2
TST2/DZFR
14
PDN
15
42
1
41
DVDD
AVDD
MCLK
2008/10
-3-
[AK4399]
PIN/FUNCTION
No.
Pin Name
I/O
1
DVDD
-
2
PDN
I
BICK
I
DCLK
SDATA
DSDL
LRCK
DSDR
WCK
I
I
I
I
I
I
SMUTE
I
CSN
TST1
CAD0
DEM0
CCLK
DEM1
CDTI
DIF0
CAD1
DIF1
DZFL
I
I
I
I
I
I
I
I
I
I
O
12
DIF2
I
13
NC
-
3
4
5
6
7
8
9
10
11
Function
Digital Power Supply Pin, 4.75 ∼ 5.25V
Power-Down Mode Pin
When at “L”, the AK4399 is in power-down mode and is held in reset.
The AK4399 should always be reset upon power-up.
Audio Serial Data Clock Pin in PCM Mode
DSD Clock Pin in DSD Mode
Audio Serial Data Input Pin in PCM Mode
DSD Lch Data Input Pin in DSD Mode
L/R Clock Pin in PCM Mode
DSD Rch Data Input Pin in DSD Mode
Word Clock input pin
Soft Mute Pin in Parallel Control Mode
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
Chip Select Pin in Serial Control Mode
Test Pin in Parallel Control Mode
(Internal pull-down pin)
Chip Address 0 Pin in Serial Control Mode
(Internal pull-down pin)
De-emphasis Enable 0 Pin in Parallel Control Mode
Control Data Clock Pin in Serial Control Mode
De-emphasis Enable 1 Pin in Parallel Control Mode
Control Data Input Pin in Serial Control Mode
Digital Input Format 0 Pin in PCM Mode
Chip Address 1 Pin in Serial Control Mode
Digital Input Format 1 Pin in PCM Mode
Lch Zero Input Detect Pin in Serial Control Mode
Digital Input Format 2 Pin in PCM Mode
No internal bonding.
Connect to GND.
Note: All input pins except internal pull-up/down pins must not be left floating.
MS1005-E-00
2008/10
-4-
[AK4399]
14
PSN
I
TST2
I
DZFR
O
16
BCK
I
17
NC
-
18
19
DINR
DINL
I
I
20
NC
-
21
VCMR
-
22
23
24
25
26
27
AOUTRP
AOUTRN
VSS1
VDDR
VREFHR
VREFLR
O
O
I
I
28
NC
-
29
30
31
32
33
34
VREFLL
VREFHL
VDDL
VSS2
AOUTLN
AOUTLP
I
I
O
O
35
VCML
-
36
NC
-
37
NC
-
38
NC
-
39
NC
-
40
41
42
43
VSS3
AVDD
MCLK
VSS4
I
-
44
NC
-
15
Parallel or Serial Select Pin
(Internal pull-up pin)
“L”: Serial Control Mode, “H”: Parallel Control Mode
Test pin in Parallel Control Mode.
Connect to GND.
Rch Zero Input Detect Pin in Serial Control Mode
Audio Serial Data Clock Pin
(Internal pull-down pin)
No internal bonding.
Connect to GND.
Rch Audio Serial Data Input Pin
(Internal pull-down pin)
Lch Audio Serial Data Input Pin
(Internal pull-down pin)
No internal bonding.
Connect to GND.
Right channel Common Voltage Pin,
Normally connected to VSS with a 10uF electrolytic cap.
Rch Positive Analog Output Pin
Rch Negative Analog Output Pin
Ground Pin
Rch Analog Power Supply Pin, 4.75 ∼ 5.25V
Rch High Level Voltage Reference Input Pin
Rch Low Level Voltage Reference Input Pin
No internal bonding.
Connect to GND.
Lch Low Level Voltage Reference Input Pin
Lch High Level Voltage Reference Input Pin
Lch Analog Power Supply Pin, 4.75 ∼ 5.25V
Ground Pin
Lch Negative Analog Output Pin
Lch Positive Analog Output Pin
Left channel Common Voltage Pin,
Normally connected to VSS with a 10uF electrolytic cap.
No internal bonding.
Connect to GND.
No internal bonding.
Connect to GND.
No internal bonding.
Connect to GND.
No internal bonding.
Connect to GND.
Ground Pin
Analog Power Supply Pin, 4.75 ∼ 5.25V
Master Clock Input Pin
Ground Pin
No internal bonding.
Connect to GND.
Note: All input pins except internal pull-up/down pins must not be left floating.
MS1005-E-00
2008/10
-5-
[AK4399]
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
(1) Parallel Mode (PCM Mode only)
Classification
Pin Name
AOUTLP, AOUTLN
AOUTRP, AOUTRN
SMUTE
TST1
TST2
Analog
Digital
Setting
These pins must be open.
These pins must be open.
This pin must be connected to VSS4.
This pin must be open.
This pin must be connected to VSS4.
(2) Serial Mode
1. PCM Mode
Classification
Analog
Digital
Pin Name
AOUTLP, AOUTLN
AOUTRP, AOUTRN
DIF2
DZFL, DZFR
Setting
These pins must be open.
These pins must be open.
These pins must be connected to VSS4.
These pins must be open.
2. DSD Mode
Classification
Pin Name
Analog
AOUTLP, AOUTLN
AOUTRP, AOUTRN
DZFL, DZFR
Setting
These pins must be open.
These pins must be open.
These pins must be open.
MS1005-E-00
2008/10
-6-
[AK4399]
ABSOLUTE MAXIMUM RATINGS
(VSS1-4 =0V; Note 1)
Parameter
Power Supplies:
Analog
Analog
Digital
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Temperature (Power applied)
Storage Temperature
Symbol
min
AVDD
VDDL/R
DVDD
−0.3
−0.3
−0.3
−0.3
−10
−65
IIN
VIND
Ta
Tstg
max
6.0
6.0
6.0
±10
DVDD+0.3
70
150
Units
V
V
V
mA
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. VSS1-4 must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1-4 =0V; Note 1)
Parameter
Analog
Power Supplies
Analog
(Note 3)
Digital
Voltage
“H” voltage reference
Reference
“L” voltage reference
(Note 4)
VREFH − VREFL
Symbol
AVDD
VDDL/R
DVDD
VREFHL/R
VREFLL/R
ΔVREF
min
4.75
4.75
4.75
AVDD−0.5
VSS
3.0
typ
5.0
5.0
5.0
-
max
5.25
5.25
5.25
AVDD
AVDD
Units
V
V
V
V
V
V
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between AVDD, VDDL/R and DVDD is not critical.
Note 4. The analog output voltage scales with the voltage of (VREFH − VREFL).
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFHL/R − VREFLL/R)/5.
* AKEMD assumes no responsibility for the usage beyond the conditions in this data sheet.
MS1005-E-00
2008/10
-7-
[AK4399]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS;
Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz;
Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 20; unless otherwise specified.)
Parameter
min
typ
max
Resolution
24
Dynamic Characteristics
(Note 5)
0dBFS
fs=44.1kHz
-105
98
THD+N
BW=20kHz
-60
−60dBFS
0dBFS
fs=96kHz
102
BW=40kHz
-57
−60dBFS
0dBFS
102
fs=192kHz
BW=40kHz
-57
−60dBFS
BW=80kHz
-54
−60dBFS
117
123
Dynamic Range (−60dBFS with A-weighted)
(Note 6)
S/N (A-weighted)
(Note 7)
117
123
Interchannel Isolation (1kHz)
110
120
DC Accuracy
Interchannel Gain Mismatch
0.15
0.3
Gain Drift
(Note 8)
20
Output Voltage
(Note 9)
±2.65
±2.8
±2.95
Load Capacitance
25
Load Resistance
(Note 10)
1
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD + VDDL/R
DVDD (fs ≤ 96kHz)
DVDD (fs = 192kHz)
Power down (PDN pin = “L”)
AVDD+VDDL/R+DVDD
Units
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
Vpp
pF
kΩ
-
60
43
46
90
70
mA
mA
mA
-
10
100
μA
(Note 11)
Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.
Note 6. Figure 20 External LPF Circuit Example 2. 101dB for 16-bit data and 118dB for 20-bit data.
Note 7. Figure 20 External LPF Circuit Example 2. S/N does not depend on input data size.
Note 8. The voltage on (VREFH − VREFL) is held +5V externally.
Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R − VREFLL/R).
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFHL/R − VREFLL/R)/5.
Note 10. Regarding Load Resistance, AC load is 1kΩ (min) with a DC cut capacitor (Figure 20). DC load is 1.5k ohm
(min) without a DC cut capacitor (Figure 19). The load resistance value is with respect to ground. Analog
characteristics are sensitive to capacitive load that is connected to the output pin. Therefore the capacitive load
must be minimized.
Note 11. In the power down mode. The P/S pin = DVDD, and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held VSS4.
MS1005-E-00
2008/10
-8-
[AK4399]
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SD bit=“0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
20.0
kHz
kHz
−6.0dB
22.05
Stopband
(Note 12)
SB
24.1
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
100
dB
Group Delay
(Note 13)
GD
36
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 20.0kHz
±0.2
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SD bit=“0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
43.5
kHz
48.0
kHz
−6.0dB
Stopband
(Note 12)
SB
52.5
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
95
dB
Group Delay
(Note 13)
GD
36
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 40.0kHz
±0.3
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SD bit=“0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
87.0
kHz
96.0
kHz
−6.0dB
Stopband
(Note 12)
SB
105
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
90
dB
Group Delay
(Note 13)
GD
36
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 80.0kHz
+0/−1
Note 12. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@±0.01dB), SB=0.546×fs.
Note 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of
both channels to input register to the output of analog signal.
MS1005-E-00
2008/10
-9-
[AK4399]
SHORT DELAY FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SD bit=“1”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
20.0
kHz
22.05
kHz
−6.0dB
Stopband
(Note 12)
SB
24.1
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
100
dB
Group Delay
(Note 13)
GD
7
1/fs
Digital Filter + SCF
dB
Frequency Response : 0 ∼ 20.0kHz
±0.2
SHORT DELAY FILTER CHARACTERISTICS (fs = 96kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SD bit=“1”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
43.5
kHz
48.0
kHz
−6.0dB
Stopband
(Note 12)
SB
52.5
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
95
dB
Group Delay
(Note 13)
GD
7
1/fs
Digital Filter + SCF
dB
Frequency Response : 0 ∼ 40.0kHz
±0.3
SHORT DELAY FILTER CHARACTERISTICS (fs = 192kHz)
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SD bit=“1”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 12) ±0.01dB
PB
0
87.0
kHz
96.0
kHz
−6.0dB
Stopband
(Note 12)
SB
105
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
90
dB
Group Delay
(Note 13)
GD
7
1/fs
Digital Filter + SCF
dB
Frequency Response : 0 ∼ 80.0kHz
+0/−1
MS1005-E-00
2008/10
- 10 -
[AK4399]
DC CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.4
Low-Level Input Voltage
VIL
VOH
High-Level Output Voltage
(Iout=−100μA)
DVDD−0.5
VOL
Low-Level Output Voltage
(Iout=100μA)
Input Leakage Current
(Note 14)
Iin
-
typ
-
max
0.8
0.5
±10
Units
V
V
V
V
μA
Note 14. The TST1/CAD0 and P/S pins have internal pull-up devices, nominally 100kΩ. Therefore The TST1/CAD0 and
P/S pins are not included.
MS1005-E-00
2008/10
- 11 -
[AK4399]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter
Symbol
Master Clock Timing
Frequency
Duty Cycle
LRCK Frequency
1152fs, 512fs or 768fs
256fs or 384fs
128fs or 192fs
Duty Cycle
PCM Audio Interface Timing
BICK Period
1152fs, 512fs or 768fs
256fs or 384fs
128fs or 192fs
BICK Pulse Width Low
BICK Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDATA Hold Time
SDATA Setup Time
(Note 16)
(Note 16)
(Note 17)
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
typ
max
Units
fCLK
dCLK
7.7
40
41.472
60
MHz
%
fsn
fsd
fsq
Duty
30
54
108
45
54
108
216
55
kHz
kHz
kHz
%
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/64fsd
1/64fsq
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
tB tBL
tBH
tBW
tWB
tWCK
tWCH
tDH
tDS
27
10
10
5
5
54
54
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDCK
tDCKL
tDCKH
tDDD
1/64fs
160
160
−20
ns
ns
ns
ns
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
tPD
150
ns
(Note 15)
External Digital Filter Mode
BICK Period
BCK Pulse Width Low
BCK Pulse Width High
BCK “↑” to WCK Edge
WCK Edge to BCK “↑”
WCK Pulse Width Low
WCK Pulse Width High
DATA Hold Time
DATA Setup Time
DSD Audio Interface Timing
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R
min
(Note 18)
MS1005-E-00
20
2008/10
- 12 -
[AK4399]
Note 15. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4399 should be reset by the
PDN pin or RSTN bit.
Note 16. BICK rising edge must not occur at the same time as LRCK edge.
Note 17. DSD data transmitting device must meet this time.
Note 18. The AK4399 can be reset by bringing the PDN pin “L” to “H” upon power-up.
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
1/fs
VIH
WCK
VIL
tB
VIH
BCK
VIL
tBH
tBL
Clock Timing
MS1005-E-00
2008/10
- 13 -
[AK4399]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDS
tSDH
VIH
SDATA
VIL
Audio Interface Timing (PCM Mode)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
MS1005-E-00
2008/10
- 14 -
[AK4399]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
CDTI
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
MS1005-E-00
2008/10
- 15 -
[AK4399]
tPD
PDN
VIL
Power Down & Reset Timing
VIH
WCK
VIL
tBW
tW B
VIH
BCK
VIL
tDS
tDH
VIH
DATA
VIL
External Digital Filter I/F mode
MS1005-E-00
2008/10
- 16 -
[AK4399]
OPERATION OVERVIEW
■ D/A Conversion Mode
In serial mode, the AK4399 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,
PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode is changed by D/P bit, the AK4399
should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4399 performs for
only PCM data.
DP bit
Interface
0
PCM
1
DSD
Table 1. PCM/DSD Mode Control
When DP bit= “0”, an internal digital filter or external digital filter can be selected. When using an external digital filter
(EX DF I/F mode), data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXD bit controls the modes. When
switching internal and external digital filters, the AK4399 must be reset by RSTN bit. A Digital filter switching takes
2~3k/fs.
Ex DF bit
Interface
0
PCM
1
EX DF I/F
Table 2. Digital Filter Control (DP bit = “0”)
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4399, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the initial master clock
is set to the appropriate frequency (Table 3). When external clocks are changed, the AK4399 should be reset by the PDN
pin or RSTN bit.
The AK4399 is automatically placed in reset state when MCLK and LRCK are stopped during a normal operation (PDN
pin =“H”), and the analog output becomes Hi-Z. When MCLK and LRCK are input again, the AK4399 exit reset state and
starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the AK4399 is in
power-down mode until MCLK and LRCK are supplied.
The MCLK frequency corresponding to each sampling speed should be provided (Table 4).
MCLK
1152fs
512fs
256fs
128fs
Mode
Normal
768fs
Normal
384fs
Double
192fs
Quad
Table 3. Sampling Speed
MS1005-E-00
Sampling Rate
30kHz~32kHz
30kHz~54kHz
30kHz~108kHz
108kHz~216kHz
2008/10
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[AK4399]
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
128fs
192fs
256fs
384fs
512fs
768fs
N/A
N/A
8.1920
12.2880
16.3840
24.5760
N/A
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
N/A
Table 4. System Clock Example (Parallel Control Mode) (N/A: Not available)
1152fs
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
MCLK= 256fs/384fs supports sampling rate of 30kHz~108kHz (Table 5). But, when the sampling rate is 30kHz~54kHz,
DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
MCLK
DR,S/N
256fs/384fs
120dB
512fs/768fs
123dB
Table 5. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
[2] DSD Mode
The external clocks, which are required to operate the AK4399, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
The AK4399 is automatically placed in reset state when MCLK is stopped during a normal operation (PDN pin =“H”),
and the analog output becomes Hi-Z. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations,
the AK4399 is in power-down mode until MCLK is supplied.
DCKS bit
0
1
MCLK Frequency
DCLK Frequency
512fs
64fs
768fs
64fs
Table 6. System Clock (DSD Mode)
MS1005-E-00
(default)
2008/10
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[AK4399]
■ Audio Interface Format
[1] PCM Mode
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and selected by the
DIF2-0 pins (Parallel control mode) or DIF2-0 bits (Serial control mode) as shown in Table 7. In all formats the serial data
is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20-bit and 16-bit
MSB justified formats by zeroing the unused LSBs. Settings should be made by DIF2-0 pins in parallel mode and DIF2-0
bits in serial mode.
Mode
0
1
2
3
4
5
6
7
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
Input Format
0
16bit LSB justified
1
20bit LSB justified
0
24bit MSB justified
1
24bit I2S Compatible
0
24bit LSB justified
1
32bit LSB justified
0
32bit MSB justified
1
32bit I2S Compatible
Table 7. Audio Interface Format
BICK
≥ 32fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 64fs
≥64fs
≥ 64fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Figure 5
Figure 6
Figure 7
(default)
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDATA
Mode 0
15
0
14
6
1
5
14
4
15
3
2
16
17
1
0
31
15
0
14
6
1
5
14
4
15
3
16
2
17
1
0
31
15
14
0
1
0
1
BICK
(64fs)
SDATA
Mode 0
Don’t care
15
14
Don’t care
0
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1/4 Timing
MS1005-E-00
2008/10
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[AK4399]
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDATA
23
22
1
0
Don’t care
23
22
0
1
Don’t care
23
22
0
1
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
BICK
(64fs)
SDATA
23
1
22
0
Don’t care
23
22
0
1
23
Don’t care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
0
1
BICK(128fs)
31
SDATA
0
1
2
12
13
14
23
1
24
0
31
31
0
1
2
12
13
14
23
1
24
0
31
BICK(64fs)
SDATA
31 30
20 19 18
9
8
1
0
31 30
Lch Data
20
19 18
9
8
1
0
31
Rch Data
31: MSB, 0:LSB
Figure 5. Mode 5 Timing
MS1005-E-00
2008/10
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[AK4399]
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK(128fs)
SDATA
31 30
0
1
12 11 10
2
12
13
0
14
31 30
23
24
31
0
1
12
2
11 10
12
13
0
14
31
23
24
31
0
1
BICK(64fs)
SDATA
31 30
20 19 18
8
9
0
1
31 30
20
19 18
Lch Data
8
9
0
1
31
Rch Data
31: MSB, 0:LSB
Figure 6. Mode 6 Timing
LRCK
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
0
1
24
25
31
0
1
BICK(128fs)
SDATA
31
0
1
13 12 11
2
12
13
0
14
31
24
25
31
0
1
13 12 11
2
12
0
13
14
BICK(64fs)
0
SDATA
31
21 20 19
8
9
1
2
0
31
21
20 19
Lch Data
9
8
2
1
0
Rch Data
31: MSB, 0:LSB
Figure 7. Mode 7 Timing
[2] DSD Mode
In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can
invert the polarity of DCLK.
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D1
D2
D3
D2
D3
Figure 8. DSD Mode Timing
MS1005-E-00
2008/10
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[AK4399]
[3] External Digital Filter Mode (EX DF I/F Mode)
DW indicates the number of BCK in one WCK cycle. The audio data is input by MCLK, BCK and WCK from the DINL
and DINR pins. Three formats are available (Table 9) by DIF2-0 bits setting. The data is latched on the rising edge of
BCK. The BCK and MCLK clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each
sampling speed are shown in Table 8.
The AK4399 is automatically placed in reset state when MCLK and WCK are stopped during a normal operation (PDN
pin =“H”), and the analog output becomes Hi-Z. When MCLK and WCK are input again, the AK4399 exit reset state and
starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the AK4399 is in
power-down mode until MCLK and WCK are supplied.
Sampling
Speed[kHz]
44.1(30~54)
44.1(30~54)
96(54~108)
96(54~108)
192(108~216)
192(108~216)
MCLK&BCK [MHz]
128fs
N/A
512fs
768fs
22.5792
33.8688
48
11.2896
32
16.9344
32
N/A
N/A
24.576
36.864
48
12.288
32
18.432
32
N/A
24.576
36.864
32
N/A
48
N/A
N/A
256fs
N/A
WCK
384fs
N/A
N/A
192fs
N/A
48
36.864
48
36.864
33.8688
96
N/A
N/A
N/A
N/A
96
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
96
Table 8 System Clock Example (EX DF I/F mode) (N/A: Not available)
16fs
DW
8fs
DW
8fs
DW
4fs
DW
4fs
DW
2fs
DW
ECS
0
1
0
1
0
1
Mode
DIF2
DIF1
DIF0
Input Format
0
0
0
0
16bit LSB justified
1
0
0
1
N/A
2
0
1
0
N/A
3
0
1
1
N/A
4
1
0
0
24bit LSB justified
5
1
0
1
32bit LSB justified
6
1
1
0
N/A
7
1
1
1
N/A
Table 9 Audio Interface Format (EX DF I/F mode) (N/A: Not available)
MS1005-E-00
2008/10
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[AK4399]
1/16fs or 1/8fs or 1/4fs or 1/2fs
WCK
0
1
8
9
10
11
16
17
26
27
28
29
30
31
0
1
BCK
DINL or
DINR
31
0
30
1
24 23
5
22
6
21
7
20
8
17
16
47
15
48
14
6
5
65
49
4
3
92
2
93
1
94
0
95
0
1
BCK
DINL or
DINR
Don’t care
0
1
Don’t care
5
6
7
Don’t care
8
23
24
31
17
25
2
3
44
45
1
46
0
47
on’t care
0
1
BCK
DINL or
DINR
Don’t care
Don’t care
Don’t care
31
3
2
1
0
Don’t care
Figure 9 EX DF I/F Mode Timing
MS1005-E-00
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[AK4399]
■ D/A Conversion Mode Switching Timing
RSTN bit
≥4/fs
D/A Mode
PCM Mode
DSD Mode
≥0
D/A Data
PCM Data
DSD Data
Figure 10. D/A Mode Switching Timing (PCM to DSD)
RSTN bit
D/A Mode
DSD Mode
PCM Mode
≥4/fs
D/A Data
DSD Data
PCM Data
Figure 11. D/A Mode Switching Timing (DSD to PCM)
Note. The signal range is identified as 25% ~ 75% duty ratios in DSD mode. DSD signal must not go beyond this duty
range at the SACD format book (Scarlet Book).
■ De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is enabled or
disabled with DEM1-0 pins or DEM1-0 bits. In case of 256fs/384fs and 128fs/192fs, the digital de-emphasis filter is
always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode are
switched.
DEM1
0
0
1
1
DEM0
Mode
0
44.1kHz
1
OFF
(default)
0
48kHz
1
32kHz
Table 10. De-emphasis Control
■ Output Volume
The AK4399 includes channel independent digital output volumes (ATT) with 255 levels at linear step including MUTE.
These volume control is in front of the DAC and it can attenuate the input data from 0dB to –127dB and mute. When
changing output levels, transitions are executed in soft change; thus no switching noise occurs during these transitions.
MS1005-E-00
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[AK4399]
■ Zero Detection (PCM mode, DSD mode)
The AK4399 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately return to “L”
if the input data of each channel is not zero after going to “H”. If the RSTN bit is “0”, the DZF pins of both channels go to
“H”. The DZF pins of both channels go to “L” at 4 ~ 5/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, the DZF
pins of both channels go to “H” only when the input data for both channels are continuously zeros for 8192 LRCK cycles.
The zero detect function can be disabled by setting the DZFE bit. In this case, DZF pins of both channels are always “L”.
The DZFB bit can invert the polarity of the DZF pin.
■ Mono Output
The AK4399 can select input/output for both output channels by setting the MONO bit and SELLR bit. This function is
available for any audio format.
MONO bit
0
0
1
1
SELLR bit
0
1
0
1
Lch Out
Lch In
Rch In
Lch In
Rch In
Rch Out
Rch In
Lch In
Lch In
Rch In
Table 11 MONO Mode Output Select
MS1005-E-00
2008/10
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[AK4399]
■ Soft Mute Operation
The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE bit set to “1”,
the output signal is attenuated by −∞ during ATT_DATA × ATT transition time from the current ATT level. When the
SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation
gradually changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before
attenuating −∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle.
The soft mute is effective for changing the signal source without stopping the signal transmission.
S M U T E pin or
S M U T E b it
(1 )
(1 )
AT T _ L e ve l
(3 )
A tte nu atio n
-∞
GD
(2 )
GD
(2 )
AO U T
D Z F pin
(4 )
81 92 /fs
Notes:
(1) ATT_DATA × ATT transition time. For example, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in
Normal Speed Mode.
(2) The analog output corresponding to the digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles, the DZF pin for each channel
goes to “H”. The DZF pin immediately returns to “L” if input data are not zero.
Figure 12. Soft Mute Function
■ System Reset
The AK4399 should be reset once by bringing the PDN pin = “L” upon power-up. It initializes register settings of the
device. The AK4399 exits this system reset (power-down mode) by MCLK and LRCK after the PDN pin = “H”, and the
analog block exits power-down mode. The digital block exits power-down mode after the internal counter counts MCLK
for 4/fs.
MS1005-E-00
2008/10
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[AK4399]
■ Power ON/OFF timing
The AK4399 is placed in the power-down mode by bringing the PDN pin “L” and the registers are initialized. the analog
outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN pin signal, the analog output should be
muted externally if the click noise influences system application.
The DAC can be reset by setting RSTN bit to “0”. In this case, the registers are not initialized and the corresponding
analog outputs go to VCML/R. As some click noise occurs at the edge of RSTN signal, the analog output should be muted
externally if click noise aversely affect system performance.
Power
PDN pin
(1)
Internal
State
Normal Operation
“0”data
(Digital)
“0”data
GD
DAC Out
(Analog)
(3)
Reset
(2)
(4)
GD
(4)
(3)
(5)
Clock In
MCLK,LRCK,BICK
Don’t care
Don’t care
(7)
DZFL/DZFR
External
Mute
(6)
Mute ON
Mute ON
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) Analog outputs are floating (Hi-Z) in power-down mode.
(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(6) Mute the analog output externally if click noise (3) adversely affect system performance
The timing example is shown in this figure.
(7) DZFL/R pins are “L” in the power-down mode (PDN pin = “L”).
Figure 13. Power-down/up Sequence Example
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[AK4399]
■ Reset Function
(1) RESET by RSTN bit = “0”
When the RSTN bit = “0”, the AK4399’s digital block is powered down, but the internal register values are not initialized.
In this time, the analog outputs go to VCML/R voltage and DZFL/DZFR pins are “H”. Figure 14 shows an example of
reset by RSTN bit.
RSTN bit
3~4/fs (5)
2 ~3 /fs (5)
In ternal
RSTN bit
In ternal
Stat e
Normal Operation
P
D/ A In
(Dig ital)
“0 ” data
(1)
D/ A Out
(Ana log )
Normal O peration
D igital Block
GD (1)
GD
(3)
(2)
(3)
2/ fs(4 )
DZF
(6)
Notes:
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs settle to VCOM voltage.
(3) Small pop noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0”
data is input.
(4) The DZF pins change to “H” when the RSTN bit becomes “0”, and return to “L” at 2/fs after RSTN bit becomes
“1”.
(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN bit “1”.
(6) Mute the analog output externally if click noise (3) and Hi-Z (2) adversely affect system performance
Figure 14. Reset Sequence Example 1
MS1005-E-00
2008/10
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[AK4399]
(2) RESET by MCLK or LRCK/WCK Stop
The AK4399 is automatically placed in reset state when MCLK or LRCK is stopped during PDM mode (RSTN pin
=“H”), and the analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4399 exits reset state
and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped. In DSD mode the AK4399 is in
reset state when MCLK is stopped, and it is in reset state when MCLK and WCK are stopped in external digital filter
mode.
AVDD pin
DVDD pin
RSTB pin
(1)
In ternal
Stat e
Power-down
D/ A In
(Dig ital)
Power-down
Normal O peration
Digital Circuit P ower-down
Normal Operation
(3)
GD (2)
D/A Out
(Analog)
GD (2)
(4)
Hi-Z
(5)
(4 )
(4)
(5)
Cl ock In
MCLK, BICK, LRC K Stop
MCLK , BICK, LRCK
Externa l
MUTE
(6)
(6)
(6)
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) The digital data can be stopped. Click noise after MCLK, BICK and LRCK are input again can be reduced by
inputting “0” data during this period.
(4) Click noise occurs within 3 ~ 4LRCK cycles from the riding edge (“↑”) of the PDN pin or MCLK inputs. This
noise occurs even when “0” data is input.
(5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset state (MCLK or LRCK is stopped).
(6) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown
in this figure.
Figure 15. Reset Sequence Example 2
MS1005-E-00
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[AK4399]
■ Register Control Interface
Pins (parallel control mode) or registers (serial control mode) can control the functions of the AK4399. In parallel control
mode, the register setting is ignored, and in serial control mode the pin settings are ignored. When the state of the PSN pin
is changed, the AK4399 should be reset by the PDN pin. The serial control interface is enabled by the PSN pin = “L”. In
this mode, pin settings must be all “L”. Internal registers may be written to through3-wire µP interface pins: CSN, CCLK
and CDTI. The data on this interface consists of Chip address (2-bits, C1/0), Read/Write (1-bit; fixed to “1”), Register
address (MSB first, 5-bits) and Control data (MSB first, 8-bits). The AK4399 latches the data on the rising edge of CCLK,
so data should be clocked in on the falling edge. The writing of data is valid when CSN “↑”. The clock speed of CCLK is
5MHz (max).
Function
Parallel Control Mode Serial Control Mode
Audio Format
Y
Y
De-emphasis
Y
Y
SMUTE
Y
Y
DSD Mode
Y
EX DF I/F
Y
Short delay Filter
Y
Digital Attenuator
Y
Table 12. Function List1 (Y: Available, -: Not available)
Setting the PDN pin to “L” resets the registers to their default values. In serial control mode, the internal timing circuit is
reset by the RSTN bit, but the registers are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 16. Control I/F Timing
* The AK4399 does not support the read command.
* When the AK4399 is in power down mode (PDN pin = “L”) or the MCLK is not provided, a writing into the control
registers is prohibited.
* The control data can not be written when the CCLK rising edge is 15 times or less or 17 times or more during CSN is
“L”.
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[AK4399]
Function List
Function
Attenuation Level
Default
0dB
Address
03H
04H
00H
00H
00H
01H
01H
01H
01H
01H
02H
02H
Bit
ATT7-0
External Digital Filter I/F Mode
Disable
EXDF
Ex DF I/F mode clock setting
16fs(fs=44.1kHz)
ESC
Audio Data Interface Modes
24bit MSB justified
DIF2-0
Data Zero Detect Enable
Disable
DZFE
Data Zero Detect Mode
Separated
DZFM
Short delay Filter Enable
Sharp roll-off filter
SD
De-emphasis Response
OFF
DEM1-0
Soft Mute Enable
Normal Operation
SMUTE
DSD/PCM Mode Select
PCM mode
DP
Master Clock Frequency Select at
512fs
DCKS
DSD mode
MONO mode Stereo mode select
Stereo
02H
MONO
Inverting Enable of DZF
“H” active
02H
DZFB
The data selection of L channel and R channel
02H
SELLR
R channel
Table 13. Function List2 (Y: Available, -: Not available)
MS1005-E-00
PCM
DSD
Ex DF I/F
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
-
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
-
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[AK4399]
■ Register Map
Addr
00H
01H
02H
03H
04H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
D7
0
DZFE
DP
ATT7
ATT7
D6
EXDF
DZFM
0
ATT6
ATT6
D5
ECS
SD
DCKS
ATT5
ATT5
D4
0
0
DCKB
ATT4
ATT4
D3
DIF2
0
MONO
ATT3
ATT3
D2
DIF1
DEM1
DZFB
ATT2
ATT2
D1
DIF0
DEM0
SELLR
ATT1
ATT1
D0
RSTN
SMUTE
0
ATT0
ATT0
Notes:
Data must not be written into addresses from 05H to 1FH.
When the PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default
values.
When the state of the PSN pin is changed, the AK4399 should be reset by the PDN pin.
■ Register Definitions
Addr Register Name
00H Control 1
Default
D7
0
1
D6
EXDF
0
D5
ECS
0
D4
0
0
D3
DIF2
0
D2
DIF1
1
D1
DIF0
0
D0
RSTN
1
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized.
1: Normal Operation (default)
When internal clocks are changed, the AK4399 should be reset by the PDN pin or RSTN bit.
DIF2-0: Audio Data Interface Modes (Table 7)
Initial value is “010” (Mode 2: 24-bit MSB justified).
ECS: Ex DF I/F mode clock setting (Table 8)
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
EXDF: External Digital Filter I/F Mode (Serial mode only)
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
DIF2-0: Audio Data Interface Modes (Table 7)
Initial value is “010” (Mode2: 24bit MSB justified)
MS1005-E-00
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[AK4399]
Addr Register Name
01H Control 2
Default
D7
DZFE
0
D6
DZFM
0
D5
SD
0
D4
0
0
D3
0
0
D2
DEM1
0
D1
DEM0
1
D0
SMUTE
0
SMUTE: Soft Mute Enable
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM1-0: De-emphasis Response (Table 10)
Initial value is “01” (OFF).
SD:
Short delay Filter Enable
0: Sharp roll-off filter (default)
1: Short delay filter
DZFM:
Data Zero Detect Mode
0: Channel Separated Mode (default)
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
DZFE:
Data Zero Detect Enable
0: Disable (default)
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.
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[AK4399]
Addr Register Name
02H Control 3
Default
D7
DP
0
D6
0
0
D5
DCKS
0
D4
DCKB
0
D3
MONO
0
D2
DZFB
0
D1
SELLR
0
D0
0
0
SELLR: The data selection of L channel and R channel, when MONO mode
0: All channel output R channel data, when MONO mode. (default)
1: All channel output L channel data, when MONO mode.
It is enabled when MONO bit is “1”, and outputs Rch date to both channels when “0”,outputs Lch data to
both channels when “1”.
DZFB: Inverting Enable of DZF
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
When MONO bit is “1”, MONO mode is enabled.
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP:
DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When D/P bit is changed, the AK4399 should be reset by RSTN bit.
Addr Register Name
03H Lch ATT
04H Rch ATT
Default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
ATT7-0: Attenuation Level
256 levels, 0.5dB step
Data
FFH
FEH
FDH
:
:
02H
01H
00H
Attenuation
0dB
-0.5dB
-1.0dB
:
:
-126.5dB
-127.0dB
MUTE (-∞)
The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from
FFH (0dB) to 00H (MUTE). If the PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH
when RSTN bit= “0”. When RSTN return to “1”, the ATTs fade to their current value. This digital attenuator is
independent of soft mute function.
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[AK4399]
SYSTEM DESIGN
Figure 17 shows the system connection diagram. Figure 19, Figure 20 and Figure 21 show the analog output circuit
examples. The evaluation board (AKD4399) demonstrates the optimum layout, power supply arrangements and
measurement results.
Master clock
Analog5.0V
Digital 5.0V
+
10u
10u
+
+
34
Lch
LPF
AOUTLP
VCML 35
NC 36
NC 37
NC 38
NC 39
VSS3 40
AVDD 41
VSS4 43
0.1u
10u
+
MCLK 42
NC 44
0.1u
1
DVDD
Reset & PD
64fs
2
PDN
VSS2 32
3
BICK
VDDL 31
Audio Data
4
SDATA
fs
5
LRCK
6
CSN
7
CAD0
8
CCLK
9
CDTI
MicroController
AOUTLN
VREFLL 29
0.1u
10u
+
+
10u
0.1u
NC 28
VREFLR 27
VREFHR 26
Top View
0.1u
VSS1 24
11 DZFL
22 AOUTRP
21 VCMR
20 NC
19 DINL
18 DINR
17 NC
16 BCK
15 DZFR
14 PSN
13 NC
12 DIF2
AOUTRN
+
10u
10u
+
+
VDDR 25
10 CAD1
Digital
Lch Out
33
VREFHL 30
AK4399EQ
Lch
Mute
0.1u
10u
23
Rch
LPF
Rch
Mute
Rch Out
Analog
+
Electrolytic Capacitor
Ceramic Capacitor
Notes:
- Chip Address = “00”. BICK = 64fs, LRCK = fs
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc.
- VSS1-4 must be connected to the same analog ground plane.
- When AOUT drives a capacitive load, some resistance should be connected in series between AOUT and the
capacitive load.
- All input pins except pull-down/pull-up pins should not be allowed to float.
Figure 17. Typical Connection Diagram (AVDD=VDDL/R=5V, DVDD=5V, Serial control mode)
MS1005-E-00
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[AK4399]
AOUTL P 34
NC 36
VCML 35
NC 37
NC 38
NC 39
VS S3 40
AVDD 41
DVDD
PDN
VSS2
32
3
BICK/DCLK
VDDL
31
4
SDATA/DSDL
VREFHL
30
5
LRCK/DSDR/W CK
6
SMUTE/CSN
AK4399EQ
VREFLL
29
NC
28
VREFLR
27
7
DFS0 /CAD0
8
DEM0/CCLK
9
DEM1/CDTI
VDDR
25
10 DIF0/CAD1
VSS1
24
VREFHR 26
22 AOUTRP
21 VCMR
20 NC
19 DINL
18 DINR
AOUTRN 23
17 NC
14 PSN
13 NC
12 DIF2
11 DIF1/ DZFL
16 BCK
Controller
AOUTLN 33
1
2
15 A CKS/DZFR
System
MCLK 42
NC 44
Analog Ground
VSS4 43
Digital Ground
Figure 18. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and DVDD
respectively. AVDD and VDDL/R are supplied from analog supply in system and DVDD is supplied from digital supply in
system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately from the point with low impedance of
regulator etc. The power up sequence between AVDD, VDDL/R and DVDD is not critical. VSS1-4 must be
connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as
possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin is
normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R
should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency
noise. No load current may be drawn from VCML/R pin. All signals, especially clocks, should be kept away from the
VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4399.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R − VREFLL/R = 5V) centered around
AVDD/2. The differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−. If
the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive
full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for
000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Figure 19 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 20 shows an example of differential outputs and LPF circuit example by three op-amps.
MS1005-E-00
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[AK4399]
AK43 99
2.4k
AOUT-
2.4k
150
680p
+ Vop
3.3n
2.4k
AOU T+
Analog
Out
150
2.4k
680p
-Vop
Figure 19. External LPF Circuit Example 1 for PCM (fc = 125kHz, Q=0.692)
Frequency Response
Gain
20kHz
−0.012dB
40kHz
−0.083dB
80kHz
−0.799dB
Table 14. Frequency Response of External LPF Circuit Example 1 for PCM
+15
3.3n
+
180
10k
AOUTL- +
330
0.1u
7
3
2 +
4
3.9n
-15
10u
6
NJM5534D
+
10u
620
620
3.3n
+
100u
+
330
3
+
2 -
3.9n
2 - 4
6
+
3
7
1.0n
100
Lch
NJM5534D
10u
0.1u
7
6
0.1u
4
NJM5534D
+
+
10u
10u
0.1u
1.2k
10k
AOUTL+
180
+10u
1.0n
1.2k
680
0.1u
560
0.1u
560
100u
680
Figure 20. External LPF Circuit Example 2 for PCM
1st Stage
2nd Stage
Total
Cut-off Frequency
182kHz
284kHz
Q
0.637
Gain
+3.9dB
-0.88dB
+3.02dB
20kHz
-0.025
-0.021
-0.046dB
Frequency
40kHz
-0.106
-0.085
-0.191dB
Response
80kHz
-0.517
-0.331
-0.848dB
Table 15. Frequency Response of External LPF Circuit Example 2 for PCM
MS1005-E-00
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[AK4399]
It is recommended for SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass
filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4399 can achieve this filter
response by combination of the internal filter (Table 16) and an external filter (Figure 21).
Frequency
Gain
20kHz
−0.4dB
50kHz
−2.8dB
100kHz
−15.5dB
Table 16. Internal Filter Response at DSD Mode
2.0k
1.8k
4.3k
AOUT1.0k
270p
2.8Vpp
2200p
+Vop
3300p
2.0k
1.8k
1.0k
+
AOUT+
2.8V pp
4.3k
270p
Analog
Out
6.34Vpp
-Vop
Figure 21. External 3rd Order LPF Circuit Example for DSD
Frequency
Gain
20kHz
−0.05dB
50kHz
−0.51dB
100kHz
−16.8dB
DC gain = 1.07dB
Table 17. 3rd Order LPF (Figure 21) Response
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[AK4399]
PACKAGE
■ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS1005-E-00
2008/10
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[AK4399]
MARKING
AK4399EQ
XXXXXXX
AKM
1
1) Pin #1 indication
2) AKM Logo
3) Date Code: XXXXXXX(7 digits)
4) Marking Code: AK4399
5) Audio 4 pro Logo
REVISION HISTORY
Date (YY/MM/DD)
08/10/20
Revision
00
Reason
First Edition
Page
MS1005-E-00
Contents
2008/10
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[AK4399]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or
strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or
distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS1005-E-00
2008/10
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工商网监
湘ICP备2023018690号
