[AK4421A]
AK4421A
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4421A is 3.3V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4421A delivers a wide dynamic range while
preserving linearity for improved THD+N performance. The AK4421A integrates a combination of
switched-capacitor and continuous-time filters, increasing performance for systems with excessive clock
jitter. The 24-bit word length and 192kHz sampling rate make this part ideal for a wide range of consumer
audio applications, such as portable A/V players, set-top boxes, and digital televisions. The AK4421A is
offered in a space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
Switched-Capacitor Filter with High Tolerance to Clock Jitter
Single Ended 2Vrms Output Buffer
Soft mute
I/F format: 24-Bit MSB justified or I2S
Master clock: 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
128fs or 192fs (Quad Speed Mode)
THD+N: -92dB
Dynamic Range: 102dB
Automatic Power-on Reset Circuit
Power supply: +3.0 ∼ +3.6V
Ta = -20 to 85°C
Small Package: 16pin TSSOP (6.4mm x 5.0mm)
MCLK
SMUTE
DIF
VDD
Clock
Divider
Control
Interface
DZF
VSS1
LRCK
BICK
SDTI
Audio
Data
Interface
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
AOUTL
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
AOUTR
Charge
Pump
CP
CN
2.2 μ
MS1086-E-01
VEE
VSS2
CVDD
2.2μ
2009/09
-1-
[AK4421A]
■ Ordering Guide
-20 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4421A
AK4421AET
AKD4421A
■ Pin Layout
CN
1
16
VEE
CP
2
15
VSS2
SMUTE
3
14
CVDD
MCLK
4
13
DZF
BICK
5
12
VSS1
SDTI
6
11
VDD
LRCK
7
10
AOUTL
DIF
8
9
AOUTR
AK4421A
Top
View
Compatibility with AK4420, AK4421, AK4424, AK4423 and AK4421A
Power Supply
Digital de-emphasis
I/F format
Pin#3
Pin out
Pin#8
THD+N
DR
Operating
Temperature
AK4420
AK4424
AK4421
+4.5 ∼ +5.5V
+4.5 ∼ +5.5V
+3.0 ∼ +3.6V
X
24-bit MSB/I²S
I²S
24-bit MSB/I²S
SMUTE
DEM
SMUTE
DIF
SMUTE
DIF
-92dB
-92dB
-92dB (-3dBFS)
105dB
105dB
102dB
ET: -20 ∼ +85°C
VT: -40 ∼
ET: -20 ∼ +85°C ET: -20 ∼ +85°C
+85°C
AK4421A
+3.0 ∼ +3.6V
24-bit MSB/I²S
SMUTE
DIF
-92dB
102dB
AK4423
+3.0 ∼ +3.6V
X
I²S
SMUTE
DEM
-92dB
102dB
ET: -20 ∼ +85°C
ET: -20 ∼ +85°C
-: Not available
X: Available
MS1086-E-01
2009/09
-2-
[AK4421A]
PIN/FUNCTION
No.
Pin Name
I/O
Function
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 2.2μF low ESR (Equivalent Series Resistance) capacitor
1
CN
I
over temperature. When this capacitor is polarized, the positive polarity pin
should be connected to the CP pin. Non-polarized capacitors can also be
used.
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 2.2μF low ESR (Equivalent Series Resistance)
2
CP
I
capacitor over temperature. When this capacitor is polarized, the positive
polarity pin should be connected to the CP pin. Non-polarized capacitors can
also be used.
Soft Mute Enable Pin (Internal pull down: 100kΩ)
3
SMUTE
I
“H”: Enable, “L”: Disable
4
MCLK
I
Master Clock Input Pin
5
BICK
I
Audio Serial Data Clock Pin
6
SDTI
I
Audio Serial Data Input Pin
7
LRCK
I
L/R Clock Pin
Audio Data Interface Format Pin (Internal pull up: 100kΩ)
8
DIF
I
“L”: 24-bit MSB Justified, “H”: I2S
Right channel Analog Output Pin
9
AOUTR
O
When power down, outputs VSS voltage (0V, typ).
Left channel Analog Output Pin
10
AOUTL
O
When power down, outputs VSS voltage (0V, typ).
11
VDD
DAC Power Supply Pin, 3.0V∼3.6V
12
VSS1
Ground Pin 1
13
DZF
O
Zero Input Detect Pin
14
CVDD
Charge Pump Power Supply Pin, 3.0V∼3.6V
15
VSS2
Ground Pin 2
Negative Voltage Output Pin
Connect to VSS2 with a 2.2μF low ESR capacitor over temperature. When
16
VEE
O
this capacitor is polarized, the positive polarity pin should be connected to
the VSS2 pin. Non-polarized capacitors can also be used.
Note: All input pins except for the SMUTE and DIF pins should not be left floating.
MS1086-E-01
2009/09
-3-
[AK4421A]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
CVDD
IIN
VIND
Ta
Tstg
Input Current (Note 3)
Input Voltage
Ambient Operating Temperature
Storage Temperature
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 connect to the same analog ground.
Note 3. SMUTE, MCLK, BICK, SDTI, LRCK and DIF pins.
min
-0.3
-0.3
-0.3
-20
-65
max
+6.0
+6.0
±10
VDD+0.3
85
150
Units
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
CVDD
min
+3.0
typ
+3.3
VDD
max
+3.6
Units
V
Note 4. CVDD should be equal to VDD.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1086-E-01
2009/09
-4-
[AK4421A]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +3.3V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥10kΩ, unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
24
Bits
THD+N
fs=44.1kHz, BW=20kHz
-92
-84
dB
fs=96kHz, BW=40kHz
-92
dB
fs=192kHz, BW=40kHz
-92
dB
Dynamic Range (-60dBFS with A-weighted, Note 6)
96
102
dB
S/N (A-weighted, Note 7)
96
102
dB
Interchannel Isolation (1kHz)
90
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
DC Accuracy
DC Offset (at output pin)
-40
0
40
mV
Gain Drift
100
ppm/°C
Output Voltage (Note 8)
1.85
2.0
2.15
Vrms
Load Capacitance (Note 9)
25
pF
Load Resistance
10
kΩ
Power Supplies
Power Supply Current: (Note 10)
14
21
mA
Normal Operation (fs≤96kHz)
16
24
mA
Normal Operation (fs=192kHz)
10
100
Power-Down Mode (Note 11)
μA
Note 5. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 6. 98dB for 16-bit input data
Note 7. S/N does not depend on input data size.
Note 8. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD:
AOUT (typ.@0dB) = 2Vrms × VDD/3.3.
Note 9. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load.
Note 10. The current into VDD and CVDD.
Note 11. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD. (The SMUTE and
DIF pins are not included)
MS1086-E-01
2009/09
-5-
[AK4421A]
FILTER CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +3.0 ∼ +3.6V; fs = 44.1 kHz)
Parameter
Symbol
min
typ
max
Units
Digital filter
PB
0
20.0
kHz
Passband
±0.05dB (Note 12)
22.05
kHz
–6.0dB
Stopband (Note 12)
SB
24.1
kHz
Passband Ripple
PR
dB
± 0.02
Stopband Attenuation
SA
54
dB
Group Delay (Note 13)
GD
19.3
1/fs
Digital Filter + LPF
Frequency Response
fs=44.1kHz, 20.0kHz
FR
dB
± 0.05
fs=96kHz, 40.0kHz
FR
dB
± 0.05
fs=192kHz, 80.0kHz
FR
dB
± 0.05
Note 12. The passband and stopband frequencies scale with fs (system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 13. Calculated delay time caused by the digital filter. This time is measured from setting the 16/24bit data
of both channels to input register to the output of the analog signal.
DC CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +3.0 ∼ +3.6V)
Parameter
Symbol
min
typ
max
Units
High-Level Input Voltage
VIH
70%VDD
V
Low-Level Input Voltage
VIL
30%VDD
V
High-Level Output Voltage (Iout = -80uA)
VOH
VDD-0.4
V
Low-Level Output Voltage (Iout = 80uA)
VOL
0.4
V
Input Leakage Current (Note 14)
Iin
± 10
μA
Note 14. The SMUTE and DIF pins are not included. The SMUTE pin has an internal pull-down resistor (typ.100kΩ).
The DIF pin has an internal pull-up resistor (typ.100kΩ).
MS1086-E-01
2009/09
-6-
[AK4421A]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +3.0 ∼ +3.6V)
Parameter
Symbol
min
fCLK
4.096
Master Clock Frequency
dCLK
40
Duty Cycle
LRCK Frequency
8
fsn
Normal Speed Mode
32
fsd
Double Speed Mode
120
fsq
Quad Speed Mode
45
Duty
Duty Cycle
Audio Interface Timing
BICK Period
tBCK
1/128fsn
Normal Speed Mode
tBCK
1/64fsd
Double Speed Mode
tBCK
1/64fsq
Quad Speed Mode
tBCKL
30
BICK Pulse Width Low
tBCKH
30
Pulse Width High
tBLR
20
BICK “↑” to LRCK Edge (Note 15)
tLRB
20
LRCK Edge to BICK “↑” (Note 15)
tSDH
20
SDTI Hold Time
tSDS
20
SDTI Setup Time
Note 15. BICK rising edge must not occur at the same time as LRCK edge.
MS1086-E-01
typ
max
36.864
60
Units
MHz
%
48
96
192
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
2009/09
-7-
[AK4421A]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 1. Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Figure 2. Serial Interface Timing
MS1086-E-01
2009/09
-8-
[AK4421A]
OPERATION OVERVIEW
■ System Clock
The external clocks required to operate the AK4421A are MCLK, LRCK, and BICK. The master clock (MCLK) should
be synchronized with LRCK, but the phase is not critical. The MCLK is used to operate the digital interpolation filter and
the delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically, and then the internal master
clock is set to the appropriate frequency (Table 1).
The AK4421A is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal
operation mode, and the analog output goes to 0V(typ). When MCLK, LRCK and BICK are input again, the AK4421A is
powered up. After exiting reset following power-up, the AK4421A is not fully operational until MCLK, LRCK and BICK
are input.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
-
192fs
-
22.5792
24.5760
33.8688
36.8640
256fs
8.192
11.2896
12.288
22.5792
24.5760
-
MCLK (MHz)
384fs
512fs
16.3840
22.5792
24.5760
12.288
16.9344
18.432
33.8688
36.8640
-
768fs
24.5760
33.8688
36.8640
1152fs
36.8640
-
-
-
Sampling
Speed
Normal
Double
Quad
Table 1. System Clock Example
When MCLK= 256fs/384fs, the Auto Setting Mode supports sampling rate of 32kHz~96kHz (Table 1). But, when the
sampling rate is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK=
512fs/768fs (Table 2).
MCLK
DR,S/N
256fs/384fs
99dB
512fs/768fs
102dB
Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
■ Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The DIF pin can select between two serial
data modes as shown in Table 3. In all modes the serial data is MSB-first, two’s complement format and it is latched on
the rising edge of BICK. In one cycle of LRCK, eight “H” pulses or more must not be input to the DIF pin.
Mode
0
1
DIF
L
H
SDTI Format
24bit MSB justified
24bit I2S
BICK
≥48fs
≥48fs
Figure
Figure 3
Figure 4
Table 3. Audio Data Formats
MS1086-E-01
2009/09
-9-
[AK4421A]
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
0
1
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 0 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 1 Timing
MS1086-E-01
2009/09
- 10 -
[AK4421A]
■ Zero Detect Function
When the input data for both channels are continuously zero for 8192 LRCK cycles, the DZF pin goes to “H”. The DZF
pin immediately returns to “L” if the input data for both channels are not zero.
■ Analog Output Block
The internal negative power supply generation circuit (Figure 5) provides a negative power supply for the internal 2Vrms
amplifier. It allows the AK4421A to output an audio signal centered at VSS (0V, typ) as shown in Figure 6. The negative
power generation circuit (Figure 5) needs 2.2uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). If this
capacitor is polarized, the positive polarity pin should be connected to the CP and VSS2 pins. This circuit operates by
clocks generated from MCLK. When MCLK stops, the AK4421A is placed in reset mode automatically and the analog
outputs settle to VSS (0V, typ).
AK4421A
CVDD
Charge
Pump
CP
Negative Power
CN
VSS2
(+)
2.2uF
Ca
VEE
Cb
2.2uF
(+)
Figure 5. Negative Power Generation Circuit
AK4421A
2Vrms
0V
AOUTR
(AOUTL)
Figure 6. Audio Signal Output
MS1086-E-01
2009/09
- 11 -
[AK4421A]
■ Soft Mute Operation
Soft mute operation is performed in the digital domain. When the SMUTE pin is set “H”, the output signal is attenuated to
-∞ in 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting
this operation, the attenuation is discontinued and it is returned to 0dB by the same cycle. Soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE pin
1024/fs
0dB
1024/fs
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) The time for input data attenuation to -∞ is :
Normal Speed Mode: 1024 LRCK cycles (1024/fs).
Double Speed Mode: 2048 LRCK cycles (2048/fs).
Quad Speed Mode : 4096 LRCK cycles (4096/fs).
(2) The analog output corresponding to a specific digital input has a group delay, GD.
(3) If soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level in the same cycle.
(4) When the input data for both channels are continuously zero for 8192 LRCK cycles, the DZF pin goes to “H”. The
DZF pin immediately returns to “L” if the input data are not zero.
Figure 7. Soft Mute and Zero Detect Function
MS1086-E-01
2009/09
- 12 -
[AK4421A]
■ System Reset
The AK4421A is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped
up. The AK4421A is in power-down mode until LRCK are input.
Power Supply
(VDD, CVDD)
(6)
MCLK
Low
20 us
Analog
Circuit
Digital
Circuit
Charge Pump
Circuit
(1)
Power down
Power down
(2)
Power-up
2, 3
LRCK
Power down
Power-up
Power-up
(3)
Charge Pump
Time A
Counter circuit
D/A In
(Digital)
“0” data
D/A Out
(Analog)
DZF
MUTE (D/A Out)
(4)
(5)
Notes:
(1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up.
(2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK.
(3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A = 1024/ (fs x 16): Normal speed mode
Time A = 1024/ (fs x 8): Double speed mode
Time A = 1024/ (fs x 4): Quadruple speed mode
(4) No audible click noise occurs under normal conditions.
(5) The DZF pin is “L” in the power-down mode.
(6) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power
supply voltage achieves 80% of VDD. If not, click noise may occur at a different time from this figure.
Figure 8. System Reset Diagram
MS1086-E-01
2009/09
- 13 -
[AK4421A]
■ Reset Function
When the MCLK or LRCK stops, the AK4421A is placed in reset mode and its analog outputs are set to VSS (0V, typ).
When the MCLK and LRCK are restarted, the AK4421A returns to normal operation mode.
Internal
State
Normal Operation
Reset
D/A In
(Digital)
Normal Operation
(1)
GD
D/A Out
(Analog)
(3)
VSS
(2)
(3)
Clock In
MCLK, BICK, LRCK
(4) MCLK Stop
DZF
(5)
Clock In
(4)
MCLK, BICK, LRCK
LRCK Stop
(5)
DZF
Clock In
(4) BICK Stop
MCLK, BICK, LRCK
(5)
DZF
Notes:
(1) Digital data can be stopped. The click noise after MCLK, LRCK and BICK are input again can be reduced by
inputting the “0” data during this period.
(2) The analog output corresponding to a specific digital input has group delay (GD).
(3) No audible click noise occurs under normal conditions.
(4) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK, LRCK or BICK is stopped).
(5) The DZF pin is set to “L” in the reset mode.
Figure 9. Reset Timing Example
MS1086-E-01
2009/09
- 14 -
[AK4421A]
SYSTEM DESIGN
Figure 10 shows the system connection diagram. An evaluation board (AKD4421A) is available for fast evaluation as
well as suggestions for peripheral circuitry.
1
CN
VEE 16
2
CP
VSS2 15
3
SMUTE
Master Clock
4
MCLK
64fs
5
BICK
24bit Audio Data
6
SDTI
fs
7
LRCK
AOUTL 10
8
DIF
AOUTR
2.2u (1)
ModeSetting
Digital Ground
+
CVDD 14
DZF 13
AK4421A
VSS1 12
VDD 11
9
Analog
3.3V
2.2u (1)
+
0.1u
+ 10u
10Ω
External Mute Circuits
0.1u
+ 10u
Lch Out
Rch Out
Analog Ground
Note:
Use low ESR (Equivalent Series Resistance) capacitors. When using polarized capacitors, the positive polarity pin
should be connected to the CP and VSS2 pin.
VSS1 and VSS2 should be separated from digital system ground.
Digital input pins should not be allowed to float.
Figure 10. Typical Connection Diagram
MS1086-E-01
2009/09
- 15 -
[AK4421A]
1. Grounding and Power Supply Decoupling
VDD, CVDD and VSS are supplied from the analog supply and should be separated from the system digital supply.
Decoupling capacitors, especially 0.1μF ceramic capacitors for high frequency bypass, should be placed as near to VDD
and CVDD as possible. The differential voltage between VDD and VSS pins set the analog output range. The power-up
sequence between VDD and CVDD is not critical.
2. Analog Outputs
The analog outputs are single-ended and centered around the VSS (ground) voltage. The output signal range is typically
2.0Vrms (typ @VDD=3.3V). The internal switched-capacitor filter (SCF) and continuous-time filter (CTF) attenuate the
noise generated by the delta-sigma modulator beyond the audio passband. Using a 1st-order LPF (Figure 11) can reduce
noise beyond the audio passband.
The output voltage is positive full scale for 7FFFFFH (@24-bit data) and negative full scale for 800000H (@24-bit
data). The ideal output is 0V (VSS) for 000000H (@24bit). The DC offset is ±40mV or less.
AK4421A
560
AOUT
R
Analog
Out
C
2.2nF
2.00Vrms (typ)
(fc = 129kHz, gain = -0.4dB @ 40kHz, gain = -1.4dB @ 80kHz)
Figure 11. External 1st order LPF Circuit Example
MS1086-E-01
2009/09
- 16 -
[AK4421A]
PACKAGE
16pin TSSOP (Unit: mm)
1.1 (max)
*5.0±0.1
16
9
8
1
0.13
M
6.4±0.2
*4.4±0.1
A
0.65
0.22±0.1
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy, Halogen (bromine and chlorine) free
Cu
Solder (Pb free) plate
MS1086-E-01
2009/09
- 17 -
[AK4421A]
MARKING
AKM
4421AET
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4421AET
Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD)
09/07/03
09/09/17
Revision
00
01
Reason
First Edition
Error Correction
Page
Contents
2
Compatibility table was changed.
Pin #8, AK4421A: DEM → DIF
Pin #8, AK4423: DIF → DEM
Note 3 was changed. DEM was deleted.
4
MS1086-E-01
2009/09
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[AK4421A]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use
of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from
any and all claims arising from the use of said product in the absence of such notification.
MS1086-E-01
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工商网监
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