AK4432
108dB 192kHz 32bit 2-Channel Audio DAC
1. General Description
The AK4432 is a 32-bit Stereo DAC which corresponds to digital audio systems. An internal circuit
includes 32-bit Digital Filter achieving short group delay and high quality sound. The AK4432 has single
end SCF outputs, increasing performance for systems with excessive clock jitter. The AK4432 is ideal
for a wide range of applications that demands high sound quality including Home Theater and Car
audio surround systems. It is housed in a 16-pin TSSOP package, saving more board space.
2. Features
1. 2ch 32bit DAC
- 128 times Oversampling
- 32-bit High Quality Sound Low Group Delay Digital Filter
- Single Ended Output, Smoothing Filter
- THD+N: 91dB
- DR, S/N: 108dB
- Channel Isolation Digital Volume (12dB to -115dB, 0.5dB Step, Mute)
- Soft Mute
- Audio I/F Format: MSB justified, LSB justified, I2S, TDM
2. Sampling Frequency
- Normal Speed Mode:
8kHz to 48kHz
- Double Speed Mode:
48kHz to 96kHz
- Quad Speed Mode:
96kHz to 192kHz
3. Master Clock
256fs, 384fs, 512fs or 768fs
(Normal Speed Mode: fs=8kHz to 48kHz)
256fs or 384fs
(Double Speed Mode: fs=48kHz to 96kHz)
128fs or 192fs
(Quad Speed Mode: fs=96kHz to 192kHz)
4. P Interface: 3-wire Serial (7MHz max)
I2C bus (Fast Mode: 400kHz, Fast Mode Plus: 1MHz)
5. Power Supply
- Analog: AVDD = 3.0 to 3.6V
- Input/Output Buffer: LVDD = 3.0 to 3.6V
- Integrated LDO for Digital Power Supply
6. Power Consumption: 7.8mA (fs=48kHz)
7. Operational Temperature: Ta = - 40 to 105°C
8. Package: 16-pin TSSOP (0.65mm pitch)
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3. Table of Contents
1.
2.
3.
4.
General Description ............................................................................................................................ 1
Features .............................................................................................................................................. 1
Table of Contents ................................................................................................................................ 2
Block Diagram and Functions ............................................................................................................. 3
◼ Block Diagram ................................................................................................................................. 3
◼ Compatibility with AK4438, AK4452 and AK4458 ........................................................................... 4
5. Pin Configurations and Functions ....................................................................................................... 5
◼ Pin Configurations ........................................................................................................................... 5
◼ Functions ......................................................................................................................................... 6
◼ Handling of Unused Pin................................................................................................................... 6
6. Absolute Maximum Ratings ................................................................................................................ 7
7. Recommended Operating Conditions................................................................................................. 7
8. Analog Characteristics ........................................................................................................................ 8
9. Filter Characteristics ........................................................................................................................... 9
◼ Sharp Roll-Off Filter (DASD bit = “0”, DASL bit = “0”) ..................................................................... 9
◼ Slow Roll-Off Filter (DASD bit = “0”, DASL bit = “1”) ..................................................................... 10
◼ Short Delay Sharp Roll-Off Filter (DASD bit = “1”, DASL bit = “0”) ................................................11
◼ Short Delay Slow Roll-Off Filter (DASD bit = “1”, DASL bit = “1”)................................................. 12
10.
DC Characteristics......................................................................................................................... 13
11.
Switching Characteristics .............................................................................................................. 13
◼ Clock Timing .................................................................................................................................. 13
◼ Audio Interface Timing................................................................................................................... 14
◼ Serial Interface Timing................................................................................................................... 15
◼ Timing Diagram ............................................................................................................................. 16
12.
Functional Descriptions ................................................................................................................. 19
◼ System Clocks ............................................................................................................................... 19
◼ Audio Interface Format .................................................................................................................. 21
◼ Data Slot and Data Select ............................................................................................................. 26
◼ Digital Volume Function................................................................................................................. 27
◼ Soft Mute Operation ...................................................................................................................... 28
◼ Error Detection .............................................................................................................................. 28
◼ System Reset ................................................................................................................................ 28
◼ Power Down Function ................................................................................................................... 29
◼ Power Off Functions ...................................................................................................................... 30
◼ Clock Synchronization ................................................................................................................... 31
◼ Parallel Mode................................................................................................................................. 32
◼ Serial Control Interface.................................................................................................................. 33
◼ Register Map ................................................................................................................................. 38
◼ Register Definitions ....................................................................................................................... 38
13.
Recommended External Circuits................................................................................................... 40
14.
Package ......................................................................................................................................... 42
◼ Outline Dimensions ....................................................................................................................... 42
◼ Material & Lead Finish................................................................................................................... 42
◼ Marking .......................................................................................................................................... 43
15.
Ordering Guide .............................................................................................................................. 43
16.
Revision History............................................................................................................................. 44
IMPORTANT NOTICE .......................................................................................................................... 46
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4. Block Diagram and Functions
◼
Block Diagram
PDN
AOUTL
SMF
SCF
DAC
DVOL
AOUTR
SMF
SCF
DAC
DVOL
MCLK
Audio
I/F
LRCK
BICK
SDTI
VSS
AVDD
REF
Internal Reference
Voltage
SMUTE/CSN/I2CFIL
Supply for Internal
Digital Circuit
VCOM
P I/F
(I2C/SPI)
ACKS/CCLK/SCL
DIF/CDTI/SDA
P/S
LDO
LDOO
LVDD
Figure 1. Block Diagram
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[AK4432]
◼
Compatibility with AK4438, AK4452 and AK4458
Channel
Sampling Frequency fs
S/(N+D)
Dynamic Range
AVDD (Analog Supply)
TVDD or LVDD (Digital Supply)
Stopband Attenation
(Sharp Roll-off)
Group Delay
Digital
(Sharp Roll-off)
Filter
Group Delay
(Short Delay Slow Roll-off)
Super Slow Roll-off
OSR Doubler
(Over Sampling)
Zero Detection
Digital Volume
Attenation Level Transition Time
between Max. Gain and Mute
(*: default)
LR Ch Output Select
Reset Function (MCLK detect)
Clock Synchronization
De-emphasis
Package
AK4432
2ch
8k to 192kHz
91dB
108dB
3.0 to 3.6V
3.0 to 3.6V
AK4436 / 38
6ch / 8ch
8k to 768kHz
91dB
108dB
3.0 to 3.6V
1.7 to 3.6V
AK4452 / 54 / 56 / 58
2ch / 4ch / 6ch / 8ch
8k to 768kHz
107dB
115dB
3.0 to 5.5V
1.7 to 3.6V
69.9dB
80dB
80dB
26.4/fs
26.8/fs
26.8/fs
5.2/fs
4.8/fs
4.8/fs
No
No
(128x)
No
+12 to -115.0dB
No
No
Yes (Note)
No
Yes
Yes
(256x)
Yes
+0 to -127.0dB
4080/fs*
2040/fs
510/fs
255/fs
Yes
Yes
Yes
Yes
16-pin TSSOP
32-pin QFN
4080/fs
1020/fs*
Yes
Yes
(256x)
Yes
+0 to -127.0dB
4080/fs*
2040/fs
510/fs
255/fs
Yes
Yes
Yes
Yes
AK4452/54: 32-pin QFN
AK4456/58: 48-pin QFN
Note. MSB justified and 32-bit I2S compatible formats are available for audio interface but LSB justified
format is not available.
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[AK4432]
5. Pin Configurations and Functions
◼
Pin Configurations
MCLK
1
16
LDOO
BICK
2
15
LVDD
SDTI
3
14
AVDD
LRCK
4
13
VSS
PDN
5
12
VCOM
SMUTE/CSN/I2CFIL
6
11
AOUTL
ACKS/CCLK/SCL
7
10
AOUTR
DIF/CDTI/SDA
8
9
P/S
AK4432
Top
View
Figure 2. Pin Layout
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[AK4432]
Functions
◼
No.
Pin
Name
MCLK
BICK
SDTI
LRCK
I/O
Function
Master Clock Input Pin
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
Input Channel Clock Pin
Power-Down & Reset Pin
5
PDN
I
Input “L”
When “L”, the AK4432 is powered-down and the control
registers are reset to default state.
Soft Mute Pin in Parallel Control mode.
SMUTE
I
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
6
Hi-z
CSN
I
Chip Select Pin in 3-wire Serial Control mode
I2C Interface Mode Select Pin
I2CFIL
I
“L”: Fast Mode (400kHz), “H”: Fast Mode Plus (1MHz).
Do not change this pin during PDN pin = “H”.
Auto Setting Mode Select Pin in Parallel Control mode
ACKS
I
“L”: Manual Setting mode, “H”: Auto Setting mode
7
Hi-z
CCLK
I
Control Data Clock Input Pin in 3-wire Serial Control mode
SCL
I
Control Data Clock Input Pin in I2C Bus Serial Control mode
Audio Data Format Select Pin in Parallel Control mode.
DIF
I
“L”: 32bit MSB Justified, “H”: 32bit I2S Compatible
8
Hi-z
CDTI
I
Control Data Input Pin in 3-wire Serial Control mode
SDA
I/O
Control Data Input/Output Pin in I2C Bus Serial Control mode
Parallel/Serial Mode Select Pin
9
P/S
I
Hi-z
“L”: Serial Mode, “H”: Parallel Mode
Do not change this pin during PDN pin = “H”.
10 AOUTR
O
Hi-z
Rch Analog Output Pin
11 AOUTL
O
Hi-z
Lch Analog Output Pin
Common Voltage Output Pin, AVDDx1/2
500ohm
12 VCOM
O
Large external capacitor around 2.2µF is used to reduce
Pull-down
power-supply noise.
13 VSS
Ground Pin
14 AVDD
Analog Power Supply Pin, 3.0V to 3.6V
15 LVDD
LDO and Digital I/F Power Supply Pin, 3.0V to 3.6V
580ohm
LDO Output Pin
16 LDOO
O
Pull-down
This pin should be connected to ground with 1.0µF.
Note 1. All digital input pins must not be allowed to float.
1
2
3
4
◼
I
I
I
I
State at
Power Down
Hi-z
Hi-z
Hi-z
Hi-z
Handling of Unused Pin
Handle unused I/O pins as follows.
Classification
Analog
Pin Name
AOUTL, AOUTR
Setting
Open
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[AK4432]
6. Absolute Maximum Ratings
(VSS =0V; Note 2)
Parameter
Power Supply
Power Supply
Input Current (any pins except for supplies)
Input Voltage
(Note 3)
Symbol
AVDD
LVDD
IIN
VIN
Min.
-0.3
-0.3
-0.3
Max.
Unit
4.3
V
4.3
V
mA
10
(LVDD+0.3) or
V
4.3
Ambient Temperature (power applied)
Ta
-40
105
C
Storage Temperature
Tstg
-65
150
C
Note 2. All voltages with respect to ground. VSS must be connected to the analog ground plane.
Note 3. The maximum Digital input voltage is smaller value between (LVDD+0.3)V and 4.3V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(VSS=0V; Note 2)
Parameter
Power Supplies
Analog
Symbol
AVDD
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
LDO, Digital (I/F)
LVDD
3.0
3.3
3.6
V
Note 4. There are no restrictions on the power-up order of AVDD and LVDD. Do not turn off the power
supply of the AK4432 with the power supply of the peripheral device turned on. The AK4432's
SDA and SCL pins are connected to LVDD with internal protection diodes. When the LVDD pin
goes to 0V, the SDA and SCL pins will be shorted to 0V through protection diodes, and as a
result other devices on the I2C bus will not be able to communicate. When using the I2C
interface, pull-up resistors of SDA and SCL pins should be connected to LVDD or less voltage.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
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[AK4432]
8. Analog Characteristics
(Ta=25C; AVDD = LVDD=3.3V; VSS =0V; fs=48kHz, 96kHz, 192kHz; BICK=64fs; Signal
Frequency=1kHz; 32bit Data; Measurement Frequency=20Hz to 20kHz at fs=48kHz, 20Hz to 40kHz at
fs=96kHz, 20Hz to 40kHz at fs=192kHz, unless otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
DAC Analog Output Characteristics
Resolution
32
bit
Output Voltage (Note 5)
2.55
2.83
3.11
Vpp
S/(N+D)
fs=48kHz
80
91
dB
(0dBFS)
fs=96kHz
89
dB
fs=192kHz
89
dB
Dynamic Range
fs=48kHz
(A-weighted)
108
dB
(-60dBFS)
fs=96kHz
101
dB
fs=192kHz
101
dB
S/N
fs=48kHz
(A-weighted)
108
dB
fs=96kHz
101
dB
fs=192kHz
101
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0
0.7
dB
Load Resistance (Note 6)
10
k
Load Capacitance
30
pF
Note 5. Full-scale output voltage. The output voltage is always proportional to AVDD (AVDD x 0.86).
Note 6. AC Load
Parameter
Power Supplies Current
Normal Operation (PDN pin = “H”)
AVDD
fs=48kHz, 96kHz, 192kHz
LVDD
fs=48kHz
fs=96kHz
fs=192kHz
Min.
Typ.
Max.
Unit
-
6.5
1.3
1.6
2.1
9.0
2
2.5
3.0
mA
mA
mA
mA
Power-down mode (PDN pin = “L”) (Note 7)
10
200
Note 7. Quiescent Current. All digital input pins including clock pins are fixed to VSS.
µA
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9. Filter Characteristics
(Ta= -40 to +105C; AVDD =3.0 to 3.6V, LVDD=3.0 to 3.6V)
◼
Sharp Roll-Off Filter (DASD bit = “0”, DASL bit = “0”)
fs=48kHz
Parameter
-0.08dB to +0.08dB
Passband
(Note 8)
-6.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response : 0Hz to 20kHz
fs=96kHz
Parameter
-0.08dB to +0.08dB
Passband
(Note 8)
-6.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response : 0Hz to 40kHz
fs=192kHz
Parameter
-0.08dB to +0.08dB
Passband
(Note 8)
-6.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response : 0Hz to 80kHz
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.08
26.2
69.9
-
Typ.
23.99
26.4
Max.
22.2
+0.08
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-0.20
-
0.10
dB
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.08
52.5
69.8
-
Typ.
48.00
26.4
Max.
44.4
+0.08
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-0.50
-
0.10
dB
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.08
104.9
69.8
-
Typ.
96.00
26.4
Max.
88.8
+0.08
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-2.00
-
0.00
dB
Note 8. The passband and stopband frequencies are proportional to “fs” (sampling rate). Each
frequency response refers to that of 1kHz.
Note 9. The calculated delay time caused by digital filtering. The digital filter’s delay is calculated as the
time from setting 16/24/32bit impulse data into the input register until an analog peak signal is
output.
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[AK4432]
◼
Slow Roll-Off Filter (DASD bit = “0”, DASL bit = “1”)
fs=48kHz
Parameter
-0.07dB to +0.021dB
Passband
(Note 8)
-3.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response: 0Hz to 20kHz
fs=96kHz
Parameter
-0.07dB to +0.023dB
Passband
(Note 8)
-3.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response: 0Hz to 40kHz
fs=192kHz
Parameter
-0.07dB to +0.023dB
Passband
(Note 8)
-3.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response: 0Hz to 80kHz
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.07
42.6
72.6
-
Typ.
19.75
26.4
Max.
9.0
+0.021
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-3.75
-
-2.75
dB
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.07
85.1
72.6
-
Typ.
39.6
26.4
Max.
18.1
+0.023
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-4.25
-
-2.75
dB
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.07
170.3
72.6
-
Typ.
79.3
26.4
Max.
36.1
+0.023
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-5.00
-
-3.00
dB
Note 8. The passband and stopband frequencies are proportional to “fs” (sampling rate). Each
frequency response refers to that of 1kHz.
Note 9. The calculated delay time caused by digital filtering. The digital filter’s delay is calculated as the
time from setting 16/24/32bit impulse data into the input register until an analog peak signal is
output.
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[AK4432]
◼
Short Delay Sharp Roll-Off Filter (DASD bit = “1”, DASL bit = “0”)
fs=48kHz
Parameter
-0.07dB to +0.07dB
Passband
(Note 8)
-6.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response : 0Hz to 20kHz
fs=96kHz
Parameter
-0.08dB to +0.08dB
Passband
(Note 8)
-6.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response : 0Hz to 40kHz
fs=192kHz
Parameter
-0.08dB to +0.08dB
Passband
(Note 8)
-6.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response : 0Hz to 80kHz
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.07
26.2
56.6
-
Typ.
24.11
5.9
Max.
22.0
+0.07
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-0.20
-
0.10
dB
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.08
52.5
56.4
-
Typ.
48.25
5.9
Max.
44.3
+0.08
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-0.50
-
0.10
dB
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.08
104.9
56.4
-
Typ.
96.50
5.9
Max.
88.6
+0.08
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-2.00
-
0.00
dB
Note 8. The passband and stopband frequencies are proportional to “fs” (sampling rate). Each
frequency response refers to that of 1kHz.
Note 9. The calculated delay time caused by digital filtering. The digital filter’s delay is calculated as the
time from setting 16/24/32bit impulse data into the input register until an analog peak signal is
output.
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[AK4432]
◼
Short Delay Slow Roll-Off Filter (DASD bit = “1”, DASL bit = “1”)
fs=48kHz
Parameter
-0.07dB to +0.05dB
Passband
(Note 8)
-3.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response : 0Hz to 20kHz
fs=96kHz
Parameter
-0.07dB to +0.05dB
Passband
(Note 8)
-3.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response : 0Hz to 40kHz
fs=192kHz
Parameter
-0.07dB to +0.05dB
Passband
(Note 8)
-3.0dB
Passband Ripple
Stopband
(Note 8)
Stopband Attenuation
Group Delay
(Note 9)
Digital Filter + SCF + SMF
Frequency Response : 0Hz to 80kHz
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.07
43.0
74.9
-
Typ.
20.24
5.2
Max.
10.1
+0.05
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-3.50
-
-2.50
dB
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.07
86.0
74.9
-
Typ.
40.50
5.2
Max.
20.3
+0.05
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-4.00
-
-2.50
dB
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-0.07
172.0
74.9
-
Typ.
81.00
5.2
Max.
40.6
+0.05
-
Unit
kHz
kHz
dB
kHz
dB
1/fs
FR
-4.75
-
-2.75
dB
Note 8. The passband and stopband frequencies are proportional to “fs” (sampling rate). Each
frequency response refers to that of 1kHz.
Note 9. The calculated delay time caused by digital filtering. The digital filter’s delay is calculated as the
time from setting 16/24/32bit impulse data into the input register until an analog peak signal is
output.
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[AK4432]
10. DC Characteristics
(Ta= -40 to +105C; AVDD =3.0 to 3.6V, LVDD =3.0 to 3.6V, VSS=0V)
Parameter
Symbol
Min.
All digital input pins except SCL and SDA pins
High-Level Input Voltage
VIH1
80%LVDD
Low-Level Input Voltage
VIL1
SCL, SDA Pin
High-Level Input Voltage
VIH2
70%LVDD
Low-Level Input Voltage
VIL2
SDA Pin
Low-Level Output Voltage
Fast Mode
(Iout= 3mA)
VOL1
Fast Mode Plus
(Iout= 20mA)
VOL2
Input Leakage Current
Iin
-
Typ.
Max.
Unit
-
20%LVDD
V
V
-
30%LVDD
V
V
-
0.4
0.4
10
V
V
A
11. Switching Characteristics
◼
Clock Timing
(Ta=-40 to 105C; AVDD=LVDD=3.0 to 3.6V; CL=20pF, unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Max.
Master Clock Timing
256fsn
Frequency
fCLK
2.048
12.288
Pulse Width Low
tCLKL
32
Pulse Width High
tCLKH
32
384fsn
Frequency
fCLK
3.072
18.432
Pulse Width Low
tCLKL
22
Pulse Width High
tCLKH
22
512fsn, 256fsd, 128fsq
Frequency
fCLK
4.096
24.576
Pulse Width Low
tCLKL
16
Pulse Width High
tCLKH
16
768fsn, 384fsd, 192fsq
Frequency
fCLK
16.384
36.864
Pulse Width Low
tCLKL
11
Pulse Width High
tCLKH
11
LRCK Timing
Stereo mode (TDM1-0 bits = “00”)
Frequency (fs)
Normal Speed mode fsn
8
48
Double Speed mode fsd
48
96
Quad Speed mode
fsq
96
192
Duty Cycle
Duty
50
TDM128 mode (TDM1-0 bits = “01”)
Frequency (fs)
Normal Speed mode fsn
8
48
Double Speed mode fsd
48
96
Quad Speed mode
fsq
96
192
I2S compatible: Pulse Width Low
tLRL
1/(128fs)
127/(128fs)
MSB or LSB justified: Pulse Width High tLRH
1/(128fs)
127/(128fs)
TDM256 mode (TDM1-0 bits = “10”, “11”)
Frequency (fs)
Normal Speed mode fsn
8
48
Double Speed mode fsd
48
96
I2S compatible: Pulse Width Low
tLRL
1/(256fs)
255/(256fs)
MSB or LSB justified: Pulse Width High tLRH
1/(256fs)
255/(256fs)
015002029-E-02
Unit
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
kHz
kHz
%
kHz
kHz
kHz
s
s
kHz
kHz
s
s
2023/03
- 13 -
[AK4432]
◼
Audio Interface Timing
(Ta=-40 to 105C; AVDD=LVDD=3.0 to 3.6V; CL=20pF, unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Audio Interface Timing
Normal mode (TDM1-0 bits = “00”)
BICK Period
Normal Speed mode
tBCK
1/256fsn
Double Speed mode
tBCK
1/256fsd
Quad Speed mode
tBCK
1/128fsq
BICK Pulse Width Low
tBCKL
18
BICK Pulse Width High
tBCKH
18
BICK “” to LRCK Edge
(Note 10) tBLR
5
5
LRCK Edge to BICK “”
(Note 10) tLRB
tSDH
5
SDTI Hold Time
tSDS
5
SDTI Setup Time
TDM128 mode (TDM1-0 bits = “01”)
BICK Period
Normal Speed mode
tBCK
1/128fsn
Double Speed mode
tBCK
1/128fsd
Quad Speed mode
tBCK
1/128fsq
BICK Pulse Width Low
tBCKL
18
BICK Pulse Width High
tBCKH
18
BICK “” to LRCK Edge
(Note 10) tBLR
5
5
LRCK Edge to BICK “”
(Note 10) tLRB
tSDH
5
SDTI Hold Time
tSDS
5
SDTI Setup Time
TDM256 mode (TDM1-0 bits = “10”, “11”)
BICK Period
Normal Speed mode
tBCK
1/256fsn
Double Speed mode
tBCK
1/256fsd
BICK Pulse Width Low
tBCKL
18
BICK Pulse Width High
tBCKH
18
BICK “” to LRCK Edge
(Note 10) tBLR
5
tLRB
5
LRCK Edge to BICK “”
(Note 10)
tSDH
5
SDTI Hold Time
tSDS
5
SDTI Setup Time
Note 10. BICK rising edge must not occur at the same time as LRCK edge.
015002029-E-02
Max.
Unit
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
ns
ns
ns
ns
ns
ns
ns
ns
2023/03
- 14 -
[AK4432]
◼
Serial Interface Timing
(Ta=-40 to 105C; AVDD=LVDD=3.0 to 3.6V; CL=20pF, unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Max. Unit
3-wire Serial mode
CCLK frequency
tCCK
7
MHz
CCLK Pulse Width Low
tCCKL
60
ns
Pulse Width High
tCCKH
60
ns
CDTI Setup Time
tCDS
60
ns
CDTI Hold Time
tCDH
60
ns
CSN “H” Time
tCSW
150
ns
tCSS
150
ns
CSN “” to CCLK “”
tCSH
240
ns
CCLK “” to CSN “”
I2C Fast mode
kHz
SCL Clock Frequency
fSCL
400
s
Bus Free Time Between Transmissions
tBUF
1.3
s
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
s
Clock Low Time
tLOW
1.3
s
Clock High Time
tHIGH
0.6
s
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
(Note 11)
tHD:DAT
0
s
SDA Setup Time from SCL Rising
tSU:DAT
0.1
s
Rise Time of Both SDA and SCL Lines
tR
1.0
s
Fall Time of Both SDA and SCL Lines
tF
0.3
s
Setup Time for Stop Condition
tSU:STO
0.6
s
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
50
ns
pF
Capacitive load on bus
Cb
400
I2C Fast mode Plus
MHz
SCL Clock Frequency
fSCL
1
s
Bus Free Time Between Transmissions
tBUF
0.5
s
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.26
s
Clock Low Time
tLOW
0.5
s
Clock High Time
tHIGH
0.26
s
Setup Time for Repeated Start Condition
tSU:STA
0.26
SDA Hold Time from SCL Falling
(Note 12)
tHD:DAT
0
s
SDA Setup Time from SCL Rising
tSU:DAT
0.05
s
Rise Time of Both SDA and SCL Lines
tR
0.12
s
Fall Time of Both SDA and SCL Lines
tF
0.12
s
Setup Time for Stop Condition
tSU:STO
0.26
s
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
50
ns
pF
Capacitive load on bus
Cb
550
Power-down & Reset Timing
PDN Pulse Width
(Note 13)
tPD
800
ns
Note 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 12. Data must be held for sufficient time to bridge the 120ns transition time of SCL.
Note 13. The AK4432 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must
held “L” for more than 800ns for a certain reset. The AK4432 is not reset by the “L” pulse less
than 50ns.
Note 14. I2C is a trademark of NXP B.V.
015002029-E-02
2023/03
- 15 -
[AK4432]
◼
Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
LRCK
VIL
tdLRKH
tdLRKL
Duty
= tdLRKH (or tdLRKL) x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 3. Clock Timing (TDM1-0 bits = “00”)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 4. Clock Timing (Except TDM1-0 bits = “00”)
015002029-E-02
2023/03
- 16 -
[AK4432]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Figure 5. Audio Interface Timing (TDM1-0 bits = “00”)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (Except TDM1-0 bits = “00”)
VIH
VIL
CCLK
tCCKL
tCCKH
1/fCCK
1/fCCK
Figure 7. 3-wire Serial Mode Interface Timing
015002029-E-02
2023/03
- 17 -
[AK4432]
VIH
VIL
tCSW
CSN
VIH
CDTI
VIL
tCDS
tCDH
VIH
VIL
CCLK
tCSS
tCSH
tCSS
tCSH
Figure 8. WRITE Data Input Timing (3-wire Serial mode)
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
Start
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 9. I2C Bus Mode Timing
tPD
VIH
PDN
VIL
Figure 10. Power-down & Reset Timing
015002029-E-02
2023/03
- 18 -
[AK4432]
12. Functional Descriptions
◼
System Clocks
The external clocks which are required to operate the AK4432 are MCLK, LRCK and BICK. MCLK
should be synchronized with LRCK and BICK but the phase is not critical. There are two methods to set
sampling frequency. ACKS bit = “0” for manual setting mode and ACKS bit = “1” for auto setting mode.
In manual setting mode, the sampling speed mode is set by DFS1-0 bits (Table 1). Table 2, Table 3 and
Table 4 show the MCLK frequencies that can be used in each sampling speed mode. In auto setting
mode, DFS1-0 bits do not need to be set. Sampling speed mode is automatically detected. The DFS1-0
bits setting is ignored. Table 5 and Table 6 show the MCLK frequencies that can be used in each
sampling speed mode.
The internal reset is released by inputting MCLK and LRCK after setting the PDN pin to “H”. If the clock
is stopped, a click noise occurs when restarting the clock. Mute the digital output externally if the click
noise affects system applications.
DFS1
bit
0
0
1
1
LRCK Freq.
fs
8.0kHz
44.1kHz
48.0kHz
DFS0
bit
0
1
0
1
Sampling Speed Mode (fs)
(default)
8kHz to 48kHz
48kHz to 96kHz
96kHz to 192kHz
(N/A: Not available)
Table 1. Sampling Speed Mode (Manual Setting Mode)
256fs
2.0480
11.2896
12.2880
Normal Speed mode
Double Speed mode
Quad Speed mode
N/A
MCLK Frequency [MHz]
384fs
512fs
3.0720
4.0960
16.9344
22.5792
18.4320
24.5760
768fs
6.1440
33.8688
36.8640
BICK Freq. [MHz]
64fs
0.512
2.8224
3.0720
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK Freq.
fs
88.2kHz
96.0kHz
MCLK Frequency [MHz]
256fs
384fs
22.5792
33.8688
24.5760
36.8640
BICK Freq. [MHz]
64fs
5.6448
6.1440
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK Freq.
fs
176.4kHz
192.0kHz
MCLK Frequency [MHz]
128fs
192fs
22.5792
33.8688
24.5760
36.8640
BICK Freq. [MHz]
64fs
11.2896
12.2880
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
015002029-E-02
2023/03
- 19 -
[AK4432]
Sampling Speed Mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
MCLK Frequency
512fs
768fs
256fs
384fs
128fs
192fs
Table 5. Sampling Speed Mode and Available MCLK Frequency (Auto Setting Mode)
LRCK
MCLK Frequency [MHz]
Sampling
Speed Mode
fs
128fs
192fs
256fs
384fs
512fs
768fs
8.0kHz
4.0960 6.1440
44.1kHz
22.5792 33.8688 Normal Speed Mode
48.0kHz
24.5760 36.8640
88.2kHz
22.5792 33.8688
Double Speed Mode
96.0kHz
24.5760 36.8640
176.4kHz 22.5792 33.8688
Quad Speed Mode
192.0kHz 24.5760 36.8640
(-: Not available)
Table 6. System Clock Example (Auto Setting Mode)
015002029-E-02
2023/03
- 20 -
[AK4432]
◼
Audio Interface Format
Audio data is shifted in via the SDTI pin using BICK and LRCK inputs. The audio data is latched on the
rising edge of BICK. The serial data is MSB first, 2's complement. Data format is selected by the TDM10 bits and DIF2-0 bits as shown in Table 7. Input “0” data to unused bits if the data does not use
maximum bits when MSB justified, I2S format is selected. (e.g. Mode2 can be used in 16-bit MSB
justified by zeroing the unused 8bits LSB). TDM1-0 bits, DIF2-0 bits, SDS2-0 bits and DIF pin settings
should not be changed during operation.
Normal Mode (TDM1-0 bit=“00”)
Two channels audio data is shifted in via the SDTI pin. Eight data formats are supported.
TDM128 Mode (TDM1-0 bit=“01”)
Four channels audio data is shifted in via the SDTI pin. Two channel data is selected by SDS1-0 bits.
BICK is fixed to 128fs. Six data formats are supported.
TDM256 Mode (TDM1-0 bit=“1X”)
Eight channels audio data is shifted in via the SDTI pin. Two channel data is selected by SDS1-0 bits.
BICK is fixed to 256fs. Six data formats are supported.
TDM1 TDM0
bit
bit
Mode
0
1
2
Normal
(Note 15)
TDM128
TDM256
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0
0
0
1
1
x
DIF2
bit
0
0
0
DIF1
bit
0
0
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DIF0
SDTI Input Data
bit
Format
0
16-bit LSB justified
1
20-bit LSB justified
0
24-bit MSB justified
16-bit I2S compatible
1
24-bit I2S compatible
0
24-bit LSB justified
1
32-bit LSB justified
0
32-bit MSB justified
1
32-bit I2S compatible
0
N/A
1
N/A
0
24-bit MSB justified
1
24-bit I2S compatible
0
24-bit LSB justified
1
32-bit LSB justified
0
32-bit MSB justified
1
32-bit I2S compatible
0
N/A
1
N/A
0
24-bit MSB justified
1
24-bit I2S compatible
0
24-bit LSB justified
1
32-bit LSB justified
0
32-bit MSB justified
1
32-bit I2S compatible
LRCK
Polarity
H/L
H/L
H/L
L/H
BICK
Frequency
32fs
40fs
48fs
32fs
L/H
H/L
H/L
H/L
L/H
48fs
48fs
64fs
64fs
64fs
128fs
128fs
128fs
128fs
128fs
128fs
128fs
128fs
256fs
256fs
256fs
256fs
256fs
256fs
256fs
256fs
(N/A: Not available, x: “0” or “1”)
Note 15. BICK that is input to each channel must be longer than the bit length of setting format. For
16-bit I2S compatibility, set BICK to 16 clocks per channel.
Table 7. Audio Data Format
015002029-E-02
2023/03
- 21 -
[AK4432]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
14
6
1
0
5
14
4
15
3
16
2
1
17
0
31
15
0
14
6
5
14
1
4
15
3
16
2
1
17
0
31
15
14
0
1
0
1
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
Don’t care
0
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 11. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 12. Mode 1/4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDTI
23
22
1
0
Don’t care
23
22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 13. Mode 2 Timing
015002029-E-02
2023/03
- 22 -
[AK4432]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
23
0
1
22
Don’t care
23
22
0
1
23
Don’t care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 14. Mode 3 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDTI
Mode 5,6
31
30
1
0
31
30
0
1
31
30
32:MSB, 0:LSB
Lch Data
Rch Data
Figure 15. Mode 5/6 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
0
31
2
3
23
24
25
31
0
1
0
31
BICK
(64fs)
SDTI
31
30
1
30
1
30
32:MSB, 0:LSB
Lch Data
Rch Data
Figure 16. Mode 7 Timing
015002029-E-02
2023/03
- 23 -
[AK4432]
128 BICK
LRCK
BICK(128fs)
SDTI
Mode8
23 22
SDTI
Mode11,12
31 30
0
23 22
0
0 31 30
23 22
23 22
0
0 31 30
0
0 31 30
23 22
0 31 30
2
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
Figure 17. Mode 8/11/12 Timing
128 BICK
LRCK
BICK(128fs)
SDTI
Mode9
23 22
SDTI
Mode13
31 30
0
0
23 22
0
23 22
0 31 30
23 22
0 31 30
L1
R1
32 BICK
32 BICK
23
0
0 31 30
2
0 31 30
L2
R2
32 BICK
32 BICK
Figure 18. Mode 9/13 Timing
128 BICK
LRCK
BICK(128fs)
SDTI
23 22
0
23 22
0
23 22
0
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 19. Mode 10 Timing
015002029-E-02
2023/03
- 24 -
[AK4432]
256 BICK
LRCK
BICK (256fs)
SDTI
Mode14
SDTI
Mode17,18
23 22
0
31 30
23 22
0
23 22
0 31 30
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0
0 31 30
23 22
0 31 30
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
23
Figure 20. Mode 14/17/18 Timing
256 BICK
LRCK
BICK (256fs)
SDTI
Mode15
SDTI
Mode19
23
0
23
31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
23
0 31 30
0
0 31 30
0
0 31 30
0
0 31 30
23
0 31
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 21. Mode 15/19 Timing
256 BICK
LRCK
BICK(256fs)
SDTI
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0
23
Figure 22. Mode 16 Timing
015002029-E-02
2023/03
- 25 -
[AK4432]
◼
Data Slot and Data Select
Data slots for each input mode are assigned as follows. For TDM128 or TDM256, select the data slot to
be played back with SDS1-0 bits.
LRCK
SDTI
L1
R1
Figure 23. Data Slot in Normal mode
128 BICK
LRCK
SDTI
L1
R1
L2
R2
Figure 24. Data Slot in TDM128 mode
256 BICK
LRCK
SDTI
L1
R1
L2
R2
L3
R3
L4
R4
Figure 25. Data Slot in TDM256 mode
Input Mode
Normal
TDM128
TDM256
SDS1
bit
SDS0
bit
Lch Slot
Rch Slot
L1
R1
x
0
L1
R1
x
1
L2
R2
0
0
L1
R1
0
1
L2
R2
1
0
L3
R3
1
1
L4
R4
(x: don’t care)
Table 8. Data Slot Select
x
x
015002029-E-02
2023/03
- 26 -
[AK4432]
◼
Digital Volume Function
The AK4432 has channel-independent digital volume (256 levels, 0.5dB steps). Attenuation level of each
channel can be set by ATTL/R7-0 bits, respectively (Table 9).
Lch
Rch
Attenuation Level
ATTL7-0 bits
ATTR7-0 bits
00h
00h
+12.0dB
01h
01h
+11.5dB
02h
02h
+11.0dB
:
:
:
17h
17h
+0.5dB
18h
18h
0.0dB
19h
19h
-0.5dB
:
:
:
FDh
FDh
-114.5dB
FEh
FEh
-115.0dB
FFh
FFh
MUTE (-∞)
Table 9. Attenuation level of Digital Volume
(default)
When ATTL/R7-0 bits are changed, the attenuation level changes by 0.125dB every fixed time and
reaches the new attenuation level (soft transition). This suppresses switching noise when changing the
attenuation level. The time it takes for the attenuation level to change by 0.125dB can be selected with
the ATS bit (Table 10).
Mode
ATS bit
0
1
0
1
Transition Time
between 00h and FFh
0.125dB per 1/fs
1020/fs
0.125dB per 4/fs
4080/fs
Table 10. Transition time of attenuation level
Attenation Transition Speed
(default)
The transition time from 00h (+12dB) to FFh (MUTE) is 255 0.5dB / 0.125dB 1/fs = 1020/fs in
Mode0 and 255 0.5dB / 0.125dB 4/fs = 4080/fs in Mode1.
Mode
0
1
Transition Time between 00h and FFh
1/fs units
fs=48kHz
fs=44.1kHz
0
1020/fs
21.3ms
23.1ms
1
4080/fs
85.0ms
92.5ms
Table 11. Digital Volume Transition Time 00h ⇔ FFh
ATS bit
fs=8kHz
127.5ms
510.0ms
(default)
Just after power up, the digital volume level is at MUTE. The volume changes to the value set by
registers in soft transition after releasing the power-down state.
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[AK4432]
◼
Soft Mute Operation
The soft mute operation is performed at digital domain. When the SMUTE pin is set to “H” or the
SMUTE bit is set to “1”, the attenuation level softly transitions from the current level to MUTE (- dB).
After that, when the SMUTE pin is set to “L” or the SMUTE bit is set to “0”, the attenuation level returns
from MUTE to the level set by ATTL/R7-0 bits by soft transition. The transition speed is determined by
the ATS bit setting. If the soft mute is cancelled before attenuating to - dB, the attenuation is
discontinued and returned to the level set by ATTL/R7-0 bits in the same cycle. The soft mute is
effective for changing the signal source without stopping the signal transmission.
SMUTE pin or
SMUTE bit
(1)
(1)
ATTL/R7-0 bits
Setting
Attenuation Level
(3)
- dB
GD
(2)
GD
(2)
AOUTL/R
Note:
(1) (255 – ATTL/R7-0 bits setting) 4 transition time per 0.125dB.
For example, this time is 1020/fs at ATTL/R7-0 bits = “00h”.
(2) The analog output corresponding to the digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating − dB, the attenuation is discontinued and returned
to the level set by ATTL/R7-0 bits in the same cycle.
Figure 26. Soft Mute Function
◼
Error Detection
Three types of error can be detected by the AK4432 (Table 12). The internal LDO will be powered down
and register access will be disabled when an error is detected. Once an error is detected, the AK4432
will not return to normal operation automatically even if all error conditions are removed. Reset the
AK4432 once by bringing the PDN pin = “L” and start up again. In I2C mode, errors can be detected by
monitoring Acknowledge. If an error occurs, the AK4432 stops sending Acknowledge.
No
Error
Error Condition
1
Internal Reference Voltage Error
Internal reference voltage is not powered up.
2
LDO Over Voltage Detection
LDO voltage > 1.6V (Typ)
3
LDO Over Current Detection
LDO current > 100mA (Typ)
Table 12. ERROR Detection
◼
System Reset
The AK4432 should be reset once by bringing the PDN pin = “L” upon power-up. Power-down state of
the reference voltage such as LDO and VCOM will be released by the PDN pin = “H”, and then after
1ms register writing becomes available. The internal DAC will be powered up after MCLK and LRCK
are input. The AK4432 is in power-down state until MCLK and LRCK are input.
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[AK4432]
◼
Power Down Function
The AK4432 is placed in power-down mode by bringing the PDN pin “L” and the analog outputs
become floating (Hi-Z) state. Power-up and power-down timings are shown in Figure 27.
Power
AVDD, LVDD
PDN pin
(1)
LDOO pin
(2)
Internal PDN
Internal
State
Normal Operation (Register Access and Audio Data Input Available)
Reset
DAC In
(Digital)
“0”data
“0”data
GD
DAC Out
(Analog)
(4)
Reset
(3)
GD
(5)
(5)
(4)
(6)
Clock In
MCLK, LRCK, BICK
External
Mute
(7)
Mute ON
Mute ON
(1) After AVDD and LVDD are powered-up, the PDN pin should be “L” for more than 800ns.
(2) After PDN pin = “H”, the LDO circuit (internal digital block driving power supply) and REF block
(analog reference voltage source) are powered up, and control registers are initialized. The
Internal PDN (internal power down) is released at maximum 1ms after the PDN pin is set to “H”
and normal operation starts. Since the clocks are used to release the internal power down, if
the clocks are input after the PDN pin is set to “H”, the internal power down will be released in
max.1ms from the start of clock input. Set the control register after releasing the internal power
down.
(3) The analog output corresponding to digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at an edge of PDN signal. This noise is output even if “0” data is input.
(6) After powering down with the PDN pin = “L”, stop the clock and drop AVDD and LVDD.
(7) Mute the analog output externally if click noise (5) adversely affect system performance. The
timing example is shown in this figure.
Figure 27. Pin Power Down/Up Sequence Example
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[AK4432]
◼
Power Off Functions
PMDA
bit
DAC Block
0
1
OFF
ON
AOUTL/R pins
Digital
Output
Circuit
Hi-Z
OFF
Normal
ON
Table 13. Power OFF Function
Register
Contents
Keep
Keep
(default)
When the PMDA bit is set to "0", all internal circuits except registers are powered down immediately. At
this time, the analog output becomes floating state (Hi-Z). Figure 28 shows a timing example of poweroff and power-on.
PMDA bit
Internal
State
Normal Operation
Power-off
D/A In
(Digital)
Normal Operation
“0” data
GD
D/A Out
(Analog)
(1)
GD
(3)
(2)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, BICK, LRCK
External
MUTE
(5)
Mute ON
Note:
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs are floating (Hi-Z) in power-off state.
(3) Click noise occurs at the edges (“ ”) of the internal timing of PMDA bit. This noise is output
even if “0” data is input.
(4) Each clock input (MCLK, BICK, LRCK) can be stopped in power down mode (PMDA bit = “0”).
(5) Mute the analog output externally if the click noise (3) adversely affects system performance.
Figure 28. Power-off/on Sequence Example
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[AK4432]
◼
Clock Synchronization
The AK4432 has a function to adjust the phase difference with the DAC output of the AK7738 within
13/256fs. Clock synchronization function is enabled by SYNCE bit = “1” (default = “1”). SYNCE bit
setting must be changed when audio data is all “0” (no audio data input). When SYNCE bit = “1”
(default) MSB justified and 32-bit I2S compatible formats are available but LSB justified format is not
available.
Synchronization with AK7738
In the use cases shown below (Figure 29), the phase difference of DAC output between the AK7738
and the AK4432 can be kept less than 13/256fs by clock synchronization function. Only BICK=64fs,
32bit MSB justified (DIF2-0 bits = “110b”) can be used when synchronizing with the AK7738.
Use Case1
Volume
Control
Use Case2
Figure 29. Available Use Cases for Synchronization with the AK7738
Speed LRCK freq.
BICK freq. MCLK freq.
Mode
[kHz]
Normal
48
64fs
256fs
Double
96
64fs
256fs
Quad
192
64fs
128fs
MCLK freq.
[MHz]
12.288
24.576
24.576
Phase Diff.
[1/MCLK]
7 ~ 13
9 ~ 12
7 ~ 10
Phase Diff.
[µs]
0.57 ~ 1.06
0.37 ~ 0.49
0.29 ~ 0.41
Phase Diff.
[deg] (Note 16)
4.1 ~ 7.6
2.6 ~ 3.5
2.1 ~ 2.9
Table 14. Phase Difference Relationship between the AK7738 and the AK4432
Note 16. Phase difference to a 20 kHz signal.
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[AK4432]
◼
Parallel Mode
When P/S pin= “H”, AK4432 is in parallel mode. Parallel mode does not require any register settings,
and the following three settings can be made with pins. Functions that cannot be set with pins operate
with the default setting of the register.
(1) Audio Interface
The DIF pin controls audio interface mode (Table 15). Available modes are 32-bit MSB justified (DIF pin
= “L”) and 32-bit I2C compatible (DIF pin = “H”). TDM input mode is not available.
DIF pin
L
H
Mode
Normal Input, 32-bit Justified (Mode6 in Table 7)
Normal Input, 32-bit I2S Compatible (Mode7 in Table 7)
Table 15. Audio Interface Forma (Parallel Mode)
(2) Soft Mute
Soft mute function can be used by the SMUTE pin. (Figure 26)
(3) System Clock
Sampling frequency and MCLK frequency can be selected by ACKS pin. When the ACKS pin is “L”, the
sampling frequency is fixed at Normal Speed mode. Double Speed mode and Quad Speed mode can
also be used when the ACKS pin is set to “H”. Table 16 shows the MCLK frequencies that can be used
for each combination of ACKS pin state and Sampling Speed Mode.
ACKS pin
L
H
H
H
MCLK
Sampling Speed Mode
768fs, 512fs, 384fs, 256fs
Normal Speed Mode
512fs, 768fs
Normal Speed Mode
256fs, 384fs
Double Speed Mode
128fs, 192fs
Quad Speed Mode
Table 16. System Clock (Parallel Mode)
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[AK4432]
◼
Serial Control Interface
The AK4432 corresponds to both 3-wire serial and I2C bus interfaces. After releasing power-down
mode, the AK4432 is in I2C interface mode. The 3-wire serial mode will be enabled by writing a dummy
command four times continuously following power-up when the CSN pin = “H” (Figure 30) The dummy
command is “0xDE, 0xADDA, 0x7A”. The data is MSB first.
CSN
CCLK
CDTI
Dummy Command
Dummy Command
Dummy Command
Dummy Command
CSN
CCLK
CDTI
don’tcare
(L/H)
0xDE (8bit)
0x7A(8bit)
0xADDA (16bit)
don’tcare
(L/H)
Figure 30. Switch to 3-wire serial mode
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[AK4432]
(1) 3-wire Serial Control Mode
Write to the register with CSN, CCLK and CDTI pins. CDTI data consists of 8-bit command code, 16-bit
register address, and 8-bit control data (Figure 31). Data is MSB first. The most significant bit of the
command code is the R/W bit, and only ”1” (Write) is valid for the AK4432. The 7 bits following the R/W
bit should be ”1000000b” (Figure 32). The register address is specified by the lower 3 bits (Figure 33).
The AK4432 captures CDTI data at the “” of CCLK. Control data is written to the register at the 8th bit
CCLK “”. The frequency of CCLK is up to 7MHz.
Control data can be written continuously (Figure 35). If control data is sent without rising CSN to “H”
after sending control data, the register address is automatically incremented and the control data is
written to the next address. If control data is sent after writing control data to address 05h, it will be
written to address 00h.
The registers are initialized by setting the PDN pin = “L”.
CSN
CCLK
don’tcare
CDTI (L/H)
Command Code (8bit)
don’tcare
(L/H)
Control Data (8bit)
Register Address (16bit)
Figure 31. Control I/F Timing
R/W
1
0
0
0
0
0
0
R/W: READ/WRITE (Fixed to “1”, Write only)
Figure 32. Command Code
0
0
0
0
0
0
0
0
0
0
0
0
0
A2
A1
A0
Figure 33. Register Address
D7
D6
D5
D4
D3
D2
D1
D0
Figure 34. Control Data
* The AK4432 does not support data read in 3-wire serial mode.
* Control register write is not possible when the PDN pin = “L”.
* Cntrol data is not written if CCLK rises 31 times or less during CSN = “L” period.
CSN
CCLK
CDTI
don’t care
(L/H)
Command
Code
Register
Address
Control
Data
Control
Data
Control
Data
Control
Data
Control don’t care
(L/H)
Data
Figure 35. Continuous Write of Control Data
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[AK4432]
(2) I2C-bus Control Mode
The I2C-bus in the AK4432 can run in fast-mode (max: 400kHz) and fast-mode plus (max: 1MHz) (Table
17). I2C-bus mode should be fixed to either mode during operation. The PDN pin must be “L” when
changing the I2C-bus mode.
I2CFIL pin
I2C Bus Mode
L
Fast mode
H
Fast mode Plus
Table 17. I2C-Bus Mode Setting
WRITE Operation
Figure 36 shows the data transfer sequence of the I2C-bus mode. Master begins access to the AK4432
with a START condition. The START condition is to change the SDA line from “H” to “L” while the SCL
line is “H” (Figure 44). After the START condition, the master sends the first byte consisting of the 7-bit
slave address and data direction bit (R/W) (Figure 37). The slave address of AK4432 is “0011001b”. If
the slave addresses match, the AK4432 returns an acknowledge (ACK). The master must send a clock
pulse to the SCL line for the AK4432 to return the ACK and release the SDA line (Figure 45). When R/W
bit is “0”, data is written to AK4432, and when R/W bit is “1”, data is read from AK4432.
The second byte is an 8-bit command code. The format is MSB first, and it is fixed to “11000000b” (Figure
38).
The third byte and fourth byte consist of the sub address (the control register address of the AK4432).
The sub address is 16 bits MSB first, all bits of the third byte are fixed to “0”, and the upper 5 bits of the
fourth byte are fixed to “0” (Figure 39, Figure 40). The fifth and subsequent bytes are control data to be
written to the register. The control data is 8 bits MSB first (Figure 41). The AK4432 returns an
acknowledg every time it completes receiving one byte. Data transfer ends with a stop condition
(STOP) generated by the master. The stop condition is to change the SDA line from “L” to “H” while the
SCL line is “H” (Figure 44).
The AK4432 can write multiple bytes of control data at once. After sending one byte of control data, if
the master sends more control data without sending a stop condition, the data is written to an
automatically incremented address. After writing the control data to address “05h”, if further control data
is sent, it will be written to address “00h”.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW
state of the data line can only be changed when the clock signal on the SCL line is LOW (Figure 46)
except for the START and STOP conditions.
S
T
A
R
T
S
T
O
P
R/W=”0”
Slave
SDA S Address
SubAddress
（Upper）
Command
Code
A
C
K
A
C
K
SubAddress
（Lower）
A
C
K
Control
Data
A
C
K
Control
Data
A
C
K
Control
Data
A
C
K
A
C
K
P
A
C
K
Figure 36. Data Transfer Sequence in I2C-bus Mode
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[AK4432]
0
0
1
1
0
0
1
R/W
R/W “0”: Write, “1”: Read
Figure 37. The First Byte (Slave Address)
1
1
0
0
0
0
0
0
Figure 38. The Second Byte (Command Code: Write)
0
0
0
0
0
0
0
0
Figure 39. The Third Byte (Sub-Address Upper Byte)
0
0
0
0
0
A2
A1
A0
Figure 40. The Fourth Byte (Sub-Address Lower Byte)
D7
D6
D5
D4
D3
D2
D1
D0
Figure 41. The Fifth and Succeeding Bytes (Control Data)
READ Operation
After the START condition, the master sends the AK4432 slave address and R/W bit = “0” in the first
byte, read command code “01000000b” (Figure 43) in the second byte, and register address (sub
address) in the third and fourth bytes. Next, when the master sends the AK4432's slave address and
R/W bit = “1” after the RESTART condition, the AK4432 outputs the control data of the register specified
by the sub address. The AK4432 increments the register address and outputs the control data each
time it receives an acknowledg from the master. The read operation ends when the master sends a
STOP condition without sending an acknowledg (NACK) after reading the control data. The RESTART
condition is the same as the START condition.
S
T
A
R
T
R
E
S
T
A
R
T
R/W=”0”
Slave
SDA S Address
SubAddress
（Upper）
Command
Code
A
C
K
A
C
K
SubAddress
（Lower）
A
C
K
S
T
O
P
R/W=”1”
Slave
Control
Data
S Address
A
C
K
A
C
K
Control
Data
MA
AC
S K
T
E
R
Control
Data
MA
A C
S K
T
E
R
MA
AC
S K
T
E
R
P
M
A
S
T
E
R
N
A
C
K
Figure 42. Data read sequence in I2C bus mode
0
1
0
0
0
0
0
0
Figure 43. The Second Byte (Command Code: Read)
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[AK4432]
SDA
SCL
S
P
START Condition
STOP Condition
Figure 44. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 45. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
Data valid
change
of data
allowed
Figure 46. Bit Transfer on the I2C-Bus
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[AK4432]
◼
Register Map
Addr
00H
01H
02H
03H
04H
05H
Register Name
D7
Power Management
0
Control 1
0
Data interface
0
Control 2
0
AOUTL Volume Control ATTL7
AOUTR Volume Control ATTR7
D6
0
0
SDS1
0
ATTL6
ATTR6
D5
0
0
SDS0
0
ATTL5
ATTR5
D4
0
0
TDM1
DASL
ATTL4
ATTR4
D3
0
0
TDM0
DASD
ATTL3
ATTR3
D2
0
DFS1
DIF2
ATS
ATTL2
ATTR2
D1
D0
PMDA
0
DFS0
ACKS
DIF1
DIF0
SMUTE SYNCE
ATTL1
ATTL0
ATTR1 ATTR0
Note 17. Data must not be written into addresses from 06H to FFH.
Note 18. The bit defined as 0 must contain a “0” value.
Note 19. When the PDN pin goes to “L”, the registers are initialized to their default values.
◼
Register Definitions
Addr Register Name
00H Power Management
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
PMDA
R/W
1
D0
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D2
DFS1
R/W
0
D1
DFS0
R/W
0
D0
ACKS
R/W
0
PMDA
DAC Power Management
0: Power Down
1: Normal Operation
Addr Register Name
01H Control 1
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
ACKS
Clock Auto-Recognition Mode Enable
0: Disable (Manual Setting Mode)
1: Enable (Auto Setting Mode)
Sampling speed mode is auto-detected when ACKS = “1”. DFS1-0 bits settings are ignored.
When ACKS = “0”, sampling speed mode is set by DFS1-0 bits.
DFS1-0
Sampling Speed Mode Select (Table 1)
The setting of DFS bits is ignored at ACKS bit =“1”.
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[AK4432]
Addr Register Name
02H Data interface
R/W
Default
D7
0
R/W
0
D6
SDS1
R/W
0
D5
SDS0
R/W
0
D4
TDM1
R/W
0
D3
TDM0
R/W
0
D2
DIF2
R/W
1
D1
DIF1
R/W
1
D0
DIF0
R/W
0
DIF2-0
Audio Interface Mode Select (Table 7)
Default: “110b” (32bit MSB justified)
TDM1-0
TDM Format Select
Default: “00b” (Stereo Mode)
Mode TDM1 TDM0
Sampling Speed Mode
0
0
0
Stereo mode (Normal, Double, Quad Speed Mode)
1
0
1
TDM128 mode (Normal, Double, Quad Speed Mode)
2
1
0
TDM256 mode (Double, Quad Speed Mode)
3
1
1
TDM256 mode (Double, Quad Speed Mode)
SDS1-0
Data Slot Select in TDM mode (Table 8)
Default: “00b”
Addr Register Name
03H Control 2
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
DASL
R/W
0
D3
DASD
R/W
0
D2
ATS
R/W
0
D1
D0
SMUTE SYNCE
R/W
R/W
0
1
SYNCE
Clock Synchronization Enable
0: OFF
1: ON (default)
SMUTE
Soft Mute Enable
0: Normal Operation
1: DAC outputs are soft muted
ATS
Transition Time Setting of Attenuation Level Select
0: 1/fs (default)
1: 4/fs
DASD
Digital Filter Group Delay Select
0: Conventional Delay (default)
1: Short Delay
DASL
Digital Filter Roll-Off Select
0: Sharp Roll-Off (default)
1: Slow Roll-Off
DASD bit
0
0
1
1
DASL bit
0
1
0
1
Mode
Sharp roll-off filter
SLow roll-off filter
Short Delay Sharp roll-off filter
Short Delay Slow roll-off filter
(default)
Table 18 Digital Filter setting for DAC
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[AK4432]
Addr Register Name
D7
04H AOUTL Volume Control ATTL7
05H AOUTR Volume Control ATTR7
R/W
R/W
Default
0
D6
ATTL6
ATTR6
R/W
0
D5
ATTL5
ATTR5
R/W
0
D4
ATTL4
ATTR4
R/W
1
D3
ATTL3
ATTR3
R/W
1
D2
ATTL2
ATTR2
R/W
0
D1
ATTL1
ATTR1
R/W
0
D0
ATTL0
ATTR0
R/W
0
ATTL7-0: Lch Attenuation Level (Table 9)
Default:18h (0dB)
ATTR7-0: Rch Attenuation Level (Table 9)
Default:18h (0dB)
13. Recommended External Circuits
Audio
Controller
P
Connect to
AVDD or VSS
Digital Ground
1
MCLK
LDOO
16
2
BICK
LVDD
15
3
SDTI
AVDD
14
4
LRCK
5
PDN
6
SMUTE
7
ACKS
8
DIF
AK4432
VSS
13
VCOM
12
AOUTL
11
AOUTR
10
P/S
9
1
0.1
10
0.1 10
LDO Supply
3.0 to 3.6V
Analog Supply
3.0 to 3.6V
2.2
1
Lch Out
1
Rch Out
Analog Ground
Figure 47. System Connection Diagram (Parallel mode)
Audio
Controller
P
Digital Ground
1
MCLK
LDOO
16
2
BICK
LVDD
15
3
SDTI
AVDD
14
4
LRCK
VSS
13
5
PDN
VCOM
12
6
CSN/I2CFIL
AOUTL
11
7
CCLK/SCL
AOUTR
10
8
CDTI/SDA
P/S
9
AK4432
1
0.1 10
0.1
10
LDO Supply
3.0 to 3.6V
Analog Supply
3.0 to 3.6V
2.2
1
1
Lch Out
Rch Out
Analog Ground
Figure 48. System Connection Diagram (Serial mode)
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[AK4432]
1. Grounding and Power Supply Decoupling
The AK4432 requires careful attention to power supply and grounding arrangements. VSS must be
connected to the analog ground plane. Decoupling capacitors should be as near to the AK4432 as
possible.
2. Voltage Reference
VCOM is a signal ground of this chip and output the voltage AVDDx1/2. A 2.2F (±50% includes
temperature characteristics) ceramic capacitor attached between the VCOM pin and VSS eliminates
the effects of high frequency noise. This capacitor should be as close to the pin as possible. No current
can be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM
pin in order to avoid unwanted coupling into the AK4432.
The LDOO pin is a power supply for internal digital circuit and outputs 1.2V. A 1F (±50% includes
temperature characteristics) ceramic capacitor attached between the LDOO pin and VSS eliminates the
effects of high frequency noise. This capacitor should be connected as close as possible to the pin. No
current can be drawn from the LDOO pin.
3. Analog Output
The output signal range is nominally 0.86 x AVDD Vpp (typ.) centered around the VCOM voltage. The
DAC input data format is 2’s complement. The output voltage is a positive full scale for
7FFFFFFFH(@32bit) and a negative full scale for 80000000H(@32bit). The ideal output is VCOM
voltage for 00000000H(@32bit). The internal switched capacitor filter (SCF) and smoothing filter (SMF)
remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband.
The DAC output has a few mV DC offset with respect to VCOM. The DC offset and VCOM voltage are
rejected with an external AC-coupling capacitor.
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[AK4432]
14. Package
Outline Dimensions
(Unit: mm)
5±0.1
9
1
8
6.4±0.2
4.4±0.1
16
0.6±0.1
16-pin TSSOP
0.13～ 0.18
◼
0.13
M
0゜～ 10゜
1.1MAX
0.19～ 0.27
0.9±0.05
0.65
0.1
◼
0.1±0.05
S
S
Material & Lead Finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy, Halogen (Br and Cl) free
Cu
Solder (Pb free) plate
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[AK4432]
◼
Marking
AKM
4432
XXXYY
1) Pin #1 Index Mark
2) Date Code 5 digits
XXX:
Week Code (Last Digit of the Year 1 digit + Week’s Serial# 2 digits)
YY:
Factory Control Code
3) Marking Code: 4432
4) AKM Logo
15. Ordering Guide
AK4432VT
AKD4432
-40 +105C
16-pin TSSOP (0.65mm pitch)
Evaluation Board for the AK4432
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[AK4432]
16. Revision History
Date (Y/M/D) Revision Reason
Page
15/02/18
00
First Edition
22/12/20
01
Error
1
Correction
Description
1
Change
Error
Correction
6
Description
Change
Error
Correction
6
Error
Correction
9
Error
Correction
11
Description
Change
Error
Correction
27
Error
Correction
27
Description
Change
28
Error
Correction
28
Error
Correction
Description
Change
28
Error
Correction
32
9
27
29
Contents
Removed from features because it does not have deemphasis function and zero detection function.
2. Sampling Frequency
Make the lower frequency the same as the switching
specification.
Double Speed Mode “64kHz” → “48kHz”
Quad Speed Mode “128kHz” → “96kHz”
Pin Funcion of SDA
“Caintrol Data Input Pin “
→ ”Control Dara Input/Output Pin”
Power down states of digital input pins
“-“ → ”Hi-z” for clarification (Only PDN pin “Input “L””)
Conditions for filter characteristics
Removed “DEM=OFF” because it does not have deemphasis function.
Filter Characteristics Sharp Roll-Off Filter
fs=48k, 96kHz
Frequency Response max.-0.1dB → max.0.1dB
Filter Characteristics Short Delay Sharp Roll-Off Filter
fs=48k, 96kHz
Frequency Response max.-0.1dB → max.0.1dB
Digital Volume Function Table 10
Simplified to only 0.125dB transition time
Transition time from 00H (+12dB) to FFH (MUTE)
Mode0: 255step*4/fs+1/fs=1020/fs
→ 255 x 0.5 / 0.125 x 1/fs = 1020/fs
Mode1: 255step*16/fs+4/fs=4084/fs
→ 255 x 0.5 / 0.125 x 4/fs = 4080/fs
Digital Volume Function Table 11
Recalculation of transition time based on 1020/fs and
4080/fs
Soft Mute Operation Note (1)
Write formulas with concrete elements.
“ATT_DATA ATT transition time”
→”(255 – ATTL/R7-0 bits setting) 4 transition time
per 0.125dB”
Soft Mute Operation Note (1)
“at ATT_DATA=255 in Normal Speed Mode”
→ ”at ATTL/R7-0 bits = 00h”
Error Detection Table 12 LDO Over Current Detection
“< 100mA (Typ)” → “> 100mA (Typ)”
Power Down Function Note (1)
“the PDN pin should be “L” for 800ns.”
→ “the PDN pin should be “L” for more than 800ns.”
Clarified that 800ns is a minimum value.
(3) System Clock
In the description and the table
“MCKI” → “MCLK”
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[AK4432]
Date (Y/M/D) Revision Reason
Page
22/12/20
01
Error
34
Correction
Description
Change
23/3/31
02
Description
Change
Error
Correction
Description
Added
Contents
(1) 3-wire Serial Control Mode
“if there are 17times or more CCLK rising edges, or
15times or less CCLK rising edges while the CSN pin
is “L”.”
→ “if CCLK rises 31 times or less during CSN = “L”
period.”
39 Register Definitions Address 02H, SDS1-0 bits
Only default value and reference table are described
according to the description of other registers.
whole Fixed unclear description
43
43
Marking
(In figure) “XXYYY” → “XXXYY”
2) Date Code 4 digits → 5 digits
Add characters meaning.
Marking
Add “4) AKM Logo”
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[AK4432]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third party
with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the
aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other
transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations
in which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or
related technology or any information contained in this document, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws
and regulations. The Products and related technology may not be used for or incorporated into
any products or systems whose manufacture, use, or sale is prohibited under any applicable
domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws
and regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as
a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without
prior written consent of AKM.
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