AK4499EQ

[AK4499] = Preliminary = AK4499 Premium Switched Resistor 4ch DAC 1. General Description The AK4499 is a 32-bit 4ch Switched Resistor DAC which adopts newly developed technology, achieving the industry’s leading level low distortion and low noise characteristics. It corresponds to a 768kHz PCM input and an DSD512 input at maximum, suitable for playback of high resolution audio sources that are becoming widespread in Network Audio and USB-DACs Audio systems. In addition, it is capable of supporting a wide range of signals and achieving low out-of-band noise. The AK4499 has six types of 32-bit digital filters, realizing simple and flexible sound reproduction in wide range of applications. 2. Features • 4-ch Switched Resistor DAC • THD+N: -124 dB • Dynamic Range, S/N: 140 dB (Mono), 137 dB (Stereo), 134 dB (4ch) • 128x Over Sampling • Sampling Rate: 8 kHz  768 kHz • 32-bit 8x Digital Filter Short Delay Sharp Roll-off, GD = 6.0/fs Short Delay Slow Roll-off, GD = 5.0/fs Sharp Roll-off Slow Roll-off Super Slow Roll-off Low Dispersion Short Delay Filter • DSD64, DSD128, DSD256, DSD512 Input Support Filter1 (fc = 37 kHz, DSD64 mode) Filter2 (fc = 65 kHz, DSD64 mode) • Digital De-emphasis for 32, 44.1 and 48kHz sampling • Soft Mute • Digital Attenuator (0 dB ~ -127 dB, 0.5 dB step + mute) • Mono Mode • External Digital Filter Interface (EXDF Mode) • PCM/DSD, EXDF/DSD Mode Automatic Mode Switching Function • Audio I/F Format - MSB Justified - LSB Justified - I2S - DSD - TDM • Daisy Chain • Master Clock - fs = 8 kHz ~ 32 kHz: 256fs, 384fs, 512fs, 768fs, 1152fs - fs = 32 kHz ~ 54 kHz: 256fs, 384fs, 512fs, 768fs - fs = 54 kHz ~ 108 kHz : 256fs, 384fs - fs = 108 kHz ~ 216 kHz : 128fs, 192fs - fs = 384 kHz : 32fs, 48fs, 64fs, 96fs - fs = 768 kHz : 16fs, 32fs, 48fs, 64fs • Register Control Mode with 3-wire Serial or I2C interface Rev. 0.0-PB 2018/12 -1- [AK4499] • Pin Control Mode • Power Supply: Internal LDO (LDOE pin = “H”); TVDD = 3.0  3.6 V, AVDD = 4.75  5.25 V, VDDL1/R1/L2/R2 = 4.75  5.25 V External Supply (LDOE pin = “L”); TVDD = 1.7  3.6 V, DVDD = 1.7 ~ 1.98 V, AVDD = 4.75  5.25 V, VDDL1/R1/L2/R2 = 4.75  5.25 V • Operational Temperature: -40 ~ 85 C • Digital Input Level: CMOS • Package: 128-pin HTQFP Rev. 0.0-PB 2018/12 -2- [AK4499] 3. Block Diagram and Functions 3.1. Block Diagram TVDD DVDD DVSS LDOE PDN BICK/BCK/DCLK SDATA1/DINL1/DSDL1 LRCK/DINR1/DSDR1 SDATA2/DINL2/DSDL2 L TDMO DINR2/DSDR2 AVDD AVSS LDO PCM Data Interface External DF Interface De-emphasis & Interpolator SR DACL1  Modulator DATT Soft Mute SSLOW/WCK TDM0/DCLK DEM0/DSDL1 DSDR1 TDM1/DSDL2 DCHAIN/DSDR22 SR DACR1 Normal path DSDD bit “0” PCM/DSD EXDF/DSD Automatic Mode Switching Volume Bypass DSDD bit “1” DSD Data Interface/ DSD Filter De-emphasis 8x & Interpolator Interpolator SR DACL2  Modulator DATT Soft Mute SR DACR2 Normal path DSDD bit “0” Volume Bypass DSDD bit “1” Clock Divider Control Register SMUTE/CSN SD/ CCLK/SCL SLOW/CDTI/SDA VREFHL1 VREFLL1 1 VSSL1 VDDL1 VCOML1 EXTCL1N IOUTL1N OPINL1N OPINL1P IOUTL1P EXTCL1P EXTCR1P IOUTR1P OPINR1P OPINR1N IOUTR1N EXTCR1P VCOMR1 VDDR1 VSSR1 VREFLR1 VREFHR1 VREFHL2 VREFLL2 21 VSSL2 VDDL2 VCOML2 EXTCL2N IOUTL2N OPINL2N OPINL2P IOUTL2P EXTCL2P EXTCR2P IOUTR2P OPINR2P OPINR2N IOUTR2N EXTCR2P VCOMR2 VDDR2 VSSR2 VREFLR2 VREFHR2 MCLK Stop Detection IREF INVR/ ACKS/ TEST MCLK VTSEL CAD1 I2C PSN DIF0/ DIF1/ DIF2/ DZFL DZFR CAD0 EXTR Figure 1. AK4499 Block Diagram Rev. 0.0-PB 2018/12 -3- [AK4499] 3.2. Functions Block PCM Data Interface External DF Interface DSD Data Interface DSD Filter Function Execute serial/parallel conversion of SDATA1/2 input data by synchronizing with LRCK and BICK, and generate TDM output data. Receive external digital filter outputs. Execute serial/parallel conversion of DINL1/2 and DINR1/2 input data by synchronizing with BICK. 1-bit data that is input from DSDL1/2 and DSDR1/2 pins is received by synchronizing with DCLK. FIR filter that reduces high frequency noise of DSD input data DATT, Soft Mute De-emphasis & Interpolator ΔΣ Modulator Apply DATT and Soft Mute process to input data. A digital filter that applies De-emphasis process to input data and executes over sampling. Output multi-bit data to SR DAC. This block consists of a third-order digital delta-sigma modulator. SR DAC Convert multi bit output of ΔΣ Modulator into analog signal. This block consists of a switched resistor DAC. Control Register Keep register settings for each mode. Control registers are accessed in 3-wire (CSN, CCLK, CDTI) or I2C-Bus (SCL, SDA) control mode. Clock Divider Divide Master Clock In PCM mode, master clock is divided automatically by fs rate auto detection function. In DSD mode, the master clock frequency is set by DCKS bit. MCLK Stop Detection Detects when the master clock input is absent. IREF Generate reference current from the reference voltage generated internally, using an external resistor. LDO Generate power for internal digital circuit (1.8V typ.). Rev. 0.0-PB 2018/12 -4- [AK4499] 4. Pin Configurations and Functions VSSR2 VSSR2 VSSR2 VDDR2 VDDR2 VCOMR2 VDDR2 EXTCR2N IOUTR2N IOUTR2N OPINR2N IOUTR2P OPINR2P IOUTR2P EXTCR2P NC EXTCL2P NC IOUTL2P IOUTL2P OPINL2N OPINL2P IOUTL2N EXTCL2N IOUTL2N VDDL2 VCOML2 VDDL2 VDDL2 VSSL2 VSSL2 VSSL2 4.1. Pin Configurations VREFLL2 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 97 VREFLR2 VREFLL2 98 63 VREFLR2 VREFLL2 62 VREFLR2 VREFLL2 99 100 VREFHL2 101 VREFHL2 102 VREFHL2 VREFHL2 10 3 104 EXTR 105 AVSS 10 6 107 AVDD MCLK AK4499 108 DVDD 109 DVSS 110 TVDD 111 61 VREFLR2 60 VREFHR2 59 VREFHR2 58 VREFHR2 57 VREFHR2 56 TEST 55 INVR/I2C 54 DCHAIN/DSDR2 53 TDM1/DSDL2 52 TDM0/DCLK 51 DSDR1 50 DEM0/DSDL1 LDOE 112 PDN 113 SMUTE/CSN 114 47 DINR2/DSDR2 SD/CCLK/SCL 115 46 SDATA2/DINL2/DSDL2 SLOW/CDTI/SDA 116 45 LRCK/DINR1/DSDR1 DIF0/DZFL1 117 44 SDATA1/DINL1/DSDL1 DIF1/DZFR2 118 43 BICK/BCK/DCLK DIF2/CAD0 119 42 ACKS/CAD1 VTSEL 120 41 PSN VREFHL1 121 40 VREFHR1 VREFHL1 122 39 VREFHR1 VREFHL1 123 38 VREFHR1 VREFHL1 124 VREFLL1 125 128pin HTQFP (Top View) Back TAB: Note1 49 TDMO 48 SSLOW/WCK 37 VREFHR1 36 VREFLR1 VREFLL1 126 35 VREFLR1 VREFLL1 127 34 VREFLR1 VREFLL1 128 33 30 31 32 VREFLR1 VSSR1 VSSR1 Input VSSR1 VDDR1 VDDR1 VDDR1 26 27 28 29 VCOMR1 25 EXTCR1N IOUTR1N OPINR1N IOUTR1N OPINR1P IOUTR1P IOUTR1P NC EXTCR1P NC EXTCL1P IOUTL1P IOUTL1P OPINL1P IOUTL1N 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 OPINL1N 9 IOUTL1N 8 EXTCL1N 7 VCOML1 6 VDDL1 5 VDDL1 4 VDDL1 3 VSSL1 2 VSSL1 VSSL1 1 Output I/O Power Note 1: The exposed pad on the bottom surface of the package must be connected to ground (AVSS). Rev. 0.0-PB 2018/12 -5- [AK4499] 4.2. Functions No. Pin Name I/O Function 1-3 4-6 VSSL1 VDDL1 - 7 VCOML1 I 8 EXTCL1N O External Capacitor connection pin. This pin should be connected to 1 µF to VSSL1. 9,10 IOUTL1N O Current Output pin (L1ch Negative Signal). 11 OPINL1N O Common Voltage Input pin (L1ch Negative Signal). 12 OPINL1P O Common Voltage Input pin (L1ch Positive Signal). 13,14 IOUTL1P O Current Output pin (L1ch Positive Signal). 15 EXTCL1P O External Capacitor connection pin. This pin should be connected to 1 µF to VSSL1. 16,17 NC - No internal bonding. Connect to AVSS. 18 EXTCR1P O External Capacitor connection pin. This pin should be connected to 1 µF to VSSR1. 19,20 IOUTR1P O Current Output pin (R1ch positive signal). 21 OPINR1P O Common Voltage input pin (R1ch positive signal). 22 OPINR1N O Common Voltage input pin (R1ch negative signal). 23,24 IOUTR1N O Current Output pin (R1ch negative signal). 25 EXTCR1N O External Capacitor connection pin. This pin should be connected to 1 µF to VSSR1. 26 VCOMR1 I 27-29 30-32 33-36 37-40 VDDR1 VSSR1 VREFLR1 VREFHR1 I I 41 PSN I L1ch Analog Ground pin. L1ch Analog Power Supply pin. L1ch VCOM pin. VCOML1 is connected to the midpoint of resistors between VREFHL1 and VREFL1. R1ch VCOM pin. VCOMR1 is connected to the midpoint of resistors between VREFHR1 and VREFLR1. R1ch Analog Power Supply pin. R1ch Analog Ground pin. R1ch Low Level Reference Voltage Input pin. R1ch High Level Reference Voltage Input pin. Control Mode Select pin (Internal pull-up pin) “L”: Register Control mode “H”: Pin Control mode Rev. 0.0-PB Power Down State Hi-Z Pull-down to VSSL1 (250 kΩ, typ) Connected to OPINL1N (64 Ω, typ) Connected to IOUTL1N (64 Ω, typ) Connected to IOUTL1P (64 Ω, typ) Connected to OPINL1P (64 Ω, typ) Pull-down to VSSL1 (250 kΩ, typ) Pull-down to VSSR1 (250 kΩ, typ) Connected to OPINR1P (64 Ω, typ) Connected to IOUTR1P (64 Ω, typ) Connected to IOUTR1N (64 Ω, typ) Connected to OPINR1N (64 Ω, typ) Pull-down to VSSR1 (250 kΩ, typ) Hi-Z Hi-Z Hi-Z Pull-Up to TVDD (100 kΩ, typ) 2018/12 -6- [AK4499] No. Pin Name I/O ACKS I CAD1 BICK BCK DCLK SDATA1 DINL1 I I I I I I DSDL1 I LRCK DINR1 I I DSDR1 I SDATA2 DINL2 I I DSDL2 I DINR2 I DSDR2 I 48 SSLOW WCK I I 49 TDMO O DEM0 I DSDL1 I DSDR1 I TDM0 DCLK TDM1 I I 42 43 44 45 46 47 50 51 52 53 54 DSDL2 I DCHAIN I DSDR2 I INVR I I2C I TEST I 55 56 Power Down State Function Clock Setting Mode Select pin in Pin Control mode “L”: Fixed Speed mode “H”: Auto Setting mode Chip Address 1 pin in Register Control mode Audio Serial Data Clock pin in PCM mode Audio Serial Data Clock pin in EXDF mode DSD Clock Pin in DSD mode (@DSDPATH bit = ”1”) Audio Serial Data Input pin in PCM mode Audio Serial Data Input pin in EXDF mode Audio Serial Data Input pin in DSD mode (@DSDPATH bit = ”1”) Input Channel Clock pin in PCM mode Audio Serial Data Input pin in EXDF mode Audio Serial Data Input pin in DSD mode (@DSDPATH bit = ”1”) Audio Serial Data Input pin in PCM mode Audio Serial Data Input pin in EXDF mode Audio Serial Data Input pin in DSD mode (@DSDPATH bit = ”1”) Audio Serial Data Input pin in EXDF mode Audio Serial Data Input pin in DSD mode (@DSDPATH bit = ”1”) Digital Filter Select pin in Pin Control mode Word Clock input pin in EXDF mode Audio Serial Data Output pin in Daisy Chain mode (Internal pull-down pin) De-emphasis Enable pin in Pin Control mode Audio Serial Data Input pin in DSD mode (@DSDPATH bit = ”0”) Audio Serial Data Input pin in DSD mode (@DSDPATH bit = ”0”) TDM Mode select 0 pin in Pin control mode. DSD Clock pin in DSD mode (@DSDPATH bit =”0”) TDM Mode select 1 pin in Pin control mode. Audio Serial Data Input pin in DSD mode (@DSDPATH bit = ”0”) Daisy Chain Mode Select pin in Pin Control mode. Audio Serial Data Input Pin in DSD mode (@DSDPATH bit = ”0”) R1/2ch Signal Invert pin in Pin Control mode Serial Control Interface Select pin in Register Control mode. “L”: 3-wire serial control interface. “H”: I2C Bus serial control interface. Connect to DVSS (Internal pull-down pin) Rev. 0.0-PB Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Pull-down to DVSS (100 kΩ, typ) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Pull-down to DVSS (100 kΩ, typ) 2018/12 -7- [AK4499] No. Pin Name I/O Function 57-60 61-64 65-67 68-70 VREFHR2 VREFLR2 VSSR2 VDDR2 I I - 71 VCOMR2 I 72 EXTCR2N O External Capacitor Connection pin. This pin should be connected to 1 µF to VSSR2. 73,74 IOUTR2N O Current Output pin (R2ch negative signal). 75 OPINR2N O Common Voltage Input pin (R2ch negative signal). 76 OPINR2P O Common Voltage Input pin (R2ch positive signal). 77,78 IOUTR2P O Current Output pin (R2ch positive signal). 79 EXTCR2P O External Capacitor connection pin. This pin should be connected to 1 µF to VSSR2. 80,81 NC - No internal bonding. Connect to AVSS. 82 EXTCL2P O External Capacitor connection pin. This pin should be connected to 1 µF to VSSL2. 83,84 IOUTL2P O Current Output pin (L2ch positive signal). 85 OPINL2P O Common Voltage Input pin (L2ch positive signal). 86 OPINL2N O Common Voltage Input pin (L2ch negative signal). 87,88 IOUTL2N O Current Output pin (L2ch negative signal). 89 EXTCL2N O External Capacitor connection pin. This pin should be connected to 1 µF to VSSL2. 90 VCOML2 I 91-93 94-96 97-100 101-104 VDDL2 VSSL2 VREFLL2 VREFHL2 I I 105 EXTR I 106 107 AVSS AVDD - R2ch High Level Reference Voltage Input pin. R2ch Low Level Reference Voltage Input pin. R2ch Analog Ground pin. R2ch Analog Power Supply pin. R2ch VCOM pin. VCOMR2 is connected to the midpoint of resistors between VREFHR2 and VREFLR2. L2ch VCOM pin. VCOML2 is connected to the midpoint of resistors between VREFHL2 and VREFLL2. L2ch Analog Power Supply pin. L2ch Analog Ground pin. L2ch Low Level Reference Voltage Input pin. L2ch High Level Reference Voltage Input pin. External Resistor connection pin. This pin should be connected to 33 kΩ (±1 %) to AVSS. Analog Ground pin Clock Interface Power Supply Pin, 4.75  5.25 V Rev. 0.0-PB Power Down State Hi-Z Hi-Z Hi-Z Pull-down to VSSR2 (250 kΩ, typ) Connected to OPINR2N (64 Ω, typ) Connected to IOUTR2N (64 Ω, typ) Connected to IOUTR2P (64 Ω, typ) Connected to OPINR2P (64 Ω, typ) Pull-down to VSSR2 (250 kΩ, typ) Pull-down to VSSL2 (250 kΩ, typ) Connected to OPINL2P (64 Ω, typ) Connected to IOUTL2P (64 Ω, typ) Connected to IOUTL2N (64 Ω, typ) Connected to OPINL2N (64 Ω, typ) Pull-down to VSSL2 (250 kΩ, typ) Hi-Z Hi-Z Hi-Z Hi-Z 2018/12 -8- [AK4499] No. Pin Name I/O 108 MCLK I Power Down State Hi-Z Function Master Clock Input pin (LDOE pin = “H”) LDO Output pin. This pin should be O connected to DVSS with 1.0 µF. This pin is DVSS 109 DVDD prohibited to connect to other devices. (LDOE pin = “L”) 1.8 V Digital Power Supply pin 110 DVSS Digital Ground pin 111 TVDD Digital Power Supply pin, 3.0 V3.6 V Internal LDO Enable pin. 112 LDOE I Hi-Z “L”: Disable, “H”: Enable Power-Up, Power-Down pin When at “L”, the AK4499 is in Power-Down mode. Hi-Z 113 PDN I The AK4499 must always be in Power-Down mode (PDN = “L”) upon supply power on. When this pin is changed to “H”, Soft Mute cycle is SMUTE I initiated. When returning to “L”, Soft Mute releases. 114 Hi-Z Chip Select pin in 3-wire serial Register Control CSN I mode SD I Digital Filter Select pin in Pin Control mode Control Data Clock pin in 3-wire serial Register CCLK I 115 Control mode Hi-Z Control Data Clock Input pin in I2C Bus Register SCL I Control mode SLOW I Digital Filter Select pin in Pin Control mode Control Data Input pin in 3-wire serial Register CDTI I 116 Control mode Hi-Z 2 Control Data Input pin in I C Bus Register Control SDA I/O mode DIF0 I Digital Input Format 0 pin in Pin Control mode Pull-down to 117 DVSS Lch Zero Input Detect pin in Register Control mode DZFL O (100 kΩ, typ) (Internal pull-down pin) DIF1 I Digital Input Format 1 pin in Pin Control mode Pull-down to 118 DVSS Rch Zero Input Detect pin in Register Control mode DZFR O (100 kΩ, typ) (Internal pull-down pin) DIF2 I Digital Input Format 2 pin in Pin Control mode 119 Hi-Z CAD0 I Chip Address 0 pin in Register Control mode MCLK VIH/L Level Select pin. 120 VTSEL I VTSEL = “L”; VIH = 1.36 V, VIL = 0.34 V Hi-Z VTSEL = “H”; VIH = 2.2 V, VIL = 0.8 V 121-124 VREFHL1 I L1ch High Level Reference Voltage Input pin. Hi-Z 125-128 VREFLL1 I L1ch Low Level Reference Voltage Input pin. Hi-Z The TAB on the bottom surface of the package TAB should be connected to AVSS. Note 2. All input pins except internal pull-up/down pins must not be left floating. Note 3. The AK4499 must be powered down by the PDN pin when changing Pin Control/Register Control modes by the PSN pin. Note 4. PCM mode, DSD mode, and EXDF mode are selectable in Register Control mode. Rev. 0.0-PB 2018/12 -9- [AK4499] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. 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Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. Thank you for your access to AKM products information. More detail product information is available, please contact our sales office or authorized distributors. Rev. 0.0-PB 2018/12 - 10 -