[AK4528]
AK4528
High Performance 24Bit 96kHz Audio CODEC
GENERAL DESCRIPTION
The AK4528 is a high performance 24bit CODEC for the 96kHz recording system. The ADC has an
Enhanced Dual Bit architecture with wide dynamic range. The DAC uses the new developed Advanced
Multi Bit architecture and achieves low out-band noise and high jitter tolerance by use of SCF (switched
capacitor filter) techniques.
FEATURES
• 24bit 2ch ADC
- 64x Oversampling
- Full differential Inputs
- S/(N+D): 94dB
- Dynamic Range, S/N: 108dB
- Digital HPF for offset cancellation
- I/F format: MSB justified or I2S
• 24bit 2ch DAC
- 128x Oversampling
- 24bit 8 times Digital Filter
Ripple: ±0.005dB, Attenuation: 75dB
- SCF
- Differential Outputs
- S/(N+D): 94dB
- Dynamic Range, S/N: 110dB
- De-emphasis for 32kHz, 44.1kHz and 48kHz sampling
- Output DATT with –72dB att
- Soft Mute
- I/F format: MSB justified, LSB justified or I2S
• High Jitter Tolerance
• 3-wire Serial Interface for Volume Control
• Master Clock
- 256fs/384fs/512fs/768fs/1024fs
• 5V operation
• 3V Power Supply Pin for 3V I/F
• Small 28pin SSOP package
MS0011-E-03
2013/03
-1-
[AK4528]
Block Diagram
AINL+
AINLAINR+
AINR-
ADC
VD
VT
DGND
PDN
HPF
Audio I/F
Controller
VCOM
AOUTL+
AOUTLAOUTR+
AOUTR-
DAC
VREF
VA
AGND
P/S
LRCK
BICK
SDTO
SDTI
DATT
SMUTE
Control Register I/F
Clock Divider
CSN CCLK CDTI
(DIF) (CKS1) (CKS0)
MCLK
DEM0
DEM1
DFS
Block Diagram
• Compatibility of AK4528 with AK4524
Function
ADC S/(N+D)
ADC DR, S/N
Input PGA & ATT
ADC Inputs
Master Mode
X’tal Oscillating Circuit
Quad Speed Mode
Parallel Mode
AK4528
94dB
108dB
X
Differential Inputs
X
X
X
O
O: Available, X: Not Available
MS0011-E-03
AK4524
90dB
100dB
O
Single-end Inputs
O
O
O
X
2013/03
-2-
[AK4528]
Ordering Guide
−40 ∼ +85°C
AK4528VM
28pin SSOP (0.65mm pitch)
Pin Layout
VCOM
1
28
AOUTR+
AINR+
2
27
AOUTR-
AINR-
3
26
AOUTL+
AINL+
4
25
AOUTL-
AINL-
5
24
DGND
VREF
6
23
VD
AGND
7
22
VT
VA
8
21
DEM1
P/S
9
20
DEM0
MCLK
10
19
PDN
LRCK
11
18
DFS
BICK
12
17
CSN(DIF)
SDTO
13
16
CCLK(CKS1)
SDTI
14
15
CDTI(CKS0)
AK4528
Top
View
MS0011-E-03
2013/03
-3-
[AK4528]
PIN/FUNCTION
No.
Pin Name
I/O
Function
1
VCOM
O
2
3
4
5
AINR+
AINR−
AINL+
AINL−
I
I
I
I
6
VREF
I
7
8
AGND
VA
-
9
P/S
I
10
11
12
13
14
MCLK
LRCK
BICK
SDTO
SDTI
CDTI
CKS0
CCLK
CKS1
I
I
I
O
I
I
I
I
I
Common Voltage Output Pin, VA/2
Bias voltage of ADC inputs and DAC outputs.
Rch Positive Input Pin
Rch Negative Input Pin
Lch Positive Input Pin
Lch Negative Input Pin
Voltage Reference Input Pin, VA
Used as a voltage reference by ADC & DAC. VREF is connected externally to
filtered VA.
Analog Ground Pin
Analog Power Supply Pin, 4.75 ∼ 5.25V
Parallel/Serial Mode Select Pin
“L”: Serial Mode, “H”: Parallel Mode
Master Clock Input Pin
Input/Output Channel Clock Pin
Audio Serial Data Clock Pin
Audio Serial Data Output Pin
Audio Serial Data Input Pin
Control Data Input Pin in Serial Mode
Master Clock Select Pin
Control Data Clock Pin in Serial Mode
Master Clock Select Pin
CSN
I
Chip Select Pin in Serial Mode
DIF
I
18
DFS
I
19
PDN
I
20
21
22
23
24
25
26
27
28
DEM0
DEM1
VT
VD
DGND
AOUTL−
AOUTL+
AOUTR−
AOUTR+
I
I
O
O
O
O
15
16
17
Digital Audio Interface Select Pin
“L”: 24bit MSB justified, “H”: I2S compatible
Double Speed Sampling Mode Pin
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initialize the control register.
De-emphasis Control Pin
De-emphasis Control Pin
Output Buffer Power Supply Pin, 2.7 ∼ 5.25V
Digital Power Supply Pin, 4.75 ∼ 5.25V
Digital Ground Pin
Lch Negative Analog Output Pin
Lch Positive Analog Output Pin
Rch Negative Analog Output Pin
Rch Positive Analog Output Pin
Note: All input pins should not be left floating.
MS0011-E-03
2013/03
-4-
[AK4528]
ABSOLUTE MAXIMUM RATINGS
(AGND=DGND=0V; Note 1)
Parameter
Power Supplies:
Analog
Digital
Output Buffer
VD−VA
Input Current, Any Pin Except Supplies
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (powered applied)
Storage Temperature
Symbol
VA
VD
VT
VDA
IIN
VINA
VIND
Ta
Tstg
min
−0.3
−0.3
−0.3
−0.3
−0.3
−40
−65
max
6.0
6.0
6.0
0.3
±10
VA+0.3
VA+0.3
85
150
Unit
V
V
V
V
mA
V
V
°C
°C
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND= DGND=0V; Note 1)
Parameter
Power Supplies Analog
Digital
Output Buffer
Voltage Reference
Symbol
VA
VD
VT
VREF
min
4.75
4.75
2.7
3.0
typ
5.0
5.0
3.0
-
max
5.25
VA
VD
VA
Unit
V
V
V
V
Note: 1. All voltages with respect to ground.
2. VA and VD should be powered at the same time or VA should be powered earlier than VD.
The power up sequence between VA and VT, or VD and VT is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0011-E-03
2013/03
-5-
[AK4528]
ANALOG CHARACTERISTICS
(Ta=25°C; VA=VD=VT=5.0V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit Data;
Measurement frequency = 20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs=96kHz; unless otherwise specified)
Parameter
min
typ
max
Unit
Input PGA Characteristics:
ADC Analog Input Characteristics: Analog Source impedance = 330Ω
Resolution
24
Bits
Input Voltage
(Note 3)
±2.6
±2.8
±3.0
Vpp
Input Resistance
fs=44.1kHz
16
27
kΩ
fs=96kHz
7
12
kΩ
S/(N+D)
(−0.5dBFS)
fs=44.1kHz
88
94
dB
fs=96kHz
84
92
dB
DR
(−60dBFS)
fs=44.1kHz, A-weighted
100
108
dB
fs=96kHz
95
103
dB
S/N
fs=44.1kHz, A-weighted
100
108
dB
fs=96kHz
95
103
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
20
ppm/°C
Input Voltage
(Note 3)
±2.6
±2.8
±3.0
Vpp
Input Resistance
fs=44.1kHz
16
27
kΩ
fs=96kHz
7
12
kΩ
Input DC Bias Voltage
(Note 4)
0.56VA
0.60VA
V
Power Supply Rejection
(Note 5)
50
dB
DAC Analog Output Characteristics:
Resolution
24
Bits
S/(N+D)
(0dBFS)
fs=44.1kHz
88
94
dB
fs=96kHz
85
93
dB
DR
(−60dBFS)
fs=44.1kHz, A-weighted
104
110
dB
fs=96kHz
96
104
dB
S/N
fs=44.1kHz, A-weighted
104
110
dB
fs=96kHz
96
104
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
20
ppm/°C
Output Voltage
(Note 6)
5.0
5.4
5.8
Vpp
Load Resistance
(In case of AC load)
1
kΩ
Output Current
1.5
mA
Load Capacitance
25
pF
Power Supply Rejection
(Note 5)
50
dB
Note: 3. This voltage is input to AIN+ and AIN− pin, and is proportional to VREF. Vin = 0.56 x VREF.
4. Measured by Figure 12. DC Bias Voltage, Vb = 4.7k / (3.3k + 4.7k) x VA = 0.5875VA.
5. PSR is applied to VA, VD, VT with 1kHz, 50mVpp. VREF pin is held a constant voltage.
6. Full scale (0dB) of the output voltage when summing the differential outputs, AOUT+/− by unity gain.
This voltage is proportional to VREF. Vout=1.08 x VREF x Gain.
MS0011-E-03
2013/03
-6-
[AK4528]
Parameter
min
typ
max
Unit
38
10
18
57
20
36
mA
mA
mA
10
10
100
100
μA
μA
Power Supplies
Power Supply Current
Normal Operation (PDN=“H”)
VA
VD+VT
(fs=44.1kHz)
(fs=96kHz)
Power-down mode (PDN=“L”)
(Note 7)
VA
VD+VT
Note: 7. All digital input pins are held VD or DGND.
FILTER CHARACTERISTICS
(Ta=25°C; VA, VD=4.75 ∼ 5.25V; VT=2.7 ∼ 5.25V; fs=44.1kHz; DEM=OFF)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
Passband
(Note 8) −0.005dB
PB
0
−0.02dB
−0.06dB
−6.0dB
Stopband
SB
24.34
Passband Ripple
PR
Stopband Attenuation
SA
80
Group Delay
(Note 9)
GD
Group Delay Distortion
ΔGD
ADC Digital Filter (HPF):
Frequency Response (Note 8) −3dB
FR
−0.5dB
−0.1dB
DAC Digital Filter:
Passband
(Note 8) −0.01dB
PB
0
−6.0dB
Stopband
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
75
Group Delay
(Note 9)
GD
DAC Digital Filter + SCF:
Frequency Response:
FR
0 ∼ 20.0kHz
∼ 40kHz (Note 10)
typ
max
Unit
20.02
20.20
22.05
19.76
-
31
0
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
0.9
2.7
6.0
Hz
Hz
Hz
±0.005
30
kHz
kHz
kHz
dB
dB
1/fs
±0.2
±0.3
dB
dB
22.05
20.0
±0.005
Note: 8. The passband and stopband frequencies scale with fs.
For example, 20.02kHz at -0.02dB is 0.454 x fs. The reference frequency of these responses is 1kHz.
9. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to
setting the 24bit data of both channels to the output register for ADC.
For DAC, this time is from setting the 24bit data of both channels on input register to the output of analog signal.
10. fs=96kHz.
MS0011-E-03
2013/03
-7-
[AK4528]
DC CHARACTERISTICS
(Ta=25°C; VA=VD=4.75 ∼ 5.25V; VT=2.7 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout=−100μA) (Note 11)
VOH
2.7 / VT−0.5
Low-Level Output Voltage (Iout=100μA)
VOL
Input Leakage Current
Iin
-
typ
-
max
0.8
0.5
±10
Unit
V
V
V
V
μA
Note: 11. The min value is lower voltage of 2.7V or VT−0.5V.
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=VD=4.75 ∼ 5.25V, VT=2.7 ∼ 5.25V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
7.68
fCLK
Frequency
0.4/fCLK
tCLKL
Pulse Width Low
0.4/fCLK
tCLKH
Pulse Width High
LRCK Frequency
Normal Speed Mode (DFS = “0”)
Double Speed Mode (DFS = “1”)
Duty Cycle
Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 12)
BICK “↑” to LRCK Edge
(Note 12)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
fsn
fsd
Duty
30
60
45
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
33
33
20
20
typ
44.1
88.2
max
Unit
55.296
MHz
ns
ns
54
108
55
kHz
kHz
%
40
40
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 12. BICK rising edge must not occur at the same time as LRCK edge.
MS0011-E-03
2013/03
-8-
[AK4528]
Parameter
Symbol
min
Control Interface Timing (P/S=“L”)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “L” Time
CSN “↑” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSW
tCSS
tCSH
200
80
80
40
40
150
150
150
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPD
tPDV
tPDV
150
ns
1/fs
1/fs
Reset Timing
PDN Pulse Width
RSTADN “↑” to SDTO valid
PDN “↑” to SDTO valid
(Note 13)
(Note 14)
(Note 15)
typ
max
516
516
Unit
Note: 13. The AK4528 can be reset by bringing PDN “L”.
14. In serial mode, these cycles are the number of LRCK rising from RSTADN bit.
15. In parallel mode, these cycles are the number of LRCK rising from PDN pin.
Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
MS0011-E-03
2013/03
-9-
[AK4528]
VIH
VIL
LRCK
tBLR
tLRB
VIH
VIL
BICK
tLRS
tBSD
SDTO
50%VT
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing
VIH
VIL
CSN
tCCKL tCCKH
tCSS
VIH
VIL
CCLK
tCDS
CDTI
C1
tCDH
C0
A4
R/W
VIH
VIL
WRITE Command Input Timing
tCSW
VIH
VIL
CSN
tCSH
VIH
VIL
CCLK
CDTI
D3
D2
D1
VIH
VIL
D0
WRITE Data Input Timing
tPD
PDN
VIL
Power Down & Reset Timing
MS0011-E-03
2013/03
- 10 -
[AK4528]
OPERATION OVERVIEW
System Clock Input
The external clocks, which are required to AK4528, are MCLK, BICK and LRCK. MCLK should be synchronized with
LRCK but the phase is not critical. The frequency of MCLK is set by CMODE, CKS0-1 and DFS bits in serial mode, or
by CKS0-1, DFS pins in parallel mode (see Table 2 and 3). The CKS0-1 and DFS pin should be changed during the PDN
pin = “L”. The CMODE, CKS0-1 and DFS bits are changed during RSTADN = RSTDAN = “0”.
External clocks (MCLK, BICK and LRCK) should always be present whenever the AK4528 is in normal operation mode
(PDN = “H” and at least one of ADC and DAC is in normal operation mode). If these clocks are not provided, the
AK4528 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are
not present, the AK4528 should be in the power-down mode (PDN = “L” or set both ADC and DAC power down mode
by the register).
CMODE bit
CKS1 bit
CKS0 bit
MCLK
Normal Speed
(DFS bit = “0”)
MCLK
Double Speed
(DFS bit = “1”)
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
256fs
512fs
1024fs
384fs
768fs
N/A
256fs
512fs
N/A
384fs
Default
Table 1. Master Clock Frequency Select in Serial Mode
CKS1 pin
CKS0 pin
MCLK
Normal Speed
(DFS pin = “L”)
L
L
H
H
L
H
L
H
256fs
512fs
384fs
1024fs
MCLK
Double Speed
(DFS pin = “H”)
N/A
256fs
N/A
512fs
Table 2. Master Clock Frequency Select in Parallel Mode
MCLK
Normal Speed
(DFS = “0”)
256fs
512fs
1024fs
384fs
768fs
fs=44.1kHz
fs=48kHz
11.2896MHz
22.5792MHz
45.1584MHz
16.9344MHz
33.8688MHz
12.288MHz
24.576MHz
49.152MHz
18.432MHz
36.864MHz
MCLK
Double Speed
(DFS = “1”)
N/A
256fs
512fs
N/A
384fs
fs=88.2kHz
fs=96kHz
N/A
22.5792MHz
45.1584MHz
N/A
33.8688MHz
N/A
24.576MHz
49.152MHz
N/A
36.864MHz
Table 3. Master Clock Frequencies example
Note. Do not set any mode which is not described in Table1-3.
MS0011-E-03
2013/03
- 11 -
[AK4528]
Audio Serial Interface Format
In case of serial mode, the DIF0-2 bits as shown in Table 4 support five serial formats. In case of parallel mode, two
formats (Mode 2 and 3) are supported by DIF pin (Table 5). In all modes the serial data is MSB-first, 2’s compliment
format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge.
Mode
DIF2 bit
DIF1 bit
DIF0 bit
SDTO
SDTI
LRCK
BICK
0
1
2
3
0
0
0
0
0
0
1
1
0
1
0
1
24bit, MSB justified
24bit, MSB justified
24bit, MSB justified
24bit, I2S
16bit, LSB justified
20bit, LSB justified
24bit, MSB justified
24bit, I2S
H/L
H/L
H/L
L/H
≥ 32fs
≥ 40fs
≥ 48fs
≥ 48fs
4
1
0
0
24bit, MSB justified
24bit, LSB justified
H/L
≥ 48fs
Defaul
t
Table 4. Audio data format in Serial Mode
Mode
DIF pin
SDTO
SDTI
LRCK
BICK
2
3
0
1
24bit, MSB justified
24bit, I2S
24bit, MSB justified
24bit, I2S
H/L
L/H
≥ 48fs
≥ 48fs
Table 5. Audio data format in Parallel Mode
LRCK
0
1
2
3
9
10
11
12
13
14
15
0
1
2
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
23 22 21
15 14 13 12 11 10
SDTI(i)
15 14 13
7
0
1
2
3
6
17
4
5
18
19
3
2
20
9
8
23 22 21
15 14 13 12 11 10
9
8
23
1
0
15 14 13
7
1
0
15
30
31
0
1
2
3
6
17
5
18
4
19
3
2
20
31
0
1
BICK(64fs)
SDTO(o)
23 22 21
SDTI(i)
7
Don’t Care
6
5
4
3
23 22 21
15 14 13 12 11
2
1
7
Don’t Care
0
6
5
4
3
23
15 14 13 12 11
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
2
1
0
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
12 11 10
Don’t Care
19 18
0
8
23 22
7
1
0
12 11 10
Don’t Care
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
19 18
0
8
23
7
1
0
Rch Data
Figure 2. Mode 1 Timing
MS0011-E-03
2013/03
- 12 -
[AK4528]
LRCK
0
1
2
18
19
20
21
22
23
24
25
0
1
2
18
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
19
20
21
22
23
24
25
0
1
2
3
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
LRCK
0
1
2
8
9
10
20
21
31
0
1
2
8
9
10
20
21
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
16 15 14
Don’t Care
23:MSB, 0:LSB
23 22
0
12 11
23 22
1
0
16 15 14
Don’t Care
Lch Data
23 22
0
12 11
23
1
0
Rch Data
Figure 5. Mode 4 Timing
MS0011-E-03
2013/03
- 13 -
[AK4528]
Parallel/Serial Mode Control
When P/S= “H”, AK4528 is in parallel mode. The audio interface format is selected by DIF pin, and DFS and CK0-1 pins
select the frequency of MCLK.
When P/S= “L”, AK4528 is in serial mode. The CKS1, CKS0 and DIF pins are changed to CDTI, CCLK and CSN pins
respectively. The DEM0-1 and DFS are ORed between pin and register respectively, so those are able to control by pins
even in serial mode. To control all the functions by register, set DEM0-1 and DFS pins “L”.
Digital High Pass Filter
The ADC has a digital high pass filter (HPF) for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at
fs=44.1kHz and also scales with sampling rate (fs). This HPF can be off for each channel by register.
Output Volume
The AK4528 includes digital volumes (OATT) with 128 levels (including MUTE) in front of DAC. The OATT is a
pseudo-log volume linear-interpolated internally. When the level is changed, the transition to new value takes 8031 levels
(max) and is done by soft transition. Therefore, there is not any switching noise.
De-emphasis Filter
The DAC includes the digital de-emphasis filter (tc=50/15μs) by IIR filter. This filter supports to three frequencies
(32kHz, 44.1kHz and 48kHz). This setting is done by contorl register and always OFF at double speed mode.
No
0
1
2
DEM1
0
0
1
DEM0
0
1
0
Mode
44.1kHz
OFF
48kHz
3
1
1
32kHz
Default in serial
mode
Table 6. De-emphasis control (DFS=“0”)
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[AK4528]
Soft Mute Operation
Soft mute operation is performed at digital domain. When SMUTE goes “1”, the output signal is attenuated by −∞ during
1024 LRCK cycles. When SMUTE is returned to “0”, the mute is cancelled and the output attenuation gradually changes
to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting of the operation,
the attenuation is discontinued and returned to 0dB.
Soft mute function is independent to output volume, and those two functions are cascade connected.
SMUTE
1024/fs
0dB
1024/fs
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
Notes:
(1) The output signal is attenuated by −∞ during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
Figure 6. Soft Mute
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[AK4528]
Power Down & Reset
The ADC and DAC of AK4528 are placed in the power-down mode by bringing a power down pin (PDN)=“L” and each
digital filter is also reset at the same time. The internal register values are initialized by PDN = “L”. This reset should
always be done after power-up.
In case of serial mode, the default value of both control registers for ADC and DAC are in reset state (RSTADN =
RSTDAN = “0”), each register sholud be cancelled after doing the needed setting. In case of the ADC, an analog
initialization cycle starts after exiting the power-down or reset state. Therefore, the output data, SDTO becomes available
after 516 cycles of LRCK. In case of DAC, the initialization cycle starts after PDN = “H” or PWVR bit = “1”. The power
down mode can be also controlled by the registers (PWAD, PWDA).
Power Supply
PDN pin
RSTADN(registe
RSTDAN(registe
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
PD
Reset INITA
SDTO
DAC Internal State
Normal
“0”
PD
Output
Reset
INITD
OATT
PD
INITA
“0”
Normal
00H → XXH
00H
Normal
PD
Output
“0”
PD
XXH
PD
Normal
00H → XXH
00H
00H
XXH
Normal
INITD
00H → XXH
512/fs
AOUT
External Mute
Example
External clocks
“0”
Hi-Z
*
XXH
512/fs
FI
Output
*
FI
Hi-Z
*
Output
*
FI
Hi-Z
*
Output
*
MCLK, LRCK, BICK
The clocks can be stopped.
• INITA:
• INITD:
• PD:
hold.
• XXH:
• FI:
• AOUT:
Initializing period of ADC analog section (516/fs).
Initializing period of DAC analog section (512/fs).
Power down state. In case of PDN = “L”, the contents of all registers are initialized, otherwise
The current value in ATT register.
Fade in. After exiting power down and reset state, ATT value fades in by 8032/fs cycles (max).
Some pop noise may occur at “*”.
Figure 7. Reset & Power down sequence in Serial Mode
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[AK4528]
In case of parallel mode, both ADC and DAC are powered up with releasing internal reset state when PDN is set to “H”.
Therefore each outputs start to output at once. However the initialization of ADC/DAC, and the fade-in cycle of OATT
(8031/fs) are exist.
Power Supply
PDN pin
ADC Internal State
PD
INITA
Normal
“0”
Output
INITD
Normal
SDTO
DAC Internal State
PD
OATT
00H
PD
INITA
Normal
“0”
PD
00H → 7FH
7FH
Output
INITD
Normal
00H → 7FH
00H
512/fs
AOUT
External Mute
Example
External clocks
Hi-Z
FI
7FH
512/fs
Output
*
Hi-Z
*
MCLK, LRCK, BICK
FI
Output
*
MCLK, LRCK, BICK
The clocks can be stopped.
• INITA:
• INITD:
• PD:
• FI:
• AOUT:
Initializing period of ADC analog section (516/fs).
Initializing period of DAC analog section (512/fs).
Power down state.
Fade in. After exiting power down state, ATT value fades in by 8032/fs cycles.
Some pop noise may occur at “*”.
Figure 8. Reset & Power Down Sequence in Parallel Mode
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[AK4528]
Serial Control Interface
The serial control interface is enabled by the P/S pin = “L”. The internal registers are written by the 3-wire μP interface
pins: CSN, CCLK, CDTI. The data on this interface consists of Chip address (2bits, fixed to C0/1 = “01”) Read/Write
(1bit, fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in
on the rising edge of CCLK. Data is latched after a low-to-high transition of CSN. The maximum clock speed of the
CCLK is 5MHz. The CSN should be “H” if no access. The chip address is fixed to “10”. Writing is invalid for the access
to the chip address except for “10”. PDN = “L” resets the registers to their default values.
Function
Parallel mode
Serial mode
Double speed
O
De-emphasis
O
SMUTE
X
Output Digital ATT
X
HPF off
X
MCLK; 768fs@Normal Speed
X
384fs@Double Speed
16/20/24bit LSB justified format
X
Table 7. Function list (O: available, X: not available)
O
O
O
O
O
O
O
When PDN = “L”, internal registers are initialized. In case of changing P/S pin, please set PDN = “L” to reset the device.
In case of serial mode, the internal timings are initialized by RSTN = “0”, but the contents of registers are hold.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “10”)
READ/WRITE (Fixed to “1”:WRITE only)
Register Address
Control data
Figure 9. Control I/F Timing
*AK4528 does not support the READ. C1, C0 and R/W are fixed (“101”).
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[AK4528]
Register Map
Addr
00H
01H
02H
03H
04H
05H
Register Name
Power Down Control
Reset Control
Clock and Format Control
Deem and Volume Control
Lch ATT Control
Rch ATT Control
D7
0
TE7
DIF2
SMUTE
0
0
D6
0
TE6
DIF1
0
ATTL6
ATTR6
D5
0
TE5
DIF0
0
ATTL5
ATTR5
D4
0
TE4
CMODE
0
ATTL4
ATTR4
D3
0
0
CKS1
HPFR
ATTL3
ATTR3
D2
PWVR
0
CKS0
HPFL
ATTL2
ATTR2
D1
PWAD
RSTADN
0
DEM1
ATTL1
ATTR1
D0
PWDA
RSTDAN
DFS
DEM0
ATTL0
ATTR0
Note: For address from 06H to 1FH, data should not be written.
In case of writing to 01H, write “0000” to D7-4.
PDN = “L” resets the registers to their default values.
Control Register Setup Sequence
The setting of clock mode or data format by control register should be done during RSTADN = RSTDAN = “0”, and
outputs of ADC/DAC should be muted.
1. In case of using PDN pin
(1) Set PDN= “H”.
(2) Set registers for clock mode, data format, etc.
(3) Cancel the reset state by setting RSTADN or RSTDAN to “1”. Refer to Reset Contorl Register (01H).
2. In case of not using PDN pin
(1) Set RSTADN = RSTDAN = “0”.
(2) Set registers for clock mode, data format, etc.
(3) Cancel the reset state by setting RSTADN or RSTDAN to “1”. Refer to Reset Contorl Register (01H).
Note: Those settings may generate pop noise. Please mute the output of ADC and DAC externally.
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[AK4528]
Register Definitions
Addr
00H
Register Name
Power Down Control
default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
PWVR
1
D1
PWAD
1
D0
PWDA
1
PWDA: DAC power down
0: Power down
1: Power up
Only DAC section is powered down by “0” and then the AOUTs go Hi-Z immediately. The OATTs also go
“00H”. But the contents of all register are not initialized and enabled to write to the registers.
After exiting the power down mode, the OATTs fade in the setting value of the control register (04H &
05H). The analog outputs should be muted externally as some pop noise may occur when entering to and
exiting from this mode.
PWAD: ADC power down
0: Power down
1: Power up
Only ADC section is powered down by “0” and then the SDTO goes “L” immediately. The contents of all
register are not initialized and enabled to write to the registers.
After exiting the power down mode, ADC outputs “0” during first 516 LRCK cycles.
PWVR: Vref power down
0: Power down
1: Power up
All sections are powered down by “0” and then both ADC and DAC do not operate. The contents of all
register are not initialized and enabled to write to the registers. When PWAD and PWDA go “0” and
PWVR goes “1”, only VREF section can be powered up.
Addr
01H
Register Name
Reset Control
default
D7
TE7
0
D6
TE6
0
D5
TE5
0
D4
TE4
0
D3
0
0
D2
0
0
D1
RSTADN
0
D0
RSTDAN
0
TE7-4: Test Control Register Enable
Must be fixed to “0000”.
RSTDAN: DAC reset
0: Reset
1: Normal Operation
The internal timing is reset by “0” and then the AOUTs go VCOM voltage immediately. The OATTs also
go “00H”. But the contents of all register are not initialized and enabled to write to the registers. After
exiting the power down mode, the OATTs fade in the setting value of the control register (06H & 07H). The
analog outputs should be muted externally as some pop noise may occur when entering to and exiting from
this mode.
RSTDAN: ADC reset
0: Reset
1: Normal Operation
The internal timing is reset by “0” and then SDTO goes “L” immediately. But the contents of all register are
not initialized and enabled to write to the register.
After exiting the power down mode, ADCs output “0” during first 516 LRCK cycles.
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[AK4528]
Addr
02H
Register Name
Clock and Format Control
default
D7
DIF2
0
D6
DIF1
1
D5
DIF0
0
D4
CMODE
0
D3
CKS1
0
D2
CKS0
0
D1
0
0
D0
DFS
0
D3
HPFR
1
D2
HPFL
1
D1
DEM1
0
D0
DEM0
0
DFS: Sampling Speed Control (see Table 1 and Table 3)
Default : normal speed mode.
Ored with DFS pin internally.
CMODE, CKS1-0: Master Clock Frequency Select (see Table 1)
Default: 256fs
DIF2-0: Audio data interface modes (see Table 4)
000: Mode 0
001: Mode 1
010: Mode 2
011: Mode 3
100: Mode 4
Default : 24bit MSB justified for both ADC and DAC
Addr
03H
Register Name
Deem and Volume Control
default
D7
SMUTE
0
D6
0
0
D5
0
0
D4
0
0
DEM1-0: De-emphasis response (see Table 6)
00: 44.1kHz
01: OFF
10: 48kHz
11: 32kHz
Default : 44.1kHz.
ORed with DEM1, DEM0 pins respectively.
HPFR: Right channel Digital High Pass Filter Control
0: Disable
1: Enable
Default : Enable
HPFL: Left channel Digital High Pass Filter Control
0: Disable
1: Enable
Default : Enable
SMUTE: DAC Input Soft Mute control
0: Normal operation
1: DAC outputs soft-muted
The soft mute is independent of the output ATT and performed digitally.
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[AK4528]
Addr
04H
05H
Register Name
Lch OATT Control
Rch OATT Control
default
D7
0
0
0
D6
ATTL6
ATTR6
1
D5
ATTL5
ATTR5
1
D4
ATTL4
ATTR4
1
D3
ATTL3
ATTR3
1
D2
ATTL2
ATTR2
1
D1
ATTL1
ATTR1
1
D0
ATTL0
ATTR0
1
ATTL/R6-0: DAC ATT Level (see Table 8)
Default : 7FH (0dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
ATT (dB)
Step (dB)
127
111
95
79
63
47
31
Step(dB)
ATT(dB)
The OATTs are set to “00H” when PDN pin goes “L”. After returning to “H”, the OATTs fade in the
initial value, “7FH” by 8031 cycles. The OATTs are set to “00H” when PWDA goes “0”. After returning to
“1”, the OATTs fade in the current value. The OATTs are set to “00H” when RSTDAN goes “0”. Afer
returning to “1”, the OATTs fade in the current value.
15
Input Data(Level)
Figure 10. ATT characteristics
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[AK4528]
Data
127
126
125
:
112
111
110
:
96
95
94
:
80
79
78
:
64
63
62
:
48
47
46
:
32
31
30
:
16
15
14
:
5
4
3
2
1
0
Internal
(DATT)
8031
7775
7519
:
4191
3999
3871
:
2079
1983
1919
:
1023
975
943
:
495
471
455
:
231
219
211
:
99
93
89
:
33
30
28
:
10
8
6
4
2
0
Gain (dB)
Step width (dB)
0
−0.28
−0.57
:
−5.65
−6.06
−6.34
:
−11.74
−12.15
−12.43
:
−17.90
−18.32
−18.61
:
−24.20
−24.64
−24.94
:
−30.82
−31.29
−31.61
:
−38.18
−38.73
−39.11
:
−47.73
−48.55
−49.15
:
−58.10
−60.03
−62.53
−66.05
−72.07
MUTE
0.28
0.29
:
0.51
0.41
0.28
:
0.52
0.41
0.28
:
0.53
0.42
0.29
:
0.54
0.43
0.30
:
0.58
0.46
0.32
:
0.67
0.54
0.38
:
0.99
0.83
0.60
:
1.58
1.94
2.50
3.52
6.02
OATT
External 128 levels are converted to internal
8032 linear levels of DATT. Internal DATT
soft-changes between DATAs.
DATT=2^m x (2 x l + 33) – 33
m: MSB 3-bits of data
l: LSB 4-bits of data
Table 8. OATT code table
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[AK4528]
SYSTEM DESIGN
Figure 11 shows the system connection diagram. An evaluation board (AKD4528) is available which demonstrates
application circuits, the optimum layout, power supply arrangements and measurement results.
4.75 ∼ 5.25V
Analog Supply
0.1u
2.2u
+
1
VCOM
AOUTR+ 28
Rch
Input
Buffer
2
AINR+
AOUTR-
27
3
AINR-
AOUTL+
26
Lch
Input
Buffer
4
AINL+
AOUTL-
25
5
AINL-
DGND
24
6
VREF
VD
23
7
AGND
VT
22
8
VA
DEM1
21
9
P/S
DEM0
20
10 MCLK
PDN
19
11 LRCK
DFS
18
12 BICK
CSN/DIF 17
10u +
AK4528
Rch
LPF
Rch Out
Lch
LPF
Lch Out
5
0.1u
0.1u
2.7 ∼ 5.25V
Digital Supply
0.1u
Audio
Controller
13 SDTO
CCLK/CKS1 16
14 SDTI
CDTI/CKS0
Mode
Setting
15
Notes:
- AGND and DGND of AK4528 should be distributed separately from the ground of external controller etc.
- When AOUT+/− drives some capacitive load, some resistor should be added in series between AOUT+/− and
capacitive load.
- All input pins should not be left floating.
Figure 11. Typical Connection Diagram
1. Grounding and Power Supply Decoupling
The AK4528 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied
from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is taken care.
VT is a power supply pin to interface with the external ICs and is supplied from digital supply in system. AGND and
DGND of the AK4528 should be connected to analog ground plane. System analog ground and digital ground should be
connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be
as near to the AK4528 as possible, with the small value ceramic capacitor being the nearest.
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[AK4528]
2. Voltage Reference
The differential voltage between VREF and AGND sets the analog input/output range. VREF pin is normally connected
to VA with a 0.1µF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2µF parallel with
a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be
drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to
avoid unwanted coupling into the AK4528.
3. Analog Inputs
The IPGA inputs are single-ended and the input resistance 27kΩ (typ. @fs=44.1kHz). The input signal range scales with
the VREF voltage and nominally 0.56 x VREF Vpp. It is recommended that the input DC bias voltage is 0.56VA ∼
0.60VA as centered in the internal common voltage about VA/2). The AK4528 can accept input voltages from AGND to
VA. The ADC output data format is 2’s complement. The output code is 7FFFFFH(@24bit) for input above a positive full
scale and 800000H(@24bit) for input below a negative fill scale. The ideal code is 000000H(@24bit) with no input
signal. The DC offset including ADC own DC offset removed by the internal HPF (fc=0.9Hz@fs=44.1kHz).
The AK4528 samples the analog inputs at 64fs. The digital filter rejects noise above the stopband except for multiples of
64fs. A simple RC filter may be used to attenuate any noise around 64fs though most audio signals do not have significant
energy at 64fs. Figure 12 is an example of differential input circuit.
5.96Vpp
4.7k
4.7k
2.8Vpp
AK4528
1.5nF
330
AINR+ 2
330
AINR-
Vop+
10k
4.7k
+
NJM5532
Signal
VA
Vop-
3
3.3k
2.8Vpp
AINL+ 4
Vop+/-=+/-15V
VA=5V
AINL-
5
fc = 160kHz,
0.1µ
BIAS
4.7k
Same circuit
Input RC filter response :
22µ
+
+
10µ
g = -0.07dB at 20kHz, -0.26dB at 40kHz.
Figure 12. Differential Input Buffer Example
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[AK4528]
4. Analog Outputs
The analog outputs are full differential outputs and nominally 0.54 x VREF Vpp centered in the internal common voltage
(about VA/2). The differential outputs are summed externally, Vout=(AOUT+) − (AOUT−) between AOUT+ and
AOUT−. If the summing gain is 1, the output range is 5.4Vpp (typ@VREF=5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2’s complement. The output voltage is a positive full scale
for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal AOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filter and the external LPF attenuate the noise generated by the delta-sigma modulator
beyond the audio passband.
Differential outputs can eliminate any DC offset on analog outputs without using capacitors. Figure 13 to Figure 15 show
the example of external op-amp circuit summing the differential outputs.
4.7k
4.7k
AOUTR1
Vop
3300p
4.7k
R1
AOUT+
Vop
4.7k
470p
+
Analog
Out
470p
1k
BIAS 0.1µ
+
47µ
1k
When R1=200ohm
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180ohm
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 13. External 2nd order LPF Example (using single supply op-amp)
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[AK4528]
4.7k
4.7k
AOUT470p
R1
+Vop
3300p
4.7k
R1
4.7k
Analog
Out
+
AOUT+
470p
-Vop
When R1=200ohm
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180ohm
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 14. External 2nd order LPF Example (using dual supply op-amp)
180p
4.7k
4.7k
AOUT+Vop
4.7k
4.7k
Analog
Out
+
AOUT+
180p
-Vop
fc=188kHz
Figure 15. External low cost 1st order LPF Example (using dual supply op-amp)
Peripheral I/F Example
The digital inputs of the AK4528 are TTL inputs and can accept the signal of device with a nominal 3V supply. The
digital output can interface with the peripheral device with a nominal 3V supply when the VT supply operates at a
nominal 3V supply.
5V Analog
3V Digital
Audio signal
Analog
Digital
DSP
I/F
3 or 5V Digital
AK4528
Control signal
uP &
Others
Figure 16. Power supply connection example
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[AK4528]
PACKAGE
28pin SSOP (Unit: mm)
2.1MAX
10.40MAX
28
15
5.30
7.90±0.20
A
14
1
0.22±0.05
0.65
0.32±0.08
0.1±0.1
0.60±0.15
Detail A
0.10
1.30
Seating Plane
NOTE: Dimension "*" does not include mold flash.
0-8°
Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate
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[AK4528]
MARKING
AKM
AK4528VM
XXXBYYYYC
XXXBYYYYC: Date code identifier
XXXB: Lot number (X: Digit number, B: Alpha character)
YYYYC: Assembly date (Y: Digit number, C: Alpha character)
REVISION HISTORY
Date (Y/M/D)
00/01/24
03/01/07
Revision
00
01
12/01/12
02
13/03/08
03
Reason
First Edition
Error
Correction
Specification
Change
Error
Correction
Page
Contents
7
FILTER CHARACTERISTICS
ADC Passband: 22.20 → 20.20
AK4528VF was deleted. (28pin VSOP)
AK4528VM was added. (28pin SSOP)
Ordering Guide was changed.
PACKAGE was changed.
MARKING was changed.
MARKING
Marking drawing was changed.
1, 3,
28, 29
29
MS0011-E-03
2013/03
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[AK4528]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants
any license to any intellectual property rights or any other rights of AKM or any third party with
respect to the information in this document. You are fully responsible for use of such information
contained in this document in your product design or applications. AKM ASSUMES NO
LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which
may cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace
industry, medical equipment, equipment used for automobiles, trains, ships and other
transportation, traffic signaling equipment, equipment used to control combustions or explosions,
safety devices, elevators and escalators, devices related to electric power, and equipment used in
finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in
writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations in
which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and
regulations. The Products and related technology may not be used for or incorporated into any
products or systems whose manufacture, use, or sale is prohibited under any applicable domestic
or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as
a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
MS0011-E-03
2013/03
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