AK4637EN

[AK4637] AK4637 24bit Mono CODEC with MIC/SPK-AMP 1. General Description The AK4637 is a low power 24-bit Mono CODEC with a microphone and speaker amplifiers. The AK4637 supports sampling frequency from 8kHz to 48kHz. It is suitable for a wide range of application from speech signal processing for narrowband, wideband and super wideband to sound signal processing for audio band. The input circuits include a microphone amplifier and a high performance digital ALC (automatic level control) circuit. In addition, the output circuits include a speaker amplifier with 1W output power. It is suitable for various products as well as portable applications with recording/playback function. The AK4637 are available in a small 20-pin QFN (3mm x 3mm, 0.4mm pitch: AK4637EN) package saving mounting area on the board. Application:  IP Camera  Digital Camera  MFP(Multi Function Printer) 2. Features 1. 2. 3. Recording Functions  Analog Input 1 Monaural Single-ended input or Differential input  Microphone Amplifier: +30dB ~ 0dB, 3dB Step  Microphone Power Supply: 2.0V or 2.4V, Noise Level= 108dBV  Digital ALC (Automatic Level Control) - Setting Range: +36dB  52.5dB, 0.375dB Step & Mute  ADC Performance: S/(N+D): 83dB, DR, S/N: 88dB (MIC-Amp=+18dB) S/(N+D): 84dB, DR, S/N: 95dB (MIC-Amp=0dB)  Wind Noise Reduction Filter  5-Band Notch Filter: Include Dynamic Gain Control  Digital Microphone Interface Playback Functions  Digital ALC (Automatic Level Control) - Setting Range: +36dB ~ 52.5dB, 0.375dB Step & Mute  Sidetone Mixer & Volume Control (0dB ~ 18dB, 6dB Step)  Digital Volume Control - +12dB ~ 89.5dB, 0.5dB Step & Mute  Mono Speaker Amplifier (with Line Output Switch) - Speaker Amplifier Porformance: S/(N+D): 75dB@250mW, S/N: 97 dB - BTL Output - Output Power: 400mW@8 (AVDD=3.3V), 1W@8 (AVDD=5V)  Analog Mixing: BEEP Input Power Management 015010680-E-00 2015/09 -1- [AK4637] 4. Master Clock: (1) PLL Mode Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin), 16fs, 32fs, 64fs (BICK pin) (2) External Clock Mode Frequencies: 256fs, 384fs, 512fs or 1024fs (MCKI pin) 5. Sampling Frequencies  PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz  PLL Slave Mode (BICK pin): 8kHz ~ 48kHz  EXT Master/Slave Mode: 8kHz ~ 48kHz (256fs, 384fs, 512fs), 8kHz  24kHz (1024fs) 6. Master/Slave Mode 7. Audio Interface Format: MSB First, 2’s complement  ADC: DSP Mode, 16/24bit MSB justified, 16/24bit I2S  DAC: DSP Mode, 16/24bit MSB justified, 16bit LSB justified, 16/24bit I2S 8. P I/F: I2C Bus (Ver 1.0, 400kHz Fast-Mode) 9. Operating Temperature: Ta = 40  85C 10. Power Supply  Analog Power Supply (AVDD): 2.8 ~ 5.5V  Digital Power Supply (DVDD): 1.6 ~ 1.98V  Digital I/O Power Supply (TVDD): 1.6 or (DVDD – 0.2) ~ 3.6V 11. Package:  20-pin QFN (3 x 3 mm, 0.4mm pitch) 015010680-E-00 2015/09 -2- [AK4637] 3. Table of Contents 1. 2. 3. 4. 5. General Description ............................................................................................................................. 1 Features............................................................................................................................................... 1 Table of Contents ................................................................................................................................ 3 Block Diagram ..................................................................................................................................... 5 Pin Configurations and Functions ....................................................................................................... 6 ■ Pin Layout .......................................................................................................................................... 6 ■ Comparison Table of the AK4951EN................................................................................................. 7 ■ PIN/FUNCTION.................................................................................................................................. 9 ■ Handling of Unused Pin ..................................................................................................................... 9 6. Absolute Maximum Ratings............................................................................................................... 10 7. Recommended Operating Conditions ............................................................................................... 10 8. Electrical Characteristics ................................................................................................................... 11 ■ Analog Characteristics ..................................................................................................................... 11 ■ Power Consumption on Each Operation Mode ............................................................................... 13 ■ Filter Characteristics ........................................................................................................................ 14 ■ DC Characteristics ........................................................................................................................... 15 ■ Switching Characteristics ................................................................................................................. 16 ■ Timing Diagram ................................................................................................................................ 20 9. Functional Descriptions ..................................................................................................................... 27 ■ System Clock ................................................................................................................................... 27 ■ Master Mode/Slave Mode ................................................................................................................ 27 ■ PLL Mode ......................................................................................................................................... 28 ■ PLL Unlock State ............................................................................................................................. 28 ■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) .......................................................................... 29 ■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) ............................................................................ 31 ■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) ........................................................................... 32 ■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) ......................................................................... 33 ■ System Reset ................................................................................................................................... 34 ■ Audio Interface Format .................................................................................................................... 35 ■ MIC/LINE Input Selector .................................................................................................................. 39 ■ Microphone Gain Amplifier............................................................................................................... 39 ■ Microphone Power ........................................................................................................................... 40 ■ Digital Microphone ........................................................................................................................... 41 ■ Digital Block ..................................................................................................................................... 43 ■ Digital HPF1 ..................................................................................................................................... 45 ■ Digital Programmable Filter Circuit .................................................................................................. 45 ■ ALC Operation ................................................................................................................................. 50 ■ Input Digital Volume (Manual Mode) ............................................................................................... 56 ■ Sidetone Digital Volume ................................................................................................................... 57 ■ DAC Input Selector .......................................................................................................................... 57 ■ Output Digital Volume ...................................................................................................................... 57 ■ Soft Mute .......................................................................................................................................... 58 ■ BEEP Input ....................................................................................................................................... 59 ■ Speaker Output (SPP/SPN pins, LOSEL bit = “0”) .......................................................................... 60 ■ Thermal Shutdown Function ............................................................................................................ 61 ■ Monaural Line Output (AOUT pin, LOSEL bit = “1”) ........................................................................ 62 ■ Regulator Block ................................................................................................................................ 64 ■ Serial Control Interface .................................................................................................................... 65 ■ Register Map .................................................................................................................................... 68 ■ Register Definitions .......................................................................................................................... 70 015010680-E-00 2015/09 -3- [AK4637] 10. Recommended External Circuits....................................................................................................... 82 11. Control Sequence .............................................................................................................................. 84 ■ Clock Set Up .................................................................................................................................... 84 ■ Microphone Input Recording ............................................................................................................ 87 ■ Digital Microphone Input .................................................................................................................. 88 ■ Speaker Amplifier Output ................................................................................................................. 89 ■ Beep Signal Output from Speaker Amplifier .................................................................................... 90 ■ Lineout Output.................................................................................................................................. 91 ■ Stop of Clock .................................................................................................................................... 92 ■ Power Down ..................................................................................................................................... 93 12. Package ............................................................................................................................................. 94 ■ Outline Dimensions .......................................................................................................................... 94 ■ Material & Lead finish ...................................................................................................................... 94 ■ Marking............................................................................................................................................. 94 13. Ordering Guide .................................................................................................................................. 95 14. Revision History................................................................................................................................. 95 IMPORTANT NOTICE.............................................................................................................................. 96 015010680-E-00 2015/09 -4- [AK4637] 4. Block Diagram VCOM Analog Block PMMP MPWR MIC Power Supply VSS1 AVDD REGFIL DVDD LDO 2.3V VSS2 PDN Digital Core MIC-Power AVDD TVDD SPK-Amp Control Register SDA SCL PMADC Internal MIC ADC AIN/IN+/DMDAT HPF PMPFIL MIC-Amp +30~0dB HPF2 PMBP BEEP/IN-/DMCLK LPF BICK 4-band EQ BEEP Audio I/F ALC 1 Band EQ FCK SDTO PFVOL PMSL SDTI PMDAC SPP/AOUT Mono Speaker SPN DAC DVOL SMUTE PMPLL PLL MCKI Figure 1. Block Diagram 015010680-E-00 2015/09 -5- [AK4637] 5. Pin Configurations and Functions VSS1 16 VCOM 17 REGFIL 18 MPWR BEEP/IN-/DMCLK 11 DVDD 12 VSS2 13 SPN/NC 14 SPP/AOUT 15 AVDD ■ Pin Layout 10 TVDD 9 MCKI 8 BICK 19 7 FCK 20 6 SDTO AK4637 2 3 4 5 PDN SCL SDA SDTI AIN/IN+/DMDAT 1 Top View Figure 2. Pin Layout 015010680-E-00 2015/09 -6- [AK4637] ■ Comparison Table of the AK4951EN 1. Function Function Stereo/Mono AVDD SVDD DVDD TVDD Differential Input MIC Sensitivity Correction Automatic Wind Noise Reduction Stereo Separation Emphasis Circuit Headphone Amplifier Audio I/F Format Package AK4951EN Stereo 2.8V ~ 3.5V 1.8V  5.5V 1.6V ~ 1.98V 1.6V or (DVDD-0.2)V  3.5V No Yes AK4637EN Mono 2.8V ~ 5.5V ← 1.6V or (DVDD-0.2)V  3.6V Yes No Yes No Yes No Yes DSP Mode is Not Available 32-pin QFN (4 x 4mm, 0.4mm pitch) No DSP Mode is Available 20-pin QFN (3 x 3mm, 0.4mm pitch) 2. Register Map Addr Register Name 00H 01H 02H 03H 04H 05H 07H 08H 0EH 0FH 10H Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Signal Select 3 Mode Control 1 Mode Control 3 Digital MIC ALC Volume BEEP Control Digital Volume Control EQ Common Gain Select EQ2 Gain Setting EQ3 Gain Setting EQ4 Gain Setting EQ5 Gain Setting Digital Filter Select 1 Digital Filter Select 2 Digital Filter Mode HPF2 Co-efficient 0 HPF2 Co-efficient 1 HPF2 Co-efficient 2 HPF2 Co-efficient 3 LPF Co-efficient 0 LPF Co-efficient 1 LPF Co-efficient 2 LPF Co-efficient 3 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H D7 D6 D5 D4 D3 D2 D1 D0 PMPFIL PMOSC SLPSN SPKG1 LVCM1 PLL3 TSDSEL READ VOL7 HPZ DVOL7 PMVCM 0 MGAIN3 SPKG0 LVCM0 PLL2 THDET 0 VOL6 BPVCM DVOL6 PMBP PMHPR DACS 0 DACL PLL1 SMUTE PMDMR VOL5 BEEPS DVOL5 0 PMHPL MPSEL MICL 0 PLL0 DVOLC PMDM VOL4 BEEPH DVOL4 LOSEL M/S PMMP INL1 PTS1 BCKO MSBS DCLKE VOL3 BPLVL3 DVOL3 PMDAC PMPLL MGAIN2 INL0 PTS0 CKOFF BCKP 0 VOL2 BPLVL2 DVOL2 PMADR PMSL MGAIN1 INR1 MONO1 BCKO1 DIF1 DCLKP VOL1 BPLVL1 DVOL1 PMADC LOSEL MGAIN0 MDIF MONO0 BCKO0 DIF0 DMIC VOL0 BPLVL0 DVOL0 0 0 0 EQC5 EQC4 EQC3 EQC2 0 EQ2G5 EQ3G5 EQ4G5 EQ5G5 0 GN1 0 F1A7 0 F1B7 0 F2A7 0 F2B7 0 EQ2G4 EQ3G4 EQ4G4 EQ5G4 0 GN0 0 F1A6 0 F1B6 0 F2A6 0 F2B6 0 EQ2G3 EQ3G3 EQ4G3 EQ5G3 0 EQ0 PFVOL1 F1A5 F1A13 F1B5 F1B13 F2A5 F2A13 F2B5 F2B13 EQ2G2 EQ3G2 EQ4G2 EQ5G2 0 FIL3 PFVOL0 F1A4 F1A12 F1B4 F1B12 F2A4 F2A12 F2B4 F2B12 EQ2G1 EQ3G1 EQ4G1 EQ5G1 0 0 PFDAC1 F1A3 F1A11 F1B3 F1B11 F2A3 F2A11 F2B3 F2B11 EQ2G0 EQ3G0 EQ4G0 EQ5G0 HPFC1 0 PFDAC0 F1A2 F1A10 F1B2 F1B10 F2A2 F2A10 F2B2 F2B10 EQ2T1 EQ3T1 EQ4T1 EQ5T1 HPFC0 LPF ADCPF F1A1 F1A9 F1B1 F1B9 F2A1 F2A9 F2B1 F2B9 EQ2T0 EQ3T0 EQ4T0 EQ5T0 HPFAD HPF PFSDO F1A0 F1A8 F1B0 F1B8 F2A0 F2A8 F2B0 F2B8 015010680-E-00 2015/09 -7- [AK4637] Addr Register Name 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Digital Filter Select 3 E1 Co-efficient 0 E1 Co-efficient 1 E1 Co-efficient 2 E1 Co-efficient 3 E1 Co-efficient 4 E1 Co-efficient 5 E2 Co-efficient 0 E2 Co-efficient 1 E2 Co-efficient 2 E2 Co-efficient 3 E2 Co-efficient 4 E2 Co-efficient 5 E3 Co-efficient 0 E3 Co-efficient 1 E3 Co-efficient 2 E3 Co-efficient 3 E3 Co-efficient 4 E3 Co-efficient 5 E4 Co-efficient 0 E4 Co-efficient 1 E4 Co-efficient 2 E4 Co-efficient 3 E4 Co-efficient 4 E4 Co-efficient 5 E5 Co-efficient 0 E5 Co-efficient 1 E5 Co-efficient 2 E5 Co-efficient 3 E5 Co-efficient 4 E5 Co-efficient 5 D7 D6 D5 D4 D3 D2 D1 D0 0 E1A7 E1A15 E1B7 E1B15 E1C7 E1C15 E2A7 E2A15 E2B7 E2B15 E2C7 E2C15 E3A7 E3A15 E3B7 E3B15 E3C7 E3C15 E4A7 E4A15 E4B7 E4B15 E4C7 E4C15 E5A7 E5A15 E5B7 E5B15 E5C7 E5C15 0 E1A6 E1A14 E1B6 E1B14 E1C6 E1C14 E2A6 E2A14 E2B6 E2B14 E2C6 E2C14 E3A6 E3A14 E3B6 E3B14 E3C6 E3C14 E4A6 E4A14 E4B6 E4B14 E4C6 E4C14 E5A6 E5A14 E5B6 E5B14 E5C6 E5C14 0 E1A5 E1A13 E1B5 E1B13 E1C5 E1C13 E2A5 E2A13 E2B5 E2B13 E2C5 E2C13 E3A5 E3A13 E3B5 E3B13 E3C5 E3C13 E4A5 E4A13 E4B5 E4B13 E4C5 E4C13 E5A5 E5A13 E5B5 E5B13 E5C5 E5C13 EQ5 E1A4 E1A12 E1B4 E1B12 E1C4 E1C12 E2A4 E2A12 E2B4 E2B12 E2C4 E2C12 E3A4 E3A12 E3B4 E3B12 E3C4 E3C12 E4A4 E4A12 E4B4 E4B12 E4C4 E4C12 E5A4 E5A12 E5B4 E5B12 E5C4 E5C12 EQ4 E1A3 E1A11 E1B3 E1B11 E1C3 E1C11 E2A3 E2A11 E2B3 E2B11 E2C3 E2C11 E3A3 E3A11 E3B3 E3B11 E3C3 E3C11 E4A3 E4A11 E4B3 E4B11 E4C3 E4C11 E5A3 E5A11 E5B3 E5B11 E5C3 E5C11 EQ3 E1A2 E1A10 E1B2 E1B10 E1C2 E1C10 E2A2 E2A10 E2B2 E2B10 E2C2 E2C10 E3A2 E3A10 E3B2 E3B10 E3C2 E3C10 E4A2 E4A10 E4B2 E4B10 E4C2 E4C10 E5A2 E5A10 E5B2 E5B10 E5C2 E5C10 EQ2 E1A1 E1A9 E1B1 E1B9 E1C1 E1C9 E2A1 E2A9 E2B1 E2B9 E2C1 E2C9 E3A1 E3A9 E3B1 E3B9 E3C1 E3C9 E4A1 E4A9 E4B1 E4B9 E4C1 E4C9 E5A1 E5A9 E5B1 E5B9 E5C1 E5C9 EQ1 E1A0 E1A8 E1B0 E1B8 E1C0 E1C8 E2A0 E2A8 E2B0 E2B8 E2C0 E2C8 E3A0 E3A8 E3B0 E3B8 E3C0 E3C8 E4A0 E4A8 E4B0 E4B8 E4C0 E4C8 E5A0 E5A8 E5B0 E5B8 E5C0 E5C8 These bits are added to the AK4637. These bits are removed from the AK4637. These bits are changed from the AK4637. 015010680-E-00 2015/09 -8- [AK4637] ■ PIN/FUNCTION No. Pin Name I/O AIN I Function Analog Input Pin (MDIF bit = “0”: Single-ended Input, DMIC bit = “0”: default) Positive Analog Input Pin IN+ I (MDIF bit = “1”: Full-differential Input, DMIC bit = “0”) DMDAT I Digital Microphone Data Input Pin (DMIC bit = “1”) Reset & Power-down Pin 2 PDN I “L”: Reset & Power-down, “H”: Normal Operation 3 SCL I Control Data Clock Pin 4 SDA I/O Control Data Input/Output Pin 5 SDTI I Audio Serial Data Input Pin 6 SDTO O Audio Serial Data Output Pin 7 FCK I/O Frame Clock Pin 8 BICK I/O Audio Serial Data Clock Pin 9 MCKI I External Master Clock Input Pin 10 TVDD Digital I/O Power Supply Pin, 1.6 or (DVDD-0.2) ~ 3.6V 11 DVDD Digital Power Supply Pin, 1.6 ~ 1.98V 12 VSS2 Ground 2 Pin SPN O Speaker-Amp Negative Output Pin (LOSEL bit = “0”: default) 13 No Connect Pin (LOSEL bit = “1”) NC O This pin should be open. SPP O Speaker-Amp Positive Output Pin (LOSEL bit = “0”: default) 14 AOUT O Line Output Pin (LOSEL bit = “1”) 15 AVDD Analog Power Supply Pin, 2.8 ~ 5.5V 16 VSS1 Ground 1 Pin Common Voltage Output Pin Bias voltage of ADC inputs and DAC outputs. 17 VCOM O This pin must be connected to VSS1 with 2.2μF±10% or 4.7μF±10% capacitor in series. LDO Voltage Output pin for Analog Block (typ 2.3V) 18 REGFIL O This pin must be connected to VSS1 with 2.2μF±10% capacitor in series. 19 MPWR O MIC Power Supply Pin Beep Signal Input Pin BEEP I (MDIF bit=“0”: Single-ended Input, DMIC bit=“0”: default) Negative Analog Input Pin 20 INI (MDIF bit = “1”: Full-differential Input, DMIC bit=“0”) DMCLK O Digital Microphone Clock pin (DMIC bit = “1”) Note 1. All input pins except analog input pins (AIN/IN+, IN-/BEEP) must not be allowed to float. 1 ■ Handling of Unused Pin Unused I/O pins must be processed appropriately as below. Classification Pin Name AIN/IN+/DMDAT, BEEP/IN-/DMCLK, MPWR, Analog SPN, SPP/AOUT MCKI, SDTI Digital SDTO 015010680-E-00 Setting Open Connect to VSS2 Open 2015/09 -9- [AK4637] 6. Absolute Maximum Ratings (VSS1=VSS2=0V; Note 2) Parameter Power Supplies Symbol AVDD DVDD TVDD SVDD IIN VINA VIND Ta Tstg Pd Min. 0.3 0.3 0.3 0.3 0.3 0.3 40 65 - Max. 6.0 2.5 6.0 6.0 10 AVDD+0.3 TVDD+0.3 85 150 800 Unit V V V V mA V V C C mW Analog Digital Digital I/O Speaker-Amp Input Current, Any Pin Except Supplies Analog Input Voltage (Note 3) Digital Input Voltage (Note 4) Operating Temperature (powered applied) Storage Temperature Maximum Power Dissipation (Note 5) Note 2. All voltages are with respect to ground. VSS1 and VSS2 must be connected to the same analog ground plane. Note 3. AIN/IN+ and BEEP/IN- pins Note 4. PDN, SCL, SDA, SDTI, FCK, BICK and MCKI pins Pull-up resistors at the SDA and SCL pins must be connected to a voltage in the range from TVDD or more to 6V or less. Note 5. This power is the AK4637 internal dissipation that does not include power dissipation of externally connected speakers. The maximum junction temperature is 125C and θja (Junction to Ambient) is 50C/W at JESD51-9 (2p2s) for the AK4637. When Pd = 800mW and the θja is 50C/W for the AK4637, the junction temperature does not exceed 125C. In this case, the AK4637 will not be damaged by its internal power dissipation. Therefore, the AK4637 should be used in the condition of θja ≤ 50C/W. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operating Conditions (VSS1=VSS2=0V; Note 2) Parameter Power Supplies Analog (Note 6) Digital Digital I/O (Note 7) Symbol AVDD DVDD TVDD Min. 2.8 1.6 1.6 or (DVDD-0.2) Typ. 3.3 1.8 Max. 3.5 1.98 Unit V V 1.8 3.5 V Note 2. All voltages are with respect to ground. Note 6. The power-up sequence between AVDD, DVDD, TVDD and SVDD is not critical. The PDN pin must be “L” upon power up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error. Note 7. The minimum value is higher voltage between DVDD-0.2 and 1.6V. * When TVDD is powered ON and the PDN pin is “L”, AVDD and DVDD can be powered ON/OFF. The PDN pin must be set to “H” after all power supplies are ON, when the AK4637EN is powered-up from power-down state. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. 015010680-E-00 2015/09 - 10 - [AK4637] 8. Electrical Characteristics ■ Analog Characteristics (Ta=25C; AVDD=3.3V, TVDD=DVDD=1.8V; VSS1=VSS2=0V; fs=48kHz, BICK=64fs; Signal Frequency =1kHz; 24bit Data; Measurement Bandwidth=20Hz  20kHz; unless otherwise specified) Parameter Min. Typ. Max. Unit MIC Amplifier: AIN pin; MDIF bit = “0” (Single-ended input) Input Resistance (Note 8) 20 30 40 k Gain Gain Setting 0 +30 dB Step Width 3 dB MIC Power Supply: MPWR pin MICL bit = “0” 2.2 2.4 2.6 V Output Voltage MICL bit = “1” 1.8 2.0 2.2 Output Noise Level (A-weighted) -108 dBV Load Resistance 2.0 k Load Capacitance 30 pF PSRR (f = 1kHz) (Note 9) 100 dB ADC Analog Input Characteristics: AIN pins → ADC (Programmable Filter = OFF) → SDTO Resolution 24 Bits (Note 11) 0.261 Vpp Input Voltage (Note 10) (Note 12) 1.86 2.07 2.28 Vpp (Note 11) 73 83 dBFS S/(N+D) (-1dBFS) (Note 12) 84 dBFS D-Range (Note 11) 78 88 dB (Note 12) 95 dB (60dBFS, A-weighted) (Note 11) 78 88 dB S/N (A-weighted) (Note 12) 95 dB PSRR (f = 1kHz) (Note 9) 90 dB Note 8. Full Differential Input: IN+=20kΩ(typ), IN-=57kΩ(typ)@MGAIN3-0 bits = “0000” (0dB), IN+=16kΩ(typ), IN-=244kΩ(typ)@MGAIN3-0 bits = “0110” (+18dB) Note 9. PSRR applied to AVDD with 500mVpp sine wave. Note 10. Single-ended Input: Vin = 0.9 x 2.3Vpp (typ) @MGAIN3-0 bits = “0000” (0dB) Full Differential Input: Vin = (IN+) – (IN–) = 0.9 x 2.3Vpp (typ) IN+ = 0.45 x 2.3Vpp (typ), IN– = 0.45 x 2.3Vpp (typ) Note 11. MGAIN3-0 bits = “0110” (+18dB) Full Differential Input: S/(N+D) = 81dB、DR = S/N = 86dB Note 12. MGAIN3-0 bits = “0000” (0dB) Full Differential Input: S/(N+D) = 83dB、DR = S/N = 93dB 015010680-E-00 2015/09 - 11 - [AK4637] Parameter Min. Typ. Max. Unit DAC Characteristics: Resolution 24 Bit Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=DVOL= 0dB, RL=8, BTL Output Voltage 3.18 Vpp SPKG1-0 bits = “00”, 0.5dBFS (Po=150mW) 3.20 4.00 4.80 Vpp SPKG1-0 bits = “01”, 0.5dBFS (Po=250mW) 1.79 Vrms SPKG1-0 bits = “10”, 0.5dBFS (Po=400mW) SPKG1-0 bits = “11”, 0.5dBFS (Po=1000mW) 2.83 Vrms (AVDD=5V) S/(N+D) 80 dB SPKG1-0 bits = “00”, 0.5dBFS (Po=150mW) 40 75 dB SPKG1-0 bits = “01”, 0.5dBFS (Po=250mW) 20 dB SPKG1-0 bits = “10”, 0.5dBFS (Po=400mW) SPKG1-0 bits = “11”, 0.5dBFS (Po=1000mW) 20 dB (AVDD=5V) S/N (A-weighted) SPKG1-0 bits = “01” 80 97 dB Output Offset Voltage SPKG1-0 bits = “01” -30 0 +30 mV Load Resistance 8  Load Capacitance 100 pF PSRR (f = 1kHz) (Note 13) 60 dB Line Output Characteristics: DAC → AOUT pin, ALC=OFF, IVOL=DVOL= 0dB, RL=10k, LVCM1-0 bits = “01” LVCM0 bit = “0” 2.26 Vpp AVDD=2.8V (0dBFS) LVCM0 bit = “1” 1.0 Vrms Output Voltage LVCM0 bit = “0” 1.44 1.6 1.76 Vpp (-3dBFS) AVDD=2.8V LVCM0 bit = “1” 1.82 2.0 2.22 Vpp LVCM0 bit = “0” 80 dB AVDD=2.8V (0dBFS) S/(N+D) LVCM0 bit = “1” 40 dB (-3dBFS) 75 85 dB S/N (A-weighted) 82 94 dB Load Resistance 10 k Load Capacitance 30 pF Mono Input: BEEP pin (PMBP bit =“1”, BPVCM bit = “0”, BPLVL3-0 bits = “0000”) Input Resistance 46 66 86 k Maximum Input Voltage (Note 14) 1.54 Vpp Gain BEEP pin → SPKG1-0 bits = “00” +4.4 +6.4 +8.4 dB SPP/SPN pins SPKG1-0 bits = “01” +8.4 dB (Note 15) SPKG1-0 bits = “10” +11.1 dB SPKG1-0 bits = “11” +14.9 dB BEEP pin → AOUT pin LVCM1-0 bits = “00” -1 0 +1 dB LVCM1-0 bits = “01” +2 dB LVCM1-0 bits = “10” +2 dB LVCM1-0 bits = “11” +4 dB Note 13. PSRR applied to AVDD with 500mVpp sine wave. Note 14. The maximum value is the smaller one of AVDD Vpp or 3.3Vpp when BPVCM bit = “1”. However, a click noise may occur when the amplitude after BEEP-Amp is 0.5Vpp or more. (Set by BPLVL3-0 bits) Note 15. This gain is an ideal gain when no load resistance. 015010680-E-00 2015/09 - 12 - [AK4637] Parameter Min. Typ. Max. Unit Power Supplies: Power Up (PDN pin = “H”, All Circuit Power Up) AVDD+DVDD+TVDD (Note 16) 6.6 10.2 mA AVDD+DVDD+TVDD (Note 17) 5.6 mA Power Down (PDN pin = “L”) AVDD+DVDD+TVDD (Note 18) 0 10 A Note 16. When PLL Master Mode (MCKI=12MHz), PMADC=PMDAC=PMPFIL=PMSL=PMVCM=PMPLL =PMBP=PMMP=M/S=SLPSN bits = “1” and LOSEL bit = “0”. In this case, the MPWR pin outputs 0mA. AVDD= 4.9mA (typ), DVDD= 1.5mA (typ), TVDD= 0.2mA (typ). Note 17. When EXT Slave Mode (PMPLL=M/S bits =“0”), PMADC =PMDAC=PMSL=PMVCM=PMBP =PMMP=SLPSN bits = “1” and PMPFIL = LOSEL bits = “0”. In this case, the MPWR pin outputs 0mA. AVDD= 4.6mA (typ), DVDD= 1.0mA (typ), TVDD= 0.02mA (typ). Note 18. All digital input pins are fixed to TVDD or VSS2. ■ Power Consumption on Each Operation Mode PMPFIL PMSL LOSEL PMDAC PMADC PMVCM Conditions: Ta=25C; AVDD= 3.3V, TVDD=DVDD=1.8V; VSS1=VSS2=0V; fs=48kHz, Programmable Filter=OFF, External Slave Mode, BICK=64fs; AIN input = No signal; SDTI input = No data; Speaker output = No load. Power Management Bit Total AVDD DVDD TVDD Mode Power [mA] [mA] [mA] [mW] All Power-down 0 0 0 0 0 0 0 0 AIN → ADC 1 1 0 0 0 0 1.6 0.65 DAC → SPK 1 0 1 0 1 0 3.2 0.55 DAC → Line out 1 0 1 1 1 0 1.6 0.55 AIN → ADC & DAC → SPK 1 1 1 0 1 0 4.1 1.0 AIN → ADC & DAC → Line out 1 1 1 1 1 0 2.5 1.0 Table 1. Power Consumption on Each Operation Mode (typ) 015010680-E-00 0 0.02 0.02 0.02 0.02 0.02 0 6.5 11.6 6.3 15.4 10.1 2015/09 - 13 - [AK4637] ■ Filter Characteristics (Ta=25C; fs=48kHz; AVDD=2.85.5V, DVDD=1.6~1.98V, TVDD=1.6 or (DVDD-0.2)3.6V) Parameter Symbol Min. Typ. Max. Unit ADC Digital Filter (Decimation LPF): Passband (Note 19) PB 0 18.8 kHz 0.16dB 21.1 kHz 0.66dB 21.7 kHz 1.1dB 24.1 kHz 6.9dB Stopband (Note 19) SB 28.4 kHz Passband Ripple PR dB 0.16 Stopband Attenuation SA 73 dB Group Delay (Note 20) GD 17 1/fs Group Delay Distortion 0 GD s ADC Digital Filter (HPF): HPFC1-0 bits = “00” Frequency Response FR 3.7 Hz 3.0dB (Note 19) 10.9 Hz 0.5dB 23.9 Hz 0.1dB DAC Digital Filter (LPF): Passband PB 0 21.9 kHz 0.006dB ~ +0.076dB (Note 19) 24 kHz 6.0dB Stopband (Note 19) SB 26.2 kHz Passband Ripple PR -0.006 +0.076 dB Stopband Attenuation SA 70 dB Group Delay (Note 20) GD 27 1/fs DAC Digital Filter (LPF) + SCF: FR dB Frequency Response: 0  20.0kHz 1.0 Note 19. The passband and stopband frequencies scale with fs (sampling frequency). Note 20. A calculating delay time which is induced by digital filtering. This time is from the input of an analog signal to the setting of 24-bit data of both channels to the ADC output register. For the DAC, this time is from setting the 24-bit data of a channel from the input register to the output of analog signal. For the signal through the programmable filters (1st order HPF + 1st order LPF + 4-band Equalizer + ALC + 1-band Equalizer), the group delay is increased by 4/fs from the value above in both recording and playback modes if there is no phase change by the IIR filter. 015010680-E-00 2015/09 - 14 - [AK4637] ■ DC Characteristics (Ta=25C; fs=48kHz; AVDD=2.85.5V, DVDD=1.6~1.98V, TVDD=1.6 or (DVDD-0.2)3.6V) Parameter Symbol Min. Typ. Max. Unit Audio Interface & Serial µP Interface (SDA, CSL, PDN, SDTI, BICK, FCK, MCKI pins Input) High-Level Input Voltage (TVDD ≥ 2.2V) VIH 70%TVDD V (TVDD < 2.2V) 80%TVDD V Low-Level Input Voltage (TVDD ≥ 2.2V) VIL 30%TVDD V (TVDD < 2.2V) 20%TVDD V Input Leakage Current Iin1 10 A Audio Interface & Serial µP Interface (SDA, BICK, FCK, SDTO pins Output) High-Level Output Voltage (Iout = 80A) VOH TVDD0.2 V Low-Level Output Voltage (Except SDA pin: Iout = 80A) VOL1 0.2 V (SDA pin, 2.0V  TVDD  3.6V: Iout = 3mA) VOL2 0.4 V (SDA pin, 1.6V  TVDD < 2.0V: Iout = 3mA) VOL2 20%TVDD V Digital MIC Interface (DMDAT pin Input; DMIC bit = “1”, AVDD=2.8~3.6V) High-Level Input Voltage VIH2 65%AVDD V Low-Level Input Voltage VIL2 35%AVDD V Input Leakage Current Iin2 10 A Digital MIC Interface (DMCLK pin Output; DMIC bit = “1” , AVDD=2.8~3.6V) High-Level Output Voltage (Iout=80A) VOH3 AVDD-0.4 V Low-Level Output Voltage (Iout= 80A) VOL3 0.4 V 015010680-E-00 2015/09 - 15 - [AK4637] ■ Switching Characteristics (Ta=25C; fs=48kHz; CL=20pF; AVDD=2.85.5V, DVDD=1.6~1.98V, TVDD=1.6 or (DVDD-0.2)3.6V) Parameter Symbol Min. Typ. Max. Unit PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency PLL3-0 bits = “0100” fCLK 11.2896 MHz PLL3-0 bits = “0101” fCLK 12.288 MHz PLL3-0 bits = “0110” fCLK 12 MHz PLL3-0 bits = “0111” fCLK 24 MHz PLL3-0 bits = “1100” fCLK 13.5 MHz PLL3-0 bits = “1101” fCLK 27 MHz Pulse Width Low tCLKL 0.4/fCLK s Pulse Width High tCLKH 0.4/fCLK s FCK Output Timing Frequency fs Table 8 Hz DSP Mode: Pulse Width High tFCKH 1/fBCK ns Except DSP Mode: Duty Cycle Duty 50 % BICK Output Timing Frequency BCKO1-0 bit = “00” fBCK 16fs Hz BCKO1-0 bit = “01” fBCK 32fs Hz BCKO1-0 bit = “10” fBCK 64fs Hz Duty Cycle dBCK 50 % PLL Slave Mode (PLL Reference Clock = BICK pin) FCK Input Timing Frequency PLL3-0 bits = “0001” fs fBCK/16 Hz PLL3-0 bits = “0010” fs fBCK/32 Hz PLL3-0 bits = “0011” fs fBCK/64 Hz DSP Mode: Pulse Width High tFCKH ns 1/fBCK60 1/fs1/fBCK Except DSP Mode: Duty Cycle Duty 45 55 % BICK Input Timing Frequency PLL3-0 bits = “0001” fBCK 0.128 0.768 MHz PLL3-0 bits = “0010” fBCK 0.256 1.536 MHz PLL3-0 bits = “0011” fBCK 0.512 3.072 MHz Pulse Width Low tBCKL 0.4/fBCK s Pulse Width High tBCKH 0.4/fBCK s 015010680-E-00 2015/09 - 16 - [AK4637] Parameter External Slave Mode MCKI Input Timing Frequency CM1-0 bits = “00” CM1-0 bits = “01” CM1-0 bits = “10” CM1-0 bits = “11” Pulse Width Low Pulse Width High FCK Input Timing Frequency CM1-0 bits = “00” CM1-0 bits = “01” CM1-0 bits = “10” CM1-0 bits = “11” DSP Mode: Pulse Width High Except DSP Mode: Duty Cycle BICK Input Timing Frequency Pulse Width Low Pulse Width High External Master Mode MCKI Input Timing Frequency 256fs 384fs 512fs 1024fs Pulse Width Low Pulse Width High FCK Output Timing Frequency CM1-0 bits = “00” CM1-0 bits = “01” CM1-0 bits = “10” CM1-0 bits = “11” DSP Mode: Pulse Width High Except DSP Mode: Duty Cycle BICK Output Timing Frequency BCKO1-0 bit = “00” BCKO1-0 bit = “01” BCKO1-0 bit = “10” Duty Cycle Symbol Min. Typ. Max. Unit fCLK fCLK fCLK fCLK tCLKL tCLKH - - 0.4/fCLK 0.4/fCLK 256fs 384fs 512fs 1024fs - - Hz Hz Hz Hz s s fs fs fs fs tFCKH Duty 8 8 8 8 1/fBCK60 45 - 48 48 48 24 1/fs1/fBCK 55 kHz kHz kHz kHz ns % fBCK tBCKL tBCKH 16fs 130 130 - 64fs - Hz ns ns fCLK fCLK fCLK fCLK tCLKL tCLKH 2.048 3.072 4.096 8.192 0.4/fCLK 0.4/fCLK - 12.288 18.432 24.576 24.576 - MHz MHz MHz MHz s s fs fs fs fs tFCKH Duty - fCLK/256 fCLK/384 fCLK/512 fCLK/1024 1/fBCK 50 - Hz Hz Hz Hz ns % fBCK fBCK fBCK dBCK - 16fs 32fs 64fs 50 - Hz Hz Hz % 015010680-E-00 2015/09 - 17 - [AK4637] Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (DSP Mode) Master Mode tDBF FCK “” to BICK “” (Note 21) 0.5x1/fBCK40 0.5x1/fBCK 0.5x1/fBCK+40 ns tDBF FCK “” to BICK “” (Note 22) 0.5x1/fBCK40 0.5x1/fBCK 0.5x1/fBCK+40 ns tBSD 70 ns BICK “” to SDTO (BCKP bit =“0”) 70 tBSD 70 ns BICK “” to SDTO (BCKP bit =“1”) 70 SDTI Hold Time tSDH 50 ns SDTI Setup Time tSDS 50 ns Slave Mode tFCKB 0.4x1/fBCK ns FCK “” to BICK “” (Note 21) tFCKB 0.4x1/fBCK ns FCK “” to BICK “” (Note 22) tBFCK 0.4x1/fBCK ns BICK “” to FCK “” (Note 21) tBFCK 0.4x1/fBCK ns BICK “” to FCK “” (Note 22) tBSD 80 ns BICK “” to SDTO (BCKP bit =“0”) tBSD 80 ns BICK “” to SDTO (BCKP bit =“1”) SDTI Hold Time tSDH 50 ns SDTI Setup Time tSDS 50 ns Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Right/Left justified &I2S) Master Mode tBFCK 40 ns BICK “” to FCK Edge (Note 23) 40 FCK Edge to SDTO (MSB) tFCKD 70 ns 70 (Except I2S mode) tBSD 70 ns BICK “” to SDTO 70 SDTI Hold Time tSDH 50 ns SDTI Setup Time tSDS 50 ns Slave Mode tFCKB 50 ns FCK Edge to BICK “” (Note 23) tBFCK 50 ns BICK “” to FCK Edge (Note 23) FCK Edge to SDTO (MSB) tFCKD 80 ns (Except I2S mode) tBSD 80 ns BICK “” to SDTO SDTI Hold Time tSDH 50 ns SDTI Setup Time tSDS 50 ns Digital Audio Interface Timing; CL=100pF DMCLK Output Timing Period tSCK 1/(64fs) s Rising Time tSRise 10 ns Falling Time tSFall 10 ns Duty Cycle dSCK 40 50 60 % Audio Interface Timing DMDAT Setup Time tDSDS 50 ns DMDAT Hold Time tDSDH 0 ns Note 21. MSBS, BCKP bits = “00” or “11”. Note 22. MSBS, BCKP bits = “01” or “10”. Note 23. BICK rising edge must not occur at the same time as FCK edge. 015010680-E-00 2015/09 - 18 - [AK4637] Parameter Symbol Min. Typ. Max. Unit 2 Control Interface Timing (I C Bus) (Note 24) SCL Clock Frequency fSCL 400 kHz Bus Free Time Between Transmissions tBUF 1.3 s Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 s Clock Low Time tLOW 1.3 s Clock High Time tHIGH 0.6 s Setup Time for Repeated Start Condition tSU:STA 0.6 s SDA Hold Time from SCL Falling (Note 25) tHD:DAT 0 s SDA Setup Time from SCL Rising tSU:DAT 0.1 s Rise Time of Both SDA and SCL Lines tR 0.3 s Fall Time of Both SDA and SCL Lines tF 0.3 s Setup Time for Stop Condition tSU:STO 0.6 s Capacitive Load on Bus Cb 400 pF Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 50 ns Power-down & Reset Timing PDN Accept Pulse Width (Note 26) tAPD 200 ns PDN Reject Pulse Width (Note 26) tRPD 50 ns (Note 27) PMADC “” to SDTO valid ADRST1-0 bits =“00” tPDV 1059 1/fs ADRST1-0 bits =“01” tPDV 267 1/fs ADRST1-0 bits =“10” tPDV 531 1/fs ADRST1-0 bits =“11” tPDV 135 1/fs VCOM Voltage Rising Time (Note 28) tRVCM 0.6 2.0 ms Note 24. I2C Bus is a trademark of NXP B.V. Note 25. Data must be held for sufficient time to bridge the 300ns transition time of SCL. Note 26. The AK4637 can be reset by the PDN pin = “L”. The PDN pin must be held “L” for more than 200ns for a certain reset. The AK4637 is not reset by the “L” pulse less than 50ns. Note 27. This is the count of FCK “↑” from the PMADC bit = “1”. Note 28. All analog blocks including PLL block are powered up after the VCOM voltage (VCOM pin) rises up. An external capacitor of the VCOM pin is 2.2μF (AVDD ≤ 3.6V) or 4.7μF (AVDD > 3.6V) and the REGFIL pin is 2.2F. The capacitance variation should be ±10%. 015010680-E-00 2015/09 - 19 - [AK4637] ■ Timing Diagram 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs 50%TVDD FCK tFCKH tFCKL 1/fBCK Duty = tFCKH x fs x 100 tFCKL x fs x 100 BICK 50%TVDD tBCKH tBCKL Duty = tBCKH x fBCK x 100 tBCKL x fBCK x 100 Figure 3. Clock Timing (PLL/EXT Master mode) tFCKH FCK 50%TVDD tDBF BICK (BCKP = "0") 50%TVDD BICK (BCKP = "1") 50%TVDD tBSD SDTO MSB tSDS 50%TVDD tSDH VIH SDTI VIL Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit= “0”) 015010680-E-00 2015/09 - 20 - [AK4637] tFCKH FCK 50%TVDD tDBF BICK (BCKP = "1") 50%TVDD BICK (BCKP = "0") 50%TVDD tBSD SDTO 50%TVDD MSB tSDS tSDH VIH SDTI VIL Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit= “1”) 50%TVDD FCK tBFCK tBCKL BICK 50%TVDD tFCKD tBSD SDTO 50%TVDD tSDS tSDH VIH SDTI VIL Figure 6. Audio Interface Timing (PLL/EXT Master mode; Except DSP mode) 015010680-E-00 2015/09 - 21 - [AK4637] 1/fs VIH FCK VIL tFCKH tBFCK 1/fBCK VIH BICK (BCKP = "0") VIL tBCKH tBCKL VIH BICK (BCKP = "1") VIL Figure 7. Clock Timing (PLL/EXT Slave mode; DSP mode, MSBS bit= “0”) 1/fs VIH FCK VIL tFCKH tBFCK 1/fBCK VIH BICK (BCKP = "1") VIL tBCKH tBCKL VIH BICK (BCKP = "0") VIL Figure 8. Clock Timing (PLL/EXT Slave mode; DSP mode, MSBS bit= “1”) VIL MCKI 1/fs VIH FCK VIL tFCKH tFCKL Duty = tFCKH x fs x 100 tFCKL x fs x 100 1/fBCK VIH BICK VIL tBCKH tBCKL Figure 9. Clock Timing (PLL Slave mode; Except DSP mode) 015010680-E-00 2015/09 - 22 - [AK4637] 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH FCK VIL tFCKH tFCKL Duty = tFCKH x fs x 100 tFCKL x fs x 100 1/fBCK VIH BICK VIL tBCKH tBCKL Figure 10. Clock Timing (EXT Slave mode) tFCKH VIH FCK VIL tFCKB VIH BICK (BCKP = "0") VIL VIH BICK (BCKP = "1") VIL tBSD SDTO MSB tSDS 50%TVDD tSDH VIH SDTI MSB VIL Figure 11. Audio Interface Timing (PLL/EXT Slave mode, DSP mode; MSBS bit= “0”) 015010680-E-00 2015/09 - 23 - [AK4637] tFCKH VIH FCK VIL tFCKB VIH BICK (BCKP = "1") VIL VIH BICK (BCKP = "0") VIL tBSD SDTO 50%TVDD MSB tSDS tSDH VIH SDTI MSB VIL Figure 12. Audio Interface Timing (PLL/EXT Slave mode, DSP mode, MSBS bit= “1”) VIH FCK VIL tBFCK tFCKB VIH BICK VIL tFCKD tBSD SDTO MSB tSDS 50%TVDD tSDH VIH SDTI VIL Figure 13. Audio Interface Timing (PLL/EXT Slave mode; Except DSP mode) 015010680-E-00 2015/09 - 24 - [AK4637] tSCK 65%AVDD DMCLK 50%AVDD 35%AVDD tSCKL tSRise tSFall dSCK = 100 x tSCKL / tSCK Figure 14. DMCLK Clock Timing 65%AVDD DMCLK 35%AVDD tDSDS tDSDH VIH2 DMDAT VIL2 Figure 15. Audio Interface Timing (DCLKP bit = “1”) 65%AVDD DMCLK 35%AVDD tDSDS tDSDH VIH2 DMDAT VIL2 Figure 16. Audio Interface Timing (DCLKP bit = “0”) VIH SDA VIL tBUF tLOW tHIGH tR tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA Start tSU:STO Stop 2 Figure 17. I C Bus Mode Timing 015010680-E-00 2015/09 - 25 - [AK4637] tAPD tRPD PDN VIL Figure 18. Power Down & Reset Timing 1 PMAD bit or PMDM bit tPDV SDTO 50%TVDD Figure 19. Power Down & Reset Timing 2 PMVCM bit tRVCM 1.15V VCOM pin Figure 20. VCOM Rising Timing 015010680-E-00 2015/09 - 26 - [AK4637] 9. Functional Descriptions ■ System Clock There are the following four clock modes to interface with external devices (Table 2, Table 3). Mode PMPLL bit M/S bit PLL3-0 bits PLL Master Mode 1 1 Table 5 PLL Slave Mode 1 0 Table 5 (PLL Reference Clock: BICK pin) EXT Slave Mode 0 0 X EXT Master Mode 0 1 X Table 2. Clock Mode Setting (x: Don’t care) Mode Figure Figure 21 Figure 22 Figure 23 Figure 24 MCKI pin Input Frequency of Table 5 (Selected by PLL3-0 bits) BICK pin FCK pin Output Output PLL Master Mode (Selected by BCKO bit) (1fs) PLL Slave Mode Input Input GND (PLL Reference Clock: BICK pin) (Selected by PLL3-0 bits) (1fs) Input Input Frequency of Table 11 Input EXT Slave Mode (Selected by CM1-0 bits) (1fs) ( 32fs) Input Frequency of Table 14 Output Output EXT Master Mode (Selected by CM1-0 bits) (Selected by BCKO bit) (1fs) Table 3. Clock Pins States in Clock Mode ■ Master Mode/Slave Mode The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the AK4637 is in power-down mode (PDN pin = “L”) and when exits reset state, the AK4637 is in slave mode. After exiting reset state, the AK4637 goes to master mode by changing M/S bit to “1”. When the AK4637 is in master mode, the FCK and BICK pins are a floating state until M/S bit becomes “1”. The FCK and BICK pins of the AK4637 must be pulled-down or pulled-up by a resistor (about 100k) externally to avoid the floating state. M/S bit Mode 0 Slave Mode (default) 1 Master Mode Table 4. Select Master/Slave Mode 015010680-E-00 2015/09 - 27 - [AK4637] ■ PLL Mode When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) circuit generates a clock that is selected by PLL3-0 and FS3-0 bits. The PLL lock times, when the AK4637 is supplied stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or the sampling frequency is changed, are shown in Table 5. Mode 1 2 3 4 5 6 7 12 13 Others PLL3 bit 0 0 0 0 0 0 0 1 1 PLL2 PLL1 PLL0 PLL Reference Input PLL Lock Time bit bit bit Clock Input Pin Frequency (max) 0 0 1 BICK pin 16fs 2ms 0 1 0 BICK pin 32fs 2ms 0 1 1 BICK pin 64fs 2ms 1 0 0 MCKI pin 11.2896MHz 5ms 1 0 1 MCKI pin 12.288MHz 5ms 1 1 0 MCKI pin 12MHz 5ms 1 1 1 MCKI pin 24MHz 5ms 1 0 0 MCKI pin 13.5MHz 5ms 1 0 1 MCKI pin 27MHz 5ms Others N/A Table 5. PLL Mode Setting (*fs: Sampling Frequency, N/A: Not Available) (default) ■ PLL Unlock State In this mode, FCK and BICK pins go to “L” until the PLL goes to lock state after PMPLL bit = “0” → “1” (Table 6). After the PLL is locked, a first period of FCK and BICK may be invalid clock, but these clocks return to normal state after a period of 1/fs. The BICK and FCK pins do not output invalid clocks such as PLL unlock state by setting PMPLL bit to “0”. During PMPLL bit = “0”, these pins output the same clock as EXT master mode. PLL State BICK pin FCK pin After PMPLL bit “0” → “1” “L” Output “L” Output PLL Unlock (except the case above) Invalid Invalid PLL Lock Table 9 1fs Output Table 6. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) 015010680-E-00 2015/09 - 28 - [AK4637] ■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the internal PLL circuit generates BICK and FCK clocks. When the state of AK4637 is ADC power-down or Loopback mode, the output of BICK, FCK and SDTO pins can be stopped by CKOFF bit. When CKOFF bit = “1”, BICK, FCK and SDTO pins output “L”. The sampling frequency is selected by FS3-0 bits as defined in Table 7. The BICK output frequency is selected between 16fs, 32fs or 64fs, by BCKO bit (Table 9). 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz DSP or P AK4637 MCKI BICK FCK 16fs, 32fs, 64fs 1fs BCLK FCK SDTO SDTI SDTI SDTO Figure 21. PLL Master Mode Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency (Note 29) 1 0 0 0 1 8kHz mode 2 0 0 1 0 11.025kHz mode 3 0 0 1 1 12kHz mode 5 0 1 0 1 16kHz mode 6 0 1 1 0 22.05kHz mode 7 0 1 1 1 24kHz mode 9 1 0 0 1 32kHz mode 10 1 0 1 0 44.1kHz mode 11 1 0 1 1 48kHz mode (default) Others Others N/A Table 7. Setting of Sampling Frequency (Reference Clock = MCKI pin) (N/A: Not Available) Note 29. When the MCKI pin is the PLL reference clock input, the sampling frequency generated by PLL differs from the sampling frequency of mode name in some combinations of MCKI frequency(PLL3-0 bits) and sampling frequency (FS3-0 bits). Refer to Table 8 for the details of sampling frequency. In master mode, FCK and BICK output frequency correspond to sampling frequencies shown in Table 8. 015010680-E-00 2015/09 - 29 - [AK4637] Input Frequency MCKI[MHz] 12 Sampling Frequency Sampling Frequency Mode generated by PLL [kHz] (Note 30) 8kHz mode 8.000000 12kHz mode 12.000000 16kHz mode 16.000000 24kHz mode 24.000000 32kHz mode 32.000000 48kHz mode 48.000000 11.025kHz mode 11.024877 22.05kHz mode 22.049753 44.1kHz mode 44.099507 24 8kHz mode 8.000000 12kHz mode 12.000000 16kHz mode 16.000000 24kHz mode 24.000000 32kHz mode 32.000000 48kHz mode 48.000000 11.025kHz mode 11.024877 22.05kHz mode 22.049753 44.1kHz mode 44.099507 13.5 8kHz mode 8.000300 12kHz mode 12.000451 16kHz mode 16.000601 24kHz mode 24.000901 32kHz mode 32.001202 48kHz mode 48.001803 11.025kHz mode 11.025218 22.05kHz mode 22.050436 44.1kHz mode 44.100871 27 8kHz mode 8.000300 12kHz mode 12.000451 16kHz mode 16.000601 24kHz mode 24.000901 32kHz mode 32.001202 48kHz mode 48.001803 11.025kHz mode 11.025218 22.05kHz mode 22.050436 44.1kHz mode 44.100871 11.2896 8kHz mode 8.000000 12kHz mode 12.000000 16kHz mode 16.000000 24kHz mode 24.000000 32kHz mode 32.000000 48kHz mode 48.000000 11.025kHz mode Note 31 22.05kHz mode Note 31 44.1kHz mode Note 31 Sampling frequency that differs from sampling frequency of mode name Note 30. These values are rounded off to six decimal places. Note 31. The AK4637 must be in EXT master mode when selecting this mode. Table 8. Sampling Frequency at PLL mode (Reference clock is MCKI) (1) 015010680-E-00 2015/09 - 30 - [AK4637] Input Frequency MCKI[MHz] 12.288 Sampling Frequency Sampling Frequency Mode generated by PLL [kHz] (Note 30) 8kHz mode 8.000000 12kHz mode Note 31 16kHz mode 16.000000 24kHz mode Note 31 32kHz mode 32.000000 48kHz mode Note 31 11.025kHz mode 11.025000 22.05kHz mode 22.050000 44.1kHz mode 44.100000 Sampling frequency that differs from sampling frequency of mode name Note 30. These values are rounded off to six decimal places. Note 31. The AK4637 must be in EXT master mode when selecting this mode. Table 8. Sampling Frequency at PLL mode (Reference clock is MCKI) (2) Mode BCKO1 bit BCKO0 bit BICK Output Frequency 0 0 0 16fs (default) 1 0 1 32fs 2 1 0 64fs 3 1 1 N/A Table 9. BICK Output Frequency at Master Mode (N/A: Not available) ■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to the BICK pin. The required clock for the AK4637 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5). The BICK and FCK inputs must be synchronized. The sampling frequency can be selected by FS3-2 bits (Table 10). DSP or P AK4637 MCKI BICK FCK 16fs, 32fs, 64fs 1fs BCLK FCK SDTO SDTI SDTI SDTO Figure 22. PLL Slave Mode (PLL Reference Clock: BICK pin) Mode 0 1 2 Others FS3 bit 0 0 1 FS2 bit FS1 bit FS0 bit Sampling Frequency 0 x x 8kHz ≤ fs ≤ 12kHz 1 x x 12kHz < fs ≤ 24kHz 0 x x 24kHz < fs ≤ 48kHz (default) Others N/A Table 10. Setting of Sampling Frequency (Reference Clock = BICK pin) (x: Do not care, N/A: Not Available) 015010680-E-00 2015/09 - 31 - [AK4637] ■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4637 becomes EXT mode. Master clock can be input to the internal ADC and DAC directly from the MCKI pin without internal PLL circuit operation. This mode is compatible with I/F of a normal audio CODEC. The external clocks required to operate this mode are MCKI (256fs, 384fs, 512fs or 1024fs), FCK (fs) and BICK (16fs). The master clock (MCKI) must be synchronized with FCK. The phase between these clocks is not important. The input frequency of MCKI is selected by CM1-0 bits (Table 11) and the sampling frequency is selected by FS3-2 bits (Table 12). Mode 0 1 2 3 Mode 0 1 2 Others MCKI Input Sampling Frequency Frequency Range 0 0 256fs 8kHz ≤ fs ≤ 48kHz (default) 0 1 384fs 8kHz ≤ fs ≤ 48kHz 1 0 512fs 8kHz ≤ fs ≤ 48kHz 1 1 1024fs 8kHz ≤ fs ≤ 24kHz Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) CM1 bit CM0 bit FS3 bit 0 0 1 FS2 bit FS1 bit FS0 bit Sampling Frequency 0 x x 8kHz ≤ fs ≤ 12kHz 12kHz < fs ≤ 24kHz 1 x x 0 x x 24kHz < fs ≤ 48kHz Others N/A Table 12. Setting of Sampling Frequency (N/A: Not Available) (default) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through SPP/SPN pins is shown in Table 13. MCKI S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 80dB 384fs 80dB 512fs 93dB 1024fs 96dB Table 13. Relationship between MCKI and S/N of SPP/SPN pins DSP or P AK4637 256fs, 384fs, 512fs or 1024fs MCKI  16fs BICK 1fs FCK MCLK BCLK FCK SDTO SDTI SDTI SDTO Figure 23. EXT Slave Mode 015010680-E-00 2015/09 - 32 - [AK4637] ■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The AK4637 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock can be input to the internal ADC and DAC directly from the MCKI pin without the internal PLL circuit operation. The external clock required to operate the AK4637 is MCKI (256fs, 384fs, 512fs or 1024fs). The input frequency of MCKI is selected by CM1-0 bits (Table 14) and the sampling frequency is selected by FS3-2 bits (Table 15). When the state of AK4637 is ADC power-down or Loopback mode, the output of BICK, FCK and SDTO pins can be stopped by CKOFF bit. When CKOFF bit = “1”, BICK, FCK and SDTO pins output “L”. The BICK output frequency is selected between 16fs, 32fs, 64fs, by BCKO bit (Table 17). MCKI Input Sampling Frequency Frequency Range 0 0 256fs 8kHz ≤ fs ≤ 48kHz (default) 0 1 384fs 8kHz < fs ≤ 48kHz 1 0 512fs 8kHz < fs ≤ 48kHz 1 1 1024fs 8kHz ≤ fs ≤ 24kHz Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) Mode 0 1 2 3 Mode 0 1 2 Others CM1 bit CM0 bit FS3 bit 0 0 1 FS2 bit FS1 bit FS0 bit Sampling Frequency 0 x x 8kHz ≤ fs ≤ 12kHz 1 x x 12kHz < fs ≤ 24kHz 0 x x 24kHz < fs ≤ 48kHz (default) Others N/A Table 15. Setting of Sampling Frequency (x: Do not care, N/A: Not Available) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through SPP/SPN pins is shown in Table 16. MCKI S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 80dB 384fs 80dB 512fs 93dB 1024fs 96dB Table 16. Relationship between MCKI and S/N of SPP/SPN pins DSP or P AK4637 MCKI BICK 256fs, 384fs, 512fs or 1024fs 16fs, 32fs, 64fs 1fs FCK MCLK BCLK FCK SDTO SDTI SDTI SDTO Figure 24. EXT Master Mode Mode 0 1 2 3 BCKO1 bit BCKO0 bit BICK Output Frequency 0 0 16fs 0 1 32fs 1 0 64fs 1 1 N/A Table 17. BICK Output Frequency at Master Mode 015010680-E-00 (default) 2015/09 - 33 - [AK4637] ■ System Reset Upon power-up, the AK4637 must be reset by bringing the PDN pin = “L”. This reset is released when a dummy command is input after the PDN pin = “H”. This ensures that all internal registers reset to their initial value. Dummy command is executed by writing all “0” to the register address 00H (Figure 25). It is recommended to set the PDN pin to “L” before power up the AK4637. In I2C Bus mode, the AK4637 does not return an ACK after receiving a slave address by a dummy command as shown in Figure 25. In the actual case, initialization cycle starts by 8 SCL clocks during the PDN pin = “H” regardless of the SDA line. Therefore, retry command is not required (Figure 26). Executing a write or read command to the other device that is connected to the same I2C Bus also resets the AK4637. S T A R T SDA S S T O P R/W="0" Slave Address Sub N A Address(00H) C K N A C K Data(00H) N P A C K Figure 25. Dummy Command in I2C Bus Mode S T A R T SDA R/W="0" S T O P Slave S Address N P A C K Figure 26. Reset Completion for example The ADC starts an initialization cycle by setting PMADC bit to “1” from “0”. The initialization cycle is set by ADRST1-0 bits (Table 18). During the initialization cycle, the ADC digital data outputs of both channels are forced to “0” in 2's complement. The ADC output reflects the analog input signal after the initialization cycle is finished. When using a digital microphone (PMDML/R bits =“0” → “1”), the initialization cycle is the same as ADC’s. Note 32. The initial data of ADC has offset data that depends on microphones and the cut-off frequency of HPF. If this offset is not small, make initialization cycle longer by setting ADRST1-0 bits or do not use the first data of ADC outputs. ADRST1-0 bits 00 01 10 11 Cycle 1059/fs 267/fs 531/fs 135/fs Initialize Cycle fs = 8kHz fs = 16kHz 132.4ms 66.2ms 33.4ms 16.7ms 66.4ms 33.2ms 16.9ms 8.4ms Table 18. ADC Initialization Cycle fs = 48kHz 22ms 5.6ms 11.1ms 2.8ms (default) The DAC is initialized by setting PMDAC bit “0” → “1”. The initialization cycle is 2/fs. Therefore, the DAC outputs signals after group delay period and 2/fs when power up the device. Normally, this group delay period or 2/fs initialization cycle mentioned above is absorbed by power-up time of amplifiers after the DAC (Lineout-amp, SPK-amp). 015010680-E-00 2015/09 - 34 - [AK4637] ■ Audio Interface Format Four types of data formats are available and can be selected by setting the DIF1-0 bits (Table 19). In all modes, the serial data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and BICK are output from the AK4637 in master mode, but must be input to the AK4637 in slave mode. 0 DIF1 bit 0 DIF0 bit 0 1 0 1 2 1 0 3 1 1 Mode SDTO (ADC) SDTI (DAC) BICK 16bit DSP Mode 16bit DSP Mode  16fs 24/16bit 16bit LSB justified  32fs MSB justified 24bit MSB justified 24bit MSB justified  48fs =32fs or 24/16 bit 24/16 bit I2S Compatible I2S Compatible  48fs Table 19. Audio Interface Format Figure Table 20 Figure 31 Figure 32 (default) Figure 33 If 24-bit(or 16-bit) data that ADC outputs is converted to 8-bit data by removing LSB 16-bit(8-bit), “-1” at 24bit(16bit) data is converted to “-1” at 8-bit data. And when the DAC playbacks this 8-bit data, “-1” at 8-bit data will be converted to “-65536” at 24-bit (“-256” at 16-bit) data which is a large offset. This offset can be removed by adding the offset of “32768” at 24-bit (“128” at 16bit) to 24-bit(16-bit) data before converting to 8-bit data. In Mode 1, 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”). In Mode 0 (16bit DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 20). DIF1 bit 0 DIF0 bit MSBS bit BCKP bit 0 0 0 1 1 0 1 1 0 Audio Interface Format MSB of SDTO is output by the rising edge (“”) of the first BICK after the rising edge (“”) of FCK. MSB of SDTI is latched by the falling edge (“”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by the falling edge (“”) of the first BICK after the rising edge (“”) of FCK. MSB of SDTI is latched by the rising edge (“”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by next rising edge (“”) of the falling edge (“”) of the first BICK after the rising edge (“”) of FCK. MSB of SDTI is latched by the falling edge (“”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by next falling edge (“”) of the rising edge (“”) of the first BICK after the rising edge (“”) of FCK. MSB of SDTI is latched by the rising edge (“”) of the BICK just after the output timing of SDTO’s MSB. Table 20. Audio Interface Format in Mode 0 015010680-E-00 Figure Figure 27 (default) Figure 28 Figure 29 Figure 30 2015/09 - 35 - [AK4637] FCK (Master) FCK (Slave) 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 BICK(16fs) SDTO(o) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 SDTI(i) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 31 0 1 2 13 14 15 16 17 18 29 30 31 0 1 2 13 14 15 16 17 18 29 30 31 0 15 0 BICK(32fs) SDTO(o) 15 14 2 1 0 SDTI(i) 15 14 2 1 0 Don’t Care 15 14 2 1 0 15 14 2 1 0 1/fs Don’t Care 1/fs 15: MSB, 0:LSB Figure 27. Mode 0 Timing (BCKP bit = “0”, MSBS bit = “0”) FCK (Master) FCK (Slave) 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 BICK(16fs) SDTO(o) 0 15 14 SDTI(i) 0 15 14 31 0 1 8 2 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 15 14 13 14 15 16 17 18 29 30 31 0 1 8 2 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 13 14 15 16 17 18 29 30 31 0 BICK(32fs) SDTO(o) 15 14 2 1 0 SDTI(i) 15 14 2 1 0 Don’t Care 1/fs 15 14 8 2 1 0 15 14 8 2 1 0 Don’t Care 1/fs 15: MSB, 0:LSB Figure 28. Mode 0 Timing (BCKP bit = “1”, MSBS bit = “0”) 015010680-E-00 2015/09 - 36 - [AK4637] FCK (Master) FCK (Slave) 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 BICK(16fs) SDTO(o) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 SDTI(i) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 31 0 1 2 13 14 15 16 17 18 29 30 31 0 1 2 13 14 15 16 17 18 29 30 31 0 15 0 BICK(32fs) SDTO(o) 15 14 2 1 0 SDTI(i) 15 14 2 1 0 Don’t Care 15 14 2 1 0 15 14 2 1 0 1/fs Don’t Care 1/fs 15: MSB, 0:LSB Figure 29. Mode 0 Timing (BCKP bit = “0”, MSBS bit = “1”) FCK (Master) FCK (Slave) 15 0 1 2 7 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 BICK(16fs) SDTO(o) 0 15 14 SDTI(i) 0 15 14 31 0 1 8 2 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 15 14 13 14 15 16 17 18 29 30 31 0 1 8 2 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 13 14 15 16 17 18 29 30 31 0 BICK(32fs) SDTO(o) 15 14 2 1 0 SDTI(i) 15 14 2 1 0 Don’t Care 1/fs 15 14 8 2 1 0 15 14 8 2 1 0 Don’t Care 1/fs 15: MSB, 0:LSB Figure 30. Mode 0 Timing (BCKP bit = “1”, MSBS bit = “1”) 015010680-E-00 2015/09 - 37 - [AK4637] FCK 0 1 2 3 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 SDTI(i) 15 14 13 0 1 2 8 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 15 16 17 18 23 24 30 31 15 Don’t Care 0 1 2 3 15 16 17 18 15 23 24 30 31 0 1 BICK(64fs) SDTO(o) 23 22 21 SDTI(i) 8 7 Don’t Care 6 0 15 14 8 23 1 Don’t Care 0 24bit: 23:MSB, 0:LSB 16bit: 15: MSB, 0:LSB Data 1/fs Figure 31. Mode 1 Timing FCK 0 1 2 3 19 20 21 22 23 24 25 31 0 1 2 3 15 16 17 18 23 24 30 31 0 1 BICK(64fs) SDTO(o) 23 22 21 4 3 2 1 0 SDTI(i) 23 22 21 4 3 2 1 0 Don’t Care 23 Don’t Care 24bit: 23:MSB, 0:LSB Data 1/fs Figure 32. Mode 2 Timing FCK 0 1 2 3 4 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1 23 24 30 31 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 0 1 2 3 4 20 21 22 23 24 25 31 0 Don’t Care 1 2 3 15 16 17 18 BICK(64fs) SDTO(o) 23 22 21 4 3 2 1 0 SDTI(i) 23 22 21 4 3 2 1 0 Don’t Care Don’t Care 24bit: 23:MSB, 0:LSB 16bit: 15: MSB, 0:LSB Data 1/fs Figure 33. Mode 3 Timing 015010680-E-00 2015/09 - 38 - [AK4637] ■ MIC/LINE Input Selector The AK4637 has an input selector. MDIF bit select single-ended input and differential input. When MDIF bit = “0”, the AIN pin is an input pin. Single-ended signal to the MIC-Amp can be input via the AIN pin. When MDIF bit = “1”, the IN+ pin and the IN- pin are input pins. Differential signal can be input to these pins. At this time, the IN- pin cannot be used as the BEEP pin. When DMIC bit = “1”, digital microphone input is selected regardless of MDIF bit. DMIC bit MDIF bit MIC Input 0 AIN pin (default) 0 1 IN+/ pins 1 x Digital MIC Table 21. MIC/Line In Path Select (x: Do not care, N/A: Not available) AK4637 MIC-Power MPWR pin 1k IN+ pin A/D IN- pin 1k HPF Audio I/F MIC-Amp BICK pin FCK pin STDO pin Figure 34. Differential Input Block Circuit (MDIF bit = “1”) ■ Microphone Gain Amplifier The AK4637 has a gain amplifier for microphone input. It is powered-up by PMADC bit = “1”. The gain of MIC-Amp is selected by the MGAIN3-0 bits. When single-ended input, the typical input impedance is 30k. When differential input, the typical input impedances are IN+=20kΩ and IN-=57kΩ@MGAIN3-0 bits = “0000” (0dB), IN+=16kΩ and IN-=244kΩ@MGAIN3-0 bits = “0110” (+18dB). A click noise may occur if the MIC-Amp gain is changed when both MIC-Amp and ADC (PMADC bit = “1”) are powered up. High frequency characteristics are attenuated when MIC-Amp = +30dB. The attenuation amount of when MIC-Amp = +30dB is -0.5dB at 10kHz frequency and -1.5dB at 20kHz frequency comparing with when MIC-Amp = +18dB. MGAIN3 bit 0 0 0 0 0 0 0 0 1 1 1 MGAIN2 bit MGAIN1 bit MGAIN0 bit Input Gain 0 0 0 0dB 0 0 1 +3dB 0 1 0 +6dB 0 1 1 +9dB 1 0 0 +12dB 1 0 1 +15dB 1 1 0 +18dB 1 1 1 +21dB 0 0 0 +24dB 0 0 1 +27dB 0 1 0 +30dB Others N/A Table 22. Input Gain (N/A: Not available) 015010680-E-00 (default) 2015/09 - 39 - [AK4637] ■ Microphone Power When PMMP bit = “1”, the MPWR pin supplies the power for microphones. This output voltage is typically 2.4V @MICL bit =“0”, and typically 2.0V@MICL bit = “1”. The load resistance is minimum 2.0k. Any capacitor must not be connected directly to the MPWR pin (Figure 35). MICL bit Output Voltage (typ) 0 2.4V (default) 1 2.0V Table 23. Microphone Power AK4637 MIC-Power MPWR pin  2k Audio AIN pin A/D HPF I/F BICK pin FCK pin STDO pin MIC-Amp Figure 35. MIC Block Circuit (MDIF bit = “0”) 015010680-E-00 2015/09 - 40 - [AK4637] ■ Digital Microphone 1. Connection to Digital Microphones When DMIC bit is set to “1”, the AIN/IN+ and BEEP/IN- pins become DMDAT (digital microphone data input) and DMCLK (digital microphone clock supply) pins, respectively. The same voltage as AVDD must be provided to the digital microphone. The Figure 36 shows mono connection examples. The DMCLK clock is input to a digital microphone from the AK4637. The digital microphone outputs 1bit data, which is generated by Modulator using DMCLK clock, to the DMDAT pin. PMDM bit control power up/down of the digital block (Decimation Filter and Digital Filter). (PMADC bit settings do not affect the digital microphone power management.) The DCLKE bit controls ON/OFF of the output clock from the DMCLK pin. When the AK4637 is powered down (PDN pin= “L”), the DMCLK and DMDAT pins become floating state. Pull-down resistors must be connected to DMCLK and DMDAT pins externally to avoid this floating state. When the digital microphone is used, AVDD must be provided as 2.8~3.6V. AVDD （2.8V~3.6V） AK4637 VDD AMP    DMCLK(64fs) PLL MCKI 100kΩ Modulator DMDAT Decimation Filter HPF1 Programmable Filter ALC SDTO R Figure 36. Connection Example of Monaural Digital Microphone 015010680-E-00 2015/09 - 41 - [AK4637] 2. Interface When DCLKP bit = “1”, data is input to the decimation filter while DMCLK = “H”. When DCLKP bit = “0”, data is input to the decimation filter while DMCLK pin= “L”. The DMCLK pin only supports 64fs. When DCLKE bit = “1”, DMCLK pin outputs 64fs. In this case, necessary clocks must be supplied to the AK4637 for ADC operation. When DCLKE bit = “0”, DMCLK pin outputs “L”. The Figure 37 and Figure 38 show the input and output timing. When DCLKP bit = “1”, Digital MIC outputs the data by the rising edge (“”) of DMCLK, and the AK4637 latches it by the falling edge (“”) of DMCLK. When DCLKP bit = “0”, Digital MIC outputs the data by the rising edge (“”) of DMCLK, and the AK4637 latches it by the falling edge (“”) of DMCLK. The output data through “the Decimation and Digital Filters” is 24bit full scale when the 1bit data density is 0%~100%. DMCLK(64fs) DMDAT DCLKP bit = “1” Valid Data Valid Data Valid Data Valid Data Figure 37. Data In/Output Timing with Digital Microphone (DCLKP bit = “1”) DMCLK(64fs) DMDAT DCLKP bit = “0” Valid Data Valid Data Valid Data Valid Data Figure 38. Data In/Output Timing with Digital Microphone (DCLKP bit = “0”) 015010680-E-00 2015/09 - 42 - [AK4637] ■ Digital Block The digital block consists of the blocks shown in Figure 39. Recording path and playback path is selected by setting ADCPF bit, PFDAC1-0 bits and PFSDO bit (Figure 40 ~ Figure 43, Table 24). PMADC bit ADC SDTI 1st Order HPFAD bit HPF1 ADCPF bit “1” “0” PMPFIL bit HPF bit LPF bit EQ2-5 bits ALC bit 1st Order HPF2 1st Order LPF 4-band PFDAC1-0 bits EQ PMDAC bit DVOL ALC (Volume) EQ1 bit “0” SMUTE 1-band EQ DAC “1” PFVOL PFSDO bit SDTO ADC: Includes the Digital Filter (LPF) for ADC as shown in “Filter Characteristics”. HPF1: High Pass Filter (HPF) for ADC as shown in “Digital HPF1”. HPF2: High Pass Filter. (See “Digital Programmable Filter Circuit”) LPF: Low Pass Filter (See “Digital Programmable Filter Circuit”) 4 Band EQ: Applicable for use as Equalizer or Notch Filter. (See “Digital Programmable Filter Circuit”) (6) ALC (Volume): Digital Volume with ALC Function. (See “Input Digital Volume (Manual Mode)” and “ALC Operation”) (7) 1 Band EQ: Applicable for use as Notch Filter (See “Digital Programmable Filter Circuit”) (8) PFVOL: Sidetone digital volume (See “Sidetone digital Volume”) (9) DVOL: Digital volume for playback path (See “Output Digital Volume”) (10) SMUTE: Soft mute function (See “Soft Mute”) (1) (2) (3) (4) (5) Figure 39. Digital Block Path Select 015010680-E-00 2015/09 - 43 - [AK4637] ADCPF bit 1 0 Mode Example PFDAC1-0 bits 00 01 PFSDO bit 1 0 Figure Recording Mode 1 & Playback Mode 2 Figure 40 Recording Mode 2 & Playback Mode 1 Figure 41 Recording Mode 2 & Playback Mode 2 (Programmable Filter Bypass Mode: x 00 0 Figure 42 PMPFIL bit = “0”) Loopback Mode 1 01 1 Figure 43 Table 24. Recording Playback Mode Example (x: Don’t care) (default) When changing those modes, PMPFIL bit must be “0”. ADC 1st Order 1st Order 1st Order 4 Band HPF1 HPF2 LPF EQ ALC (Volume) 1 Band EQ DVOL/ SMUTE DAC Figure 40. The Path in Recording Mode 1 & Playback Mode 2 (default) 1st Order ADC HPF1 1 Band DVOL/ SMUTE DAC EQ ALC 4 Band 1st Order 1st Order EQ LPF HPF2 (Volume) Figure 41. The Path in Recording Mode 2 & Playback Mode 1 ADC DAC 1st Order HPF1 DVOL/ SMUTE Figure 42. The Path in Recording Mode 2 & Playback Mode 2 ADC DAC 1st Order 1st Order 1st Order 4 Band HPF1 HPF2 LPF EQ ALC (Volume) 1 Band EQ DVOL/ SMUTE Figure 43. The Path in Loopback Mode 015010680-E-00 2015/09 - 44 - [AK4637] ■ Digital HPF1 A digital High Pass Filter (HPF) is integrated for DC offset cancellation of the ADC input. The cut-off frequencies (fc) of the HPF1 are set by HPFC1-0 bits. It is proportional to the sampling frequency (fs) and the default value is 3.7Hz (@fs = 48kHz). HPFAD bit controls the ON/OFF of the HPF1 (HPF ON is recommended). HPFC1 bit 0 0 1 1 HPFC0 bit 0 1 0 1 fc fs=8kHz fs=16kHz fs=48kHz 0.62Hz 1.2Hz 3.7Hz 2.47Hz 4.9Hz 14.8Hz 19.7Hz 39.5Hz 118.4Hz 39.5Hz 78.9Hz 236.8Hz Table 25. HPF1 Cut-off Frequency (default) ■ Digital Programmable Filter Circuit (1) High Pass Filter (HPF2) This is composed 1st order HPF. The coefficient of HPF is set by F1A13-0 bits and F1B13-0 bits. HPF bit controls ON/OFF of the HPF2. When the HPF2 is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when PMPFIL bit = “0” or HPF bit = “0”. The HPF2 starts operation 4/fs (max) after when HPF bit = PMPFIL bit = “1” is set. fs: Sampling Frequency fc: Cutoff Frequency Register Setting (Note 33) HPF: F1A[13:0] bits =A, F1B[13:0] bits =B (MSB=F1A13, F1B13; LSB=F1A0, F1B0) 1  1 / tan (fc/fs) 1 / tan (fc/fs) A= , 1 + 1 / tan (fc/fs) B= 1 + 1 / tan (fc/fs) Transfer Function 1  z 1 H(z) = A 1 + Bz 1 The cut-off frequency must be set as below. fc/fs  0.0001 (fc min = 4.8Hz at 48kHz) (2) Low Pass Filter (LPF) This is composed with 1st order LPF. F2A13-0 bits and F2B13-0 bits set the coefficient of LPF. LPF bit controls ON/OFF of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when PMPFIL bit = “0” or LPF bit = “0”. The LPF starts operation 4/fs (max) after when LPF bit =PMPFIL bit= “1” is set. 015010680-E-00 2015/09 - 45 - [AK4637] fs: Sampling Frequency fc: Cutoff Frequency Register Setting (Note 33) LPF: F2A[13:0] bits =A, F2B[13:0] bits =B (MSB=F2A13, F2B13; LSB=F2A0, F2B0) 1  1 / tan (fc/fs) 1 A= , 1 + 1 / tan (fc/fs) B= 1 + 1 / tan (fc/fs) Transfer Function 1 + z 1 H(z) = A 1 + Bz 1 The cut-off frequency must be set as below. fc/fs  0.05 (fc min = 2400Hz at 48kHz) (3) 4-band Equalizer & 1-band Equalizer after ALC This block can be used as equalizer or Notch Filter. 4-band equalizers (EQ2~EQ5) are switched ON/OFF independently by EQ2, EQ3, EQ4 and EQ5 bits. EQ1 bit controls ON/OFF switching of the equalizer after ALC (EQ1). When the equalizer is OFF, the audio data passes this block by 0dB gain. E1A15-0 bits, E1B15-0 bits and E1C15-0 bits set the coefficient of EQ1. E2A15-0 bits, E2B15-0 bits and E2C15-0 bits set the coefficient of EQ2. E3A15-0 bits, E3B15-0 bits and E3C15-0 bits set the coefficient of EQ3. E4A15-0 bits, E4B15-0 bits and E4C15-0 bits set the coefficient of EQ4. E5A15-0 bits, E5B15-0 bits and E5C15-0 bits set the coefficient of EQ5. The EQn (n=1, 2, 3, 4 or 5) coefficient must be set when EQn bit = “0” or PMPFIL bit = “0”. EQn starts operation 4/fs(max) after when EQn = PMPFIL bit = “1” is set. Each EQ2 ~ 5 blocks have a gain controller (EQ2G ~ EQ5G) independently after the equalizer. EQnG5-0 bits (n = 2~5) setting is reflected by writing “1” to EQCn bit (n = 2~5). EQnG5-0 bits and EQCn bit (n=2~5) can be set during operation (EQn =PMPFIL bit= “1”). fs: Sampling Frequency fo1 ~ fo5: Center Frequency fb1 ~ fb5: Band width where the gain is 3dB different from the center frequency K1 ~ K5: Gain (1  Kn < 3) Register Setting (Note 33) EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1 EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2 EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3 EQ4: E4A[15:0] bits =A4, E4B[15:0] bits =B4, E4C[15:0] bits =C4 EQ5: E5A[15:0] bits =A5, E5B[15:0] bits =B5, E5C[15:0] bits =C5 (MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15, E5A15, E5B15, E5C15 ; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0, E4C0, E5A0, E5B0, E5C0) 1  tan (fbn/fs) 2 tan (fbn/fs) An = Kn x , Bn = cos(2 fon/fs) x 1 + tan (fbn/fs) , 1 + tan (fbn/fs) Cn = 1 + tan (fbn/fs) (n = 1, 2, 3, 4, 5) 015010680-E-00 2015/09 - 46 - [AK4637] Transfer Function H(z) = {1 + G2 x h2(z) + G3 x h3(z) + G4 x h4(z) + G5 x h5(z)} x {1+ h1(z) } (G2, 3, 4, 5 = 1 or G) 1  z 2 hn (z) = An 1 Bnz 1 Cnz 2 (n = 1, 2, 3, 4, 5) The center frequency must be set as below. 0.003 < fon / fs < 0.497 When gain of K is set to “1”, this equalizer becomes a notch filter. When EQ2 EQ5 is used as a notch filter, central frequency of a real notch filter deviates from the above-mentioned calculation, if its central frequency of each band is near. The control soft that is attached to the evaluation board has functions that revises a gap of frequency and calculates the coefficient. When its central frequency of each band is near, the central frequency should be revised and confirm the frequency response. Note 33. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 213 X should be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit. OUT IN EQC2 bit = “0” EQ2 EQC2 bit = “1” EQ2 Gain (EQ2G5-0 bits) EQC3 bit = “0” EQ3 EQC3 bit = “1” EQ3 Gain (EQ3G5-0 bits) EQC4 bit = “0” EQ4 EQC4 bit = “1” EQ4 Gain (EQ4G5-0 bits) EQC5 bit = “0” EQ5 EQC5 bit = “1” EQ5 Gain (EQ5G5-0 bits) Figure 44. 4-Band EQ Structure 015010680-E-00 2015/09 - 47 - [AK4637] EQnG5-0 bits 3FH 3EH 3DH : 02H 01H 00H EQG_DATA 255 251 247 Gain [dB] 0 -0.17 -0.31 Formula 20 log10 (EQG_DATA/256) 11 -27.34 7 -31.26 0 MUTE Table 26. EQn Gain Setting (n=2, 3, 4, 5) (default) Transition Time of EQnG5-0 bits = 3FH ~ 00H EQnT1-0 bits Setting Value fs=8kHz fs=48kHz 00 256/fs 32ms 5.3ms (default) 01 2048/fs 256ms 42.7ms 10 8192/fs 1024ms 170.7ms 11 16384/fs 2048ms 341.3ms Table 27. Transition Time of EQn Gain (n= 2, 3, 4, 5) 015010680-E-00 2015/09 - 48 - [AK4637] Common Gain Sequence Examples IN OUT EQCn bit = “0” EQn EQCn bit = “1” EQn Gain (EQnG5-0 bits) (assuming the noise continues) (1) Set EQCn bit: “1” → “0” (Path Setting). The gain changes immediately by this setting. (2) Set EQnT1-0 bits: “xx” → “00” (Transition Time) (3) Set EQnG5-0 bits: “xxH” → “3FH” (Gain Setting; should be set to 0dB) IN OUT EQCn bit = “0” EQn EQCn bit = “1” EQn Gain (EQnG5-0 bits) (4) Set EQCn bit: “0” → “1” (Path Setting), EQnT1-0 bits Setting (Transition Time: It should be set longer when noise is stopped.) (Note 34) (5) Set EQnG5-0 bits (Gain Setting) The gain of EQn is changed after a transition time set by EQnT1-0 bits. Note 34. When changing a path of EQC2-5 by setting EQC2-5 bits “0” → “1”, the gain should be transitioned to 0dB before the settings. Otherwise, pop noise may occur on the path change. 015010680-E-00 2015/09 - 49 - [AK4637] ■ ALC Operation The ALC (Automatic Level Control) is operated by ALC block. When ADCPF bit is “1”, the ALC circuit operates for recording path, and the ALC circuit operates for playback path when ADCPF bit is “0”. ALC bit controls ON/OFF of ALC operation. The ALC block consists of these blocks shown below. The ALC limiter detection level is monitored at the level detection2 block after EQ block. The level detection1 block also monitors clipping detection level (+0.53dBFS). ALC Control Level Detection2 EQ Level Detection1 Output Input Volume Figure 45. ALC Block The polar (fc1) and the zero point (fs2) frequencies of EQ block are set by EQFC1-0 bits. Set EQFC bits according to the sampling frequency. When ALCEQ bit is OFF (ALCEQN bit = “1”), the level detection is not executed on this block. EQFC1-0 bits 00 01 10 11 Sampling Frequency Range 8kHz ≤ fs ≤ 12kHz 12kHz < fs ≤ 24kHz 24kHz < fs ≤ 48kHz Polar Frequency Zero-point Frequency (fc1) (fc2) 150Hz @ fs=12kHz 100Hz @ fs=12kHz 150Hz @ fs=24kHz 100Hz @ fs=24kHz 150Hz @ fs=48kHz 100Hz @ fs=48kHz N/A Table 28. ALCEQ Frequency Setting (EQFC1-0 bits; N/A: Not available) (default) [ALCEQ: First order zero pole high pass filter] Gain [dB] 0dB -3.5dB 100Hz (fc2) 150Hz (fc1) Frequency [Hz] Note 35. Black: Diagrammatic Line, Red: Actual Curve Figure 46. ALCEQ Frequency Response (fs = 48kHz) 015010680-E-00 2015/09 - 50 - [AK4637] 1. ALC Limiter Operation During ALC limiter operation, when output level exceeds the ALC limiter detection level (Table 29), the VOL value is attenuated automatically by the amount defined by the ALC limiter ATT step (Table 30). (Once this ALC limiter operation is started, attenuation will be repeated sixteen times.) After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input signal level exceeds ALC limiter detection level. LMTH2 LMTH1 LMTH0 ALC Limiter Detection ALC Recovery Counter Reset Level bit bit bit Level 0 0 0 ALC Output  2.5dBFS 2.5dBFS > ALC Output  4.1dBFS (default) 0 0 1 ALC Output  2.5dBFS 2.5dBFS > ALC Output  3.3dBFS 0 1 0 ALC Output  4.1dBFS 4.1dBFS > ALC Output  6.0dBFS 0 1 1 ALC Output  4.1dBFS 4.1dBFS > ALC Output  5.0dBFS 1 0 0 ALC Output  6.0dBFS 6.0dBFS > ALC Output  8.5dBFS 1 0 1 ALC Output  6.0dBFS 6.0dBFS > ALC Output  7.2dBFS 1 1 0 ALC Output  8.5dBFS 8.5dBFS > ALC Output  12.0dBFS 1 1 1 ALC Output  8.5dBFS 8.5dBFS > ALC Output  10.1dBFS Table 29. ALC Limiter Detection Level/ Recovery Counter Reset Level Output ATT Amount [dB] +0.53dBFS ≤ Output Level (*) 0.38148 –1.16dBFS ≤ Output Level < +0.53dBFS 0.06812 LM-LEVEL ≤ Output Level < –1.16dBFS 0.02548 (*) Comparison with the next output data. Table 30. ALC Limiter ATT Step 015010680-E-00 2015/09 - 51 - [AK4637] 2. ALC Recovery Operation ALC recovery operation wait for the WTM1-0 bits (Table 31) to be set after completing ALC limiter operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 29) during the wait time, ALC recovery operation is executed. The VOL value is automatically incremented by the setting value of RGAIN2-0 bits (Table 32) up to the set reference level (Table 33) in every sampling. When the VOL value exceeds the reference level (REF value), the VOL values are not increased. The recovery speed gets slower when the VOL peak level exceeds -12dBFS to make the recovery speed for low VOL level faster relatively. When “ALC recovery waiting counter reset level  Output Signal < ALC limiter detection level” during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When “ALC recovery waiting counter reset level > Output Signal”, the waiting timer of ALC recovery operation starts. ALC operations correspond to the impulse noise. When FRN bit = “0”, the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation. When large noise is input to a microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. The speed of fast recovery operation is set by RFST1-0 bits (Table 34). When FRN bit = “1”, the fast recovery does not operate though the impulse noise is input. Limiter amount of Fast recovery is set by FRATT bit (Table 35). WTM1 bit 0 0 1 1 ALC Recovery Cycle WTM0 bit 8kHz 16kHz 48kHz 0 128/fs 16ms 8ms 2.7ms 1 256/fs 32ms 16ms 5.3ms 0 512/fs 64ms 32ms 10.7ms 1 1024/fs 128ms 64ms 21.3ms Table 31. ALC Recovery Operation Waiting Period RGAIN2 bit RGAIN1 bit 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 RGAIN0 bit GAIN Step [dB] 0 0.00424 1 0.00212 0 0.00106 1 0.00106 0 0.00106 1 0.00106 0 0.00106 1 0.00106 Table 32. ALC Recovery Gain Step 015010680-E-00 (default) GAIN Change Timing 1/fs (default) 1/fs 1/fs 2/fs 4/fs 8/fs 16/fs 32/fs 2015/09 - 52 - [AK4637] REF7-0 bits GAIN (dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E1H +30.0 (default) 0.375dB : : 92H +0.375 91H 0.0 90H –0.375 : : 06H –52.125 05H –52.5 04H~00H MUTE Table 33. Reference Level of ALC Recovery Operation RFST1-0 bits Fast Recovery Gain Step [dB] 00 0.0032 (default) 01 0.0042 10 0.0064 11 0.0127 Table 34. Fast Recovery Speed Setting (FRN bit = “0”) ATT Switch Timing -0.00106 4/fs (default) 0 -0.00106 16/fs 1 Table 35. Fast Recovery Reference Volume Attenuation Amount FRATT bit ATT Amount [dB] 3. The Volume at ALC Operation The volume value during ALC operation is reflected in VOL7-0 bits. It is possible to check the current volume in 0.75dB step by reading the register value of VOL7-0 bits. VOL7-0 bits GAIN [dB] FFH +36.0 ≤ Gain FEH +35.25 ≤ Gain < +36.0 FCH +34.5 ≤ Gain < +35.25 FAH +33.75≤ Gain < +34.5 : : A2H +0.75 ≤ Gain < +1.5 A0H 0.0 ≤ Gain < +0.75 9EH -0.75 ≤ Gain < 0.0 : : 12H -53.25 ≤ Gain < -52.5 10H -72 ≤ Gain < -53.25 00H MUTE Table 36. Value of VOL7-0 bits 015010680-E-00 2015/09 - 53 - [AK4637] 4. Example of ALC Setting Table 37 and Table 38 show the examples of the ALC setting for recording and playback path. Limiter detection Level Fast Recovery mode Recovery waiting period Maximum gain at recovery operation fs=8kHz Data Operation 010 4.1dBFS 0 Enable 01 32ms E1H +30dB fs=48kHz Data Operation 010 4.1dBFS 0 Enable 11 21.3ms E1H +30dB Gain of IVOL E1H +30dB E1H RGAIN2-0 Recovery GAIN 000 0.00424dB 011 RFST1-0 Fast Recovery GAIN 11 Register Name LMTH2-0 FRN WTM1-0 REF7-0 IVL7-0, IVR7-0 EQFC1-0 ALCEQN ALC Register Name LMTH2-0 FRN WTM1-0 REF5-0 IVL7-0, IVR7-0 Comment 0.0127dB fc1=100Hz, ALC EQ Frequency 00 fc2=67Hz ALC EQ disable 0 Enable ALC enable 1 Enable Table 37. Example of the ALC Setting (Recording) Comment fs=8kHz Operation 4.1dBFS Enable 32ms +6dB 00 10 0 1 Limiter detection Level Fast Recovery mode Recovery waiting period Maximum gain at recovery operation Data 010 0 01 28H Gain of IVOL 91H 0dB 91H RGAIN2-0 Recovery GAIN 000 0.00424dB 011 RFST1-0 Fast Recovery GAIN 11 EQFC1-0 ALCEQN ALC 0.0127dB fc1=100Hz, ALC EQ Frequency 00 fc2=67Hz ALC EQ disable 0 Enable ALC enable 1 Enable Table 38. Example of the ALC Setting (Playback) 015010680-E-00 Data 010 0 11 28H 00 10 0 1 +30dB 0.00106dB (2/fs) 0.0032dB fc1=150Hz, fc2=100Hz Enable Enable fs=48kHz Operation 4.1dBFS Enable 21.3ms +6dB 0dB 0.00106dB (2/fs) 0.0032dB fc1=150Hz, fc2=100Hz Enable Enable 2015/09 - 54 - [AK4637] 5. Example of registers set-up sequence of ALC Operation The following registers must not be changed during ALC operation. These bits must be changed after ALC operation is stopped by ALC bit = “0”. ALC output is “0” data until the AK4637 becomes manual mode after writing “0” to ALC bit. LMTH2-0, WTM1-0, RGAIN2-0, REF7-0, RFST1-0, EQFC1-0, FRATT, FRN and ALCEQN bits Example: Recovery Waiting Period = 21.3ms@48kHz Recovery Gain = 0.00106dB (2/fs) Fast Recovery Gain = 0.0032dB Maximum Gain = +30.0dB Gain of IVOL = +30.0dB Limiter Detection Level = 4.1dBFS EQFC1-0 bits = “10” ALCEQN bit = “0” FRATT bit = “0” FRN bit = “0” ALC bit = “1” Manual Mode WR (FRATT= “0”, FRN = “0”) (1) Addr=09H, Data=00H WR (EQFC1-0, WTM1-0, RFST1-0) (2) Addr=0AH, Data=6CH WR (REF7-0) (3) Addr=0CH, Data=E1H WR (IVOL7-0) * The value of IVOL should be the same or smaller than REF’s WR (ALCEQN = “0”, ALC = “1”, RGAIN2-0, LMTH2-0) (4) Addr=0DH, Data=E1H (5) Addr=0BH, Data=2EH ALC Operation WR: Write Figure 47. Registers Set-up Sequence at ALC Operation (Recording path) 015010680-E-00 2015/09 - 55 - [AK4637] ■ Input Digital Volume (Manual Mode) The input digital volume becomes manual mode when ALC bit is set to “0” while ADCPF bit is “1”. This mode is used in the cases shown below. 1. After exiting reset state, when setting up the registers for ALC operation (LMTH and etc.) 2. When the registers for ALC operation (Limiter period, Recovery period and etc.) are changed. For example; when the sampling frequency is changed. 3. When IVOL is used as a manual volume control. IVOL7-0 bits set the gain of the volume control (Table 39). This volume has a soft transition function. Therefore no switching noise occurs during the transition. IVTM bit set the transition time (Table 40). When IVTM bit = “1”, it takes 944/fs (19.7ms@fs=48kHz) from F1H (+36dB) to 05H (-52.5dB). The volume is muted after transitioned to -72dB in the period set by IVTM bit when changing the volume from 05H (-52.5dB) to 00H (MUTE). IVOL7-0 bits GAIN (dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 E1H +30.0 E0H +29.625 0.375dB : : 92H +0.375 91H 0.0 90H 0.375 : : 06H 52.125 05H 52.5 04H~00H MUTE Table 39. Input Digital Volume Setting IVTM bit 0 1 (default) Transition Time of Input Digital Volume IVOL7-0 bits = “F1H” → “05H” Setting Value fs=8kHz fs=48kHz 236/fs 29.5ms 4.9ms 944/fs 118ms 19.7ms Table 40. Transition Time of Input Digital Volume (default) If IVOL7-0 bits are written during PMPFIL bit = “0”, IVOL operation starts with the written values after PMPFIL bit is changed to “1”. 015010680-E-00 2015/09 - 56 - [AK4637] ■ Sidetone Digital Volume The AK4637 has the digital volume control (4 levels, 6dB step) for the programmable filter output. PFVOL1-0 bits Gain 00 0dB (default) 01 -6dB 10 -12dB 11 -18dB Table 41. Sidetone Digital Volume ■ DAC Input Selector PFDAC1-0 bits select the signal of the DAC input or set the data mixing for each channel data. PFDAC1 PFDAC0 DAC Input Signal bit bit 0 0 SDTI (default) 0 1 PFVOL Output 1 0 (SDTI + PFVOL) / 2 1 1 N/A Table 42. DAC Input Selector (N/A: Not available) ■ Output Digital Volume The AK4637 has a digital output volume (205 levels, 0.5dB step, Mute). The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –89.5dB or MUTE. DVOL7-0 bits control volume. This volume has soft transition function. In automatic attenuation, the volume is attenuated by soft transition in 204/fs or 816/fs to reduce switching noises. When DVTM bit = “0”, it takes 816/fs (17.0ms@fs=48kHz) from 00H (+12dB) to CCH (MUTE). DVOL7-0 bits Gain Step 00H +12.0dB 01H +11.5dB 02H +11.0dB : : 0.5dB 18H 0dB (default) : CAH 89.0dB CBH 89.5dB CCH~FFH Mute ( ) Table 43. Output Digital Volume Setting Transition Time between DVL/R7-0 bits = 00H and CCH Setting fs=8kHz fs=48kHz 0 816/fs 102ms 17.0ms (default) 1 204/fs 25.5ms 4.3ms Table 44. Transition Time Setting of Output Digital Volume DVTM bit 015010680-E-00 2015/09 - 57 - [AK4637] ■ Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit is set “1”, the output signal is attenuated by -∞ (“0”) from the value (ATT DATA) set by DVOL7-0 bits during the cycle set by DVTM bit. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to ATT DATA from -∞ during the cycle set by DVTM bit. If the soft mute is cancelled within the cycle set by DVTM bit after starting the operation, the attenuation is discontinued and returned to ATT DATA. The soft mute is effective for changing the signal source without stopping the signal transaction. SMUTE bit ATT DATA (1) (1) (3) Attenuation - GD (2) GD Analog Output Figure 48. Soft Mute Function (1) The input signal is attenuated to  (“0”) in the cycle set by DVTM bit. When ATT DATA = +12dB (DVOL7-0 bits = 00H), 816/fs = 17ms@ fs=48kHz, DVTM bit= “0”. (2) Analog output corresponding to digital input has group delay (GD). (3) If soft mute is cancelled before attenuating to , the attenuation is discounted and returned to the level set by DVOL7-0 bits within the same cycle. 015010680-E-00 2015/09 - 58 - [AK4637] ■ BEEP Input When BEEPS bit is set to “1” during PMBP = PMSL = SPLSN bits = “1”, the input signal from the BEEP pin is output to the speaker amplifier (LOSEL bit = “0”) or mono line output (LOSEL bit = “1”). When BEEP input is performed, MDIF bit must be set to “0”. BPLVL3-0 bits set the gain of BEEP-Amp. The total gain is defined according to SPKG1-0 bits setting when speaker amplifier is performed, and LVCM1-0 bits when mono line output is performed. Input BEEP gain is controlled by BPLVL3-0 bits (Table 45). BPLVL3 bit BPLVL2 bit BPLVL1 bit BPLVL0 bit BEEP Gain 0 0 0 0 0dB (default) 0 0 0 1 6dB 0 0 1 0 12dB 0 0 1 1 18dB 0 1 0 0 24dB 0 1 0 1 30dB 0 1 1 0 33dB 0 1 1 1 36dB 1 0 0 0 39dB 1 0 0 1 42dB Others N/A Table 45. BEEP Output Gain Setting (N/A: Not available) BPVCM bit set the common voltage of BEEP input amplifier (Table 46). BPVCM bit BEEP-Amp Common Voltage (typ) 0 1.15V (default) 1 1.65V (Note 14, Note 36) Note 14. The maximum value is the smaller one of AVDD Vpp or 3.3Vpp when BPVCM bit = “1”. However, a click noise may occur when the amplitude after BEEP-Amp is 0.5Vpp or more. (Set by BPLVL3-0 bits) Note 36. When the BEEP signal is output to the speaker amplifier and BPVCM bit = “1”, AVDD must be supplied 2.8V or more. Table 46. Common Potential Setting of BEEP-Amp To MIC-Amp BEEP/IN- pin BPLVL3-0 bits “1” BEEPS bit To Speaker-Amp or Lineout-Amp “0” MDIF bit BEEP-Amp Figure 49. Block Diagram of BEEP pin 015010680-E-00 2015/09 - 59 - [AK4637] ■ Speaker Output (SPP/SPN pins, LOSEL bit = “0”) When LOSEL bit = “0”, the DAC output signal is input to the speaker amplifier. The speaker amplifier has mono output as it is BTL capable. The gain and output level are set by SPKG1-0 bits. The output level depends on AVDD and SPKG1-0 bits setting. SPK-Amp Output Level (DAC Input =0dBFS, AVDD=3.3V) 00 +6.4dB 3.36Vpp (default) 01 +8.4dB 4.23Vpp (Note 37) 10 +11.1dB 5.76Vpp (Note 37) 11 +14.9dB 8.90Vpp (AVDD=5.0V; Note 37) Note 37. The output level is calculated on the assumption that the signal is not clipped. However, in the actual case, the SPK-Amp output signal is clipped when DAC outputs 0dBFS signal. The SPK-Amp output level should be kept under 4.0Vpp (AVDD=3.3V) by adjusting digital volume to prevent clipped noise. Table 47. SPK-Amp Gain SPKG1-0 bits Gain < Speaker-Amp Control Sequence > The speaker amplifier is powered-up/down by PMSL bit. When PMSL bit is “0” at LOSEL bit = “0”, SPP pin is pulled-down to VSS1 by 100kΩ (typ) and the SPN pin is placed in a Hi-Z state. When PMSL bit is “1” and SLPSN bit is “0” at LOSEL bit = “0”, the speaker amplifier enters power-save mode. In this mode, the SPP pin is placed in Hi-Z state and the SPN pin outputs AVDD/2 voltage. When the PMSL bit is “1” at LOSEL bit = “0” after the PDN pin is changed from “L” to “H”, the SPP and SPN pins rise up in power-save mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to AVDD/2 voltage. Because the SPP and SPN pins rise up in power-save mode, pop noise can be reduced. When the AK4637 is powered-down (PMSL bit = “0”), pop noise can also be reduced by first entering power-save-mode. PMSL SLPSN bit bit 0 x 0 1 1 LOSEL bit Mode SPP pin SPN pin Power-down Pull-down to VSS1 Hi-Z Power-save Hi-Z AVDD/2 Normal Operation Normal Operation Normal Operation Table 48 Speaker-Amp Mode Setting (x: Don’t care) Don't care (default) "L" PMSL bit >1ms SLPSN bit SPP pin SPN pin >0ms Hi-Z Hi-Z Hi-Z AVDD/2 AVDD/2 Hi-Z Figure 50. Power-up/Power-down Timing for Speaker-Amp 015010680-E-00 2015/09 - 60 - [AK4637] ■ Thermal Shutdown Function When the internal temperature of the device rises up irregularly (e.g. Output pins of speaker-amp are shortened), the speaker-amp and the lineout-amp are automatically powered down and then THDET bit becomes “1” (thermal shutdown). When TSDSEL bit = “0” (default), the internal temperature goes down and the thermal shutdown is released, the speaker-amp or the lineout-amp is powered up automatically and THDET bit returns to “0”. When TSDSEL bit = “1”, these blocks will not return to a normal operation until being reset by the PDN pin. THDET bit becomes “0” by this PDN pin reset. 015010680-E-00 2015/09 - 61 - [AK4637] ■ Monaural Line Output (AOUT pin, LOSEL bit = “1”) When LOSEL bit is set to “1”, the output signal of DAC is output in single-ended format via AOUT pin. The monaural line output is valid at AVDD = 2.8~3.6V. When DACL bit is “0” at LOSEL = PMSL = SLPSN bits = “1”, output signal is muted and AOUT pin output common voltage. The load impedance is 10k (min.). When PMSL bit = “0” at LOSEL = SLPSN bits = “1”, the monaural line output enters power-down mode and the output is pulled-down to VSS1 by 100k(typ). Pop noise at power-up/down can be reduced by changing PMSL bit when SLPSN bit = “0” at LOSEL bit = “1”. In this case, output signal line should be pulled-down to VSS1 by 22k after AC coupled as Figure 52. Rise/Fall time is 300ms (max) when C=1F and RL=10k. When LOSEL = PMSL = SLPSN bits = “1”, monaural line output is in normal operation. LVCM1-0 bits set the gain of monaural line output. “DACL bit” “LVCM1-0 bits” DAC AOUT pin “BEEPS bit” BEEP Figure 51. Monaural Line Output PMSL bit 0 1 SLPSN bit Mode AOUT pin 0 Power Down Fall-down to VSS1 (default) 1 Power Down Pull-down to VSS1 0 Power Save Rise up to Common Voltage 1 Normal Operation Normal Operation Table 49. Monaural Line Output Mode Select LVCM1-0 bits 00 01 10 11 AVDD Gain Common Voltage (typ) 2.8 ~ 3.6V 0dB 1.3V 3.0 ~ 3.6V +2dB 1.5V (default) 2.8 ~ 3.6V +2dB 1.3V 3.0 ~ 3.6V +4dB 1.5V Table 50. Monaural Lineout Volume Setting 1F AOUT 220 External Input 22k Note 38. If the value of 22k resistance at pop noise reduction circuit is increased, the power-up time of Monaural line output is increased but the pop noise level is not decreased. Do not use a resistor less than 22k at the pop noise reduction circuit since the line output drivability is minimum 10k. Figure 52. External Circuit for Monaural Line Output (in case of using a Pop Noise Reduction Circuit) 015010680-E-00 2015/09 - 62 - [AK4637] [Monaural Line Output Control Sequence (in case of using a Pop Noise Reduction Circuit)] (6) (1) LOSEL bit (2) (5) PMSL bit (3) (4) SLPSN bit 99% Common Voltage Normal Output AOUT pins 1% Common Voltage 300 ms 300 ms Figure 53. Monaural Line Output Control Sequence (in case of using a Pop Noise Reduction Circuit) (1) Set LOSEL bit = “1”. Enable monaural line output. (2) Set PMSL bit = “1”. Monaural line output exits power-down mode. AOUT pin rises up to common voltage. Rise time to 99% common voltage is 200ms (max. 300ms) when C=1F. (3) Set SLPSN bit = “1” after AOUT pin rises up. Monaural line output exits power-save mode. Monaural line output is enabled. (4) Set SLPSN bit = “0”. Monaural line output enters power-save mode. (5) Set PMSL bit = “0”. Monaural line output enters power-down mode. AOUT pin falls down to 1% of the common voltage. Fall time is 200ms (max. 300ms) when C=1F. (6) Set LOSEL bit = “0” after wait time (≥300ms). Disable monaural line output. 015010680-E-00 2015/09 - 63 - [AK4637] [Monaural Line Output Control Sequence (SLPSN bit = “1”: in case of not using a Pop Noise Reduction Circuit)] (8) (1) LOSEL bit (2) SLPSN bit (7) (3) PMSL bit AOUT pin External Input (4) (4) (5) External MUTE (6) MUTE Normal Operation MUTE Figure 54. Monaural Line Output Control Sequence (SLPSN bit = “1”: in case of not using a Pop Noise Reduction Circuit) (1) Set LOSEL bit = “1”. Enable monaural line output. (2) Set SLPSN bit = “1”. Pop noise reduction circuit is disabled. (3) Set PMSL bit = “1”. Monaural line output is powered-up. AOUT pin rises up to common voltage. (4) Time constant is defined according to external capacitor (C) and resistor (RL). (5) Release external MUTE when the external input is stabled. Monaural line output is enabled. (6) Set external MUTE ON (7) Set PMSL bit = “0”. Monaural line output is powered-down. AOUT pin fall down. (8) Set LOSEL bit = “0” after wait time (≥300ms). Disable monaural line output. ■ Regulator Block The AK4637 integrates a regulator. The 3.3V (typ) power supply voltage from the AVDD pin is converted to 2.3V (typ) by the regulator and supplied to the analog blocks (MIC-Amp, ADC, DAC, BEEP). The regulator is powered up by PMVCM bit = “1”, and powered down by PMVCM = “0”. Connect a 2.2µF (± 10%) capacitor to the REGFIL pin to reduce noise on AVDD. AK4637 Power-up: PMVCM bit = “1” Power-down: PMVCM bit = “0” AVDD Regulator To Analog Block typ 2.3V REGFIL 2.2F ± 10% Figure 55 Regulator Block 015010680-E-00 2015/09 - 64 - [AK4637] ■ Serial Control Interface The AK4637 supports the fast-mode I2C Bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins must be connected to a voltage in the range from TVDD or more to 6V or less. 1. WRITE Operations Figure 56 shows the data transfer sequence for the I2C Bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 62). After the START condition, a slave address is sent. This address is seven bits of the slave address are fixed as “0010010” and the next bit is a data direction bit (R/W) (Figure 57). If the slave address matches that of the AK4637, the AK4637 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 63). A R/W bit value of “1” indicates that the read operation is to be executed, and “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4637. The format is MSB first, and those most significant 1bit is fixed to zero (Figure 58). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 59). The AK4637 generates an acknowledge after each byte is received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 62). The AK4637 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4637 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal address counter is incremented by one, and the next data is automatically taken into the next address. The address counter will “roll over” to 00H and the previous data will be overwritten if the address exceeds “3FH” prior to generating a stop condition. The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line can only be changed when the clock signal on the SCL line is LOW (Figure 64) except for the START and STOP conditions. S T A R T SDA S T O P R/W="0" Slave S Address Sub Address(n) Data(n) A C K A C K Data(n+1) Data(n+x) A C K A C K A C K A C K Figure 56. Data Transfer Sequence at I2C Bus Mode 0 0 1 0 0 P 1 0 R/W A2 A1 A0 Figure 57. The First Byte 0 A6 A5 A4 A3 Figure 58. The Second Byte 015010680-E-00 2015/09 - 65 - [AK4637] D7 D6 D5 D4 D3 D2 D1 D0 Figure 59. The Third Byte 2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4637. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal address counter is incremented by one, and the next data is automatically taken into the next address. The address counter will “roll over” to 00H and the data of 00H will be read out if the address exceeds “3FH” of Register map prior to generating a stop condition. The AK4637 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. 2-1. CURRENT ADDRESS READ The AK4637 has an internal address counter that maintains the address of the last accessed word incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4637 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4637 ceases the transmission. S T A R T SDA S S T O P R/W="1" Slave Address Data(n) Data(n+1) MA AC SK T E R A C K Data(n+2) MA AC S K T E R Data(n+x) MA AC S K T E R MA AC SK T E R P MN AA SC T K E R Figure 60. Current Address Read 2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit “1”. The AK4637 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4637 ceases the transmission. S T A R T SDA S T A R T R/W="0" Slave S Address Sub Address(n) A C K Slave S Address A C K S T O P R/W="1" Data(n) A C K Data(n+1) MA AC S K T E R Data(n+x) MA AC SK T E R MA AC SK T E R P MN A A SC T K E R Figure 61. Random Address Read 015010680-E-00 2015/09 - 66 - [AK4637] SDA SCL S P start condition stop condition Figure 62. Start Condition and Stop Condition DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 63. Acknowledge (I2C Bus) SDA SCL data line stable; data valid change of data allowed Figure 64. Bit Transfer (I2C Bus) 015010680-E-00 2015/09 - 67 - [AK4637] ■ Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH Register Name D7 D6 D5 D4 D3 Power Management 1 PMPFIL PMVCM PMBP 0 LOSEL Power Management 2 0 0 0 0 M/S Signal Select 1 SLPSN MGAIN3 DACS 0 PMMP Signal Select 2 SPKG1 SPKG0 0 MICL 0 Signal Select 3 LVCM1 LVCM0 DACL 0 0 Mode Control 1 PLL3 PLL2 PLL1 PLL0 0 Mode Control 2 CM1 CM0 0 0 FS3 Mode Control 3 TSDSEL THDET SMUTE 0 MSBS Digital MIC 0 0 0 PMDM DCLKE Timer Select ADRST1 ADRST0 FRATT FRN 0 ALC Timer Select 0 IVTM EQFC1 EQFC0 WTM1 ALC Mode Control 1 ALCEQN LMTH2 ALC RGAIN2 RGAIN1 ALC Mode Control 2 REF7 REF6 REF5 REF4 REF3 Input Volume Control IVOL7 IVOL6 IVOL5 IVOL4 IVOL3 ALC Volume VOL7 VOL6 VOL5 VOL4 VOL3 BEEP Control 0 BPVCM BEEPS 0 BPLVL3 Digital Volume Control DVOL7 DVOL6 DVOL5 DVOL4 DVOL3 EQ Common Gain Select 0 0 0 EQC5 EQC4 EQ2 Gain Setting EQ2G5 EQ2G4 EQ2G3 EQ2G2 EQ2G1 EQ3 Gain Setting EQ3G5 EQ3G4 EQ3G3 EQ3G2 EQ3G1 EQ4 Gain Setting EQ4G5 EQ4G4 EQ4G3 EQ4G2 EQ4G1 EQ5 Gain Setting EQ5G5 EQ5G4 EQ5G3 EQ5G2 EQ5G1 Digital Filter Select 1 0 0 0 0 0 Digital Filter Select 2 0 0 0 0 0 Digital Filter Mode 0 0 PFVOL1 PFVOL0 PFDAC1 HPF2 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 HPF2 Co-efficient 1 0 0 F1A13 F1A12 F1A11 HPF2 Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 HPF2 Co-efficient 3 0 0 F1B13 F1B12 F1B11 LPF Co-efficient 0 F2A7 F2A6 F2A5 F2A4 F2A3 LPF Co-efficient 1 0 0 F2A13 F2A12 F2A11 LPF Co-efficient 2 F2B7 F2B6 F2B5 F2B4 F2B3 LPF Co-efficient 3 0 0 F2B13 F2B12 F2B11 Digital Filter Select 3 0 0 0 EQ5 EQ4 E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1 Co-efficient 1 E1A15 E1A14 E1A13 E1A12 E1A11 E1 Co-efficient 2 E1B7 E1B6 E1B5 E1B4 E1B3 E1 Co-efficient 3 E1B15 E1B14 E1B13 E1B12 E1B11 E1 Co-efficient 4 E1C7 E1C6 E1C5 E1C4 E1C3 E1 Co-efficient 5 E1C15 E1C14 E1C13 E1C12 E1C11 E2 Co-efficient 0 E2A7 E2A6 E2A5 E2A4 E2A3 E2 Co-efficient 1 E2A15 E2A14 E2A13 E2A12 E2A11 E2 Co-efficient 2 E2B7 E2B6 E2B5 E2B4 E2B3 E2 Co-efficient 3 E2B15 E2B14 E2B13 E2B12 E2B11 E2 Co-efficient 4 E2C7 E2C6 E2C5 E2C4 E2C3 E2 Co-efficient 5 E2C15 E2C14 E2C13 E2C12 E2C11 E3 Co-efficient 0 E3A7 E3A6 E3A5 E3A4 E3A3 E3 Co-efficient 1 E3A15 E3A14 E3A13 E3A12 E3A11 015010680-E-00 D2 D1 PMDAC 0 PMPLL PMSL MGAIN2 MGAIN1 0 0 0 0 CKOFF BCKO1 FS2 FS1 BCKP DIF1 0 DCLKP 0 0 WTM0 RFST1 RGAIN0 LMTH1 REF2 REF1 IVOL2 IVOL1 VOL2 VOL1 BPLVL2 BPLVL1 DVOL2 DVOL1 EQC3 EQC2 EQ2G0 EQ2T1 EQ3G0 EQ3T1 EQ4G0 EQ4T1 EQ5G0 EQ5T1 HPFC1 HPFC0 0 LPF PFDAC0 ADCPF F1A2 F1A1 F1A10 F1A9 F1B2 F1B1 F1B10 F1B9 F2A2 F2A1 F2A10 F2A9 F2B2 F2B1 F2B10 F2B9 EQ3 EQ2 E1A2 E1A1 E1A10 E1A9 E1B2 E1B1 E1B10 E1B9 E1C2 E1C1 E1C10 E1C9 E2A2 E2A1 E2A10 E2A9 E2B2 E2B1 E2B10 E2B9 E2C2 E2C1 E2C10 E2C9 E3A2 E3A1 E3A10 E3A9 D0 PMADC 0 MGAIN0 MDIF 0 BCKO0 FS0 DIF0 DMIC DVTM RFST0 LMTH0 REF0 IVOL0 VOL0 BPLVL0 DVOL0 0 EQ2T0 EQ3T0 EQ4T0 EQ5T0 HPFAD HPF PFSDO F1A0 F1A8 F1B0 F1B8 F2A0 F2A8 F2B0 F2B8 EQ1 E1A0 E1A8 E1B0 E1B8 E1C0 E1C8 E2A0 E2A8 E2B0 E2B8 E2C0 E2C8 E3A0 E3A8 2015/09 - 68 - [AK4637] Addr 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Register Name E3 Co-efficient 2 E3 Co-efficient 3 E3 Co-efficient 4 E3 Co-efficient 5 E4 Co-efficient 0 E4 Co-efficient 1 E4 Co-efficient 2 E4 Co-efficient 3 E4 Co-efficient 4 E4 Co-efficient 5 E5 Co-efficient 0 E5 Co-efficient 1 E5 Co-efficient 2 E5 Co-efficient 3 E5 Co-efficient 4 E5 Co-efficient 5 D7 E3B7 E3B15 E3C7 E3C15 E4A7 E4A15 E4B7 E4B15 E4C7 E4C15 E5A7 E5A15 E5B7 E5B15 E5C7 E5C15 D6 E3B6 E3B14 E3C6 E3C14 E4A6 E4A14 E4B6 E4B14 E4C6 E4C14 E5A6 E5A14 E5B6 E5B14 E5C6 E5C14 D5 E3B5 E3B13 E3C5 E3C13 E4A5 E4A13 E4B5 E4B13 E4C5 E4C13 E5A5 E5A13 E5B5 E5B13 E5C5 E5C13 D4 E3B4 E3B12 E3C4 E3C12 E4A4 E4A12 E4B4 E4B12 E4C4 E4C12 E5A4 E5A12 E5B4 E5B12 E5C4 E5C12 D3 E3B3 E3B11 E3C3 E3C11 E4A3 E4A11 E4B3 E4B11 E4C3 E4C11 E5A3 E5A11 E5B3 E5B11 E5C3 E5C11 D2 E3B2 E3B10 E3C2 E3C10 E4A2 E4A10 E4B2 E4B10 E4C2 E4C10 E5A2 E5A10 E5B2 E5B10 E5C2 E5C10 D1 E3B1 E3B9 E3C1 E3C9 E4A1 E4A9 E4B1 E4B9 E4C1 E4C9 E5A1 E5A9 E5B1 E5B9 E5C1 E5C9 D0 E3B0 E3B8 E3C0 E3C8 E4A0 E4A8 E4B0 E4B8 E4C0 E4C8 E5A0 E5A8 E5B0 E5B8 E5C0 E5C8 Note 39. PDN pin = “L” resets the registers to their default values. Note 40. The bits defined as 0 must contain a “0” value. Note 41. Writing access to 40H ~ 7FH is prohibited. 015010680-E-00 2015/09 - 69 - [AK4637] ■ Register Definitions Addr 00H Register Name Power Management 1 R/W Default D7 PMPFIL D6 PMVCM D5 PMBP D4 0 D3 LOSEL D2 PMDAC D1 0 D0 PMADC R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R 0 R/W 0 PMADC: Microphone Amplifier and ADC Power Management 0: Power-down (default) 1: Power-up When the PMADC bit is changed from “0” to “1”, the initialization cycle (1059/fs=22ms @48kHz, ADRST1-0 bits = “00”) starts. After initializing, digital data of the ADC is output. PMDAC: DAC Power Management 0: Power down (default) 1: Power up LOSEL: Monaural Line Output Select 0: Speaker Output (SPP/SPN pins) (default) 1: Monaural Line Output (AOUT pin) PMBP: BEEP Input Select and Power Management 0: Power down (IN- pin) (default) 1: Power up (BEEP pin) PMVCM: VCOM and Regulator (2.3V) Power Management 0: Power down (default) 1: Power up PMPFIL: Programmable Filter Block Power Management 0: Power down (default) 1: Power up The AK4637 can be powered down by writing “0” to the address “00H” and PMPLL, PMMP, PMSL and PMDM bits. In this case, register values are maintained. 015010680-E-00 2015/09 - 70 - [AK4637] Addr 01H Register Name Power Management 2 R/W Default D7 0 D6 0 D5 0 D4 0 D3 M/S D2 PMPLL D1 PMSL D0 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 PMSL: Speaker Amplifier or Monaural Line Output Power Management 0: Power down (default) 1: Power up PMPLL: PLL Power Management 0: EXT Mode and Power down (default) 1: PLL Mode and Power up M/S: Master / Slave Mode Select 0: Slave Mode (default) 1: Master Mode Addr 02H Register Name Signal Select 1 R/W Default D7 SLPSN D6 MGAIN3 D5 DACS D4 0 D3 PMMP D2 MGAIN2 D1 MGAIN1 D0 MGAIN0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 1 R/W 1 R/W 0 MGAIN3-0: Microphone Amplifier Gain Control (Table 22) Default: “0110” (+18dB) PMMP: MPWR pin Power Management 0: Power down: Hi-Z (default) 1: Power up DACS: Signal Switch Control from DAC to Speaker Amplifier 0: OFF (default) 1: ON SLPSN: Speaker Amplifier or Monaural Line Output Power-Save Mode LOSEL bit = “0” (Speaker Output Select) 0: Power Save Mode (default) 1: Normal Operation When SLPSN bit is “0”, Speaker Amplifier is in power-save mode. In this mode, the SPP pin goes to Hi-Z and the SPN pin outputs AVDD/2 voltage. When PMSL bit = “1”, SLPSN bit is enabled. After the PDN pin is set to “L”, Speaker Amplifier is in power-down mode since PMSL bit is “0”. LOSEL bit = “1” (Monaural Line Output Select) 0: Power Save Mode (default) 1: Normal Operation When SLPSN bit is “0”, Monaural line output is in power-save mode. In this mode, the AOUT pin output 1.5V or 1.3V. When PMSL bit = “1”, SLPSN bit is enabled. After the PDN pin is set to “L”, Monaural line output is in power-down mode since PMSL bit is “0”. 015010680-E-00 2015/09 - 71 - [AK4637] Addr 03H Register Name Signal Select 2 R/W Default D7 SPKG1 D6 SPKG0 D5 0 D4 MICL D3 0 D2 0 D1 0 D0 MDIF R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MDIF: ADC Input Source Select (Table 21) 0: AIN pin Single-ended Input (default) 1: IN+/ pins Full-differential Input MICL: MPWR pin Output Voltage Select 0: typ 2.4V (default) 1: typ 2.0V SPKG1-0: Speaker Amplifier Output Gain Select (Table 47) Default: “00” (+6.4dB) Addr 04H Register Name Signal Select 3 R/W Default D7 LVCM1 D6 LVCM0 D5 DACL D4 0 D3 0 D2 0 D1 0 D0 0 R/W 0 R/W 1 R/W 0 R 0 R 0 R 0 R 0 R 0 DACL: Signal Switch Control from DAC to Monaural Line Amplifier 0: OFF (default) 1: ON LVCM1-0: Monaural Line Output Gain and Common Voltage Setting (Table 50) Default: “01” (+2dB, 1.5V) Addr 05H Register Name Mode Control 1 R/W Default D7 PLL3 D6 PLL2 D5 PLL1 D4 PLL0 D3 0 D2 CKOFF D1 BCKO1 D0 BCKO0 R/W 0 R/W 1 R/W 0 R/W 1 R 0 R/W 0 R/W 0 R/W 0 BCKO: BICK Output Frequency Setting in Master Mode (Table 9, Table 17) 00: 16fs (default) 01: 32fs 10: 64fs 11: N/A CKOFF: FCK, BICK, SDTO Output Stop Setting in Master Mode 0: FCK, BICK, SDTO Output (default) 1: FCK, BICK, SDTO Output Stop PLL3-0: PLL Reference Clock Select (Table 5) Default: “0101” (MCKI, 12.288MHz) 015010680-E-00 2015/09 - 72 - [AK4637] Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Mode Control 2 R/W Default CM1 R/W 0 CM0 R/W 0 0 R 0 0 R 0 FS3 R/W 1 FS2 R/W 0 FS1 R/W 1 FS0 R/W 1 FS3-0: Sampling frequency Setting (Table 7, Table 10, Table 12, Table 15) Default: “1011” (fs=48kHz) CM1-0: MCKI Input Frequency Setting in EXT mode (Table 11, Table 14) Default: “00” (256fs) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H Mode Control 3 R/W Default TSDSEL R/W 0 THDET R 0 SMUTE R/W 0 0 R 0 MSBS R/W 0 BCKP R/W 0 DIF1 R/W 1 DIF0 R/W 0 DIF2-0: Audio Interface Format (Table 19) Default: “10” (MSB justified) BCKP: BICK Polarity at DSP Mode (Table 20) “0”: SDTO is output by the rising edge (“”) of BICK and SDTI is latched by the falling edge (“”). (default) “1”: SDTO is output by the falling edge (“”) of BICK and SDTI is latched by the rising edge (“”). MSBS: FCK Phase at DSP Mode (Table 20) “0”: The rising edge (“”) of FCK is half clock of BICK before the channel change. (default) “1”: The rising edge (“”) of FCK is one clock of BICK before the channel change. SMUTE: Soft Mute Control 0: Normal Operation (default) 1: DAC outputs soft-muted THDET: Thermal Shutdown Detection Result 0: Normal Operation (default) 1: During Thermal Shutdown TSDSEL: Thermal Shutdown Mode Select 0: Automatic Power up (default) 1: Manual Power up 015010680-E-00 2015/09 - 73 - [AK4637] Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H Digital MIC R/W Default 0 R 0 0 R 0 0 R 0 PMDM R/W 0 DCLKE R/W 0 0 R 0 DCLKP R/W 0 DMIC R/W 0 DMIC: Digital Microphone Connection Select 0: Analog Microphone (default) 1: Digital Microphone DCLKP: Data Latching Edge Select 0: Data is latched on the DMCLK rising edge (“”). (default) 1: Data is latched on the DMCLK falling edge (“”). DCLKE: DMCLK pin Output Clock Control 0: “L” Output (default) 1: 64fs Output PMDM: Input Signal Select with Digital Microphone 0: OFF (default) 1: ON ADC digital block is powered-down by PMDM bit = “0” when selecting a digital microphone input (DMIC bit = “1”). Addr Register Name 09H Timer Select R/W Default D7 D6 ADRST1 ADRST0 R/W R/W 0 0 D5 D4 D3 D2 D1 D0 FRATT R/W 0 FRN R/W 0 0 R 0 0 R 0 0 R 0 DVTM R/W 0 DVTM: Output Digital Volume Soft Transition Time Setting (Table 44) 0: 816/fs (default) 1: 204/fs This is the transition time between DVOL7-0 bits = 00H and CCH. FRN: ALC Fast Recovery Function Enable 0: Enable (default) 1: Disable RFATT: Fast Recovery Reference Volume Attenuation Amount (Table 35) 0: -0.00106dB (4/fs) (default) 1: -0.00106dB (16/fs) ADRST1-0: ADC Initialization Cycle Setting (Table 18) Default: “00” (1059/fs) 015010680-E-00 2015/09 - 74 - [AK4637] Addr 0AH Register Name ALC Timer Select R/W Default D7 0 D6 IVTM D5 EQFC1 D4 EQFC0 D3 WTM1 D2 WTM0 D1 RFST1 D0 RFST0 R 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RFST1-0: ALC First Recovery Speed (Table 34) Default: “00” (0.0032dB) WTM1-0: ALC Recovery Waiting Period (Table 31) Default: “00” (128/fs) EQFC1-0: ALCEQ Frequency Setting (Table 28) Default: “10” (Extreme value=150Hz, Zero point=100Hz @ fs = 48kHz) IVTM: Input Digital Volume Soft Transition Time Setting (Table 40) 0: 236/fs 1: 944/fs (default) A transition time when changing IVOL7-0 bits to F1H from 05H. Addr Register Name 0BH ALC Mode Control 1 R/W Default D7 D6 D5 D4 D3 D2 D1 D0 ALCEQN R/W 0 LMTH2 R/W 0 ALC R/W 0 RGAIN2 R/W 0 RGAIN1 R/W 0 RGAIN0 R/W 0 LMTH1 R/W 0 LMTH0 R/W 0 LMTH2-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 29) Default: “000” RGAIN2-0: ALC Recovery Gain Step (Table 32) Default: “000” (0.00424dB) ALC: ALC Enable 0: ALC Disable (default) 1: ALC Enable ALCEQN: ALC EQ Enable 0: ALC EQ On (default) 1: ALC EQ Off Addr Register Name 0CH ALC Mode Control 2 R/W Default D7 D6 D5 D4 D3 D2 D1 D0 REF7 R/W 1 REF6 R/W 1 REF5 R/W 1 REF4 R/W 0 REF3 R/W 0 REF2 R/W 0 REF1 R/W 0 REF0 R/W 1 REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 33) Default: “E1H” (+30.0dB) 015010680-E-00 2015/09 - 75 - [AK4637] Addr Register Name 0DH Input Volume Control R/W Default D7 D6 D5 D4 D3 D2 D1 D0 IVOL7 R/W 1 IVOL6 R/W 1 IVOL5 R/W 1 IVOL4 R/W 0 IVOL3 R/W 0 IVOL2 R/W 0 IVOL1 R/W 0 IVOL0 R/W 1 IVOL7-0: Digital Input Volume; 0.375dB step, 242 Level (Table 39) Default: “E1H” (+30.0dB) Addr Register Name 0EH ALC Volume R/W Default D7 D6 D5 D4 D3 D2 D1 D0 VOL7 R - VOL6 R - VOL5 R - VOL4 R - VOL3 R - VOL2 R - VOL1 R - VOL0 R - VOL7-0: Current ALC volume value; 0.375dB step, 242 Level. Read operation only. (Table 36) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH Beep Control R/W Default 0 R 0 BPVCM R/W 0 BEEPS R/W 0 0 R 0 BPLVL3 R/W 0 BPLVL2 R/W 0 BPLVL1 R/W 0 BPLVL0 R/W 0 BPLVL3-0:BEEP Output Level Setting (Table 45) Default: “0000” (0dB) BEEPS: Signal Switch Control from the BEEP pin to Speaker Amplifier 0: OFF (default) 1: ON BPVCM: Common Voltage Setting of BEEP Input Amplifier (Table 46) 0: 1.15V (default) 1: 1.65V Addr Register Name 10H Digital Volume Control R/W Default D7 D6 D5 D4 D3 D2 D1 D0 DVOL7 R/W 0 DVOL6 R/W 0 DVOL5 R/W 0 DVOL4 R/W 1 DVOL3 R/W 1 DVOL2 R/W 0 DVOL1 R/W 0 DVOL0 R/W 0 DVOL7-0: Digital Output Volume (Table 43) Default: “18H” (0dB) 015010680-E-00 2015/09 - 76 - [AK4637] Addr Register Name 11H EQ Common Gain Select R/W Default D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 EQC5 EQC4 EQC3 EQC2 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 D2 EQ2G0 EQ3G0 EQ4G0 EQ5G0 R/W 0 D1 EQ2T1 EQ3T1 EQ4T1 EQ5T1 R/W 0 D0 EQ2T0 EQ3T0 EQ4T0 EQ5T0 R/W 0 EQC2: Equalizer 2 Common Gain Selector 0: Disable (default) 1: Enable When EQC2 bit = “1”, the common gain setting (EQ2G) is reflected. EQC3: Equalizer 3 Common Gain Selector 0: Disable (default) 1: Enable When EQC3 bit = “1”, the common gain setting (EQ3G) is reflected. EQC4: Equalizer 4 Common Gain Selector 0: Disable (default) 1: Enable When EQC4 bit = “1”, the common gain setting (EQ4G) is reflected. EQC5: Equalizer 5 Common Gain Selector 0: Disable (default) 1: Enable When EQC5 bit = “1”, the common gain setting (EQ5G) is reflected. Addr 12H 13H 14H 15H Register Name EQ2 Gain Setting EQ3 Gain Setting EQ4 Gain Setting EQ5 Gain Setting R/W Default D7 EQ2G5 EQ3G5 EQ4G5 EQ5G5 R/W 0 D6 EQ2G4 EQ3G4 EQ4G4 EQ5G4 R/W 0 D5 EQ2G3 EQ3G3 EQ4G3 EQ5G3 R/W 0 D4 EQ2G2 EQ3G2 EQ4G2 EQ5G2 R/W 0 D3 EQ2G1 EQ3G1 EQ4G1 EQ5G1 R/W 0 EQ2T1-0, EQ3T1-0, EQ4T1-0, EQ5T1-0: Transition Time of EQ2~EQ5 Gain (Table 27) Default: “00H” (256/fs) EQ2G5-0, EQ3G5-0, EQ4G5-0, EQ5G5-0: Gain setting of EQ2~EQ5 (Table 26) Default: “00H” (Mute) 015010680-E-00 2015/09 - 77 - [AK4637] Addr 16H Register Name Digital Filter Select 1 R/W Default D7 0 D6 0 D5 0 D4 0 D3 0 D2 HPFC1 D1 HPFC0 D0 HPFAD R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 1 HPFAD: HPF1 Control after ADC 0: OFF 1: ON (default) When HPFAD bit is “1”, the settings of HPFC1-0 bits are enabled. When HPFAD bit is “0”, the audio data passes the HPFAD block by 0dB gain. When PMADC bit = “1”, set HPFAD bit to “1”. HPFC1-0: Cut-off Frequency Setting of HPF1 (ADC) (Table 25) Default: “00” (3.7Hz @ fs = 48kHz) Addr 17H Register Name Digital Filter Select 2 R/W Default D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 LPF D0 HPF R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 HPF: HPF2 Coefficient Setting Enable 0: OFF (default) 1: ON When HPF bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPF bit is “0”, the audio data passes the HPF2 block by is 0dB gain. LPF: LPF Coefficient Setting Enable 0: OFF (default) 1: ON When LPF bit is “1”, the settings of F2A13-0 and F2B13-0 bits are enabled. When LPF bit is “0”, the audio data passes the LPF block by 0dB gain. Addr Register Name D7 D6 18H Digital Filter Mode R/W Default 0 R 0 0 R 0 D5 D4 D3 PFVOL1 PFVOL0 PFDAC1 R/W R/W R/W 0 0 0 D2 D1 D0 PFDAC0 R/W 0 ADCPF R/W 1 PFSDO R/W 1 PFSDO: SDTO Output Signal Select 0: ADC (+ 1st order HPF) Output 1: Programmable Filter / ALC Output (default) ADCPF: Programmable Filter / ALC Input Signal Select 0: SDTI 1: ADC Output (default) PFDAC1-0: DAC Input Signal Select (Table 42) Default: 00 (SDTI) PFVOL1-0: Sidetone Digital Volume (Table 41) Default: 00 (0dB) 015010680-E-00 2015/09 - 78 - [AK4637] Addr Register Name 19H 1AH 1BH 1CH HPF2 Co-efficient 0 HPF2 Co-efficient 1 HPF2 Co-efficient 2 HPF2 Co-efficient 3 R/W Default D7 D6 D5 D4 D3 D2 D1 D0 F1A7 0 F1B7 0 F1A6 0 F1B6 0 F1A5 F1A13 F1B5 F1B13 F1A4 F1A12 F1B4 F1B12 F1A3 F1A11 F1B3 F1B11 F1A2 F1A10 F1B2 F1B10 F1A1 F1A9 F1B1 F1B9 F1A0 F1A8 F1B0 F1B8 R/W R/W R/W R/W R/W R/W R/W F1A13-0 bits = 0x1FB0, F1B13-0 bits = 0x209F R/W F1A13-0, F1B13-0: HPF2 Coefficient (14bit x 2) Default: F1A13-0 bits = 0x1FB0, F1B13-0 bits = 0x209F (fc = 150Hz@fs=48kHz) Addr Register Name 1DH 1EH 1FH 20H LPF Co-efficient 0 LPF Co-efficient 1 LPF Co-efficient 2 LPF Co-efficient 3 R/W Default D7 D6 D5 D4 D3 D2 D1 D0 F2A7 0 F2B7 0 F2A6 0 F2B6 0 F2A5 F2A13 F2B5 F2B13 F2A4 F2A12 F2B4 F2B12 F2A3 F2A11 F2B3 F2B11 F2A2 F2A10 F2B2 F2B10 F2A1 F2A9 F2B1 F2B9 F2A0 F2A8 F2B0 F2B8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 F2A13-0, F2B13-0: LPF Coefficient (14bit x 2) Default: “0000H” 015010680-E-00 2015/09 - 79 - [AK4637] Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 21H Digital Filter Select 3 R/W Default 0 R 0 0 R 0 0 R 0 EQ5 R/W 0 EQ4 R/W 0 EQ3 R/W 0 EQ2 R/W 0 EQ1 R/W 0 EQ1: Equalizer 1 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ1 bit is “1”, the settings of E1A15-0, E1B15-0 and E1C15-0 bits are enabled. When EQ1 bit is “0”, the audio data passes the EQ1 block by 0dB gain. EQ2: Equalizer 2 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ2 bit is “1”, the settings of E2A15-0, E2B15-0 and E2C15-0 bits are enabled. When EQ2 bit is “0”, the audio data passes the EQ2 block by 0dB gain. EQ3: Equalizer 3 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ3 bit is “1”, the settings of E3A15-0, E3B15-0 and E3C15-0 bits are enabled. When EQ3 bit is “0”, the audio data passes the EQ3 block by 0dB gain. EQ4: Equalizer 4 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ4 bit is “1”, the settings of E4A15-0, E4B15-0 and E4C15-0 bits are enabled. When EQ4 bit is “0”, the audio data passes the EQ4 block by 0dB gain. EQ5: Equalizer 5 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ5 bit is “1”, the settings of E5A15-0, E5B15-0 and E5C15-0 bits are enabled. When EQ5 bit is “0”, the audio data passes the EQ5 block by 0dB gain. 015010680-E-00 2015/09 - 80 - [AK4637] Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH E1 Co-efficient 0 E1 Co-efficient 1 E1 Co-efficient 2 E1 Co-efficient 3 E1 Co-efficient 4 E1 Co-efficient 5 E2 Co-efficient 0 E2 Co-efficient 1 E2 Co-efficient 2 E2 Co-efficient 3 E2 Co-efficient 4 E2 Co-efficient 5 E3 Co-efficient 0 E3 Co-efficient 1 E3 Co-efficient 2 E3 Co-efficient 3 E3 Co-efficient 4 E3 Co-efficient 5 E4 Co-efficient 0 E4 Co-efficient 1 E4 Co-efficient 2 E4 Co-efficient 3 E4 Co-efficient 4 E4 Co-efficient 5 E5 Co-efficient 0 E5 Co-efficient 1 E5 Co-efficient 2 E5 Co-efficient 3 E5 Co-efficient 4 E5 Co-efficient 5 E1A7 E1A15 E1B7 E1B15 E1C7 E1C15 E2A7 E2A15 E2B7 E2B15 E2C7 E2C15 E3A7 E3A15 E3B7 E3B15 E3C7 E3C15 E4A7 E4A15 E4B7 E4B15 E4C7 E4C15 E5A7 E5A15 E5B7 E5B15 E5C7 E5C15 E1A6 E1A14 E1B6 E1B14 E1C6 E1C14 E2A6 E2A14 E2B6 E2B14 E2C6 E2C14 E3A6 E3A14 E3B6 E3B14 E3C6 E3C14 E4A6 E4A14 E4B6 E4B14 E4C6 E4C14 E5A6 E5A14 E5B6 E5B14 E5C6 E5C14 E1A5 E1A13 E1B5 E1B13 E1C5 E1C13 E2A5 E2A13 E2B5 E2B13 E2C5 E2C13 E3A5 E3A13 E3B5 E3B13 E3C5 E3C13 E4A5 E4A13 E4B5 E4B13 E4C5 E4C13 E5A5 E5A13 E5B5 E5B13 E5C5 E5C13 E1A4 E1A12 E1B4 E1B12 E1C4 E1C12 E2A4 E2A12 E2B4 E2B12 E2C4 E2C12 E3A4 E3A12 E3B4 E3B12 E3C4 E3C12 E4A4 E4A12 E4B4 E4B12 E4C4 E4C12 E5A4 E5A12 E5B4 E5B12 E5C4 E5C12 E1A3 E1A11 E1B3 E1B11 E1C3 E1C11 E2A3 E2A11 E2B3 E2B11 E2C3 E2C11 E3A3 E3A11 E3B3 E3B11 E3C3 E3C11 E4A3 E4A11 E4B3 E4B11 E4C3 E4C11 E5A3 E5A11 E5B3 E5B11 E5C3 E5C11 E1A2 E1A10 E1B2 E1B10 E1C2 E1C10 E2A2 E2A10 E2B2 E2B10 E2C2 E2C10 E3A2 E3A10 E3B2 E3B10 E3C2 E3C10 E4A2 E4A10 E4B2 E4B10 E4C2 E4C10 E5A2 E5A10 E5B2 E5B10 E5C2 E5C10 E1A1 E1A9 E1B1 E1B9 E1C1 E1C9 E2A1 E2A9 E2B1 E2B9 E2C1 E2C9 E3A1 E3A9 E3B1 E3B9 E3C1 E3C9 E4A1 E4A9 E4B1 E4B9 E4C1 E4C9 E5A1 E5A9 E5B1 E5B9 E5C1 E5C9 E1A0 E1A8 E1B0 E1B8 E1C0 E1C8 E2A0 E2A8 E2B0 E2B8 E2C0 E2C8 E3A0 E3A8 E3B0 E3B8 E3C0 E3C8 E4A0 E4A8 E4B0 E4B8 E4C0 E4C8 E5A0 E5A8 E5B0 E5B8 E5C0 E5C8 R/W Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3) Default: “0000H” E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3) Default: “0000H” E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3) Default: “0000H” E4A15-0, E4B15-0, E4C15-0: Equalizer 4 Coefficient (16bit x3) Default: “0000H” E5A15-0, E5B15-0, E5C15-0: Equalizer 5 Coefficient (16bit x3) Default: “0000H” 015010680-E-00 2015/09 - 81 - [AK4637] 10. Recommended External Circuits Figure 65 shows the system connection diagram. An evaluation board (AKD4637) is available for fast evaluation as well as suggestions for peripheral circuitry. Analog Ground Digital Ground Speaker Power Supply 1.6  1.98V 10u 0.1u 16 VSS1 2.2u or 4.7u 17 VCOM DVD 11 D VSS2 12 SPN/NC 13 SPP/AOUT 14 0.1u 10u AVDD 15 Power Supply 2.8  5.5V AK4637 2.2u 18 REGFIL TVDD 10 MCKI 9 BICK 8 FCK 7 SDTO 6 Top View 19 MPWR C AIN/IN+ /DMDAT PDN SCL SDA SDTI 2 3 4 5 2.2k 20 /DMCLK 1 BEEP/IN- Beep In 0.1u 10u Power Supply 1.6  3.6V DSP C Internal MIC P Notes: - VSS1 and VSS2 of the AK4637 must be distributed separately from the ground of external controllers. - All digital input pins must not be allowed to float. - When the AK4637 is used in master mode, FCK pin is floating before M/S bit is changed to “1”. Therefore, a pull-up or pull-down resistor around 100k must be connected to FCK pin of the AK4637. - The pull-up resistors of the SCL and SDA pins must be connected to a voltage in the range from TVDD or more to 6V or less. - 0.1μF capacitors at power supply pins. Other capacitors do not have specific types. Figure 65. System Connection Diagram 015010680-E-00 2015/09 - 82 - [AK4637] 1. Grounding and Power Supply Decoupling The AK4637 requires careful attention to power supply and grounding arrangements. AVDD is usually supplied from the system’s analog supply, and DVDD and TVDD are supplied from the system’s digital power supply. If AVDD, DVDD and TVDD are supplied separately, the power-up sequence is not critical. The PDN pin should be held “L” when power supplies are tuning on. The PDN pin is allowed to be “H” after all power supplies are applied and settled. To avoid pop noise on line output when power up/down, the AK4637 should be operated along the following recommended power-up/down sequence. 1) Power-up - The PDN pin should be held “L” when power supplies are turning on. The AK4637 can be reset by keeping the PDN pin “L” for 200ns or longer after all power supplies are applied and settled. 2) Power-down - Each of power supplies can be powered OFF after the PDN pin is set to “L”. VSS1 and VSS2 of the AK4637 should be connected to the analog ground plane. System analog ground and digital ground should be wired separately and connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close the power supply pins as possible. Especially, the small value ceramic capacitor is to be closest. 2. Internal Regulated Voltage Power Supply REGFIL is a power supply of the analog circuit (typ. 2.3V). A 2.2F ±10% capacitor attached to the VSS1 pin eliminates the effects of high frequency noise. This capacitor should be placed as near as possible to the AK4637. No load current may be drawn from the REGFIL pin. All digital signals, especially clocks, should be kept away from the REGFIL pin in order to avoid unwanted coupling into the AK4637. 3. Reference Voltage VCOM is a signal ground of this chip. A 2.2F ±10%(AVDD ≤ 3.6V) or 4.7μF±10%(AVDD > 3.6V) capacitor attached to the VSS1 pin eliminates the effects of high frequency noise. This capacitor should be placed as near as possible to the AK4637. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4637. Attention must be paid to the printing pattern and the material of the capacitors to prevent superimposed noises and voltage drops since the VCOM voltage is the reference of many functions. 4. Analog Inputs The microphone and line inputs support single-ended or full-differential format. When single-ended input, the input signal range scales with nominally at typ. 2.07Vpp (@ MGAIN = 0dB), centered around the internal signal ground (typ. 1.15V). Usually the input signal is AC coupled with a capacitor. The cut-off frequency is fc = 1/(2RC). 5. Analog Outputs The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit data). The speaker amplifier (SPP and SPN pins) is BTL output, and they should be connected directly to a speaker. There is no need for AC coupling capacitors. The monaural line output (AOUT pin) is single-ended and centered on 1.5V (LVCM0 bit = “1”: default). This pin must be AC-coupled using a capacitor. 015010680-E-00 2015/09 - 83 - [AK4637] 11. Control Sequence ■ Clock Set Up When ADC, DAC or Programmable Filter is powered-up, the clocks must be supplied. Turn off the power management bits first when switching the master clock. The power management bits should be turned on after the master clock is stabilized. 1. PLL Master Mode Example: Audio I/F Format: I2S Compatible (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 12MHz Sampling Frequency: 48kHz Power Supply (1) (1) Power Supply & PDN pin = “L”  “H” PDN pin (2) (3) PMVCM bit (2)Dummy Command Addr:01H, Data:08H Addr:05H, Data:62H Addr:06H, Data:0BH Addr:07H, Data:03H (Addr:00H, D6) >2.0ms PMPLL bit (Addr:01H, D2) MCKI pin (4) Input (3)Addr:00H, Data:40H M/S bit (Addr:01H, D3) 5ms (max) (5) BICK pin FCK pin (4)Addr:01H, Data:0CH Output BICK and FCK output Figure 66. Clock Set Up Sequence (1) (1) After Power Up: PDN pin “L” → “H” “L” time of 200ns or more is needed to reset the AK4637. (2) After Dummy Command (Addr:00H, Data:00H) input, M/S, PLL3-0, BCKO1-0, FS3-0, MSBS, BCKP and DIF1-0 bits must be set during this period. (3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1” VCOM and Regulator must first be powered-up before the other block operates. Power up time is 2.0ms (max) when the capacitance of an external capacitor for the VCOM is 2.2μF (AVDD ≤ 3.6V), 4.7μF(AVDD > 3.6V) and the REGFIL pin is 2.2μF. (4) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source, and PLL lock time is 5ms (max) (5) The AK4637 starts to output the BICK and FCK clocks after the PLL became stable. Then normal operation starts. 015010680-E-00 2015/09 - 84 - [AK4637] 2. PLL Slave Mode (BICK pin) Example: Audio I/F Format : I2S Compatible (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 48kHz Power Supply (1) (1) Power Supply & PDN pin = “L”  “H” PDN pin (2) (3) PMVCM bit (Addr:00H, D6) (2) Dummy Command Addr:05H, Data:30H Addr:06H, Data:0BH Addr:07H, Data:03H >2.0ms PMPLL bit (Addr:01H, D2) (4) FCK pin BICK pin Input (3) Addr:00H, Data:40H 2m (max) Internal Clock (4) Addr:01H, Data:04H (5) Figure 67. Clock Set Up Sequence (2) (1) After Power Up: PDN pin “L” → “H” “L” time of 200ns or more is needed to reset the AK4637. (2) After Dummy Command (Addr:00H, Data:00H) input, DIF1-0, PLL3-0, and FS3-0 bits must be set during this period. (3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1” VCOM and Regulator must first be powered-up before the other block operates. Power up time is 2.0ms (max) when the capacitance of an external capacitor for the VCOM is 2.2μF (AVDD ≤ 3.6V), 4.7μF(AVDD > 3.6V) and the REGFIL pin is 2.2μF. (4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (BICK pin) is supplied. PLL lock time is 2ms (max) when BICK is a PLL reference clock. (5) Normal operation starts after that the PLL is locked. 015010680-E-00 2015/09 - 85 - [AK4637] 3. EXT Slave Mode Example: : Audio I/F Format: I2S Compatible (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 4 8kHz Power Supply (1) Power Supply & PDN pin = “L”  “H” (1) PDN pin (2) PMVCM bit (3) (2)Dummy Command Addr:05H, Data:00H Addr:06H, D3-2 bits = “10” Addr:07H, Data:03H (Addr:00H, D6) (4) MCKI pin Input (4) (3) Addr:00H, Data:40H FCK pin BICK pin Input MCKI, BICK and FCK input Figure 68. Clock Set Up Sequence (3) (1) After Power Up: PDN pin “L” → “H” “L” time of 200ns or more is needed to reset the AK4637. (2) After Dummy Command (Addr:00H, Data:00H) input, CM1-0, FS3-2, MSBS,BCKP and DIF1-0 bits must be set during this period. (3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1” VCOM and Regulator must first be powered-up before the other block operates. Power up time is 2.0ms (max) when the capacitance of an external capacitor for the VCOM is 2.2μF (AVDD ≤ 3.6V), 4.7μF(AVDD > 3.6V) and the REGFIL pin is 2.2μF. (4) Normal operation starts after the MCKI, FCK and BICK are supplied. 4. EXT Master Mode Example: : Audio I/F Format: I2S Compatible (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 4 8kHz BCKO: 64fs Power Supply (1) Power Supply & PDN pin = “L”  “H” (1) PDN pin (2) MCKI input (4) PMVCM bit (Addr:00H, D6) (3)Dummy Command Addr:01H, Data:08H Addr:05H, Data:02H Addr:06H, D3-2 bits = “10” Addr:07H, Data:03H (2) MCKI pin Input (3) M/S bit (Addr:01H, D3) FCK pin BICK pin BICK and FCK output Output (4) Addr:00H, Data:40H Figure 69. Clock Set Up Sequence (4) (1) After Power Up: PDN pin “L” → “H” “L” time of 200ns or more is needed to reset the AK4637. (2) MCKI is supplied. (3) After Dummy Command (Addr:00H, Data:00H) input, BCKO1-0, CM1-0, FS3-2, MSBS,BCKP and DIF1-0 bits are set. M/S bit should be set to “1”. Then FCK and BICK are output. (4) Power Up VCOM and Regulator: PMVCM bit = “0” → “1” VCOM and Regulator must first be powered-up before the other block operates. Power up time is 2.0ms (max) when both capacitances of an external capacitor for the VCOM is 2.2μF (AVDD ≤ 3.6V), 4.7μF(AVDD > 3.6V) and REGFIL pins are 2.2μF. 015010680-E-00 2015/09 - 86 - [AK4637] ■ Microphone Input Recording FS3-0 bits (Addr:06H, D3-0) 1011 Example: 1011 PLL Master Mode Audio I/F Format: I2S Compatible MIC Amp: +18dB MIC Power: ON Sampling Frequency: 48kHz ALC setting: Refer to Table 37 HPF1: fc=3.7Hz, ADRST1-0 bits = “00” (1) MGAIN3-0 bits 0,110,0 PMMP bit (Addr:02H, D6,D2-0, D3) Signal Select (Addr:03H, D3) Timer Select (Addr:09H) 0,110, 1 (2) 0 0 (1) Addr:06H, Data:0BH (3) 00H (2) Addr:02H, Data:0EH 00H (4) ALC Setting (Addr:0AH, 0BH ) (3) Addr:03H, Data:00H 60H,00H 6CH,2EH 6CH,0EH (13) (5) REF7-0 bits (Addr:0CH) IVOL7-0 bits (Addr:0DH) Filter Select (Addr:16H,17H,21H) Digital Filter Path (Addr:18H) Filter Co-efficient (Addr:19H-20H, 22H-3FH) ALC State E1H E1H (5) Addr:0AH, Data:6CH Addr:0BH, Data:2EH (6) E1H (4) Addr:09H, Data:00H E1H (6) Addr:0CH, Data:E1H (7) 01H,00H,00H 01H, xxH,xxH (7) Addr:0DH, Data:E1H 03H (8) Addr:16H, Data:01H Addr:17H, Data:xxH Addr:21H, Data:xxH (8) 03H (9) xxH (9) Addr:18H, Data:03H xxH (10) ALC Disable ALC Enable ALC Disable PMPFIL bit PMADC bit (10) Addr:19H-20H,Data:xxH Addr:22H-3FH, Data:xxH (11) Addr:00H, Data:C1H (Addr:00H, D7, D0) (11) SDTO pin State 0 data Output (12) 1059/fs Initialize Normal Data Output Recording (12) Addr:00H, Data:40H 0 data output (13) Addr:0BH, Data:0EH Figure 70. Microphone Input Recording Sequence This sequence is an example of ALC setting at fs= 48kHz. For changing the parameter of ALC, please refer to Table 37. At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4637 is in PLL mode, Microphone, ADC and Programmable Filter of (12) must be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up Microphone Amp and Microphone Power. (Addr = 02H) (3) Set up Input Signal. (Addr = 03H) (4) Set up FRN, FRATT and ADRST1-0 bits (Addr = 09H) (5) Set up ALC mode. (Addr = 0AH, 0BH) (6) Set up REF value at ALC (Addtr = 0CH) (7) Set up IVOL value at ALC operation start (Addr = 0DH) (8) Programmable Filter ON/OFF Setting (Addr: 16H, 17H, 21H) (9) Set up Programmable Filter Path: PFSDO bit = ADCPF bit = “1” (Addr = 18H) (10) Set up Coefficient Programmable Filter (Addr: 19H ~ 20H, 22H ~ 3FH) (11) Power Up Microphone Amp, ADC and Programmable Filter: PMADC =PMPFIL bits = “0” → “1” The initialization cycle time of ADC is 1059/fs=22ms @ fs=48kHz, ADRST1-0 bit = “00”. ADC outputs “0” data during the initialization cycle. After the ALC bit is set to “1”, the ALC operation starts from IVOL value of (7). (12) Power Down Microphone Amp, ADC and Programmable Filter: PMADC = PMPFIL bits = “1” → “0” (13) ALC Disable: ALC bit = “1” → “0” 015010680-E-00 2015/09 - 87 - [AK4637] ■ Digital Microphone Input Example: FS3-0 bits (Addr:06H, D3-0) PLL Master Mode Audio I/F Format: I2S Compatible Sampling Frequency: 48kHz Digital MIC setting: Data is latched on the DMCLK falling edge. ALC setting: Refer to Table 37 HPF1: fc=3.7Hz, ADRST1-0 bits = “00” 1011 1011 (1) Timer Select 00H (Addr:09H) 00H (1) Addr:06H, Data:0BH (2) ALC Setting 60H,00H (Addr:0AH, 0BH) 6CH,2EH REF7-0 bits E1H (Addr:0CH) 6CH,0EH (2) Addr:09H, Data:00H (13) (3) (3) Addr:0AH, Data:6CH Addr:0BH, Data:2EH E1H (4) (4) Addr:0CH, Data:E1H IVOL7-0 bits E1H (Addr:0DH) E1H (5) Addr:0DH, Data:E1H (5) Filter Select 01H,00H,00H (Addr:16H,17H,21H) 01H,xxH,xxH (6) Addr:16H, Data:01H Addr:17H, Data:xxH Addr:21H, Data:xxH (6) Digital Filter Path (Addr:18H) 03H 03H (7) Filter Co-efficient (Addr:19H-20H,22H-3FH) ALC State (7) Addr:18H, Data:03H xxH xxH (8) Addr:19H-20H, Data:xxH Addr:22H-3FH, Data:xxH (8) ALC Disable ALC Enable ALC Disable (9) Addr:00H, Data:C0H PMPFIL bit (10) Addr:08H, Data:11H (Addr:00H, D5) (9) Digital MIC (Addr:08H) (12) Recording 00H 11H 00H (11) Addr:08H, Data:00H 1059/fs (10) SDTO pin State 0 data output (11) Normal Data ouput (12) Addr:00H, Data:40H 0 data output (13) Addr:0BH, Data:0DH Figure 71. Digital Microphone Input Recording Sequence This sequence is an example of ALC setting at fs=48kHz. For changing the parameter of ALC, please refer to Table 37. At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4637 is PLL mode, Digital Microphone of (11) and Programmable Filter of (10) must be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up FRN, FRATT and ADRST1-0 bits (Addr = 09H) (3) Set up ALC mode. (Addr = 0AH, 0BH) (4) Set up REF value for ALC (Addtr = 0CH) (5) Set up IVOL value at ALC operation start (Addr = 0DH) (6) Set up Programmable Filter ON/OFF (Addr = 16H, 17H, 21H) (7) Set up Programmable Filter Path: PFSDO bit = ADCPF bit = “1” (Addr = 18H) (8) Set up Coefficient of Programmable Filter (Addr:19H ~ 20H, 22H ~ 3FH) (9) Power Up Programmable Filter: PMPFIL bit = “0” → “1” (10) Set Up & Power Up Digital Microphone: DMIC = PMDM bits = “0” → “1” The initialization cycle time of ADC is 1059/fs=22ms@ fs=48kHz, ADRST1-0 bit = “00”. ADC outputs “0” data during initialization cycle. After the ALC bit is set to “1”, the ALC operation starts from IVOL value of (5). (11) Power Down Digital Microphone: PMDM bit = “1” → “0” (12) Power Down Programmable Filter: PMPFIL bit = “1” → “0” (13) ALC Disable: ALC bit = “1” → “0” 015010680-E-00 2015/09 - 88 - [AK4637] ■ Speaker Amplifier Output FS3-0 bits (Addr:06H, D3-0) 1011 Example: 1011 PLL Master Mode Audio I/F Format: I2S Compatible Sampling Frequency: 48KHz Output Digital Volume: 0dB ALC setting: Refer to Table 38 Programmable Filter OFF (1) (14) DACS bit (1) Addr:06H, Data:0BH (Addr:02H, D5) (2) SPKG1-0 bits (Addr:03H, D7-6) Timer Select (Addr:09H) 00 (2) Addr:02H, Data:20H 01 (3) (3) Addr:03H, Data:40H 00H 00H (4) ALC Setting (Addr:0AH, 0BH) REF7-0 bitsl (Addr:0CH) (4) Addr:09H, Data:00H 60H, 00H 6CH, 2EH (5) (5) Addr:0AH, Data:6CH Addr:0BH, Data:2EH E1H A1H (6) IVOL7-0 bits (Addr:0DH) (6) Addr:0CH, Data:A1H E1H 91H (7) Addr:0DH, Data:91H (7) DVOL7-0 bits (Addr:10H) 18H 18H (8) Addr:10H, Data:18H 04H (9) Addr:18H, Data:04H (8) Digital Filter Path (Addr:18H) 03H (9) (10) Addr:00H, Data:C4H ALC State ALC Disable ALC Enable ALC Disable (11) Addr:01H, Data:0EH (16) (10) PMPFIL bit PMDAC bit (12) Addr:02H, Data:A0H (Addr:00H, D2) (11) PMSL bit Playback (Addr:01H, D1) > 1 ms SLPSN bit (12) (13) (15) (13) Addr:02H, Data:20H (Addr:02H, D7) (14) Addr:02H, Data:00H SPP pin Hi-Z Normal Output Hi-Z SPN pin AVDD/2 Normal Output AVDD/2 (15) Addr:01H, Data:0CH Hi-Z Hi-Z (16) Addr:00H, Data:40H Figure 72. Speaker-Amp Output Sequence At first, clocks must be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4637 is in PLL mode, DAC, Programmable Filter and Speaker-Amp of (10) must be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of DAC → SPK-Amp: DACS bit = “0” → “1” (Addr = 02H) (3) SPK-Amp gain setting: SPKG1-0 bits = “00” → “01” (Addr = 03H) (4) Set up FRN, FRATT and ADRST1-0 bits (Addr = 09H) (5) Set up ALC mode (Addr = 0AH, 0BH) (6) Set up REF value of ALC (Addr = 0CH) (7) Set up IVOL value of ALC operation start (Addr = 0DH) (8) Set up the output digital volume. (Addr = 10H) (9) Set up Programmable Filter Path: PFDAC1-0 bits=“01”, PFSDO=ADCPF bits=“0” (Addr = 18H) (10) Power up DAC and Programmable Filter: PMDAC=PMPFIL bits=“0”→“1” (Addr = 00H) (11) Power up Speaker-Amp: PMSL bit=“0”→“1” (Addr = 01H) (12) Exit the power-save mode of Speaker-Amp: SLPSN bit = “0” → “1” (Addr = 02H) (13) Enter Speaker-Amp Power Save Mode: SLPSN bit = “1” → “0” (Addr = 02H) (14) Disable the path of DAC → SPK-Amp: DACS bit = “1” → “0” (Addr = 02H) (15) Power down Speaker-Amp: PMSL bit= “1”→“0” (Addr =01H) (16) Power down DAC and Programmable Filter: PMDAC=PMPFIL bits= “1”→“0” (Addr = 00H) 015010680-E-00 2015/09 - 89 - [AK4637] ■ Beep Signal Output from Speaker Amplifier Example: SPKGain = +6.4dB (SPKG1-0 bits = “00”) PMVCM bit (Addr:00H, D6) (1) Addr:00H, Data:60H Addr:01H, Data:02H PMBP bit (Addr:00H, D5) (1) (5) PMSL bit (2) Addr:0FH, D5 bit = “1” (Addr:01H, D1) (2) (6) BEEPS bit (Addr:0FH, D5) (3) Addr:02H, Data:84H (3) BEEP Signal Output SLPSN bit (Addr:02H, D7) (4) SPP pin Hi-Z Normal Output (4) Addr:02H, Data:04H Hi-Z (5) Addr:00H, Data:40H SPN pin Hi-Z AVDD/2 Normal Output AVDD/2 Hi-Z (6) Addr:03H, Data:00H Figure 73. “BEEP-Amp → Speaker-Amp” Output Sequence Clock input is not necessary when the AK4637 is operating only on the path of “BEEP-Amp” → “SPK-Amp”. (1) Power up VCOM, MIN-Amp and Speaker: PMVCM = PMBP = PMSL bits = “0” → “1” (2) Set up the path of BEEP  SPK-Amp: BEEPS bit = “0” → “1” (3) Exit the power save mode of Speaker-Amp: SLPSN bit = “0” → “1” Period (3) should be set according to the time constant of a capacitor and a resistor that are connected to the BEEP pin. Pop noise may occur if the SPK-Amp output is enabled before the BEEP-Amp input is stabilized. The BEEP Amp is powered up after VCOM voltage rise. The maximum rise-up time of VCOM is 2msec. (4) Enter Speaker-Amp Power-save mode: SLPSN bit = “1” → “0” (5) Power Down BEEP-Amp and Speaker: PMBP = PMSL bits = “1” → “0” (6) Disable the path of BEEP  SPK-Amp: BEEPS bit = “1” → “0” 015010680-E-00 2015/09 - 90 - [AK4637] ■ Lineout Output Example: FS3-0 bits (Addr:06H, D3-0) 1011 1011 (1) (12) LOSEL bit (Addr:00H, D3) PLL Master Mode Audio I/F Format: I2S Compatible Sampling Frequency: 48KHz Output Digital Volume: 0dB Line Output Gain: +2dB Programmable Filter OFF (1) Addr:06H, Data:0BH (2) (3) (2) Addr:00H, Data:48H DACL bit (Addr:04H, D5) (3) Addr:04H, Data:60H LVCM1-0 bits (Addr:04H, D7-6) DVOL7-0 bits (Addr:10H) Digital Filter Path (Addr:18H) XX 01 18H 18H (4) Addr:10H, Data:18H (5) Addr:18H, Data:03H (4) (6) Addr:00H, Data:4CH XXH (7) Addr:01H, Data:0EH 03H (5) (11) (6) (8) Addr:02H, Data:86H PMDAC bit (Addr:00H, D2) (7) Playback (10) PMSL bit (9) Addr:02H, Data:06H (Addr:01H, D1) (8) (9) (10) Addr:01H, Data:0CH SLPSN bit (Addr:02H, D7) >300 ms AOUT pin >300 ms Normal Output (11) Addr:00H, Data:48H (12) Addr:04H, Data:40H Addr:00H, Data:40H Figure 74. Lineout Sequence At first, clocks must be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4637 is in PLL mode, DAC and Lineout Output of (6) must be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Enter Lineout Output Mode: LOSEL bit = “0”  “1” (Addr = 00H) (3) Set up the path of DAC  Lineout, and Lineout gain setting: DACL bit = “0”  “1”, LVCM1-0 bits = “xx”  “01” (Addr = 04H) (4) Set up the output digital volume. (Addr = 10H) (5) Set up Programmable Filter Path: PFDAC1-0 bit=“00”, PFSDO=ADCPF bits = “1” (Addr = 18H) (6) Power up DAC: PMDAC bit = “0”  “1” (Addr = 00H) (7) Power up Lineout Output: PMSL bit = “0”  “1” (Addr =01H) The AOUT pin starts rising after PMSL bit = “1”. The maximum rise-up time to 99% VCOM voltage is 300ms when C = 1F and RL=10k. (8) Exit the power-save mode of Lineout Output: SLPSN bit = “0”  “1” (Addr = 04H) SLPSN bit should be set after the AOUT pin is risen up. The AOUT pin starts to output sound data after SLPSN bit = “0”  “1”. (9) Enter Lineout Output Power Save Mode: SLPSN bit = “1”  “0” (Addr = 04H) (10) Power down Lineout Output: PMSL bit = “1”  “0” (Addr = 01H) (11) Power down DAC: PMDAC bit = “1”  “0” (Addr = 00H) The AOUT pin is powered down after PMSL bit = “0”. The maximum power down time to 1% VCOM voltage is 300ms. (12) Exit the path of DAC  Lineout: DACL bit = “1”  “0” (Addr = 04H) Exit Lineout Output Mode: LOSEL bit = “1”  “0” (Addr = 00H) DACL and LOSEL bits should be set after the AOUT pin is powered down. 015010680-E-00 2015/09 - 91 - [AK4637] ■ Stop of Clock When ADC, DAC or Programmable Filter is powered-up, the clocks must be supplied. 1. PLL Master Mode Example: Audio I/F Format: I2S Compatible (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 12MHz (1) PMPLL bit (Addr:01H, D2) (1) Addr:01H, Data:08H (2) External MCKI Input (2) Stop an external MCKI Figure 75. Clock Stopping Sequence (1) (1) Power down PLL: PMPLL bit = “1”  “0” (2) Stop an external master clock. 2. PLL Slave Mode (BICK pin) Example (1) PMPLL bit : I/F Format: I2S Compatible (ADC & DAC) Audio PLL Reference clock: BICK BICK frequency: 64fs (Addr:01H, D2) (2) External BICK Input (1) Addr:01H, Data:00H (2) External FCK Input (2) Stop the external clocks Figure 76. Clock Stopping Sequence (2) (1) Power down PLL: PMPLL bit = “1”  “0” (2) Stop an external master clock. 3. EXT Slave Mode (1) External MCKI Example :Audio I/F Format: I2S Compatible (ADC & DAC) Input Input MCKI frequency: 256fs (1) External BICK Input (1) Stop the external clocks (1) External FCK Input Figure 77. Clock Stopping Sequence (3) (1) Stop the external MCKI, BICK and FCK clocks. 015010680-E-00 2015/09 - 92 - [AK4637] 4. EXT Master Mode (1) External MCKI Example :Audio I/F Format: I2S Compatible (ADC & DAC) Input Input MCKI frequency: 256fs BICK Output "H" or "L" FCK Output "H" or "L" (1) Stop the external MCKI Figure 78. Clock Stopping Sequence (4) (1) Stop an external master clock. BICK and FCK are fixed to “H” or “L”. ■ Power Down Power supply current cannot be shut down by stopping clocks and setting PMVCM bit = “0”. Power supply current can be shut down (typ. 1A) by stopping clocks and setting the PDN pin = “L”. When the PDN pin = “L”, all registers are initialized. 015010680-E-00 2015/09 - 93 - [AK4637] 12. Package ■ Outline Dimensions 20-pin QFN (Unit: mm) C0.25 0.75 ± 0.05 B 16 20 1 15 A 10 3.00 ± 0.05 Exposed Pad 6 0~0.05 0.20 ± 0.05 0.07 M C A B (0.20) 0.40 0.30 ± 0.05 1.90 ± 0.10 (0.25) 3.00 ± 0.05 1.90 ± 0.10 0.05 C C Note. The exposed pad on the bottom surface of the package must be connected to the ground. ■ Material & Lead finish Package molding compound: Epoxy Resin, Halogen (Br and Cl) free Lead frame material: Cu Alloy Pin surface treatment: Solder (Pb free) plate ■ Marking 4637 XXXX 1 XXXX: Date code (4 digit) Pin #1 indication 015010680-E-00 2015/09 - 94 - [AK4637] 13. Ordering Guide 40  +85C 20-pin QFN (0.4mm pitch) Evaluation board for AK4637EN AK4637EN AKD4637EN 14. Revision History Date (Y/M/D) 15/09/30 Revision 00 Reason First Edition Page Contents 015010680-E-00 2015/09 - 95 - [AK4637] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 015010680-E-00 2015/09 - 96 -