AK4705VQ

[AK4705] AK4705 2ch 24bit DAC with AV SCART Switch GENERAL DESCRIPTION The AK4705 offers the ideal features for digital set-top-box systems. Using AKM's multi-bit architecture for its modulator, the AK4705 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4705 integrates a combination of SCF and CTF filters, removing the need for high cost external filters and increasing performance for systems with excessive clock jitter. The AK4705 also including the audio switches, volumes, video switches, video filters, etc. designed primarily for digital set-top-box systems. The AK4705 is offered in a space saving 48-pin LQFP package. FEATURES DAC † Sampling Rates Ranging from 32kHz to 50kHz † 64dB High Attenuation 8x FIR Digital Filter † 2nd Order Analog LPF † On Chip Buffer with Single-Ended Output † Digital De–Emphasis for 32k, 44.1k and 48kHz Sampling † I/F Format: 24bit MSB Justified, I2S, 18/16bit LSB Justified † Master Clock: 256fs, 384fs † High Tolerance to Clock Jitter Analog Switches for SCART Audio Section † THD+N: –86dB (@2Vrms) † Dynamic Range: 96dB (@2Vrms) † Stereo Analog Volume with Pop-noise Free Circuit (+6dB to –60dB & Mute) † Analog Inputs Two Stereo Inputs (TV&VCR SCART) One Stereo Input (Changeover to Internal DAC) † Analog Outputs Two Stereo Outputs (TV, VCR SCART) One Mono Output (Modulator) † Pop Noise Free Circuit for Power On/Off Video Section † Integrated LPF: –40dB@27MHz † 75ohm Driver † 6dB Gain for Outputs † Adjustable Gain † Four CVBS/Y Inputs (ENCx2, TV, VCR), Three CVBS/Y Outputs (RF, TV, VCR) † Three R/C Inputs (ENCx2, VCR), Two R/C outputs (TV, VCR) † Bi-Directional Control for VCR-Red/Chroma † Two G and B Inputs (ENC, VCR), One G and B Outputs (TV) † Y/Pb/Pr Option (to 6MHz) † VCR Input Monitor Loop–Through Mode for Standby Auto–Startup Mode for Power Saving SCART Pin#16(Fast Blanking), Pin#8(Slow Blanking) Control AK4702/04 Software Compatible MS0451-E-01 2007/06 -1- [AK4705] Power Supply † 5V+/–5% and 12V+/–5% † Low Power Dissipation / Low Power Standby Mode Package † Small 48-pin LQFP MS0451-E-01 2007/06 -2- [AK4705] VD VP MONOOUT VSS +6 to -60dB -6dB/0dB/ +2.44/+4dB VOL (2dB/step) MCLK LRCK TVOUTL DAC BICK TVOUTR SDTI Volume #0 Volume #1 MONO TV1/0 VCRINL VCRINR TVINL VCROUTL VCROUTR TVINR VMONO Bias (Mute) SCK SDA Register VCR1/0 DVCOM Control PVCOM PDN Audio Block(DAPD=“0”) VD VP MONOOUT VSS +6 to -60dB 0dB/+6dB VOL (2dB/step) (NC) TVOUTL DACL DACR TVOUTR (NC) Volume #2 Volume #1 MONO TV1/0 VCRINL VCRINR TVINL VCROUTL VCROUTR TVINR VMONO Bias (Mute) SCK SDA VCR1/0 Register DVCOM Control PVCOM PDN Audio Block(DAPD=“1”) MS0451-E-01 2007/06 -3- [AK4705] ( Typical connection ) ( Typical connection ) VVD1 VVD2 6dB RFV 6dB TVVOUT RF Mod VVSS ENC CVBS/Y ENCV ENC Y ENCY VCR CVBS/Y TV CVBS VCRVIN TVVIN 0, 1, 2, 3dB ENC R/C/Pr ENC C VCR R/C/Pr ENCRC 6dB ENCC TVRC TV SCART VCRRC ENC G/CVBS ENCG VCR G VCRG ENC B/Pb ENCB VCR B/Pb VCRB 6dB TVG 6dB TVB Monitor REFI 6dB VCRVOUT VCR SCART 6dB VCRC Video Block ( Typical connection ) VCR FB ( Typical connection ) VCRFB 2V 6dB TVFB 0V TV SCART 0/ 6/ 12V TVSB VCRSB VCR SCART 0/ 6/ 12V Monitor INT Video Blanking Block MS0451-E-01 2007/06 -4- [AK4705] ■ Ordering Guide -10 ∼ +70°C AK4705 48pin LQFP (0.5mm pitch) DVCOM VP MONOOUT TVOUTL TVOUTR VCROUTL VCROUTR TVINL TVINR VCRINL VCRINR 35 34 33 32 31 30 29 28 27 26 25 PVCOM 36 ■ Pin Layout VSS 37 24 TVSB VD 38 23 VCRSB MCLK 39 22 INT BICK 40 21 VCRB SDTI 41 20 VCRG LRCK 42 19 VCRRC SCL 43 18 VCRFB 17 VCRVIN AK4705VQ Top View 9 10 11 12 ENCB ENCG ENCRC ENCC REFI 13 8 48 VVD1 TVFB 7 ENCV TVB 14 6 47 TVG VCRVOUT 5 ENCY TVRC 15 4 46 VVD2 RFV 3 TVVIN TVVOUT 16 2 45 VVSS PDN 1 44 VCRC SDA MS0451-E-01 2007/06 -5- [AK4705] ■ Main difference between AK4702/4704 and AK4705 Items Audio Video Pinout Others Audio bits Digital filter attenuation level +4dB gain at DAC volume#0 (total: +10dB max) DAC power-down/analog input mode Volume#1 output for VCROUTL/R switch matrix MONO mixing for VCROUTL/R MONO input Video filter 150ohm video driver for modulator Y/C mixer for modulator VCR video input monitor VCR Slow Blanking monitor in output mode. TV/VCR CVBS input detection & Power Save Mode Y/Pb/Pr option RGB support in Auto Mode MONOIN Pin (at AK4702 Pin #28) ENCB Pin to TVINL Pin I2C speed (max) Mask bits for INT function (09H) FB/SB loop back in auto mode. MS0451-E-01 AK4702 18bit 54dB X enabled MONOIN Pin# 28 Pin #9 ~ #27 100kHz - AK4704 AK4705 24bit 24bit 64dB 64dB X X X X X X X X X X X X X X X disabled disabled X X X X FILT REFI Pin #28 Pin #9 Pin #9 ~ #27 Pin #10 ~ #28 400kHz 400kHz X X X (-: NOT available. X: Available) 2007/06 -6- [AK4705] PIN/FUNCTION No. 1 2 3 4 Pin Name VCRC VVSS TVVOUT VVD2 I/O O O - 5 6 7 8 TVRC TVG TVB VVD1 O O O - 9 REFI O 10 11 12 13 14 15 16 17 18 19 20 21 22 ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB INT I I I I I I I I I I I I O 23 24 25 26 27 28 29 30 31 32 33 34 VCRSB TVSB VCRINR VCRINL TVINR TVINL VCROUTR VCROUTL TVOUTR TVOUTL MONOOUT VP 35 DVCOM O 36 PVCOM O I/O O I I I I O O O O O - Function Chrominance Output Pin for VCR Video Ground Pin. 0V. Composite/Luminance Output Pin for TV Video Power Supply Pin #2, 5V Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel with a 10μF electrolytic cap. Red/Chrominance/Pr Output Pin for TV Green/Y Output Pin for TV Blue/Pb Output Pin for TV Video Power Supply Pin #1, 5V Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel with a 10μF electrolytic cap. Video Current Reference Setup Pin Normally connected to VVD1 through a 10kΩ±1% resistor externally. Blue/Pb Input Pin for Encoder Green/Y Input Pin for Encoder Red/Chrominance/Pr Input Pin for Encoder Chrominance Input Pin for Encoder Composite/Luminance Input1 Pin for Encoder Composite/Luminance Input2 Pin for Encoder Composite/Luminance Input Pin for TV Composite/Luminance Input Pin for VCR Fast Blanking Input Pin for VCR Red/Chrominance/Pr Input Pin for VCR Green Input Pin for VCR Blue/Pb Input Pin for VCR Interrupt Pin for Video Blanking. Normally connected to VD(5V) through 10kΩ resistor externally. Slow Blanking Input/Output Pin for VCR Slow Blanking Output Pin for TV Rch VCR Audio Input Pin Lch VCR Audio Input Pin Rch TV Audio Input Pin Lch TV Audio Input Pin Rch VCR Audio Output Pin Lch VCR Audio Output Pin Rch TV Audio Output Pin Lch TV Audio Output Pin MONO Analog Output Pin Power Supply Pin, 12V Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a 10μF electrolytic cap. DAC Common Voltage Pin Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a 10μF electrolytic cap. Audio Common Voltage Pin Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a 10μF electrolytic cap. The caps affect the settling time of audio bias level. MS0451-E-01 2007/06 -7- [AK4705] PIN/FUNCTION (Continued) 37 38 VSS VD 39 43 44 45 MCLK (NC) BICK DACR SDTI (NC) LRCK DACL SCL SDA PDN 46 47 48 RFV VCRVOUT TVFB 40 41 42 - I I I I I I I I/O I O O O Ground Pin. 0V. DAC Power Supply Pin, 5V Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a 10μF electrolytic cap. Master Clock Input Pin at DAPD= “0”. No Connect pin at DAPD= “1”. This pin should be open. Audio Serial Data Clock Pin at DAPD= “0”. Rch Analog Audio Input Pin at DAPD= “1”. Audio Serial Data Input Pin at DAPD= “0”. No Connect pin at DAPD= “1”. This pin should be open. L/R Clock Pin at DAPD= “0”. Lch Analog Audio Input Pin at DAPD= “1”. Control Data Clock Pin Control Data Pin Power-Down Mode Pin When at “L”, the AK4705 is in the power-down mode and is held in reset. The AK4705 should always be reset upon power-up. Composite Output Pin for RF modulator Composite/Luminance Output Pin for VCR Fast Blanking Output Pin for TV ■ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name VCRC, TVVOUT, TVRC, TVG, TVB, ENCB, ENCG, ENCRC, ENCC, ENCV, ENCY, TVVIN, VCRVIN, VCRRC, VCRG, VCRB, VCRINR, VCRINL, TVINR, TVINL, VCROUTR, VCROUTL, TVOUTR, TVOUTL, MONOOUT, DACR, DACL, RFV, VCRVOUT VCRSB (O), TVFB, TVSB VCRFB, VCRSB (I), MCLK, BICK, SDTI, LRCK, SCL, SDA, INT MS0451-E-01 Setting These pins should be open. These pins should be open. These pins should be connected to VSS. 2007/06 -8- [AK4705] Internal Equivalent Circuits Pin No. Pin Name 39 40 41 42 43 45 MCLK BICK SDTI LRCK SCL PDN Type Equivalent Circuit VD (60k) Digital IN (DAPD= “0”) Description The 60kΩ is attached only for BICK pin and LRCK pin. 200 Analog IN (DAPD= “1”) VSS VD 44 SDA 200 Digital I/O I2C Bus voltage must not exceed VD. VSS VP 22 INT Normally connected to VD(5V) through 10kΩ resistor externally. Digital OUT VSS 46 47 48 1 3 5 6 7 RFV VCROUT TVFB VCRC TVVOUT TVRC TVG TVB VVD1 VVD2 Video OUT VVSS VVSS VVD1 200 9 REFI REFI IN Normally connected to VVD1 through a 10kΩ ±1% resistor. VVSS MS0451-E-01 2007/06 -9- [AK4705] Pin No. 10 11 12 13 14 15 16 17 18 19 20 21 Pin Name ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB Type Equivalent Circuit VVD1 VCRSB TVSB The 60kΩ is attached for ENCC pin, ENCRC (chroma mode) pin and VCRRC (chroma mode) pin. 200 Video IN (60k) VVSS VP 23 24 Description VP 200 The 120kΩ is not attached for TVSB pin. Video SB (120k) VSS VSS VSS VP 25 26 27 28 VCRINR VCRINL TVINR TVINL 150k Audio IN VSS VP 29 30 31 32 33 VCROUTR VCROUTL TVOUTR TVOUTL MONOOU T VP 100 Audio OUT VSS VD 35 36 DVCOM PVCOM VSS VD VD 100 VCOM OUT VSS VSS MS0451-E-01 VSS 2007/06 - 10 - [AK4705] ABSOLUTE MAXIMUM RATINGS (VSS=VVSS=0V;Note: 1) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Video Input Voltage Audio Input Voltage (except DACL/R pins) Audio Input Voltage (DACL/R pins) Ambient Operating Temperature Storage Temperature Note: 1. All voltages with respect to ground. Symbol VD VVD1 VVD2 VP IIN VIND VINV VINA VINA Ta Tstg min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -10 -65 max 6.0 6.0 6.0 14 ±10 VD+0.3 VVD1+0.3 VP+0.3 VD+0.3 70 150 Units V V V V mA V V V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS=VVSS=0V; Note: 1) Parameter Power Supply (Note: 2) Symbol VD VVD1/VVD2 VP Note: 2. Analog output voltage scales with the voltage of VD. AOUT (typ@0dB) = 2Vrms × VD/5. The VVD1 and VVD2 must be the same voltage. min 4.75 4.75 11.4 typ 5.0 5.0 12 max 5.25 5.25 12.6 Units V V V max Units 120 12 mA mA mA mA 100 100 100 μA μA μA *AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. ELECTRICAL CHARACTERISTICS (Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs) Power Supplies Parameter min typ Power Supply Current Normal Operation (PDN pin = “H”; Note: 3) VD 14 VVD1+VVD2 46 VD+ VVD1+VVD2 6 VP Power-Down Mode (PDN pin = “L”; Note: 4) 10 VD VVD1+VVD2 10 VP 10 Note: 3. STBY bit = “L”, all video outputs are active. No signal, no load for A/V switches. fs=48kHz “0”data input for DAC. Note: 4. All digital inputs including clock pins (MCLK, BICK and LRCK) are held at VD or VSS. MS0451-E-01 2007/06 - 11 - [AK4705] DIGITAL CHARACTERISTICS (Ta = 25°C; VD = 4.75 ∼ 5.25V) Parameter High-Level Input Voltage Low-Level Input Voltage Low-Level Output Voltage (SDA pin: Iout= 3mA, INT pin: Iout= 1mA) Input Leakage Current Symbol VIH VIL VOL min 2.0 - typ - max 0.8 0.4 Units V V V Iin - - ± 100 μA ANALOG CHARACTERISTICS (AUDIO) (Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥4.5kΩ; Volume #0=Volume #1=0dB, 0dB=2Vrms output; unless otherwise specified) Parameter min typ max Units 24 bit DAC Resolution Analog Input: (TVINL/TVINR/VCRINL/VCRINR pins) Analog Input Characteristics Input Voltage 2 Vrms Input Resistance 100 150 kΩ Analog Input: (DACL/DACR pin) Analog Input Characteristics Input Voltage 1 Vrms Input Resistance 40 60 kΩ Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR/MONOOUT pins; Note: 5) Analog Output Characteristics Volume#0 Gain (DAPD bit = “0”) (DVOL1-0 = “00”) 0 dB (DVOL1-0 = “01”) dB -6 (DVOL1-0 = “10”) +2.44 dB (DVOL1-0 = “11”. Note: 6) dB +4 Volume#2 Gain (DAPD bit = “1”) (DVOL1-0 = “00”) 5.3 6 6.7 dB (DVOL1-0 = “01”) -0.7 0 0.7 dB Volume#1 Step Width (+6dB to –12dB) dB 1.6 2 2.4 (-12dB to –40dB) 0.5 2 3.5 dB (-40dB to –60dB) dB 0.1 2 3.9 THD+N (at 2Vrms output. Note: 7) -86 -80 dB (at 3Vrms output. Note: 7, Note: 8) -60 dB Dynamic Range (-60dB Output, A-weighted. Note: 7) 92 96 dB S/N (A-weighted. Note: 7) 92 96 dB Interchannel Isolation (Note: 7, Note: 9) 80 90 dB Interchannel Gain Mismatch (Note: 7, Note: 9) 0.3 dB Gain Drift 200 ppm/°C Load Resistance (AC-Lord) kΩ TVOUTL/R, VCROUTL/R, MONOOUT 4.5 Load Capacitance TVOUTL/R, VCROUTL/R, MONOOUT Output Voltage (Note: 10) 1.85 Power Supply Rejection (PSR. Note: 11) Note: 5. Measured by Audio Precision System Two Cascade. Note: 6. Output clips over –2.5dBFS digital input. Note: 7. DAC to TVOUT Note: 8. Except VCROUTL/VCROUTL pins. Note: 9. Between TVOUTL and TVOUTR with digital inputs 1kHz/0dBFS. MS0451-E-01 2 50 20 2.15 pF Vrms dB 2007/06 - 12 - [AK4705] Note: 10. Full-scale output voltage by DAC (0dBFS). Output voltage of DAC scales with the voltage of VD, Stereo output (typ@0dBFS) = 2Vrms × VD/5 when volume#0=volume#1=0dB. The output must not exceed 3Vrms. Note: 11. The PSR is applied to VD with 1kHz, 100mV. FILTER CHARACTERISTICS (Ta = 25°C; VP=11.4∼12.6V, VD = 4.75∼5.25V, VVD1=VVD2 = 4.75∼5.25V; fs = 48kHz; DEM0 = “1”, DEM1 = “0”) Parameter Symbol min typ max Units Digital filter kHz PB 0 21.77 Passband ±0.05dB (Note: 12) 24.0 kHz -6.0dB Stopband (Note: 12) SB 26.23 kHz Passband Ripple PR dB ± 0.01 Stopband Attenuation SA 64 dB Group Delay (Note: 13) GD 24 1/fs Digital Filter + LPF FR dB Frequency Response 0 ∼ 20.0kHz ± 0.5 Note: 12. The passband and stopband frequencies scale with fs. e.g.) PB=0.4535×fs (@±0.05dB), SB=0.546×fs. Note: 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/18/24bit data of both channels to input register to the output of analog signal. MS0451-E-01 2007/06 - 13 - [AK4705] ANALOG CHARACTERISTICS (VIDEO) (Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; VVOL1/0= “00” unless specified.) Parameter Conditions min Sync Tip Clamp Voltage at output pin. Chrominance Bias Voltage at output pin. Pb/Pr Clamp Voltage at output pin. Gain Input=0.3Vp-p, 100kHz 5.5 RGB Gain Input=0.3Vp-p, VVOL1/0= “00” 5.5 100kHz VVOL1/0= “01” 6.7 VVOL1/0= “10” 7.7 VVOL1/0= “11” 8.6 Interchannel Gain Mismatch TVRC, TVG, TVB. Input=0.3Vp-p, 100kHz. -0.5 Frequency Response Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz. -1.0 at 10MHz. at 27MHz. Group Delay Distortion At 4.43MHz with respect to 1MHz. Input Impedance Chrominance input (internally biased) 40 Input Signal f=100kHz, maximum with distortion < 1.0%, gain=6dB. Load Resistance (Figure 1) 150 Load Capacitance C1 (Figure 1) C2 (Figure 1) Dynamic Output Signal f=100kHz, maximum with distortion < 1.0% Y/C Crosstalk f=4.43MHz, 1Vp-p input. Among TVVOUT, TVRC, VCRVOUT and VCRC outputs. S/N Reference Level = 0.7Vp-p, CCIR 567 weighting. BW= 15kHz to 5MHz. Differential Gain 0.7Vpp 5steps modulated staircase. chrominance &burst are 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. chrominance &burst are 280mVpp, 4.43MHz. typ 0.7 2.2 2.2 6 6 7.2 8.2 9.1 - -25 15 1.5 Units V V V dB dB dB dB dB dB dB dB dB ns kΩ Vpp -50 400 15 3 - Ω pF pF Vpp dB 74 - dB +0.4 - % +0.8 - Degree -3 -40 60 - max 6.5 6.5 7.7 8.7 9.6 0.5 0.5 R1 75 Ω Video Signal Output R2 75 Ω C2 C1 max: 15pF max: 400pF Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2. MS0451-E-01 2007/06 - 14 - [AK4705] SWITCHING CHARACTERISTICS (Ta = 25°C; VP=11.4 ∼ 12.6V, VD = 4.75 ∼ 5.25V, VVD1=VVD2 = 4.75 ∼ 5.25V) Parameter Symbol Min typ fCLK 8.192 Master Clock Frequency 256fs: dCLK Duty Cycle 40 fCLK 12.288 384fs: dCLK Duty Cycle 40 fs 32 LRCK Frequency Duty 45 Duty Cycle Audio Interface Timing tBCK 312.5 BICK Period tBCKL 100 BICK Pulse Width Low tBCKH 100 Pulse Width High tBLR 50 (Note: 14) BICK “↑” to LRCK Edge tLRB 50 (Note: 14) LRCK Edge to BICK “↑” tSDH 50 SDTI Hold Time tSDS 50 SDTI Setup Time Control Interface Timing (I2C Bus): SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time tHD:STA 0.6 (prior to first clock pulse) tLOW Clock Low Time 1.3 tHIGH Clock High Time 0.6 tSU:STA Setup Time for Repeated Start Condition 0.6 SDA Hold Time from SCL Falling (Note: 15) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 tR Rise Time of Both SDA and SCL Lines tF Fall Time of Both SDA and SCL Lines tSU:STO Setup Time for Stop Condition 0.6 tSP Pulse Width of Spike Noise 0 Suppressed by Input Filter Capacitive load on bus Cb Reset Timing PDN Pulse Width (Note: 16) tPD 150 Note: 14. BICK rising edge must not occur at the same time as LRCK edge. Note: 15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note: 16. The AK4705 should be reset by PDN pin = “L” upon power up. Note: 17. I2C is a registered trademark of Philips Semiconductors. MS0451-E-01 max 12.8 60 19.2 60 50 55 Units MHz % MHz % kHz % ns ns ns ns ns ns ns 400 0.3 0.3 50 kHz μs μs μs μs μs μs μs μs μs μs ｎs ｐF 400 ns 2007/06 - 15 - [AK4705] ■ Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Serial Interface Timing MS0451-E-01 2007/06 - 16 - [AK4705] tPD PDN VIL Power-down Timing VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop I2C Bus mode Timing MS0451-E-01 2007/06 - 17 - [AK4705] OPERATION OVERVIEW 1. System Reset and Power-down options The AK4705 should be reset once by bringing PDN pin = “L” upon power-up. The AK4705 has several operation modes. The PDN pin, AUTO bit, DAPD bit, MUTE bit and STBY bit control operation modes as shown in Table 1 and Table 2. 0 PDN pin L AUTO bit x STBY bit x MUTE bit x DAPD bit x 1 H 1 x x x 2 3 H H 0 0 1 1 1 0 x x 4 H 0 0 1 1 5 H 0 0 1 0 6 H 0 0 0 1 7 H 0 0 0 0 Mode Mode Full Power-down Auto Startup mode (power-on default) Standby & mute Standby Mute (DAC power down) Mute (DAC operation) Normal operation (DAC power down & Analog input) Normal operation (DAC operation) x: Don’t Care Table 1. Operation Mode Settings Mode Register Control 0 Full Power-down NOT available 1 Auto Startup mode (power-on default) 2 Standby & mute 3 Standby Mute (DAC power down) Mute (DAC operation) Normal operation (DAC power down & Analog input) Normal operation (DAC operation) 4 5 6 7 No video input Video input (3) MCLK, BICK, LRCK Not needed Audio Bias Level Video Output TVFB, TVSB VCRSB Power down Hi-Z Hi-Z Pull-down (2) Active Active Available Active Power down Active Power down Active (4) Hi-Z/ Active Needed Not needed Active (1) Needed Notes: (1) TVOUTL/R are muted by VMUTE bit in the default state. (2) Internally pulled down by 120kohm(typ) resistor. (3) Video input to TVVIN or VCRVIN. (4) VCRC outputs 0V for termination. Table 2. Status of each operation modes MS0451-E-01 2007/06 - 18 - [AK4705] ■ Full Power-down Mode The AK4705 should be reset once by bringing PDN pin = “L” upon power-up. PDN pin: Power down pin “H”: Normal operation “L”: Device power down. ■ Auto Startup Mode After when the PDN pin is set to “H”, the AK4705 is in the auto startup mode. In this mode, all blocks except for the video detection circuit are powered down. Once the video detection circuit detects video signal from TVVIN pin or VCRVIN pin, the AK4705 goes to the stand-by mode (Both Fast Blanking and Slow Blanking are also fixed to VCR-TV Loop-through) automatically and sends “H” pulse via INT pin. To exit the auto startup mode, set the AUTO bit to “0”. AUTO bit (00H D3): Auto startup bit “1”: Auto startup enable (default). “0”: Auto startup disable (Manual startup). ■ DAC Power-down Mode The internal DAC block can be powered-down and switched to 1Vrms analog input mode. When DAPD bit =“1”, the zero-cross detection and offset calibration does not work. DAPD bit (00H D2): DAC power-down bit. “1”: DAC power-down. Analog-input mode. #39 pin: MCLK -> (NC) #40 pin: BICK -> DACR. Rch analog input. #41 pin: SDTI -> (NC) #42 pin: LRCK -> DACL. Lch analog input. “0”: DAC operation. (default) ■ Standby Mode When the AUTO bit = MUTE bit = “0” and the STBY bit = “1”, the AK4705 is forced into TV-VCR loop through mode. In this mode, the sources of TVOUTL/R and MONOOUT pins are fixed to VCRINL/R pins; the sources of VCROUTL/R are fixed to TVINL/R pins respectively. The gain of volume#1 is fixed to 0dB. All register values themselves are NOT changed by STBY bit = “1”. STBY bit (00H D0): Standby bit. “1”: Standby mode. (default) “0”: Normal operation. „ Mute Mode (Bias-off Mode. 00H: D1) When the MUTE bit = “1”, the bias voltage on the audio output goes to GND level. Bringing MUTE bit to “0” changes this bias voltage smoothly from GND to VP/2 by 2sec(typ.). This removes the huge click noise related the sudden change of bias voltage at power-on. The change of MUTE bit from “1” to “0” also makes smooth transient from VP/2 to GND by 2sec(typ). This removes the huge click noise related the sudden change of bias voltage at power-off. MUTE bit: Bias-off bit. “1”: Set the audio bias to GND. (default) “0”: Normal operation MS0451-E-01 2007/06 - 19 - [AK4705] ■ Normal Operation Mode To use the DAC or change analog switches, set the AUTO bit, DAPD bit, MUTE bit and STBY bit to “0”. The DAC is in power-down mode until MCLK and LRCK are input. The AK4705 is in power-down mode until MCLK and LRCK are input. Figure 2 shows an example of the system timing at the power-down and power-up by PDN pin. ■ Typical Operation Sequence (auto setup mode) Figure 2 shows an example of the system timing for the auto setup mode. PDN pin Low Power Mode Low Power Mode Clock, Data in Low Power Mode don’t care TVVIN don’t care VCRVIN don’t care TVVOUT, VCRVOUT No Signal No Signal No Signal Hi-Z Audio out (DC) Signal in Signal in No Signal Signal in Active (loop-through) Hi-Z No Signal Active (loop-through) Active (loop-through) don’t care don’t care Hi-Z Active (loop-through) (GND) Figure 2. Typical operating sequence (auto setup mode) „ Typical Operation Sequence (except auto setup mode) Figure 3 shows an example of the system timing except for the auto setup mode. PDN pin AUTO bit MUTE bit STBY bit Clock in Data in “Stand-by“ “Mute” “1” (default) “1” (default) “0” “0” “1” “1” (default) “0” don’t care (2) normal operation don’t care “Stand-by“ “0” Audio data GD (1) “1” “0” “1” don’t care (2) don’t care “0” GD (1) D/A Out (internal) TV-Source select fixed to VCR in(Loop-through) VCR in DAC (default) VCR in (4) offset calibration TV out VCR in VCR in (3) MS0451-E-01 2007/06 - 20 - [AK4705] Figure 3. Typical operating sequence (except auto setup mode) Notes: (1) The analog output corresponding to the digital input has a group delay, GD. (2) The external clocks (MCLK, BICK and LRCK) can be stopped in standby mode. (3) Mute the analog outputs externally if click noise(3) adversely affects the system. (4) In case of the CAL bit = “1”, the offset calibration is always executed when the source of TVOUTL/R pins are switched to DAC after the STBY bit is changed to “0”. To disable this function, set the CAL bit = “0”. 2. Audio Block ■ System Clock The external clocks required to operate the DAC section of AK4705 are MCLK, LRCK and BICK. The master clock (MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock becomes 256fs. The MCLK should be synchronized with LRCK but the phase is not critical. Table 3 illustrates corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC section of AK4705 is in the normal operating mode (STBY bit = “0” and DAPD bit = “0”). If these clocks are not provided, the AK4705 may draw excess current because the device utilizes dynamically refreshed logic internally. The DAC section of AK4705 should be reset by STBY bit = “0” after threse clocks are provided. If the external clocks are not present, place the AK4705 in power-down mode (STBY bit = “1”). After exiting reset at power-up etc., the AK4705 remains in power-down mode until MCLK and LRCK are input. LRCK fs 32.0kHz 44.1kHz 48.0kHz MCLK 256fs 384fs 8.1920MHz 12.2880MHz 11.2896MHz 16.9344MHz 12.2880MHz 18.4320MHz Table 3. System clock example BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz ■ Audio Serial Interface Format (00H: D5-D4) Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0 and DIF1 bits can select four formats in serial mode as shown in Table 4. In all modes, the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs. Mode 0 1 2 DIF1 0 0 1 DIF0 0 1 0 3 1 1 SDTI Format 16bit LSB Justified 18bit LSB Justified 24bit MSB Justified BICK ≥32fs ≥36fs ≥48fs ≥48fs or 2 24bit I S Compatible 32fs Table 4. Audio Data Formats MS0451-E-01 Figure Figure 4 Figure 4 Figure 5 Figure 6 (default) 2007/06 - 21 - [AK4705] LRCK BICK SDTI Mode 0 Don’t care 15 14 0 Don’t care 15 0 Don’t care 15 14 0 15 0 15:MSB, 0:LSB SDTI Mode 1 Don’t care 17 16 14 17 16 14 17:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 0,1 Timing LRCK BICK SDTI 23 22 1 0 Don’t care 23 22 1 0 Don’t care 17 16 23:MSB, 0:LSB Lch Data Rch Data Figure 5. Mode 2 Timing LRCK BICK SDTI 23 22 1 0 Don’t care 23 22 1 0 Don’t care 17 23:MSB, 0:LSB Lch Data Rch Data Figure 6. Mode 3 Timing MS0451-E-01 2007/06 - 22 - [AK4705] ■ De-emphasis filter (00H: D7-D6) A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is controlled by the DEM0 and DEM1 bits. DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz Table 5. De-emphasis filter control (default) ■ Switch Control The AK4705 has switch matrixes designed primarily for SCART routing. Those are controlled via the control register as shown in Table 6, Table 7 and Table 8 (refer to the block diagram). (01H: D1-D0) TV1 TV0 Source of TVOUTL/R 0 0 DAC 0 1 VCRIN (default) 1 0 Mute 1 1 (Reserved) Table 6. TVOUT Switch Configuration (01H: D2-D0) VOL TV1 TV0 Source of MONOOUT 0 0 0 DAC (L+R)/2 Bypass the 0 0 1 DAC (L+R)/2 volume #1 0 1 0 DAC (L+R)/2 0 1 1 (Reserved) Through the 1 0 0 DAC (L+R)/2 volume #1 1 0 1 VCRIN (L+R)/2 (default) 1 1 0 Mute 1 1 1 (Reserved) Table 7. MONOOUT Switch Configuration (01H: D5-D4) VCR1 VCR0 Source of VCROUTL/R 0 0 DAC 0 1 TVIN 1 0 Mute 1 1 Output of volume #1 Table 8. VCROUT Switch Configuration MS0451-E-01 (default) 2007/06 - 23 - [AK4705] ■ Volume Control #0, #2 (4-Level Volume) The AK4705 has a 4-level volume control (Volume #0, #2) as shown in Table 9 and Table 10. The volume reflects the change of register value immediately. (03H: D4-D3) DVOL1 DVOL0 0 0 0 1 1 0 1 1 (03H: D4-D3) DVOL1 DVOL0 0 0 0 1 1 0 1 1 Volume #0 Gain 0dB -6dB +2.44dB Output Level (Typ) 2Vrms (with 0dBFS input & volume #1=0dB) 1Vrms (with 0dBFS input & volume #1=0dB.) 2.65Vrms (with 0dBFS input & volume #1=0dB.) 2Vrms (with –10dBFS input & volume #1=+6dB. +4dB Clips over –2.5dBFS digital input.) Table 9. Volume #0 (at DAPD bit = “0”. DAC mode) Volume #2 Gain Output Level (Typ) +6dB 2Vrms (with 1Vrms input & volume #1=0dB) 0dB 1Vrms (with 1Vrms input & volume #1=0dB.) (reserved) (reserved) Table 10. Volume #2 (at DAPD bit = “1”. analog input mode.) MS0451-E-01 (default) (default) 2007/06 - 24 - [AK4705] ■ Volume Control #1 (Main Volume) The AK4705 has main volume control (Volume #1) as shown in Table 11. (02H: D5-D0) L5 L4 L3 L2 L1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 … … … … … 0 0 0 0 0 0 0 0 0 0 Note: The output must not exceed 3Vrms. Table 11. Volume #1 L0 0 1 0 1 … 1 0 Gain +6dB +4dB +2dB 0dB … -60dB Mute (default) When the MOD bit = “1”(default), changing levels don’t have pop noise. MDT1-0 bits select the transition time (Table 12). When the new gain value 1EH(-2dB) is written to gain resistor while the actual (stable) gain is 1FH(0dB), the gain changes to 1EH(-2dB) within the transition time selected by MDT1-0 bits. The AK4705 compares the actual gain to the value of gain register after finishing the transition time, and re-changes the actual gain to new resister value within the transition time if the register value is different from the actual gain. When the MOD bit = “0”, there is no transition time and the gain changes immediately. This change may cause a click noise. WR [Gain=1EH] Gain Register WR [Gain=1DH] 1FH WR [Gain=1CH] 1DH 1EH compare Actual Gain 1FH (to 1EH) 1CH compare 1EH (to 1DH) compare (to 1CH) 1CH 1DH Transition Time (256/fs to 2048/fs. pop free.) Figure 7. Volume Change Operation (MOD bit = “1”) MDT1 0 0 1 1 MDT0 0 1 0 1 Transition Time 256/fs 512/fs 1024/fs 2048/fs Table 12. Volume Transition Time MS0451-E-01 (default) 2007/06 - 25 - [AK4705] 3. Video Block ■ Video Switch Control The AK4705 has switches for TV, VCR and RF modulator. Each switches can be controlled via registers independently. When AUTO bit = “1” or STBY bit = “1”, these switch setting are ignored and set to fixed configuration (loop-through mode). Please refer to the auto setup mode and standby mode. (04H: D2-D0) VTV2-0 bit 000 Mode Shutdown Encoder CVBS+RGB or Encoder YPbPr 001 Encoder Y/C 1 010 Encoder Y/C 2 011 VCR 100 TV CVBS 101 (reserved) (reserved) 110 111 Source of TVVOUT pin (Hi-Z) ENCV pin. Encoder CVBS or Y. ENCV pin. Encoder Y. ENCY pin. Encoder Y. VCRVIN pin. VCR CVBS or Y. TVVIN pin. TV CVBS. - Source of TVRC pin (Hi-Z) ENCRC pin. Encoder Red,C or Pb. ENCRC pin. Encoder C. ENCC pin. Encoder C. VCRRC pin. VCR Red,C or Pb. Source of TVG pin (Hi-Z) ENCG pin. Encoder Green or Y. Source of TVB pin (Hi-Z) ENCB pin. Encoder Blue or Pr. (Hi-Z) (Hi-Z) (Hi-Z) (Hi-Z) VCRG pin. VCR Green or Y. VCRB pin. VCR Blue or Pr. (Hi-Z) (Hi-Z) (Hi-Z) - - (default) (Note: 18, Note: 19) Table 13. TV video output (04H: D5-D3) Mode VVCR2-0 bit Shutdown 000 Encoder CVBS or Y/C 1 001 Encoder CVBS or Y/C 2 010 TV CVBS 011 VCR 100 (reserved) (reserved) (reserved) 101 110 111 Source of VCRVOUT pin (Hi-Z) ENCV pin. Encoder CVBS or Y. ENCY pin. Encoder CVBS or Y. TVVIN pin. TV CVBS. VCRVIN pin. VCR CVBS. - Source of VCRC pin (Hi-Z) ENCRC pin. Encoder C. ENCC pin. Encoder C. (Hi-Z) (default) VCRRC pin. VCR C. (Note: 18) Table 14. VCR video output MS0451-E-01 2007/06 - 26 - [AK4705] (04H: D7-D6) Mode Encoder CVBS1 Encoder CVBS2 VCR Shutdown VRF1-0 bit Source of RFV pin ENCV pin. 00 Encoder CVBS. ENCG pin. 01 Encoder CVBS. (Note: 19) VCRVIN pin. 10 (default) VCR CVBS. 11 (Hi-Z) (Note: 19) Table 15. RF video output Note: 18: When input the video signal via ENCRC pin or VCRRC pin, set CLAMP1-0 bits respectively. Note: 19 When VTV2-0 bit =“001”, TVG bit =“1” and VRF1-0 bit =“01”, RFV pin output is same as TVG pin output (Encoder G). ■ Video Output Control (05H: D6-D0) Each video outputs can be set to Hi-Z individually via control registers. These setting are ignored when the AUTO bit = “1”. When the CIO bit = “1”, the VCRC pin outputs 0V even if the VCRC bit = “0”. When the CIO bit = “0”, the VCRC pin follows the setting of VCRC bit. Please refer to the “Red/Chroma Bi-directional Control for VCR SCART”. TVV: TVR: TVG: TVB: VCRV: VCRC: TVFB: TVVOUT output control TVRCOUT output control TVGOUT output control TVBOUT output control VCRVOUT output control VCRC output control TVFB output control 0: Hi-Z (default) 1: Active. MS0451-E-01 2007/06 - 27 - [AK4705] ■ Red/Chroma Bi-directional Control for VCR SCART (05H: D7, D5) The AK4705 supports the bi-directional Red/Chroma signal on the VCR SCART. (CIO bit & VCRC bit) #15 pin 75 VCRC pin VCRRC pin VCR SCART 0.1u (AK4705) Figure 8. Red/Chroma Bi-directional Control CIO 0 0 1 1 VCRC State of VCRC pin (default) 0 Hi-z 1 Active 0 Connected to GND 1 Connected to GND Table 16 Red/Chroma Bi-directional Control MS0451-E-01 2007/06 - 28 - [AK4705] ■ RGB Video Gain Control (06H: D1-D0) VVOL1-0 bits set the RGB video gain. VVOL1 0 0 1 1 VVOL0 0 1 0 1 Gain Output level (Typ. @Input=0.7Vpp) +6dB 1.4Vpp +7.2dB 1.6Vpp +8.2dB 1.8Vpp +9.1dB 2.0Vpp Table 17. RGB video gain control (default) ■ Clamp and DC-restore circuit control (06H: D7-D2) Each CVBS and Y input has the sync tip clamp circuit. The DC-restore circuit has two clamp voltages 0.7V(typ) and 2.2V(typ) to support both RGB and YPbPr signal. They correspond to 0.35V(typ) and 1.1V(typ) at the SCART connector when matched by 75ohm resistors. The CLAMP1, CLAMP0 and CLAMPB bits select the input circuit for ENCRC pin (Encoder Red/Chroma), ENCB pin (Encoder Blue), VCRRC pin (VCR Red/Chroma) and VCRB pin (VCR Blue) respectively. VCLP1-0 bits select the sync source of DC- restore circuit. CLAMPB CLAMP0 0 0 0 1 1 0 1 1 VCRRC Input Circuit DC restore clamp active (0.7V at sync timing/output pin) Biased (2.2V at sync timing/output pin) DC restore clamp active (2.2V at sync timing/output pin) (reserved) VCRB Input Circuit DC restore clamp active (0.7V at sync timing/output pin) (DC restore clamp active) (0.7V at sync timing output pin) DC restore clamp active (2.2V at sync timing/output pin) (reserved) note for RGB for Y/C (default) for Y/Pb/Pr Table 18. DC-restore control for VCR Input CLAMPB CLAMP1 0 0 0 1 1 0 1 1 ENCRC Input Circuit DC restore clamp active (0.7V at sync timing/output pin) Biased (2.2V at sync timing/output pin) DC restore clamp active (2.2V at sync timing/output pin) (reserved) ENCB Input Circuit DC restore clamp active (0.7V at sync timing/output pin) DC restore clamp active (0.7V at sync timing output pin) DC restore clamp active (2.2V at sync timing/output pin) (reserved) note for RGB (default) for Y/C for Y/Pb/Pr Table 19. DC-restore control for Encoder Input CLAMP2 0 1 ENCG Input Circuit DC restore clamp active (0.7V at sync timing/output pin) Sync tip clamp active (0.7V at sync timing/output pin) note for RGB (default) for Y/Pb/Pr Note: When the VTV2-0 bits = “001”(source for TV = Encoder CVBS /RGB), TVG bit = “1” (TVG = active) and VCLP1-0 bits = “11”(DC restore source = ENCG), the sync tip is selected even if the CLAMP2 bit = “0”. Table 20. DC-restore control for Encoder Green/Y Input MS0451-E-01 2007/06 - 29 - [AK4705] VCLP1-0: DC restore source control VCLP1 0 0 1 1 VCLP0 0 1 0 1 Sync Source of DC Restore ENCV ENCY VCRVIN ENCG (default) Note: When the AUTO bit = “1”, the source is fixed to VCRVIN. Table 21. DC-restore source control MS0451-E-01 2007/06 - 30 - [AK4705] 4. Blanking Control The AK4705 supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV/VCR SCART. ■ Input/Output Control for Fast/Slow Blanking FB1-0: TV Fast Blanking output control (07H: D1-D0) FB1 0 0 1 1 FB0 0 1 0 1 TVFB pin Output Level (default) 0V 4V Same as VCR FB input (4V/0V) (Reserved) (Note: Minimum load is 150ohm) Table 22. TV Fast Blanking output SBT1-0: TV Slow Blanking output control (07H: D3-D2) SBT1 0 0 1 1 SBT0 0 1 0 1 TVSB pin Output Level (default)