[AK5701]
AK5701
16-Bit Stereo ADC with PLL & MIC-AMP
GENERAL DESCRIPTION
The AK5701 features a 16-bit stereo ADC. Input circuits include a Microphone-Amplifier and an ALC
(Auto Level Control) circuit that is suitable for portable application with recording function. On-chip PLL
supports base-band clock of mobile phone, therefore it is easy to connect with DSP. The AK5701 is
available in a 24-pin QFN, utilizing less board space than competitive offerings.
FEATURES
1. Resolution: 16bits
2. Recording Function
- 2 Stereo Input Selector
- Full-differential or Single-ended Input
- MIC Amplifier (+30dB/+15dB or 0dB)
- Input Voltage: 1.8Vpp@VA=3.0V (= 0.6 x AVDD)
- ADC Performance: S/(N+D): 78dB, DR, S/N: 89dB@MGAIN=0dB
S/(N+D): 77dB, DR, S/N: 87dB@MGAIN=+15dB
S/(N+D): 72dB, DR, S/N: 77dB@MGAIN=+30dB
- Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
- Digital ALC (Automatic Level Control)
(+36dB 54dB, 0.375dB Step, Mute)
3. Sampling Rate:
- PLL Slave Mode (EXLRCK pin): 7.35kHz 48kHz
- PLL Slave Mode (EXBCLK pin): 7.35kHz 48kHz
- PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- EXT Slave Mode:
7.35kHz 48kHz (256fs), 7.35kHz 26kHz (512fs), 7.35kHz 13kHz (1024fs)
4. PLL Input Clock:
- MCKI pin:
27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
- EXLRCK pin: 1fs
- EXBCLK pin: 32fs/64fs
5. Master/Slave mode
6. Audio Interface Format: MSB First, 2’s compliment
- DSP Mode, 16bit MSB justified, I2S
7. P I/F: 3-wire Serial
8. Power Supply:
- AVDD: 2.4 3.6V
- DVDD: 1.6 3.6V
9. Power Supply Current: 8mA
10. AK5701VN: Ta = 30 85C
AK5701KN: Ta = 40 85C
11. Package: 24-pin QFN (4mm x 4mm)
12. AEC-Q100 Qualified (AK5701KN)
MS0404-E-05
2015/11
-1-
[AK5701]
■ Block Diagram
DVDD
DVSS
PDN
LIN1
RIN1
LIN2
S
E
L
ADC
ALC
or
HPF MIX
IVOL
RIN2
LRCK
Audio I/F
Controller
BCLK
S
E
L
SDTO
MPWR
VCOM
AVDD
AVSS
VCOC
Control
Register
PLL
MCKO MCKI
CSP
EXLRCK
EXBCLK
EXSDTI
CSN CCLK CDTI
Figure 1. Block Diagram
MS0404-E-05
2015/11
-2-
[AK5701]
■ Ordering Guide
30 +85C
24-pin QFN (0.5mm pitch)
40 +85C
24-pin QFN (0.5mm pitch)
Evaluation board for AK5701
AK5701VN
AK5701KN
AKD5701
PDN
CSN
CCLK
CDTI
MCKI
EXBCLK
18
17
16
15
14
13
■ Pin Layout
MCKO
RIN1
22
Top View
9
CSP
LIN1
23
8
SDTO
VCOC
24
7
LRCK
6
10
BCLK
AK5701
5
21
DVSS
LIN2
4
EXSDTI
DVDD
11
3
2
20
AVDD
RIN2
2
EXLRCK
AVSS
12
1
19
VCOM
MPWR
■ Comparison with AK5355VN
Function
Input Selector
Input Gain
Mic Bias
ALC
Mono Mic Mode
Audio I/F Format
PLL
Master Mode
Output Data Selector
Serial Control
AK5355VN
No
+15dB/0dB
No
No
No
Left justified, I2S
No
No
No
No
Power Supply
2.1 3.6V
Package
Ambient Temperature
20-pin QFN (4.2mm x 4.2mm)
40 +85C
MS0404-E-05
AK5701
Yes
+30dB/+15dB/0dB
Yes
Yes
Yes
DSP Mode, Left justified, I2S
Yes
Yes
Yes
Yes
AVDD=2.4 3.6V
DVDD=1.6 3.6V
24-pin QFN (4mm x 4mm)
AK5701VN : 30 +85C
AK5701KN : 40 +85C
2015/11
-3-
[AK5701]
PIN/FUNCTION
No.
Pin Name
I/O
Function
Common Voltage Output Pin, 0.5 x AVDD
1 VCOM
O
Bias voltage of ADC inputs.
2 AVSS
Analog Ground Pin
3 AVDD
Analog Power Supply Pin
4 DVDD
Digital Power Supply Pin
5 DVSS
Digital Ground Pin
6 BCLK
O
Audio Serial Data Clock Pin
7 LRCK
O
Input / Output Channel Clock Pin
8 SDTO
O
Audio Serial Data Output Pin
Chip Select Polarity Pin
9 CSP
I
“H”: CSN pin = “H” active, C1-0 = “01”
“L”: CSN pin = “L” active, C1-0 = “10”
10 MCKO
O
Master Clock Output Pin
11 EXSDTI
I
External Audio Serial Data Input Pin
12 EXLRCK
I
External Input / Output Channel Clock Pin
13 EXBCLK
I
External Audio Serial Data Clock Pin
14 MCKI
I
External Master Clock Input Pin
15 CDTI
I
Control Data Input Pin
16 CCLK
I
Control Data Clock Pin (Internal Pull-down at CSP pin = “H”)
17 CSN
I
Chip Select Pin
Power-Down Mode Pin
18 PDN
I
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
19 MPWR
O
MIC Power Supply Pin
RIN2
I
Rch Analog Input 2 Pin
(MDIF2 bit = “0”)
20
RIN+
I
Rch Positive Input Pin
(MDIF2 bit = “1”)
LIN2
I
Lch Analog Input 2 Pin
(MDIF2 bit = “0”)
21
I
Rch Negative Input Pin
(MDIF2 bit = “1”)
RIN
RIN1
I
Rch Analog Input 1 Pin
(MDIF1 bit = “0”)
22
I
Lch Negative Input Pin
(MDIF1 bit = “1”)
LIN
LIN1
I
Lch Analog Input 1 Pin
(MDIF1 bit = “0”)
23
LIN+
I
Lch Positive Input Pin
(MDIF1 bit = “1”)
Output Pin for Loop Filter of PLL Circuit
24 VCOC
O
This pin should be connected to AVSS with one resistor and capacitor in series.
Note 1. All input pins except analog input pins (LIN1, RIN1, LIN2, RIN2) should not be left floating.
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MPWR, VCOC, LIN1/LIN+, RIN1/LIN,
LIN2/RIN, RIN2/RIN+
BCLK, LRCK, SDTO, MCKO
MCKI, EXBCLK, EXLRCK, EXSDTI
MS0404-E-05
Setting
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.
2015/11
-4-
[AK5701]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 2)
Parameter
Symbol
Min.
Power Supplies:
Analog
AVDD
0.3
Digital
DVDD
0.3
|AVSS – DVSS| (Note 3)
GND
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (Note 4)
VINA
0.3
Digital Input Voltage (Note 5)
VIND
0.3
Ambient Temperature
AK5701VN
Ta
30
(powered applied)
AK5701KN
Ta
40
Storage Temperature
Tstg
65
Note 2. All voltages with respect to ground.
Note 3. AVSS and DVSS must be connected to the same analog ground plane.
Note 4. LIN1/LIN+, RIN1/LIN, LIN2/RIN, RIN2/RIN+ pins
Note 5. PDN, CSN, CCLK, CDTI, CSP, MCKI, EXSDTI, EXLRCK, EXBCLK pins
Max.
4.6
4.6
0.3
10
AVDD+0.3
DVDD+0.3
85
85
150
Unit
V
V
V
mA
V
V
C
C
C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 2)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supplies
Analog
AVDD
2.4
3.0
3.6
V
(Note 6)
Digital
DVDD
1.6
3.0
AVDD
V
Note 2. All voltages with respect to ground.
Note 6. The power-up sequence between AVDD and DVDD is not critical. When only AVDD is powered OFF, the power
supply current of DVDD at power-down mode may be increased. DVDD should not be powerd OFF while AVDD
is powered ON.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0404-E-05
2015/11
-5-
[AK5701]
ANALOG CHARACTERISTICS
(Ta=25C; AVDD, DVDD=3.0V; AVSS=DVSS=0V; PLL Master Mode; MCKI=12MHz, fs=44.0995kHz, BCLK=64fs;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 20kHz; unless otherwise specified)
Parameter
Min.
Typ.
Max.
Unit
MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins; MDIF1 = MDIF2 bits = “0” (Single-ended inputs)
MGAIN1-0 bits = “00”
40
60
80
k
Input
Resistance MGAIN1-0 bits = “01” or “10”
20
30
40
k
MGAIN1-0 bits = “00”
0
dB
Gain
MGAIN1-0 bits = “01”
+15
dB
MGAIN1-0 bits = “10”
+30
dB
MIC Amplifier: LIN+, LIN, RIN+, RIN pins; MDIF1 = MDIF2 bits = “1” (Full-differential input)
Input Voltage (Note 7)
MGAIN1-0 bits = “01”
0.37
Vpp
MGAIN1-0 bits = “10”
0.066
Vpp
MIC Power Supply: MPWR pin
Output Voltage (Note 8)
2.02
2.25
2.48
V
Load Resistance
0.5
k
Load Capacitance
30
pF
ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins (Single-ended inputs) ADC IVOL,
MGAIN=+15dB, IVOL=0dB, ALC=OFF
Resolution
16
Bits
MGAIN=+30dB
0.057
Vpp
Input Voltage (Note 9)
MGAIN=+15dB
0.27
0.32
0.37
Vpp
MGAIN=0dB
1.53
1.80
2.07
Vpp
67
77
dB
S/(N+D) (0.5dBFS) (Note 10)
79
87
dB
D-Range (60dBFS, A-weighted) (Note 11)
S/N (A-weighted) (Note 11)
79
87
dB
Interchannel Isolation (Note 12)
80
90
dB
MGAIN=+30dB
0.2
dB
Interchannel Gain Mismatch
MGAIN=+15dB
0.2
1.0
dB
MGAIN=0dB
0.2
0.5
dB
Power Supplies:
Power Supply Current: AVDD+DVDD
Power Up (PDN pin = “H”) (Note 13)
8
12
mA
Power Down (PDN pin = “L”) (Note 14)
1
20
A
Note 7. The voltage difference between LIN+/RIN+ and LIN/RIN pins. AC coupling capacitor should be connected in
series at each input pin. Full-differential input is not available at MGAIN1-0 bits = “00”. Maximum input voltage
of LIN+, LIN, RIN+ and RIN pins is proportional to AVDD voltage, respectively.
Vin = |(L/RIN+) (L/RIN)| = 0.123 x AVDD (max)@MGAIN1-0 bits = “01”, 0.022 x AVDD
(max)@MGAIN1-0 bits = “10”.
When the signal larger than above value is input to LIN+, LIN, RIN+ or RIN pin, ADC does not operate
normally.
Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ).
Note 9. Input voltage is proportional to AVDD voltage. Vin = 0.107 x AVDD (typ)@MGAIN1-0 bits = “01” (+15dB), Vin
= 0.6 x AVDD(typ)@MGAIN1-0 bits = “00” (0dB).
Note 10. 80dB(typ)@MGAIN=0dB, 70dB(typ)@MGAIN=+30dB
Note 11. 89dB(typ)@MGAIN=0dB, 77dB(typ)@MGAIN=+30dB
Note 12. 100dB(typ)@MGAIN=0dB, 80dB(typ)@MGAIN=+30dB
Note 13. PLL Master Mode (MCKI=12MHz), PMADL = PMADR = PMVCM = PMPLL = PMMP = M/S bits = “1” and
MCKO bit = “0”. MPWR pin outputs 0mA. AVDD=6.4mA(typ), DVDD=1.6mA(typ).
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=5.7mA(typ), DVDD=1.3mA(typ).
Bypass Mode (THR bit = “1”, PMADL = PMADR = M/S bits = “0”), fs=8kHz: AVDD=1A(typ),
DVDD=150A(typ).
Note 14. All digital input pins are fixed to DVDD or DVSS.
MS0404-E-05
2015/11
-6-
[AK5701]
FILTER CHARACTERISTICS
(Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V; fs=44.1kHz)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 15)
PB
0
17.4
kHz
0.1dB
20.0
kHz
1.0dB
21.1
kHz
3.0dB
Stopband (Note 15)
SB
25.7
kHz
Passband Ripple
PR
dB
0.1
Stopband Attenuation
SA
65
dB
Group Delay (Note 16)
GD
18
1/fs
Group Delay Distortion
0
GD
s
ADC Digital Filter (HPF): HPF1-0 bits = “00”
Frequency Response (Note 15) 3.0dB
FR
3.4
Hz
10
Hz
0.5dB
22
Hz
0.1dB
Note 15. The passband and stopband frequencies scale with fs (system sampling rate).
For example, PB=0.454*fs (@1.0dB). Each response refers to that of 1kHz.
Note 16. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data of both channels from the input register to the output register of the ADC. This time includes the group
delay of the HPF.
DC CHARACTERISTICS
(Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V)
Parameter
Symbol
Min.
Typ.
High-Level Input Voltage
Except CSP pin; 2.2V DVDD 3.6V
VIH
70DVDD
Except CSP pin; 1.6V DVDD ALC Output 6.0dBFS
0
ALC Output 6.0dBFS
6.0dBFS > ALC Output 8.5dBFS
1
ALC Output 8.5dBFS
8.5dBFS > ALC Output 12dBFS
Table 22. ALC Limiter Detection Level / Recovery Counter Reset Level
ZELMN
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
LMAT1
0
0
1
1
x
LMAT0
ALC Limiter ATT Step
0
1 step
0.375dB
1
2 step
0.750dB
0
4 step
1.500dB
1
8 step
3.000dB
x
1step
0.375dB
Table 23. ALC Limiter ATT Step
(default)
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 24. ALC Zero Crossing Timeout Period
MS0404-E-05
(default)
(default)
2015/11
- 35 -
[AK5701]
2.
ALC Recovery Operation
The ALC recovery operation waits for the WTM1-0 bits (Table 25) to be set after completing the ALC limiter operation.
If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 22) during the wait time, the ALC
recovery operation is executed. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 26) up
to the set reference level (Table 27) with zero crossing detection which is timeout period set by ZTM1-0 bits (Table 24).
Then the IVL and IVR are set to the same value for both channels. The ALC recovery operation is executed at a period set
by WTM1-0 bits. If ZTM1-0 is longer than WTM1-0 and no zero crossing occurs, the ALC recovery operation is executed
at a period set by ZTM1-0 bits.
For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to “01”, IVOL is changed to 32H by the auto
limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds the
reference level (REF7-0), the IVOL values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation
becomes faster than a normal recovery operation. When large noise is input to microphone instantaneously, the quality of
small level in the large noise can be improved by this fast recovery operation.
WTM1
WTM0
0
0
1
1
0
1
0
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 25. ALC Recovery Operation Waiting Period
RGAIN1
0
0
1
1
RGAIN0
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 26. ALC Recovery GAIN Step
(default)
(default)
REF7-0
GAIN(dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E2H
+30.375
E1H
+30.0
(default)
0.375dB
E0H
+29.625
:
:
03H
53.25
02H
53.625
01H
54.0
00H
MUTE
Table 27. Reference Level at ALC Recovery operation
MS0404-E-05
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[AK5701]
3.
Example of ALC Operation
Table 28 shows the examples of the ALC setting for mic recording.
Register Name
Comment
LMTH
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
WTM1-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
ALC
Data
01
0
00
Data
01
0
10
fs=44.1kHz
Operation
4.1dBFS
Enable
11.6ms
00
16ms
10
11.6ms
E1H
+30dB
E1H
+30dB
91H
0dB
91H
0dB
00
00
1
1 step
1 step
Enable
Gain of IVOL
Limiter ATT step
Recovery GAIN step
ALC enable
fs=8kHz
Operation
4.1dBFS
Enable
16ms
00
1 step
00
1 step
1
Enable
Table 28. Example of the ALC setting
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.
LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = 4.1dBFS
Manual Mode
WR (IVL/R7-0)
ALC bit = “1”
* The value of IVOL should be
(1) Addr=18H&19H, Data=91H
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0)
(2) Addr=1AH, Data=00H
WR (REF7-0)
(3) Addr=1BH, Data=E1H
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC= “1”)
(4) Addr=1CH, Data=81H
ALC Operation
Note : WR : Write
Figure 39. Registers set-up sequence at ALC operation
MS0404-E-05
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[AK5701]
■ Input Digital Volume (Manual Mode)
The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below.
1.
2.
3.
After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH and etc)
When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed.
For example; when the change of the sampling frequency.
When IVOL is used as a manual volume.
IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 29). The IVOL value is changed at zero crossing or
timeout. Zero crossing timeout period is set by ZTM1-0 bits.
If IVL7-0 or IVR7-0 bits are written during PMADL=PMADR bits = “0”, IVOL operation starts with the written values at
the end of the ADC initialization cycle after PMADL or PMADR bit is changed to “1”.
IVL7-0
IVR7-0
F1H
F0H
EFH
:
92H
91H
90H
:
03H
02H
01H
00H
GAIN (dB)
Step
+36.0
+35.625
+35.25
:
+0.375
0.0
0.375dB
0.375
:
53.25
53.625
54
MUTE
Table 29. Input Digital Volume Setting
MS0404-E-05
(default)
2015/11
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[AK5701]
When writing to the IVL7-0 and IVR7-0 bits continuouslly, the control register should be written in an interval more than
zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write operation. If
the same register value as the previous write operation is written to IVL and IVR, this write operation is ignored and zero
crossing counter is not reset. Therefore, IVL and IVR can be written in an interval less than zero crossing timeout.
ALC bit
ALC Status
Disable
Enable
Disable
IVL7-0 bits
E1H(+30dB)
IVR7-0 bits
C6H(+20dB)
Internal IVL
E1H(+30dB)
Internal IVR
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
(1)
E1(+30dB)
(2)
E1(+30dB) --> F1(+36dB)
C6H(+20dB)
Figure 40. IVOL value during ALC operation
(1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. The wait time from ALC
bit = “1” to ALC operation start by IVL7-0 bits is at most recovery time (WTM1-0 bits) plus zerocross timeout period
(ZTM1-0 bits).
(2) Writing to IVL and IVR registers (18H and 19H) is ignored during ALC operation. After ALC is disabled, the IVOL
changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1”
by an interval more than zero crossing timeout period after ALC bit = “0”.
■ System Reset
When power-up, the AK5701 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1”. The
initialization cycle time is 3088/fs=70.0ms@fs=44.1kHz when HPF1-0 bits are “00” (Table 30). During the initialization
cycle, the ADC digital data outputs of both channels are forced to a 2’s compliment, “0”. The ADC output reflects the
analog input signal after the initialization cycle is complete.
Init Cycle
fs=44.1kHz
fs=22.05kHz
70.0ms
140.0ms
HPF1 bit
HPF0 bit
0
0
3088/fs
0
1
1552/fs
35.2ms
1
0
784/fs
17.8ms
1
1
Cycle
(Recommendation)
70.4ms
(Recommendation)
35.6ms
N/A
N/A
N/A
Table 30. ADC Initialization Cycle (N/A: Not available)
MS0404-E-05
fs=11.025kHz
280.1ms
(default)
140.8ms
71.1ms
(Recommendation)
N/A
2015/11
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[AK5701]
■ Serial Control Interface
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The CSP pin selects the
polarity of the CSN pin and chip address.
1) CSP pin = “L”
The data on this interface consists of a 2-bit Chip address (Fixed to “10”), Read/Write (Fixed to “1”), Register address
(MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“”) of CCLK. Address
and data are latched on the 16th CCLK rising edge (“”) after CSN falling edge(“”). CSN should be set to “H” once after
16 CCLKs for each address. Clock speed of CCLK is 7MHz (max). The value of internal registers are initialized by the
PDN pin = “L”.
CSN
0
CCLK
CDTI
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Clock, “H” or “L”
Clock, “H” or “L”
“H” or “L”
“H” or “L”
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “1”, C0 = CAD0) ; Fixed to “10”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 41. Serial Control I/F Timing (CSP pin = “L”)
2) CSP pin = “H”
The data on this interface consists of a 2-bit Chip address (Fixed to “01”), Read/Write (Fixed to “1”), Register address
(MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“”) of CCLK. Address
and data are latched on the 16th CCLK rising edge (“”) after CSN rising edge(“”). CSN should be set to “L” once after
16 CCLKs for each address. Clock speed of CCLK is 7MHz (max). The value of internal registers are initialized by the
PDN pin = “L”.
CSN
0
CCLK
CDTI
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Clock, “H” or “L”
Clock, “H” or “L”
“H” or “L”
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
“H” or “L”
Chip Address (C1 = “0”, C0 = CAD1) ; Fixed to “01”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 42. Serial Control I/F Timing (CSP pin = “H”)
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[AK5701]
■ Register Map
Addr
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
Register Name
Power Management
PLL Control
Signal Select
Mic Gain Control
Audio Format Select
fs Select
Clock Output Select
Volume Control
Lch Input Volume Control
Rch Input Volume Control
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Mode Control 1
Mode Control 2
D7
0
0
0
0
0
HPF1
0
0
IVL7
IVR7
0
REF7
ALC
TE3
0
D6
0
0
0
0
0
HPF0
0
0
IVL6
IVR6
0
REF6
ZELMN
TE2
0
D5
0
PLL3
0
0
1
BCKO1
0
0
IVL5
IVR5
0
REF5
LMAT1
TE1
0
D4
0
PLL2
PMMP
0
MIX
BCKO0
0
0
IVL4
IVR4
0
REF4
LMAT0
TE0
0
D3
0
PLL1
MDIF2
0
MSBS
FS3
THR
0
IVL3
IVR3
ZTM1
REF3
RGAIN1
0
0
D2
PMVCM
PLL0
MDIF1
0
BCKP
FS2
MCKO
0
IVL2
IVR2
ZTM0
REF2
RGAIN0
0
0
D1
PMADR
M/S
INR
D0
PMADL
PMPLL
INL
MGAIN1
MGAIN0
DIF1
FS1
PS1
0
IVL1
IVR1
WTM1
REF1
LMTH1
0
DIF0
FS0
PS0
IVOLC
IVL0
IVR0
WTM0
REF0
LMTH0
0
0
TMASTER
Note 31. PDN pin = “L” resets the registers to their default values.
Note 32. “0” must be sent to the register written as “0” and “1” must be sent to the register written as “1”. For addresses
except for 10H to 1EH, data must not be written.
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[AK5701]
■ Register Definitions
Addr
10H
Register Name
Power Management
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
PMVCM
0
D1
PMADR
0
D0
PMADL
0
PMADL: MIC-Amp Lch and ADC Lch Power Management
0: Power down (default)
1: Power up
PMADR: MIC-Amp Rch and ADC Rch Power Management
0: Power down (default)
1: Power up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (3088/fs=70.0ms@fs=
44.1kHz, HPF1-0 bits = “00”) starts. After initializing, digital data of the ADC is output.
PMVCM: VCOM Power Management
0: Power down (default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only when
PMADL=PMADR=PMPLL=PMMP=MCKO bits = “0”.
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When PMVCM, PMADL, PMADR, PMPLL and MCKO bits are “0”, all blocks are powered-down. The register values
remain unchanged. Power supply current is 20A(typ) in this case. For fully shut down (typ. 1A), the PDN pin should
be “L”.
When the ADC is not used, external clocks may not be present. When ADC is used, external clocks must always be
present.
Addr
11H
Register Name
PLL Control
Default
D7
0
0
D6
0
0
D5
PLL3
1
D4
PLL2
0
D3
PLL1
0
D2
PLL0
1
D1
M/S
0
D0
PMPLL
0
PMPLL: PLL Power Management
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
PLL3-0: PLL Reference Clock Select (Table 4)
Default: “1001”(MCKI pin=12MHz)
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Addr
12H
Register Name
Signal Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
PMMP
0
D3
MDIF2
0
D2
MDIF1
0
D1
INR
0
D0
INL
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
D0
MGAIN1
MGAIN0
0
1
D4
MIX
0
D3
MSBS
0
D1
DIF1
1
D0
DIF0
1
INL: ADC Lch Input Source Select
0: LIN1 pin (default)
1: LIN2 pin
INR: ADC Rch Input Source Select
0: RIN1 pin (default)
1: RIN2 pin
MDIF1: ADC Lch Input Type Select
0: Single-ended input (LIN1/LIN2 pin: default)
1: Full-differential input (LIN+/LIN pin)
MDIF2: ADC Rch Input Type Select
0: Single-ended input (RIN1/RIN2 pin: default)
1: Full-differential input (RIN+/RIN pin)
PMMP: MPWR pin Power Management
0: Power down: Hi-Z (default)
1: Power up
Addr
13H
Register Name
Mic Gain Control
Default
D7
0
0
D6
0
0
MGAIN1-0: MIC-Amp Gain Control (Table 20)
Default: “01”(+15dB)
Addr
14H
Register Name
Audio Format Select
Default
D7
0
0
D6
0
0
D5
1
1
D2
BCKP
0
DIF1-0: Audio Interface Format (Table 15)
Default: “11” (I2S)
BCKP: BCLK/EXBCLK Polarity at DSP Mode (Table 16)
“0”: SDTO is output by the rising edge (“”) of BCLK/EXBCLK. (default)
“1”: SDTO is output by the falling edge (“”) of BCLK/EXBCLK.
MSBS: LRCK/EXLRCK Polarity at DSP Mode (Table 16)
“0”: The rising edge (“”) of LRCK/EXLRCK is half clock of BCLK/EXBCLK before the channel change. (default)
“1”: The rising edge (“”) of LRCK/EXLRCK is one clock of BCLK/EXBCLK before the channel change.
MIX: ADC Output Data Select (Table 17)
“0”: Normal operation (default)
“1”: (L+R)/2
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[AK5701]
Addr
15H
Register Name
fs Select
Default
D7
HPF1
0
D6
HPF0
0
D5
BCKO1
0
D4
BCKO0
1
D3
FS3
1
D2
FS2
1
D1
FS1
1
D0
FS0
1
FS3-0: Sampling Frequency Select (Table 5 and Table 6) and MCKI Frequency Select (Table 11)
Default: “1111” (44.1kHz)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKO1-0: BCLK Output Frequency Select at Master Mode (Table 10)
Default: “01” (32fs)
HPF1-0: Offset Cancel HPF Cut-off Frequency and ADC Initialization Cycle (Table 18, Table 30)
Default: “00” (fc=3.4Hz@fs=44.1kHz, Init Cycle=3088/fs)
Addr
16H
Register Name
Clock Output Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
THR
0
D2
MCKO
0
D1
PS1
0
D0
PS0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
IVOLC
1
PS1-0: MCKO Output Frequency Select (Table 9)
Default: “00”(256fs)
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
THR: Bypass Mode (Table 14)
0: OFF (default)
1: ON
Addr
17H
Register Name
Volume Control
Default
D7
0
0
D6
0
0
IVOLC: Input Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0
bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits
control Rch level, respectively.
Addr
18H
19H
Register Name
Lch Input Volume Control
Rch Input Volume Control
Default
D7
IVL7
IVR7
1
D6
IVL6
IVR6
0
D5
IVL5
IVR5
0
D4
IVL4
IVR4
1
D3
IVL3
IVR3
0
D2
IVL2
IVR2
0
D1
IVL1
IVR1
0
D0
IVL0
IVR0
1
IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 29)
Default: “91H” (0dB)
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[AK5701]
Addr
1AH
Register Name
Timer Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
ZTM1
0
D2
ZTM0
0
D1
WTM1
0
D0
WTM0
0
D2
REF2
0
D1
REF1
0
D0
REF0
1
D1
LMTH1
0
D0
LMTH0
0
WTM1-0: ALC Recovery Waiting Period (Table 25)
Default: “00” (128/fs)
ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 24)
Default: “00” (128/fs)
Addr
1BH
Register Name
ALC Mode Control 1
Default
D7
REF7
1
D6
REF6
1
D5
REF5
1
D4
REF4
0
D3
REF3
0
REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 27)
Default: “E1H” (+30.0dB)
Addr
1CH
Register Name
ALC Mode Control 2
Default
D7
ALC
0
D6
ZELMN
0
D5
LMAT1
0
D4
LMAT0
0
D3
D2
RGAIN1
RGAIN0
0
0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 22)
Default: “00”
RGAIN1-0: ALC Recovery GAIN Step (Table 26)
Default: “00”
LMAT1-0: ALC Limiter ATT Step (Table 23)
Default: “00”
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (default)
1: Disable
ALC: ALC Enable
0: ALC Disable (default)
1: ALC Enable
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[AK5701]
Addr
1DH
Register Name
Mode Control 1
Default
D7
TE3
1
D6
TE2
0
D5
TE1
1
D4
TE0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
D1
D0
0
0
TE3-0: EXT Master Mode Enable
When TE3-0 bits is set to “0101”, the write operation to addr=1EH is enabled.
TE3-0 bits should be set to “1010” except for EXT Master Mode.
TE3-0 bits must not be set to the value except for “1010” and “0101”.
Default: “1010”
Addr
1EH
Register Name
Mode Control 2
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
TMASTER
0
TMASTER: EXT Master Mode
The write operation to TMASTER bit is enabled when TE3-0 bits = “0101”.
0: Except EXT Master Mode (default)
1: EXT Master Mode
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[AK5701]
R2
SYSTEM DESIGN
Figure 43 and Figure 44 shows the system connection diagram for the AK5701. The
R1 evaluation board [AKD5701]
demonstrates the optimum layout, power supply arrangements and measurement results.
17
16
15
14
CSN
CCLK
CDTI
MCKI
21 LIN2
AK5701
22 RIN1
Top View
MCKO 10
BCLK
DSP
10u 0.1u
10u 0.1u
2.2u
Power Supply
2.4 3.6V
6
7
DVSS
LRCK
DVDD
24 VCOC
5
8
4
SDTO
AVDD
23 LIN1
3
2
9
Rp
Cp
11
CSP
0.1u
0.1 x Cp
(Note)
EXSDTI
AVSS
1u
20 RIN2
2
1u
Internal MIC
EXLRCK 12
VCOM
1u
DSP
19 MPWR
1
1u
External MIC
EXBCLK 13
18
2.2k
2.2k
2.2k
2.2k
PDN
P
Power Supply
1.6 3.6V
Analog Ground
Digital Ground
Notes:
- AVSS and DVSS of the AK5701 should be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK5701 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC pin is not needed.
- When the AK5701 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC pin is shown in Table
4. 0.1 x Cp in parallel with Cp+Rp improves PLL jitter characteristics.
- Mic input AC coupling capacitor should be 1F or less to start the recording within 100ms.
Figure 43. Typical Connection Diagram (MIC Input)
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R2
[AK5701]
R1
17
16
15
14
CSN
CCLK
CDTI
MCKI
20 RIN2
EXSDTI
21 LIN2
AK5701
22 RIN1
Top View
11
MCKO 10
DVSS
BCLK
6
DSP
10u 0.1u
10u 0.1u
2.2u
Power Supply
2.4 3.6V
5
7
DVDD
LRCK
AVDD
24 VCOC
4
8
3
2
SDTO
AVSS
23 LIN1
2
9
VCOM
CSP
Rp
Cp
EXBCLK 13
18
EXLRCK 12
0.1u
0.1 x Cp
(Note)
DSP
19 MPWR
1
Line In
PDN
P
Power Supply
1.6 3.6V
Analog Ground
Digital Ground
Notes:
- AVSS and DVSS of the AK5701 should be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK5701 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC pin is not needed.
- When the AK5701 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC pin is shown in Table
4. 0.1 x Cp in parallel with Cp+Rp improves PLL jitter characteristics.
Figure 44. Typical Connection Diagram (Line Input)
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[AK5701]
1. Grounding and Power Supply Decoupling
The AK5701 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually
supplied from the system’s analog supply. If AVDD and DVDD are supplied separately, the power-up sequence is not
critical. AVSS and DVSS of the AK5701 should be connected to the analog ground plane. System analog ground and
digital ground should be connected together near to where the supplies are brought onto the printed circuit board.
Decoupling capacitors should be as near to the AK5701 as possible, with the small value ceramic capacitor being the
nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2F electrolytic capacitor in parallel with a 0.1F ceramic capacitor attached to
the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5701.
3. Analog Inputs
The analog inputs are single-ended or full-differential and input resistance is 60k (typ)@MGAIN1-0 bits = “00”, 30k
(typ)@MGAIN1-0 bits = “01” or “10”. The input signal range scales with 0.6 x AVDD Vpp(typ)@MGAIN 1-0 bits = “00”
centered around the internal common voltage (0.5 x AVDD). Usually the input signal is AC coupled using a capacitor. The
cut-off frequency is fc = 1/(2RC). The ADC output data format is 2’s complement. The DC offset including the ADC’s
own DC offset is removed by the internal HPF (fc=3.4Hz@ HPF1-0 bits = “00”, fs=44.1kHz). The AK5701 can accept
input voltages from AVSS to AVDD at single-ended.
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[AK5701]
CONTROL SEQUENCE
■ Clock Set up
When ADC is powered-up, the clocks must be supplied.
1. PLL Master Mode.
Example:
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:10H, D2)
(1) Power Supply & PDN pin = “L” “H”
(4)
MCKO bit
(Addr:16H, D2)
(2)Addr:11H, Data:12H
Addr:14H, Data:23H
Addr:15H, Data:2FH
PMPLL bit
(Addr:11H, D0)
(5)
MCKI pin
Input
(3)Addr:10H, Data:04H
M/S bit
(Addr:11H, D1)
40msec(max)
(6)
BCLK pin
LRCK pin
Output
(4)Addr:16H, Data:04H
Addr:11H, Data:13H
Output
MCKO, BCLK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 45. Clock Set Up Sequence (1)
(1) After Power Up, PDN pin “L” “H”
“L” time of 150ns or more is needed to reset the AK5701.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period as follows.
(2a) M/S bit = “1” and setting of PLL3-0, FS3-0, BCKO1-0 bits.
(2b) Setting of DIF1-0 bits.
(3) Power UpVCOM: PMVCM bit = “0” “1”
VCOM should first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL operation starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source.
PLL lock time is 40ms(max) at MCKI=12MHz (Table 4).
(6) The AK5701 starts to output the LRCK and BCLK clocks after the PLL becomes stable. Then normal operation
starts.
(7) The invalid frequency is output from the MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from the MCKO pin after the PLL is locked if MCKO bit = “1”.
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2. PLL Slave Mode (EXLRCK or EXBCLK pin)
Example:
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
Power Supply
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” “H”
(3)
PMVCM bit
(Addr:10H, D2)
(2) Addr:11H, Data:0CH
Addr:14H, Data:23H
Addr:15H, Data:2FH
PMPLL bit
(Addr:11H, D0)
EXLRCK pin
EXBCLK pin
Input
(3) Addr:10H, Data:04H
(4)
Internal Clock
(5)
(4) Addr:11H, Data:0DH
Figure 46. Clock Set Up Sequence (2)
(1) After Power Up: PDN pin “L” “H”
“L” time of 150ns or more is needed to reset the AK5701.
(2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” “1”
VCOM should first be powered up before the other block operates.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (EXLRCK or EXBCLK pin) is
supplied. PLL lock time is 160ms(max) when EXLRCK is a PLL reference clock. PLL lock time is 2ms(max)
when EXBCLK is a PLL reference clock and the external circuit at the VCOC pin is 10k+4.7nF (Table 4).
(5) Normal operation stats after that the PLL is locked.
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[AK5701]
3. PLL Slave Mode (MCKI pin)
Example:
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” “H”
(1)
PDN pin
(2)
(2)Addr:11H, Data:10H
Addr:14H, Data:23H
Addr:15H, Data:2FH
(3)
PMVCM bit
(Addr:10H, D2)
(4)
MCKO bit
(Addr:16H, D2)
(3)Addr:10H, Data:04H
PMPLL bit
(Addr:11H, D0)
(5)
MCKI pin
(4)Addr:16H, Data:04H
Addr:11H, Data:11H
Input
40msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
EXBCLK pin
EXLRCK pin
Input
EXBCLK and EXLRCK input start
Figure 47. Clock Set Up Sequence (3)
(1) After Power Up: PDN pin “L” “H”
“L” time of 150ns or more is needed to reset the AK5701.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” “1”
VCOM should first be powered up before the other block operates.
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 40ms(max) at MCKI=12MHz (Table 4).
(6) The normal clock is output from MCKO after PLL is locked.
(7) The invalid frequency is output from MCKO during this period.
(8) EXBCLK and EXLRCK clocks should be synchronized with MCKO clock.
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4. EXT Slave Mode
Example:
: Audio I/F Format: I2S
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
(1) Power Supply & PDN pin = “L” “H”
Power Supply
(1)
PDN pin
(2)
(2) Addr:11H, Data:00H
Addr:14H, Data:23H
Addr:15H, Data:2FH
(3)
PMVCM bit
(Addr:10H, D2)
(4)
MCKI pin
Input
(3) Addr:10H, Data:04H
(4)
EXLRCK pin
EXBCLK pin
Input
MCKI, EXBCLK and EXLRCK input
Figure 48. Clock Set Up Sequence (4)
(1) After Power Up: PDN pin “L” “H”
“L” time of 150ns or more is needed to reset the AK5701.
(2) DIF1-0 and FS1-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” “1”
VCOM should first be powered up before the other block operates.
(4) Normal operation starts after the MCKI, EXLRCK and EXBCLK are supplied.
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5. EXT Master Mode
Power Supply
(1)
Example:
PDN pin
(2)
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select: 256fs
Sampling Frequency: 44.1kHz
(3)
PMVCM bit
(Addr:10H, D2)
MCKI pin
(1) Power Supply & PDN pin = “L” “H”
Input
M/S bit
(Addr:11H, D1)
TE3-0 bits
(Addr:1DH, D7-4)
"1010"
(2)Addr:11H, Data:26H
Addr:14H, Data:23H
Addr:15H, Data:2FH
Addr:1DH, Data:50H
Addr:1EH, Data:02H
BCLK and LRCK output
"0101"
TMASTER bit
(Addr:1EH, D1)
BCLK pin
LRCK pin
Output
(3)Addr:10H, Data:04H
Figure 49. Clock Set Up Sequence (5)
(1) After Power Up: PDN pin “L” “H”
“L” time of 150ns or more is needed to reset the AK5701.
(2) DIF1-0, FS1-0, BCKO1-0, M/S, TE3-0 and TMASTER bits should be set during this period as follows.
(2a) M/S bit = “1”, setting of FS3-0 and BCKO1-0 bits.
(2b) Setting of DIF1-0 bits.
(2c) TE3-0 bits = “0101”
(2d) TMASTER bit = “1”: BCLK and LRCK start to output.
(3) Power Up VCOM: PMVCM bit = “0” “1”
VCOM should first be powered up before the other block operates.
When the clock mode is changed from EXT Master Mode to other modes, the register should be set as Table 1 after PDN
pin = “L” to “H” or TE3-0 bits = “1010”.
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6. Slave & Bypass Mode
Example:
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
Power Supply
(1)
4fs
(1)ofPower Supply & PDN pin = “L” “H”
PDN pin
(2)
(3)
PMVCM bit
(2) Addr:11H, Data:0CH
Addr:14H, Data:23H
Addr:15H, Data:2FH
Addr:16H, Data:08H
(Addr:10H, D2)
PMPLL bit
(Addr:11H, D0)
EXLRCK pin
EXBCLK pin
Input
(3) Addr:10H, Data:04H
(4)
Internal Clock
(5)
(4) Addr:11H, Data:0DH
Figure 50. Clock Set Up Sequence (6)
(1) After Power Up: PDN pin “L” “H”
“L” time of 150ns or more is needed to reset the AK5701.
(2) THR bit should be set to “1” and DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” “1”
VCOM should first be powered up before the other block operates.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (EXLRCK or EXBCLK pin)
is supplied. PLL lock time is 160ms(max) when EXLRCK is a PLL reference clock. PLL lock time is 2ms(max)
when EXBCLK is a PLL reference clock and the external circuit at VCOC pin is 10k+4.7nF (Table 4).
(5) Normal operation stats after that the PLL is locked.
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7. Bypass Mode
Power Supply
(1)
(1) Power Supply & PDN pin = “L” “H”
PDN pin
(2)
THR bit
(2) Addr:16H, Data:08H
(Addr:16H, D3)
EXLRCK pin
EXBCLK pin
EXSDTI pin
(3)
Input
MCKI, EXBCLK and EXLRCK input
Figure 51. Clock Set Up Sequence (7)
(1) After Power Up: PDN pin “L” “H”
“L” time of 150ns or more is needed to reset the AK5701.
(2) THR bit should be set to “1”.
(3) After EXLRCK, EXBCLK and EXSDTI are input, LRCK, BCLK and SDTO start to output.
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MIC Input Recording (Stereo)
Example:
PLL Master Mode
Audio I/F Format:I2S
Sampling Frequency:44.1kHz
Pre MIC AMP:+15dB
MIC Power On
ALC setting:Refer to Figrure 37
ALC bit = “1”
(1) Addr:15H, Data:2FH
FS3-0 bits
(Addr:15H, D3-0)
X,XXX
1111
(2) Addr:12H, Data:10H
Addr:13H, Data:01H
(1)
MIC Control
(Addr:12H, D4
& Addr:13H, D1-0)
Timer Control
(Addr:1AH)
ALC Control 1
(Addr:1BH)
ALC Control 2
(Addr:1CH)
0, 01
1, 01
(3) Addr:1AH, Data:0AH
(2)
XXH
0AH
(4) Addr:1BH, Data:E1H
(3)
XXH
E1H
(5) Addr:1CH, Data:81H
(4)
XXH
81H
01H
(5)
ALC State
(8)
ALC Disable
ALC Enable
ALC Disable
(6) Addr:10H, Data:07H
Recording
PMADL/R bit
(Addr:10H, D1-0)
3088 / fs
(7) Addr:10H, Data:04H
(7)
(6)
ADC Internal
State
Power Down
Initialize Normal State Power Down
(8) Addr:1CH, Data:01H
Figure 52. MIC Input Recording Sequence
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to
“Figure 39”.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bit). When the AK5701 is PLL mode, MIC and ADC should be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC input (Addr: 12H&13H)
(3) Set up Timer Select for ALC (Addr: 1AH)
(4) Set up REF value for ALC (Addr: 1BH)
(5) Set up LMTH1-0, RGAIN1-0, LMAT1-0 and ALC bits (Addr: 1CH)
(6) Power Up MIC and ADC: PMADL = PMADR bits = “0” “1”
The initialization cycle time of ADC is 3088/fs=70.0ms@fs=44.1kHz, HPF1-0 bits = “00”.
After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL default
value (0dB).
To start the recording within 100ms, the following sequence is required.
(6a) PMVCM=PMMP bits = “1”.
(6b) Wait for 2ms, then PMPLL bit = “1”.
(6c) Wait for 6ms, then PMADL=PMADR bits = “1”.
(7) Power Down MIC and ADC: PMADL = PMADR bits = “1” “0”
When the registers for the ALC operation are not changed, ALC bit may be kept as “1”. The ALC operation is
disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed
when the sampling frequency is changed, it should be executed after the AK5701 goes to the manual mode (ALC
bit = “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when
PMADL=PMADR bits = “0”, and then IVOL operation starts from the setting value when PMADC or PMADR
bit is changed to “1”.
(8) ALC Disable: ALC bit = “1” “0”
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■ Stop of Clock
Master clock can be stopped when ADC is not used.
1. PLL Master Mode
Example:
(1)
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
PMPLL bit
(Addr:11H, D0)
M/S bit
(Addr:11H, D1)
(1) Addr:11H, Data:10H
(2)
MCKO bit
"H" or "L"
(2) Addr:16H, Data:00H
(Addr:16H, D2)
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 53. Clock Stopping Sequence (1)
(1) Power down PLL: PMPLL=M/S bits = “1” “0”
(2) Stop MCKO clock: MCKO bit = “1” “0”
(3) Stop an external master clock.
2. PLL Slave Mode (EXLRCK, EXBCLK pin)
Example
: Audio I/F Format : I2S
(1)
PLL Reference clock: EXBCLK
BCLK frequency: 64fs
Sampling Frequency: 44.1kHz
PMPLL bit
(Addr:11H, D0)
(2)
EXBCLK
Input
(1) Addr:11H, Data:0CH
(2)
EXLRCK
Input
(2) Stop the external clocks
Figure 54. Clock Stopping Sequence (2)
(1) Power down PLL: PMPLL bit = “1” “0”
(2) Stop the external EXBCLK and EXLRCK clocks
* Clock stop sequence is the same for Slave&Bypass Mode.
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3. PLL Slave Mode (MCKI pin)
Example
: Audio I/F Format: I2S
PLL Reference clock: MCKI= 11.2896MHz
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(1) Addr:11H, Data:10H
(Addr:11H, D0)
(2)
MCKO bit
(2) Addr:16H, Data:00H
(Addr:16H, D2)
(3)
External MCKI
Input
(3) Stop the external clocks
Figure 55. Clock Stopping Sequence (3)
(1) Power down PLL: PMPLL bit = “1” “0”
(2) Stop MCKO output: MCKO bit = “1” “0”
(3) Stop the external master clock.
4. EXT Slave Mode
(1)
External MCKI
Input
Example
: Audio I/F Format :I2S
(1)
EXBCLK
Input
EXLRCK
Input
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1)
(1) Stop the external clocks
Figure 56. Clock Stopping Sequence (4)
(1) Stop the external MCKI, EXBCLK and EXLRCK clocks.
* Clock stop sequence is the same for Bypass Mode.
5. EXT Master Mode
(1)
External MCKI
Input
Example
: Audio I/F Format :I2S
BCLK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1) Stop MCKI
Figure 57. Clock Stopping Sequence (5)
(1) Stop MCKI. BCLK and LRCK are fixed to “H” or “L”.
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[AK5701]
■ Power down
Power supply current is typ. 20A by stopping clocks and setting PMVCM bit = “0” after all blocks except for VCOM are
powered-down. Power supply current can be shut down (typ. 1A) by stopping clocks and setting the PDN pin = “L”.
When the PDN pin = “L”, the registers are initialized.
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[AK5701]
PACKAGE
●24-pin QFN (Unit: mm)
[Part A Detail]
Part A
Note) The exposed pad on the bottom surface of the package must be open or connected to the ground.
■ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
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[AK5701]
MARKING
AK5701VN
5701
XXXXX
1
XXXXX: Date code identifier (5 digits)
AK5701KN
5701K
XXXXX
1
XXXXX: Date code identifier (5 digits)
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[AK5701]
REVISION HISTORY
Date (YY/MM/DD)
05/08/04
05/11/22
Revision
00
01
Reason
First Edition
Error correction
Page
Contents
8
Switching Characteristics (PLL Slave Mode)
tBCKL(min): 240ns 0.4 x tBCK
tBCKH(min): 240ns 0.4 x tBCK
PLL Slave Mode
a) Mode 1: EXBCLK or EXLRCK MCKI
b) Mode 2: MCKI EXBCLK or EXLRCK
ALC Operation
The sentence of “The IVL and IVR are then set to
the same value for both channels.” was deleted.
Control Sequence (MIC Recording)
Figure 51 (7) Data=01H 04H
(2) 72H&73H 12H&13H
(3) 7AH 1AH
(4) 7BH 1BH
(5) 7CH 1CH
AK5701KN was added.
(1) Ambient Temperature
AK5701VN : 30 +85C
AK5701KN : 40 +85C
(2) Marking
AK5701VN : “5701”
AK5701KN : “5701K”
1. Control Interface Timing(CSP pin = “L”)
(1) CSN “” to CCLK “”
→ CSN Edge to CCLK “”
(2) CCLK “” to CSN “”
→ CCLK “” to CSN Edge
2. Control Interface Timing(CSP pin = “H”)
(1) CSN “” to CCLK “”
→ CSN Edge to CCLK “”
(2) CCLK “” to CSN “”
→ CCLK “” to CSN Edge
3. Note 22 was added.
Figure 26 Figure 29 :
ECTBCLK(32fs)/BCLK(32fs)
No of 1st bit in Fugure 15 → 31
Figure 30 Figure 33 : BCLK(64fs)
No of 1st bit in Fugure : 15 → 31
Serial Control I/F
1. CSP pin = “L”
“CSN should be set to “H” once after 16 CCLKs for
each address.” was added.
2. CSP pin = “H”
“CSN should be set to “L” once after 16 CCLKs for
each address.” was added.
“12. AEC-Q100 Qualified (AK5701KN)” is
added.
PACAGE, MARKING
Package dimensions and Marking were changed.
PACAGE, MARKING
Japanese characters were deleted.
“X” was added to each marking description.
25
35
57
07/08/30
02
Product
Addition
1, 3, 5,
62
Spec Addition
11
Error Correction
30
31
13/02/22
03
15/10/30
04
15/11/27
05
Spec Addition
40
Comment
Addition
Specification
Change
Error Correction
1
61, 62
61, 62
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[AK5701]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of AKM or any third party with respect to the information in
this document. You are fully responsible for use of such information contained in this document in your
product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY
YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR
PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human
life, bodily injury, serious property damage or serious public impact, including but not limited to,
equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,
equipment used to control combustions or explosions, safety devices, elevators and escalators, devices
related to electric power, and equipment used in finance-related fields. Do not use Product for the above
use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in
this document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not
be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or
extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
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