[AK5388]
AK5388
120dB 24-bit 192kHz 4-Channel ADC
GENERAL DESCRIPTION
The AK5388 is a 24bit, 216kHz sampling 4-channel A/D converter for high-end audio systems. The
modulator in the AK5388 uses AKM’s Enhanced Dual Bit architecture, enabling the AK5388 to realize
high accuracy and low cost. The AK5388 achieves 120dB dynamic range and 110dB S/(N+D), and an
optional mono mode extends dynamic range to 123dB. The AK5388’s digital filter features a modified FIR
architecture that minimizes group delay while maintaining excellent linear phase response. So the device
is suitable for professional audio applications including recording, sound reinforcement, effects
processing, sound cards, and high-end A/V receivers. The AK5388 is available in 44pin LQFP package.
FEATURES
Sampling Rate: 8kHz ~ 216kHz
Full Differential Inputs
S/(N+D): 110dB
DR, S/N: 120dB(Mono Mode: 123dB)
Short Delay Digital Filter (GD=12.6/fs)
• Passband: 0~21.648kHz (@fs=48kHz)
• Ripple: 0.01dB
• Stopband: 80dB
Digital HPF
Power Supply: 4.75 ~ 5.25V(Analog), 3.0 ~ 3.6V(Digital)
Output format: 24bit MSB justified, I2S or TDM
Cascade TDM I/F: 8ch/48kHz, 4ch/96kHz, 4ch/192kHz
Master & Slave Mode
Overflow Flag
Power Dissipation: 575 mW (@fs=48kHz)
Package: 44pin LQFP
AVDD1 VSS1 AVDD2 VSS6 DVDD1 VSS3
LIN1+
LIN1RIN1+
RIN1LIN2+
LIN2-
ΔΣ
Modulator
Decimation
Filter
ΔΣ
Modulator
Decimation
Filter
ΔΣ
Modulator
Decimation
Filter
ΔΣ
Modulator
Decimation
Filter
DVDD2 VSS4 VSS5
LRCK
BICK
SDTO1
SDTO2
Audio
Interface
TDMIN
MSN
DIF
TDM0
RIN2+
RIN2-
TDM1
HPF
MONO
VCOM1
VCOM2
Voltage Reference
Clock Divider
VREFP1 VREFL1 VREFP2
VREFL2 OVF
MS1096-E-01
PDN
MCLK
CKS0 CKS2 CKS2
2009/08
-1-
[AK5388]
■ Ordering Guide
AK5388EQ
AKD5388
–10 ~ +70°C
44pin LQFP (0.8mm pitch)
Evaluation Board for AK5388
RIN2+
RIN2-
VSS6
AVDD2
TEST2
VSS5
VSS4
DVDD2
HPFE
MONO
DIF
33
32
31
30
29
28
27
26
25
24
23
■ Pin Layout
34
22
TDM1
VREFL 2
35
21
TDM0
VC OM 2
36
20
TDMIN
L IN2+
37
19
OVF
18
SDTO2
17
SDTO1
16
VSS3
VREFP2
L IN2-
38
TEST3
39
R IN1-
40
AK5388EQ
Top Vie w
10
11
9
C KS2
PDN
8
CKS1
MS1096-E-01
M/SN
7
C KS0
5
LIN1+
6
MCL K
VSS2
BICK
12
TEST1
13
4
43
44
AVDD1
VREFL 1
VREFP1
3
LRCK
2
DVDD1
14
LIN1-
15
VSS1
41
42
1
RIN1+
VC OM 1
2009/08
-2-
[AK5388]
PIN / FUNCTION
No.
1
2
3
4
5
6
7
8
9
Pin Name
LIN1+
LIN1−
VSS1
AVDD1
TEST1
VSS2
CKS0
CKS1
CKS2
I/O
I
I
I
10
PDN
I
11
MSN
I
12
MCLK
I
13
BICK
I/O
14
LRCK
I/O
15
16
DVDD1
VSS3
-
17
SDTO1
O
18
SDTO2
O
19
OVF
O
20
TDMIN
I
21
TDM0
I
22
TDM1
I
23
DIF
I
24
MONO
I
25
HPFE
I
26
27
28
DVDD2
VSS4
VSS5
-
I
I
I
Function
ADC1 Lch Positive Analog Input Pin
ADC1 Lch Negative Analog Input Pin
Ground Pin
Analog Power Supply Pin, 4.75 ∼ 5.25V
Test Pin
(Connected to VSS1-6)
Ground pin
Clock Mode Select #0 Pin
Clock Mode Select #1 Pin
Clock Mode Select #2 Pin
Power-Down Mode Pin
When “L”, the circuit is in power-down mode.
The AK5388should always be reset upon power-up.
Master/Slave mode Select Pin
“L”: Slave mode, “H”: Master mode
Master Clock Input Pin
Audio Serial Data Clock Pin
“L” Output in Master Mode at Power-down mode.
Output Channel Clock Pin
“L” Output in Master Mode at Power-down mode.
Digital Power Supply Pin, 3.0 ∼ 3.6V
Ground Pin
ADC1 Audio Serial Data Output Pin
“L” Output at Power-down mode.
ADC2 Audio Serial Data Output Pin
“L” Output at Power-down mode.
Analog Input Overflow Detect Pin
This pin goes to “H” if any analog inputs overflows.
“L” Output at Power-down mode.
TDM Data Input Pin
TDM I/F Format Enable Pin
“L” : Normal Mode, “H” : TDM Mode
TDM I/F BICK Frequency Select Pin
“L” : Normal Mode, “H” : TDM Mode
Audio Interface Format Pin
“L”: 24BitMSB justified, “H”: 24BitI2S Compatible
Stereo/Mono mode Select Pin
“L”: Stereo mode, “H”: Mono mode
HPF Enable Pin
“L”: Disable, “H” Enable
Digital Power Supply Pin, 3.0 ∼ 3.6V
Ground Pin
Ground pin
MS1096-E-01
2009/08
-3-
[AK5388]
No. Pin Name
29 TEST2
30 AVDD2
31 VSS6
32 RIN2−
33 RIN2+
34 VREFP2
35 VREFL2
I/O
I
I
I
I
I
36
VCOM2
O
37
38
39
40
41
LIN2+
LIN2−
TEST3
RIN1−
RIN1+
I
I
I
I
I
42
VCOM1
O
43
44
VREFL1
VREFP1
I
I
Function
Test Pin
(Connected to VSS1-6)
Analog Power Supply Pin, 4.75 ∼ 5.25V
Ground Pin
ADC2 Rch Negative Analog Input Pin
ADC2 Rch Positive Analog Input Pin
ADC2 High Level Voltage Reference Input Pin
ADC2 Low Level Voltage Reference Input Pin
Common Voltage Output Pin, (AVDD2)/2
Normally connected to AVSS2 with a 0.1μF ceramic capacitor in parallel with an
electrolytic capacitor less than 2.2μF.
ADC2 Lch Positive Analog Input Pin
ADC2 Lch Negative Analog Input Pin
Test Pin
(Connected to VSS1-6)
ADC1 Rch Negative Analog Input Pin
ADC1 Rch Positive Analog Input Pin
Common Voltage Output Pin, (AVDD1)/2
Normally connected to AVSS1 with a 0.1μF ceramic capacitor in parallel with an
electrolytic capacitor less than 2.2μF.
ADC1 Low Level Voltage Reference Input Pin
ADC1 High Level Voltage Reference Input Pin
Note: All digital input pins should not be left floating.
MS1096-E-01
2009/08
-4-
[AK5388]
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
LIN1+/−, RIN1+/−
LIN2+/−, RIN+/−
OVF
TEST1
TEST2
TEST3
Setting
These pins should be connected to VSS1-6
These pins should be connected to VSS1-6
This pin should be open.
This pin should be connected to VSS1-6
This pin should be connected to VSS1-6
This pin should be connected to VSS1-6
ABSOLUTE MAXIMUM RATINGS
(VSS1-6=0V; Note 1)
Parameter
Power
Supplies:
Analog
Analog
Digital
Digital Output Buffer
Symbol
min
max
Units
AVDD1
AVDD2
DVDD1
DVDD2
−0.3
−0.3
−0.3
−0.3
6.0
6.0
6.0
6.0
V
V
V
V
IIN
VINA
VINA
VIND
VIND
Ta
Tstg
−
−0.3
−0.3
−0.3
−0.3
−10
−65
±10
AVDD1+0.3
AVDD2+0.3
DVDD1+0.3
DVDD2+0.3
70
150
mA
Input Current, Any Pin Except Supplies
Analog Input Voltage (Note 2)
Digital Input Voltage (Note 3)
Ambient Temperature (power applied)
Storage Temperature
V
V
°C
°C
Note 1. All voltages with respect to VSS1-6 pins.
Note 2. VREFP1, VREFP2, VREFL1, VREFL2, AINL1/2+, AINL1/2-, AINR1/2+ and AINR1/2- pins
Note 3. PDN, CKS0, CKS1, CKS2, TDMIN, MCLK, BICK, LRCK, DIF, TDM0, TDM1, HPFE, MONO and TST1/2/3
pins
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
MS1096-E-01
2009/08
-5-
[AK5388]
RECOMMENDED OPERATING CONDITIONS
(VSS1-6=0V; Note 1)
Parameter
Power Supplies:
(Note 4)
Voltage Reference
(Note 5)
Analog
Analog
Digital
“H” voltage Reference
“L” voltage reference
VREFP1 – VREFL1
VREFP2 – VREFL2
Symbol
min
typ
max
Units
AVDD1
AVDD2
DVDD1/2
VREFP1
VREFP2
VREFL1
VREFL2
ΔVREF
ΔVREF
4.75
4.75
3.0
AVDD1-0.5
AVDD2-0.5
VSS1-6
VSS1-6
AVDD1-0.5
AVDD2-0.5
5.0
5.0
3.3
-
5.25
5.25
3.6
AVDD1
AVDD2
AVDD1
AVDD2
V
V
V
V
V
V
V
V
V
Note 1. All voltages with respect to VSS1-6 pins.
Note 4. The power up sequence between AVDD1/2 and DVDD1/2 is not critical.
Note 5. VREFL– and VREFR– pins should be connected to VSS1-6 pins.
Analog input voltage scales with voltage of {(VREFP) – (VREFL)}.
Vin (typ, @ 0dB) = ±2.8 x {(VREF+) – (VREF–)} / 5 [V].
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1096-E-01
2009/08
-6-
[AK5388]
ANALOG CHARACTERISTICS
(Ta = 25°C; AVDD1/2=5.0V; DVDD1/2=3.3V; VSS1-6=0V; VREFP1=VREFP2=AVDD, VREFL1 = VREFL2 =
VSS1-6; fs=48kHz, 96kHz, 192kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=10Hz ∼
20kHz at fs = 48kHz, 40Hz ∼ 40kHz at fs = 96kHz, 40Hz ∼ 40kHz at fs = 192kHz; unless otherwise specified)
Parameter
min
typ
max
Units
Analog Input Characteristics:
Resolution
24
Bits
Input Voltage
(Note 6)
±2.7
±2.8
±2.9
Vpp
−1dBFS
100
110
dB
S/(N+D)
fs=48kHz
−20dBFS
97
dB
BW=20kHz
−60dBFS
57
dB
−1dBFS
97
107
dB
fs=96kHz
−20dBFS
90
dB
BW=40kHz
−60dBFS
50
dB
−1dBFS
107
dB
fs=192kHz
−20dBFS
90
dB
BW=40kHz
−60dBFS
50
dB
Stereo Mode
Dynamic Range
114
120
dB
Mono Mode
(−60dBFS with A-weighted)
123
Stereo Mode
S/N
114
120
dB
Mono Mode
(A-weighted)
123
Input Resistance
3.3
3.7
4.1
kΩ
Interchannel Isolation
110
120
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Power Supply Rejection
(Note 7)
60
dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
mA
130
105
AVDD1/2
mA
22
15
DVDD
(fs=48kHz)
mA
39
27
DVDD
(fs=96kHz)
mA
29
20
DVDD
(fs=192kHz)
Power down mode (PDN pin = “L”)
(Note 8)
μA
100
10
AVDD+DVDD
Note 6. This value is (LIN+)−(LIN−) and (RIN+)−(RIN−). Input voltage is proportional to VREF voltage.
Vin = 0.56 x VREF1/2 (Vpp).
Note 7. PSR is applied to AVDD1/2 and DVDD1/2 with 1kHz, 20mVpp. The VREFP1 and VREFP2 pins held a constant
voltage.
Note 8. All digital input pins are held DVDD1/2 or VSS3/4.
MS1096-E-01
2009/08
-7-
[AK5388]
FILTER CHARACTERISTICS (fs=48kHz)
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V; DFS1 = “L”, DFS0 = “L”)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 9)
−0.01dB
PB
0
−0.1dB
22.0
−3.0dB
23.8
−6.0dB
24.4
Stopband
SB
27.9
Passband Ripple
PR
Stopband Attenuation
SA
80
Group Delay
(Note 10)
GD
12.6
Group Delay Distortion
ΔGD
±0.01
ADC Digital Filter (HPF):
Frequency Response (Note 9)
−3dB
FR
1.0
−0.1dB
6.5
max
Units
21.6
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
±0.01
Hz
Hz
FILTER CHARACTERISTICS (fs=96kHz)
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V; DFS1 = “L”, DFS0 = “H”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband
(Note 9) −0.01dB
PB
0
43.3
kHz
−0.1dB
44.2
kHz
−3.0dB
47.6
kHz
−6.0dB
48.9
kHz
Stopband
SB
55.9
kHz
Passband Ripple
PR
±0.01
dB
Stopband Attenuation
SA
80
dB
Group Delay
(Note 10)
GD
12.6
1/fs
Group Delay Distortion
ΔGD
±0.013
μs
ADC Digital Filter (HPF):
Frequency Response (Note 9)
−3dB
FR
1.0
Hz
−0.1dB
6.5
Hz
Note 9. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.
Note 10. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC.
MS1096-E-01
2009/08
-8-
[AK5388]
FILTER CHARACTERISTICS (fs=192kHz)
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V; DFS1 = “H”, DFS0 = “L”)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 11) −0.08dB
PB
−0.1dB
83.4
−3.0dB
99.9
−6.0dB
106.5
Stopband
SB
141.1
Passband Ripple
PR
Stopband Attenuation
SA
80
Group Delay
(Note 12)
GD
9.8
Group Delay Distortion
ΔGD
0
ADC Digital Filter (HPF):
Frequency Response (Note 11) −3dB
FR
1.0
−0.1dB
6.5
max
Units
83.0
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
±0.08
Hz
Hz
Note 11. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.
Note 12. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC.
DC CHARACTERISTICS
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V)
Parameter
Symbol
min
70%DVDD1
VIH
High-Level Input Voltage
70%DVDD2
VIL
Low-Level Input Voltage
High-Level Output Voltage
(Iout=−400μA)
VOH
Low-Level Output Voltage
Input Leakage Current
(Iout=400μA)
VOL
Iin
MS1096-E-01
DVDD1−0.4
DVDD2−0.4
-
typ
-
Max
30%DVDD1
30%DVDD2
0.4
±10
Units
V
V
V
V
V
V
V
μA
2009/08
-9-
[AK5388]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD1/2=4.75 ∼ 5.25V; DVDD1/2=3.0 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
1.024
fCLK
Master Clock
128fs:
0.4fCLK
tCLKL
Pulse Width Low
0.4fCLK
tCLKH
Pulse Width High
1.536
fCLK
192fs:
0.4fCLK
tCLKL
Pulse Width Low
0.4fCLK
tCLKH
Pulse Width High
2.048
fCLK
256fs:
0.4fCLK
tCLKL
Pulse Width Low
0.4fCLK
tCLKH
Pulse Width High
3.072
fCLK
384fs:
0.4fCLK
tCLKL
Pulse Width Low
0.4fCLK
tCLKH
Pulse Width High
4.096
fCLK
512fs:
0.4fCLK
tCLKL
Pulse Width Low
0.4fCLK
tCLKH
Pulse Width High
6.144
fCLK
768fs:
0.4fCLK
tCLKL
Pulse Width Low
0.4fCLK
tCLKH
Pulse Width High
LRCK Timing (Slave Mode)
Normal mode (TDM1=“L”, TDM0=“L”)
LRCK Frequency
fs
8
Duty Cycle
Duty
45
TDM256 MODE (TDM1=“L”, TDM0=“H”)
8
fs
LRCK Frequency
1/256fs
tLRH
“H” time
1/256fs
tLRL
“L” time
TDM128 MODE (TDM1=“H”, TDM0=“H”)
8
fs
LRCK Frequency
1/128fs
tLRH
“H” time
1/128fs
tLRL
“L” time
LRCK Timing (Master Mode)
Normal mode (TDM1=“L”, TDM0=“L”)
LRCK Frequency
fs
8
Duty Cycle
Duty
TDM256 MODE (TDM1=“L”, TDM0=“H”)
LRCK Frequency
fs
8
“H” time
(Note 13)
tLRH
TDM128 MODE (TDM1=“H”, TDM0=“H”)
LRCK Frequency
fs
8
“H” time
(Note 13)
tLRH
Note 13. “L” time at I2S format
MS1096-E-01
typ
max
Units
24.576
27.648
36.864
41.472
12.288
27.648
18.432
41.472
24.576
27.648
36.864
41.472
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
216
55
kHz
%
54
kHz
ns
ns
216
kHz
ns
ns
216
kHz
%
54
kHz
ns
216
kHz
ns
50
1/8fs
1/4fs
2009/08
- 10 -
[AK5388]
Parameter
Symbol
min
Normal mode (TDM1=“L”, TDM0=“L”)
BICK Period
Normal Speed Mode
Double , Quad Speed Mode
Duty Cycle
LRCK Edge to BICK “↑”
(Note 14)
BICK “↑” to LRCK Edge
(Note 14)
LRCK to SDTO1/2 (MSB) (Except I2S mode)
BICK “↓” to SDTO1/2
TBCK
TBCK
Duty
tLRB
tBLR
tLRS
tBSD
1/128fs
1/64fs
40
20
20
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Period
Duty Cycle
LRCK Edge to BICK “↑”
(Note 14)
BICK “↑” to LRCK Edge
(Note 14)
BICK “↓” to SDTO1/2
(Note 15)
TDMIN Setup time
tBCK
Duty
tLRB
tBLR
tBSD
tTDMS
1/256fs
40
20
20
tBCK
Duty
tLRB
tBLR
tBSD
1/128fs
40
20
20
tBCK
Duty
tLRB
tBLR
tBSS
tBSH
1/128fs
40
10
10
10
5
typ
max
Units
Audio Interface Timing (Slave mode)
TDM128 mode (TDM1=“H”, TDM0=“H”)
(8KHz ≤ fs < 108KHz)
BICK Period
Duty Cycle
LRCK Edge to BICK “↑”
(Note 14)
BICK “↑” to LRCK Edge
(Note 14)
BICK “↓” to SDTO1
(Note 15)
TDM128 mode (TDM1=“H”, TDM0=“H”)
(108KHz < fs ≤ 216KHz)
BICK Period
Duty Cycle
LRCK Edge to BICK “↑”
(Note 14)
BICK “↑” to LRCK Edge
(Note 14)
SDTO1 Setup time BICK “↑ “
(Note 15)
SDTO1 Hold time BICK “↑ “
(Note 15)
MS1096-E-01
60
20
60
20
16
60
20
60
ns
ns
%
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
%
ns
ns
ns
ns
2009/08
- 11 -
[AK5388]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing (Master mode)
Normal mode (TDM1=“L”, TDM0=“L”)
Hz
64fs
fBCK
BICK Frequency
%
50
dBCK
BICK Duty
ns
20
−20
tMBLR
BICK “↓” to LRCK
ns
20
−20
tBSD
BICK “↓” to SDTO1/2
TDM256 mode (TDM1=“L”, TDM0=“H”)
Hz
256fs
fBCK
BICK Frequency
%
50
dBCK
BICK Duty
(Note 16)
ns
12
−12
tMBLR
BICK “↓” to LRCK
ns
20
−20
tBSD
BICK “↓” to SDTO1
(Note 15)
TDM128 mode (TDM1=“H”, TDM0=“H”)
(8KHz ≤ fs < 108KHz)
Hz
128fs
BICK Frequency
fBCK
%
50
BICK Duty
dBCK
ns
12
−12
BICK “↓” to LRCK
tMBLR
ns
20
−20
BICK “↓” to SDTO1
(Note 15)
tBSD
TDM128 mode (TDM1=“H”, TDM0=“H”)
(108KHz < fs ≤ 216KHz)
Hz
128fs
fBCK
BICK Frequency
%
50
dBCK
BICK Duty
ns
6
−6
tMBLR
BICK “↓” to LRCK
ns
10
−10
tBSD
BICK “↓” to SDTO1
Power-Down & Reset Timing
PDN Pulse Width
(Note 17)
tPD
150
ns
PDN “↑” to SDTO1/2 valid
(Note 18)
tPDV
516
1/fs
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. SDTO2 output is fixed to “L”.
Note 16. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 17. The AK5388 can be reset by bringing the PDN pin = “L”.
Note 18. This cycle is the number of LRCK rising edges from the PDN pin = “H”. The value is when the AK5388 is in
master mode. In case of in slave mode, the value will be 1LRCK clock cycle (1/fs) longer.
MS1096-E-01
2009/08
- 12 -
[AK5388]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKL
tCLKH
Figure 1. MCLK Timing (TDM0 pin = “L” or “H”)
1/fs
VIH
LRCK
VIL
tLRH
tLRL
Figure 2. LRCK Timing (TDM0 pin = “L” or “H”)
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Duty = tBCKH/tBCK, tBCKL/tBCK
Figure 3.BICK Timing (TDM0 pin = “L” or “H”)
MS1096-E-01
2009/08
- 13 -
[AK5388]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
SDTO
50%DVDD
Figure 4. Audio Interface Timing (Slave mode, TDM0 pin = “L”)
Note: SDTO shows SDTO1 and SDTO2.
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
SDTO1
50%DVDD
tTDMS
VIH
TDMIN
VIL
Figure 5. Audio Interface Timing (Slave mode, TDM0 pin = “H”)
MS1096-E-01
2009/08
- 14 -
[AK5388]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
SDTO1
50%DVDD
Figure 6. Audio Interface Timing (Slave mode, TDM0 pin = “H”, TDM1 pin = “H”, 8KHz ≤ fs < 108KHz)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSS
SDTO1
tBSH
DATA
50%DVDD
Figure 7. Audio Interface Timing (Slave mode, TDM0 pin = “H”, TDM1 pin = “H”, 108KHz < fs ≤ 216KHz)
MS1096-E-01
2009/08
- 15 -
[AK5388]
50%DVDD
LRCK
tMBLR
dBCK
BICK
50%DVDD
tBSD
SDTO
50%DVDD
Figure 8. Audio Interface Timing (Master mode)
VIH
PDN
VIL
tPDV
tPD
SDTO
50%DVDD
Figure 9. Power Down & Reset Timing
Note: SDTO shows SDTO1 and SDTO2.
MS1096-E-01
2009/08
- 16 -
[AK5388]
OPERATION OVERVIEW
■ System Clock
MCLK (128fs/192fs/256fs/384fs/512fs/768fs), BICK (48fs∼) and LRCK (fs) clocks are required in slave mode. The
LRCK clock input must be synchronized with MCLK, however the phase is not critical. Table 1, Table 2 and Table 3
show the relationship of typical sampling frequency and the system clock frequency. MCLK frequency is selected by
CKS1-0 pins as shown in Table 4.
Since the AK5388 includes a phase detection circuit for LRCK, the AK5388 is reset automatically when the
synchronization is out of phase after changing the clock frequencies.
All external clocks (MCLK, BICK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not
provided, the AK5388 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5388 in power-down mode (PDN pin = “L”). In master mode, the master clock
(MCLK) must be provided unless the PDN pin = “L”. In case of using two or more devices, the AK5388 should be reset
by the PDN pin when changing clocks, changing clock modes and switching digital interfaces for a synchronization.
Clock or mode changes should be made during the reset, and a stable clock is needed after the reset.
fs
32kHz
48kHz
96kHz
192kHz
128fs
N/A
N/A
N/A
24.576MHz
192fs
N/A
N/A
N/A
36.864MHz
MCLK
256fs
384fs
8.192MHz
12.288MHz
12.288MHz
18.432MHz
24.576MHz
N/A
N/A
N/A
512fs
768fs
16.384MHz
24.576MHz
24.576MHz
36.864MHz
N/A
N/A
N/A
N/A
(N/A: Not available)
Table 1. System Clock Example (Slave Mode)
fs
32kHz
48kHz
96kHz
192kHz
128fs
N/A
N/A
N/A
24.576MHz
192fs
N/A
N/A
N/A
36.864MHz
MCLK
256fs
384fs
8.192MHz
12.288MHz
12.288MHz
18.432MHz
24.576MHz
36.864MHz
N/A
N/A
512fs
768fs
16.384MHz
24.576MHz
24.576MHz
36.864MHz
N/A
N/A
N/A
N/A
(N/A: Not available)
Table 2. System Clock Example (Master Mode)
fs
32kHz
48kHz
96kHz
192kHz
128fs
N/A
N/A
N/A
24.576MHz
192fs
N/A
N/A
N/A
36.864MHz
MCLK
256fs
384fs
N/A
N/A
N/A
N/A
24.576MHz
36.864MHz
N/A
N/A
512fs
768fs
16.384MHz
24.576MHz
24.576MHz
36.864MHz
N/A
N/A
N/A
N/A
(N/A: Not available)
Table 3. System Clock Example (Auto Mode)
MS1096-E-01
2009/08
- 17 -
[AK5388]
CKS2 pin
CKS1 pin
CKS0 pin
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
M/S Pin
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
MCLK Frequency
Double Speed Mode
128fs (108KHz < fs ≤ 216KHz)
Quad Speed Mode
192fs (108KHz < fs ≤ 216KHz)
Normal Speed Mode
256fs (8KHz ≤ fs ≤ 54KHz)
Double Speed Mode
256fs (54KHz < fs ≤ 108KHz)
Auto (8KHz ≤ fs ≤ 216KHz)
Double Speed Mode
384fs (54KHz < fs ≤ 108KHz)
Normal Speed Mode
384fs (8KHz ≤ fs ≤ 54KHz)
Normal Speed Mode
512fs (8KHz < fs ≤ 54KHz)
Normal Speed Mode
768fs (8KHz ≤ fs ≤ 54KHz)
Table 4. MCLK Frequency
When changing MCLK frequency in master/slave mode, the AK5388 should reset by PDN pin = “L”. (ex.
12.288MHz(@fs=48kHz) at CKS1 pin = CKS0 pin = “L”.
■ Audio Interface Format
12 different audio data interface formats can be selected using the TDM1-0, M/S and DIF pins as shown in Table 5. The
audio data format can be selected by the DIF pin. In all formats the serial data is MSB-first, 2's compliment format. The
SDTO1/2 is clocked out on the falling edge of BICK.
In normal mode, Mode 0-1 are the slave mode, and BICK is available up to 128fs at fs=48kHz. BICK outputs 64fs clock
in Mode 2-3.
In TDM256 mode, all of the ADC’s serial data (four channels) is output from the SDTO1 pins. The SDTO2 output is
fixed to “L”. BICK should be fixed to 256fs. In slave mode, “H” time and “L” time of LRCK should be at least 1/256fs. In
master mode, “H” time (“L” time at I2S mode) of LRCK is 1/8fs (typ). TDM256 mode only supports 48kHz sampling.
In TDM128 mode, all of the ADC’s serial data (four channels) is output from the SDTO1 pin. The SDTO2 output is fixed
to “L”. BICK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be at least 1/128fs. In
master mode, “H” time (“L” time at I2S mode) of LRCK is 1/4fs (typ). TDM128 mode supports up to 192kHz sampling.
MS1096-E-01
2009/08
- 18 -
[AK5388]
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
LRCK
I/O
L
24bit, MSB justified
H/L
I
L
2
H
24bit, I S Compatible
L/H
I
L
L
24bit, MSB justified
H/L
O
H
H
24bit, I2S Compatible
L/H
O
L
24bit, MSB justified
I
↑
L
H
24bit, I2S Compatible
I
↓
H
L
24bit, MSB justified
O
↑
H
H
24bit, I2S Compatible
O
↓
L
24bit, MSB justified
I
↑
L
2
H
24bit, I S Compatible
I
↓
H
L
24bit, MSB justified
O
↑
H
H
24bit, I2S Compatible
O
↓
L
N/A
N/A
N/A
N/A
N/A
Table 5. Audio Interface Formats (N/A: Not available)
TDM1
Normal
L
TDM256
L
TDM128
H
N/A
H
TDM0
M/S
DIF
BICK
SDTO
I/O
I
I
O
O
I
I
O
O
I
I
O
O
N/A
48-128fs
48-128fs
64fs
64fs
256fs
256fs
256fs
256fs
128fs
128fs
128fs
128fs
N/A
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO1/2(o)
23 22
12 11 10
23:MSB, 0:LSB
0
23 22
12
11 10
Lch Data
0
23
Rch Data
Figure 10. Mode 0/2 Timing (Normal mode, MSB justified)
LRCK
0
1
2
3
23
24
25
26
29
30
31
0
1
2
3
23
24
25
26
29
30
31
0
1
BICK(64fs)
SDTO1/2(o)
23 22
2
1
23:MSB, 0:LSB
0
23 22
Lch Data
2
1
0
Rch Data
Figure 11. Mode 1/3 Timing (Normal mode, I2S Compatible)
256 BICK
LRCK (Mode 6)
LRCK (Mode 4)
BICK (256fs)
SDTO1
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
Figure 12. Mode 4/6 Timing (TDM256 mode, MSB justified)
MS1096-E-01
2009/08
- 19 -
[AK5388]
256 BICK
LRCK (Mode 7)
LRCK (Mode5)
BICK (256fs)
SDTO1
23
0
23
0
23
0
23
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 13. Mode 5/7 Timing (TDM256 mode, I2S Compatible)
128 BICK
LRCK (Mode 10)
LRCK (Mode 8)
BICK (128fs)
SDTO1
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
Figure 14. Mode 8/10 Timing (TDM128 mode, MSB justified)
128 BICK
LRCK (Mode 11)
LRCK (Mode 9)
BICK (128fs)
SDTO1
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23
2
Figure 15. Mode 9/11 Timing (TDM128 mode, I S Compatible)
MS1096-E-01
2009/08
- 20 -
[AK5388]
■ Digital High Pass Filter (HPF)
The ADC has a digital high pass filter for DC offset cancellation. The HPF is controlled by the HPFE pin. If the HPF
setting (ON/OFF) is changed during operation, a click noise occurs due to the change in DC offset. The HPF setting
should only be changed when the PDN pin = “L”.
■ Overflow Detection
The AK5388 has an overflow detect function for the analog input. The OVF pin goes to “H” if either channel overflows
(more than −0.3dBFS). OVF output for overflowed analog input has the same group delay as the ADC
(GD=13/fs=0.27ms@fs=48kHz). OVF is “L” for 516/fs (=10.75ms@fs=48kHz) after the PDN pin = “↑”, and then
overflow detection is enabled.
■ Power Down and Reset
The AK5388 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. In the power-down mode, the VCOM is AGND level. An analog
initialization cycle starts after exiting the power-down mode. The output data SDTO is valid after 516 cycles of LRCK
clock in master mode (517 cycles in slave mode). During initialization, the ADC digital data outputs of both channels are
forced to “0”. The ADC outputs settle to data correspondent to the input signals after the end of initialization (Settling
takes approximately the group delay time).
The AK5388 should be reset once by bringing the PDN pin “L” after power-up. The internal timing starts clocking by the
rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK.
(1)
PDN
Internal
State
Normal Operation
Power-down
Initialize
Normal Operation
GD (2)
GD
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
(3)
“0”data
Idle Noise
“0”data
Idle Noise
(4)
Notes:
(1) 517/fs in slave mode and 516/fs in master mode.
(2) Digital output corresponding to analog input has group delay (GD).
(3) A/D output is “0” data in power-down state.
(4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5388 should be in the power-down state.
Figure 16. Power-down/up sequence example
MS1096-E-01
2009/08
- 21 -
[AK5388]
■ Cascade TDM Mode
The AK5388 supports cascading of up to two devices in a daisy chain configuration in TDM256 mode. In this mode,
SDTO1 pin of device #1 is connected to TDMIN pin of device #2. The SDTO1 pin of device #2 can output 8-chnnels of
TDM data multiplexed with 4-chnnel of TDM data from device #1 and 4-channel of TDM data from device #2. Figure 17
shows a connection example of a daisy chain.
When using two AK5388’s in slave mode by cascade connection, the internal timing between device #1 and #2 may differ
for 1MCLK clock cycle. BICK falling edge must me more than ±10ns from a MICK rising edge to prevent this phase
difference between two devices. (Table 6)
BICK must be divided by two on a MCLK falling edge (Figure 19) when MCLK=2 x BICK (Normal speed 512fs mode or
Double speed 256fs mode), and BICK must be in-phase signal to MCLK (Figure 20) when MCLK = BICK (Normal
speed 256fs mode or Quad speed 128fs mode) to achieve this internal timing synchronization.
AK5388 #1
MCLK
256fs or 512fs
LRCK
48kHz
BICK
256fs
TDMIN
SDTO1
GND
SDTO2
MCLK
AK5388 #2
LRCK
BICK
TDMIN
8ch TDM
SDTO1
SDTO2
Figure 17. Cascade TDM Connection Diagram
256 BICK
LRCK
BICK(256fs)
#1 SDTO1(o)
#1 SDTO2(o)
#2 TDMIN(i)
#2 SDTO1(o)
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L1-#1
R1-#1
L2-#1
R2-#1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
Figure 18. Cascade TDM Timing
MS1096-E-01
2009/08
- 22 -
[AK5388]
Parameter
MCLK “↑” to BICK “↓”
BICK “↓” to MCLK“↑”
Symbol
min
tMCB
tBIM
10
10
typ
max
Units
ns
ns
Table 6 TDM Mode Clock Timing
VIH
MCLK
VIL
tMCB
tBIM
VIH
B ICK
VIL
Figure 19. Audio Interface timing (Slave mode, TDM0 Mode MCLK=2 x BICK)
VIH
MCLK
VIL
tMCB
tBIM
VIH
B ICK
VIL
Figure 20. Audio Interface Timing (Slave mode, TDM0 Mode MCLK=BICK)
■ Mono mode
When the MONO pin is set to “H”, the AK5388 is in Mono mode. In this mode, dynamic range and S/N can be improved
by approximately 3dB when the same analog signal is inputted to LIN1 and RIN1, LIN2 and RIN2. The LIN1 and RIN1
data are summed and the amplitude is attenuated into half to be output from the SDTO1 pin. The LIN2 and RIN2 data are
summed and the amplitude is attenuated into half to be output from the SDTO2 pin.
MONO pin
SDTO1/2 Output Data
L
Stereo Mode
H
Mono Mode
Table 7. Setup of MONO mode
MS1096-E-01
2009/08
- 23 -
[AK5388]
SYSTEM DESIGN
10u
+
LIN2+
LIN2-
2.2u
+
0. 1u
+
0.1u
LIN1+
2
LIN1-
3
VSS1
4
AVDD1
10u
+
MicroController
0.1u
5
TEST1
6
VSS2
7
CKS0
8
CKS1
9
CKS2
LIN2+ 37
VCOM2 36
LIN2- 38
TEST3 39
RIN1- 40
RIN1+ 41
VCOM1 42
VREFL2 35
1
VREFL1 43
LIN1+
0.1u
VREFP1 44
0.1u
LIN1-
AK5388
RIN20.1u
10u
+
TEST2 29
VSS5 28
VSS4 27
Top View
DVDD2 26
HPFE 25
0.1u
10u
+
Digital3.3v
22 TDM1
21 TDM0
20 TDMIN
DIF 23
19 OVF
18 SDTO2
17 SDTO1
16 VSS3
13 BICK
14 LRCK
15 DVDD1
M ON O 24
M_SN
0.1u
Analog
Electrolytic Capacitor
Ceramic Capacitor
10 u
fs
64fs
+
+
RIN2+
RIN2 - 32
VSS6 31
12 MCLK
Digital
RIN 2+ 33
AVDD2 30
10 PDN
11
Analog5.0V
2.2u 10u
+
+
VREFP2 34
Analog5.0V
RIN1+
RIN1-
Figure 21 and Figure 22 show the system connection diagram. The evaluation board demonstrates application circuits, the
optimum layout, power supply arrangements and measurement results.
MicroController
Digital3.3v
Digital
Note:
- VSS1-6 should be distributed separately from the ground of external digital devices (MPU, DSP etc.).
- All digital input pins should not be left floating.
Figure 21. Typical Connection Diagram
MS1096-E-01
2009/08
- 24 -
[AK5388]
System
LIN1-
3
VSS1
4
AVDD1
5
TEST1
6
VSS2
7
CKS0
8
CKS1
9
CKS2
VREFP2 34
VCOM2 36
LIN2- 38
LIN2+ 37
RIN1- 40
TEST3 39
RIN1+ 41
VCOM1 42
VREFL2 35
LIN1+
2
RIN2+ 33
RIN2- 32
VSS6 31
AK5388EQ
Controller
1
VREFL1 43
Analog Ground
VREFP1 44
Digital Ground
AVDD2 30
TEST2 29
VSS5 28
VSS4 27
DVDD2 26
HPFE 25
MONO 24
22 TDM1
21 TDM0
20 TDMIN
DIF 23
19 OVF
18 SDTO2
17 SDTO1
16 VSS3
14 LRCK
12 MCLK
13 BICK
11 M/SN
15 DVDD1
10 PDN
Figure 22. Ground Layout
Note: VSS1-6 must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
The AK5388 requires careful attention to power supply and grounding arrangements. AVDD1/2 and DVDD1/2 are
usually supplied from the system’s analog supply. Alternatively if AVDD1/2 and DVDD1/2 are supplied separately, the
power up sequence is not critical. VSS1-6 of the AK5388 must be connected to the analog ground plane. System
analog ground and digital ground should be connected together near to where the supplies are brought onto the printed
circuit board. Decoupling capacitors should be as near to the AK5388 as possible, with the small value ceramic capacitor
being the nearest.
2. Voltage Reference Inputs
The reference voltage for A/D converter is supplied from VREFP1/2 pins at VREFL1/2 reference. VREFL1/2 pins are
connected to analog ground and an electrolytic capacitor over 10μF parallel with a 0.1μF ceramic capacitor between the
VREFP1/2 pins and the VREFL1/2 pins eliminate the effects of high frequency noise. It is important that a ceramic
capacitor should be as near to the pins as possible. All digital signals, especially clocks, should be kept away from the
VREFP1/2 pins in order to avoid unwanted coupling into the AK5388.
VCOM1/2 is a signal ground for this device. An electrolytic capacitor (2.2µF typical) attached to the VCOM1/2 pins
eliminates the effects of high frequency noise. It is important that a ceramic capacitor should be as near to the pins as
possible. No load current may be drawn from the VCOM1/2 pins. All signals, especially clocks, should be kept away
from the VCOM1/2 pins in order to avoid unwanted coupling into the AK5388.
3. Analog Inputs
The Analog input signal is differentially supplied into the modulator via the LIN+ (RIN+) and the LIN− (RIN−) pins. The
input voltage is the difference between the LIN+ (RIN+) and LIN− (RIN−) pins. The full scale signal on each pin is
nominally ±2.8Vpp(typ). The AK5388 can accept input voltages from VSS1-6 to AVDD1/2. The ADC output data
format is two’s complement. The internal HPF removes DC offset.
The AK5388 samples the analog inputs at 128fs (6.144MHz@fs=48kHz, Normal Speed Mode). The digital filter rejects
noise above the stop band except for multiples of 128fs. The AK5388 includes an anti-aliasing filter (RC filter) to
attenuate a noise around 128fs.
The AK5388 requires a +5V analog supply voltage. Any voltage which exceeds the upper limit of AVDD1/2+0.3V and
lower limit of VSS1-6 − 0.3V and any current beyond 10mA for the analog input pins (LIN+/−, RIN+/−) should be
avoided. Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals at
or beyond these limits. Use caution especially when using ±15V for other analog circuits in the system.
MS1096-E-01
2009/08
- 25 -
[AK5388]
4. External Analog Circuit Examples
Figure 23 shows an input buffer circuit example 1. (1st order HPF; fc=0.70Hz, 2nd order LPF; fc=351kHz, gain=-14.5dB).
The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2
for XLR input). The input level of this circuit is +/-15.0Vpp (AK5388: +/-2.8Vpp Typ.). When using this circuit, analog
characteristics at fs=48kHz is DR=120dB, S/(N+D)=110dB.
620
4.7k
4.7k
Analog In
JP1
VP+
Vin+ 68µ
+
15.4Vpp
Bias
VP-
1n
3.3k
91
+
2.9Vpp
AK5388 AIN+
NJM5534
NJM5534
XLR
2.2n
VA+
620
10k
Bias
10k
JP2
1n
3.3k
-
+
10µ
68µ
Vin-
91
AK5388 AIN-
+
0.1µ
NJM5534
Bias
VA=+5
VP=±15
2.9Vpp
Figure 23.Input Buffer example1
fin
1Hz
10Hz
Frequency Response
−1.77dB
−0.02dB
Table 8. Frequency Response of HPF
fin
20kHz
40kHz
80kHz
Frequency Response
0.00dB
0.00dB
0.00dB
Table 9. Frequency Response of LPF
MS1096-E-01
6.144MHz
−49.68dB
2009/08
- 26 -
[AK5388]
Figure 24 shows an input buffer circuit example in Mono mode. (1st order HPF; fc=0.70Hz, 2nd order LPF; fc=351kHz,
gain=-14.5dB).
4.7k
4.7k
Analog In
620
JP1
VP+
Vin+ 68µ
+
15.0Vpp
1n
3.3k
Bias
VP-
11
+
2.8Vpp
AK5388 LIN+
NJM5534
NJM5534
15n
AK5388 LINXLR
VA+
620
10k
JP2
Bias
68µ
+
11k
10µ
AK5388 RIN+
15n
1n
3.3k
Vin-
-
11
+
0.1 µ
NJM5534
Bias
VA=+5V
AK5388 RIN2.8Vpp
VP=±15V
Figure 24 External Analog Circuit Examples
fin
1Hz
10Hz
Frequency Response
−1.77dB
−0.02dB
Table 10. Frequency Response of HPF
fin
20kHz
40kHz
80kHz
Frequency Response
0.00dB
0.00dB
0.00dB
Table 11. Frequency Response of LPF
MS1096-E-01
6.144MHz
−49.68dB
2009/08
- 27 -
[AK5388]
5. Performance Plot
Figure 25 shows a FFT measurement result.
[Conditions]
Ta=25ºC; AVDD1/2=5.0V; VREFP1/2=5.0V, VREFL1/2=0V, DVDD=3.3V; VSS1=VSS2=VSS3=VSS4=0V;
fs=48kHz; Signal Frequency =1kHz, -1dBFS, Measured by Audio Precision, System Two.
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 25. FFT (Blue: Left Channel, Red: Right Channel)
MS1096-E-01
2009/08
- 28 -
[AK5388]
PACKAGE
44pin LQFP (Unit: mm)
1.70max
12.8±0.3
1.40
0.10±0.10
10.0
23
33
0.8
12.8±0.3
22
10.0
34
12
44
1
11
0.37±0.08
0.20
M
0.17±0.05
0°∼10°
0.6±0.20
0.10
■ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS1096-E-01
2009/08
- 29 -
[AK5388]
MARKING
AK5388EQ
XXXXXXX
AKM
1
1) Pin #1 indication
2) Audio 4 pro Logo
3) Date Code: XXXXXXX(7 digits)
4) Marking Code: AK5388
5) AKM Logo
REVISION HISTORY
Date (YY/MM/DD)
09/07/09
09/08/xx
Revision
00
01
Reason
First Edition
Error Correct
Page
Contents
1
Pin names of block diagram were changed.
VRP1 →VREFP1, VRL1 →VREFL1
VRP2 →VREFP2, VRL2 →VREFL2
■ Cascade TDM Mode
Figure 17 and description were corrected.
SDTO2 is connected to TDMIN
→
SDTO1 is connected to TDMIN
Figure 23
A resistor value was corrected. 3.3 → 3.3k
[Conditions]
VREFL1/2=5.0V → =0V
22
26
28
MS1096-E-01
2009/08
- 30 -
[AK5388]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use
of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from
any and all claims arising from the use of said product in the absence of such notification.
MS1096-E-01
2009/08
- 31 -
工商网监
湘ICP备2023018690号
