AK5392VS

ASAHI KASEI [AK5392] AK5392 Enhanced Dual Bit ΔΣ 24Bit ADC General Description The AK5392 is a 24bit, 128x oversampling 2ch A/D Converterfor professional digital audio systems. The modulator in the AK5392 uses the new developed Enhanced Dual Bit architecture. This new architecture achieves the wider dynamic range, while keeping much the same superior distortion characteristics as conventional Single Bit way. The AK5392 performs 116dB dynamic range, so the device is suitable for professional studio equipments such as digital mixer, digital VTR etc. Features † † † † † † † † † † † † Enhanced Dual Bit ADC Sampling Rate: 1kHz∼54kHz Full Differential Inputs S/(N+D): 105dB DR: 116dB S/N: 116dB High Performance Linear Phase Digital Anti-Alias filter • Passband: 0∼21.768kHz(@fs=48kHz) • Ripple: 0.001dB • Stopband: 110dB Digital HPF & Offset Calibration for Offset Cancel Master Clock: 256/384fs Power Supply: 5V±5%(Analog), 3∼5.25V(Digital) Power Dissipation: 470mW Package: 28pin SOP 0188-E-01 1997/11 -1- ASAHI KASEI [AK5392] „ Ordering Guide AK5392-VS -10∼ +70°C AKD5392 AK5392 Evaluation Board 28pin SOP „ Pin Layout „ Compatibility with AK5391 1. Changed Specs Parameter HPF Output Resolution DR Input Offset AK5391 No 20/24bit 113dB Required AK5392 Yes 24bit 116dB Not required 2. Pin Compatibility The following pin functions are changed from AK5391. AK5392 supports 24bit only. Pin No. 2 19 27 AK5391 VREFLSEL24 VREFR- AK5392 GNDL HPFE GNDR 0188-E-01 1997/11 -2- ASAHI KASEI [AK5392] PIN/FUNCTION No. Pin Name I/O Function Lch Reference Voltage Pin, 3.75V Normally connected to GNDL with a 10uF electrolytic capacitor and a 0.1uF ceramic capacitor Lch Reference Ground Pin, 0V Lch Common Voltage Pin, 2.5V Lch Analog positive input Pin Lch Analog negative input Pin Zero Calibration Control Pin This pin controls the calibration reference signal. "L":VCOML and VCOMR "H":Analog Input Pins(AINL±,AINR±) Digital Power Supply Pin, 3.3V Digital Ground Pin, 0V Calibration Active Signal Pin "H" means the offset calibration cycle is in progress. Offset calibration starts when RST goes "H". CAL goes "L" after 8704 LRCK cycles. Reset Pin When "L", Digital section is powered-down. Upon returning "H", an offset calibration cycle is started. An offset calibration cycle should always be initiated after power-up. Serial Interface Mode Select Pin MSB first, 2's compliment. SMODE2 SMODE1 MODE LRCK L L Slave mode : MSB justified : H/L L H Master mode : Similar to I2S : H/L H L Slave mode : I2S : L/H H H Master mode : I2S : L/H Left/Right Channel Select Clock Pin LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H" during reset when SMODE1 "H". 1 VREFL O 2 3 4 5 6 GNDL VCOML AINL+ AINLZCAL O I I I 7 8 9 VD DGND CAL O 10 RST I 11 12 SMODE2 SMODE1 I I 13 LRCK I/O 0188-E-01 1997/11 -3- ASAHI KASEI [AK5392] 14 SCLK I/O 15 SDATA O 16 FSYNC I/O 17 CLK I 18 CMODE I 19 HPFE I 20 TEST I 21 22 23 24 25 26 27 28 BGND AGND VA AINRAINR+ VCOMR GNDR VREFR I I O O Serial Data Clock Pin Data is clocked out on the falling edge of SCLK. Slave mode: SCLK requires more than 48fs clock. Master mode: SCLK outputs a 128fs clock. SCLK stays "L" during reset. Serial Data Output Pin MSB first, 2's complement. SDATA stays "L" during reset. Frame Synchronization Signal Pin Slave mode: When "H", the data bits are clocked out on SDATA. Master mode: FSYNC outputs 2fs clock. FSYNC stays "L" during reset. Master Clock Input Pin CMODE="H":384fs CMODE="L":256fs Master Clock Select Pin "L": CLK=256fs (12.288MHz @fs=48kHz) "H": CLK=384fs (18.432MHz @fs=48kHz) High Pass Filter Enable Pin "L": Disable "H": Enable Test Pin Should be connected DGND. Substrate Ground Pin, 0V Analog Ground Pin, 0V Analog Supply Pin, 5V Rch Analog negative input Pin Rch Analog positive input Pin Rch Common Voltage Pin, 2.5V Rch Reference Ground Pin, 0V Rch Reference Voltage Pin, 3.75V Normally connected to GNDR with a 10uF electrolytic capacitor and a 0.1uF ceramic capacitor 0188-E-01 1997/11 -4- ASAHI KASEI [AK5392] ABSOLUTE MAXIMUM RATINGS (AGND,BGND,DGND=0V; Note 1 ) Parameter Power Supplies: Analog Digital |BGND-DGND| (Note 2 ) Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature (power applied) Storage Temperature Symbol min max Units VA VD Δ GND -0.3 -0.3 -0.3 -0.3 -10 -65 6.0 6.0 0.3 ±10 VA+0.3 VD+0.3 70 150 V V V mA V V IIN VINA VIND Ta Tstg °C °C Note: 1 . All voltages with respect to ground. 2 . AGND and BGND must be same voltage. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND,BGND,DGND=0V; Note 1 ) Parameter Power Supplies: (Note 3 ) Analog Digital Symbol min typ max Units VA VD 4.75 3.0 5.0 3.3 5.25 5.25 V V Notes: 1 . All voltages with respect to ground. 3 . The power up sequence between VA and VD is not critical. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. 0188-E-01 1997/11 -5- ASAHI KASEI [AK5392] ANALOG CHARACTERISTICS (Ta=25°C ; VA=5.0V; VD=3.3V; AGND,BGND,DGND=0V; fs=48kHz; Signal Frequency=1kHz; 24bit Output; Measurement frequency=10Hz∼ 20kHz; unless otherwise specified) Parameter min Resolution typ max Units 24 Bits 105 93 53 116 116 120 0.1 dB dB dB dB dB dB dB ppm/°C Analog Input Characteristics: S/(N+D) (Note 4 ) -1dBFS -20dBFS -60dBFS S/N (A-Weighted) Dynamic Range (A-Weighted,-60dBFS) Interchannel Isolation Interchannel Gain Mismatch Gain Drift Offset Error after calibration, HPF=OFF after calibration, HPF=ON Offset Drift (HPF=OFF) Offset Calibration Range (HPF=OFF) Input Voltage (AIN+)-(AIN-) Input Impedance 98 112 112 110 ±2.36 3 ±200 ±1 ±10 ±50 ±2.51 5 0.5 150 ±1000 ±2.66 LSB24 LSB24 LSB24/°C mV V kΩ Power Supplies Power Supply Current VA VD Power Dissipation Power Supply Rejection 90 6 470 70 (Note 5 ) 130 9 680 mA mA mW dB Notes: 4 . The ratio of the rms value of the signal to the rms sum of all the spectral components from 20Hz to 20kHz, without A-weight. Full power input signal is -0.5dBFS. 5 . DC to 26kHz. 110dB(typ) beyond 26kHz. 0188-E-01 1997/11 -6- ASAHI KASEI [AK5392] FILTER CHARACTERISTICS (Ta=25°C ; VA=5.0V±5%; VD=3.0∼ 5.25V; fs=48kHz) Parameter Symbol min PB SB PR SA Δ GD 0 26.232 typ max Units 21.768 ADC Digital Filter(Decimation LPF): Passband Stopband Passband Ripple Stopband Attenuation Group Delay Distortion Group Delay (Note 6 ) (Note 6 ) (Note 7 ) (Note 8 ) GD 38.7 kHz kHz dB dB us 1/fs FR 1.0 2.9 6.5 Hz Hz Hz ±0.001 110 0 ADC Digital Filter(HPF): Freqency response (Note 6 ) -3dB -0.5dB -0.1dB Notes: 6 . The passband and stopband frequencies scale with fs. PB=0.4535fs, SB=0.5465fs 7 . The analog modulator samples the input at 6.144MHz for an output word rate of 48kHz. There is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144MHz±21.768kHz, where n=1,2,3…). 8 . The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 24bit data of both channels to the output register. 40.7/fs at HPF:ON. DIGITAL CHARACTERISTICS (Ta=25°C ; VA=5.0V±5%; VD=3.0∼ 5.25V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Iout=-20uA Low-Level Output Voltage Iout=20uA Input Leakage Current Symbol min typ max Units VIH VIL VOH VOL Iin 70%VD VD-0.1 - - 30%VD 0.1 ±10 V V V V uA 0188-E-01 - 1997/11 -7- ASAHI KASEI [AK5392] SWITCHING CHARACTERISTICS (Ta=25°C ; VA=5.0V±5%; VD=3.0∼ 5.25V; CL=20pF) Parameter Control Clock Frequency Master Clock 256fs: Pulse width Low Pulse width High 384fs: Pulse width Low Pulse width High Serial Data Output Clock (SCLK) Channel Select Clock (LRCK) duty cycle Serial Interface Timing (Note 9 ) Slave Mode(SMODE1="L") SCLK Period SCLK Pulse Width Low Pulse width High SCLK falling to LRCK Edge (Note 10 ) LRCK Edge to SDATA MSB Valid SCLK falling to SDATA Valid SCLK falling to FSYNC Edge Master Mode(SMODE1="H") SCLK Frequency duty cycle FSYNC Frequency duty cycle SCLK falling to LRCK Edge LRCK Edge to FSYNC rising SCLK falling to SDATA Valid SCLK falling to FSYNC Edge Reset/Calibration timing RST Pulse width RST falling to CAL rising RST rising to CAL falling (Note 11 ) RST rising to SDATA Valid (Note 11 ) Symbol Min Typ Max Units fCLK tCLKL tCLKH fCLK tCLKL tCLKH fSLK fs 0.256 29 29 0.384 20 20 12.288 13.824 18.432 20.736 6.144 48 6.912 54 75 MHz ns ns MHz ns ns MHz kHz % tSLK tSLKL tSLKH tSLR tDLR tDSS tSF 144.7 65 65 -45 45 45 45 45 ns ns ns ns ns ns ns 1 25 -45 128fs 50 2fs 50 fSLK fFSYNC tSLR tLRF tDSS tSF -20 tRTW tRCR tRCF tRTV 150 20 1 45 20 -20 50 8704 8960 Hz % Hz % ns tslk ns ns ns ns 1/fs 1/fs Notes: 9 . Refer to Serial Data interface. 10 . Specified LRCK edges not to coincide with the rising edges of SCLK. 11 . The number of the LRCK rising edges after RST brought high. The value is in master mode. In slave mode it becomes one LRCK clock(1/fs) longer. 0188-E-01 1997/11 -8- ASAHI KASEI [AK5392] „ Timing Diagram 0188-E-01 1997/11 -9- ASAHI KASEI [AK5392] 0188-E-01 1997/11 - 10 - ASAHI KASEI [AK5392] OPERATION OVERVIEW „ System Clock Input The external clocks which are required to operate the AK5392 are MCLK, LRCK(fs),SCLK. MCLK should be synchronized with LRCK but the phase is free of care. MCLK can be either 256fs or 384fs by setting CMODE pin. When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). Table 1 illustrates standard audio word rates and corresponding frequencies used in the AK5392. As the AK5392 includes the phase detect circuit for LRCK, the AK5392 is reset automatically when the synchronization is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up. MCLK fs 32.0kHz 44.1kHz 48.0kHz SCLK(128fs) 256fs 384fs 8.1920MHz 11.2896MHz 12.2880MHz 12.2880MHz 16.9344MHz 18.4320MHz 4.0960MHz 5.6448MHz 6.1440MHz Table 1 . Examples of System Clock „ Serial Data Interface AK5392 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 2 ). The data format is MSB-first, 2's complement. Figure Figure 1 Figure 2 Figure 3 Figure 4 SMODE2 SMODE1 L L H H L H L H Mode Slave Mode Master Mode I2S Slave Mode I2S Master Mode LRCK Lch=H, Rch=L Lch=H, Rch=L Lch=L, Rch=H Lch=L, Rch=H Table 2 . Serial I/F Format 0188-E-01 1997/11 - 11 - ASAHI KASEI [AK5392] 0188-E-01 1997/11 - 12 - ASAHI KASEI [AK5392] „ Offset Calibration When RST pin goes to "L", the digital section is powered-down. Upon returning "H", an offset calibration cycle is started. An offset calibration cycle should always be initiated after power-up. During the offset calibration cycle, the digital section of the part measures and stores the values of calibration input of each channel in registers. The calibration input value is subtracted from all future outputs. The calibration input may be obtained from either the analog input pins (AIN+/-) or the VCOM pins depending on the state of the ZCAL pin. With ZCAL "H", the analog input pin voltages are measured, and with ZCAL "L", the VCOM pin voltages are measured. The CAL output is "H" during calibration. „ Digital High Pass Filter The AK5392 also has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1Hz at fs=48kHz and also scales with sampling rate(fs). 0188-E-01 1997/11 - 13 - ASAHI KASEI [AK5392] SYSTEM DESIGN Figure 5 shows the system connection diagram. An evaluation board[AKD5392] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Figure 5 . Typical Connection Diagram 0188-E-01 1997/11 - 14 - ASAHI KASEI [AK5392] 1. Grounding and Power Supply Decoupling The AK5392 requires careful attention to power supply and grounding arrangements. Analog ground and digital ground should be separate and connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5392 as possible,with the small value ceramic capacitor being the nearest. 2. On-chip voltage reference and VCOM The reference voltage for A/D converter is a fifferemtial voltage between the VREFL/R output voltage and the GNDL/R input voltage. The GNDL/R are connected to AGND and a 10uF electrolytic capacitor parallel with a 0.1uF ceramic capacitor between the VREFL/R and the GNDL/R eliminate the effects of high frequency noise. Especially a ceramic capacitor should be as near to the pins as possible. And all digital signals, especially clocks, should be kept away from the VREFL/R pins in order to avoid unwanted coupling into the AK5392. No load current may be taken from the VREFL/R pins. VCOM is a common voltage of the analog signal. In order to eliminate the effects of high frequency noise, a 0.22uF ceramic capacitor should be connected as near to the VCOM pin as possible. And all signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5392. No load current may be drawn from the VCOM pin. 3. Analog Inputs Analog signal is differentially input into the modulator via the AIN+ and the AIN- pins. The input voltage is the difference between AIN+ and AIN- pins. The full-scale of each pin is nominally ±2.5Vpp(typ). The AK5392 can accept input voltages from AGND to VA. The ADC output data format is 2's complement The output code is 7FFFFFH(@24bit) for input above a positive full scale and 800000H(@24bit) for input below a negative full scale. The ideal code is 000000H(@24bit) with no input signal. The DC offset is removed by the offset calibration. The AK5392 samples the analog inputs at 128fs(6.144MHz @fs=48kHz). The digital filter rejects noise above the stop band except for multiples of 128fs. A simple RC filter may be used to attenuate any noise around 128fs and most audio signals do not have significant energy at 128fs. The AK5392 accepts +5V supply voltage. Any voltage which exceeds the upper limit of VA+0.3V and lower limit of AGND-0.3V and any current beyond 10mA for the analog input pins(AIN+/-) should be avoided. Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals at or beyond these limits. Use caution specially in case of using ±15V in other analog circuits. 0188-E-01 1997/11 - 15 - ASAHI KASEI [AK5392] Figure 6 shows a input buffer circuit example. This is a full-differential input buffer circuit with an inverted-amp (gain: -10dB). The capacitor of 2200pF between VREF+/- decreases the clock feed through noise of modulator. And the resistor of 51 ohms is inserted in order to stabilize the op-amps before the ADC. This circuit is also a low pass filter with cut-off frequency of about 220kHz. In this example, the internal offset is removed by self calibration. The evaluation board should be refered about the detail. Figure 6 . Differential Input Buffer Example 0188-E-01 1997/11 - 16 - ASAHI KASEI [AK5392] PACKAGE z 28pin SOP (Unit: mm) „ Package & Lead frame material Package molding compound : Lead frame material : Lead frame surface treatment : Epoxy Cu Solder plate 0188-E-01 1997/11 - 17 - ASAHI KASEI [AK5392] MARKING Contents of XXXBYYYYC XXXB: Lot #(X:numbers,B:alphabet) YYYYC: Date Code(Y:numbers,C:alphabet) 0188-E-01 1997/11 - 18 - IMPORTANT NOTICE zThese products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. zAKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. zAny export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. zAKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. zIt is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.