AK5483

ASAHI KASEI [AK5483] AK5483 10Bit 20MHz 3CH A/D Converter Outline AK5483 is a Cmos, 20MSPS(MAX) 、 10bit,Analog to Digital(A/D) Converter. Three Channels of high Performance ADCs are integrated into a tiny package. Employing Full-Pipeline A/D Conversion Architecture, AK5483 Converts Single End 1Vpp Analog Input into 10bit Straight Binary Format Digital Data. The analog Input Range is determined by external reference input pins[VTP,VBT]. The range is common for the three channels. Features * * * * * CMOS 3Channel A/D Converter Sampling Rate Number of Channels Single Low Supply Voltage Analog Input Range,Vref Range Single End Analog Input * Digital Output Format * Stand-by mode * Low Power Consumption * High Isolation between Channels * Linearity * Small Package AVDD : 20 MSPS : 3Channels(Simultaneous Sampling) : 3.0V.... +3.6V : Adaptive to Power Supply Voltage : 1 Vp-p [VBOT=1.3V VTOP=2.3V] (@VDD=3.0V) : Straight Binary (BOTTOM=000H , TOP=3FFH) 3CH * 10BIT (All data in Parallel) : 135 mW(15MHz mode @3V) 165 mW(20MHz mode @3V) : 55dB : Differential(DNL) +-0.6 LSB(TYP.) : Integral (INL) +-1.5 LSB(TYP.) : 48pin LQFP-0707 AVSS bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb DVDD bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb AINB AINC DIGITAL CORRECTION PIPELINE ADC DRI VER bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb AINA DA9 DOUTA bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb DA0 bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb DRI VER DIGITAL CORRECTION PIPELINE ADC DB9 DOUTB bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb DB0 VTP VREFP VREF PIPELINE ADC DIGITAL CORRECTION GEN DRI VER VCOM bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb DOUTC bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb VREFN CLOCK & CONTROL VBT DC9 bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb DC0 DVSS CKI CEN bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb bbbbbb SEL M0035-E-01 -1- 1999/03 ASAHI KASEI [AK5483] * Ordering Guide AK5483 -20deg...+85deg 48 Pin LQFP DC7 DVDD DVSS DC6 DC5 DC4 DC3 DC2 DC1 DC0 AVDD 35 34 33 32 31 30 29 28 27 26 25 37 DC8 36 36 * Pin Assignment 25 24 DC9 37 24 VBT DB0 38 23 VTP DB1 39 22 VREFN DB2 40 21 AINC DB3 41 20 VCOM DB4 42 19 AINB DB5 43 18 VREFP DB6 44 17 AINA DB7 45 16 AVSS DB8 46 15 AVDD DB9 47 14 CKI 48 13 CEN 12 11 9 8 7 6 5 13 SEL DA0 DA2 DA3 DA4 DA5 12 DA6 DVSS 4 DVDD 3 2 DA7 DA8 1 1 48 10 (48LQFP PACKAGE) DA1 DA9 TOP VIEW **ALL SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE** M0035-E-01 -2- 1999/03 ASAHI KASEI * [AK5483] Pin Descriptions PIN NO. [48LQFP] Symbol T ype Description & F unction 1 2 3 4 5 6 7 8 9 10 11 12 DA8 DA7 D VDD DVSS DA6 DA5 DA4 DA3 DA2 DA1 DAO SEL O O P P O O O O O O O I 13 CEN I 14 CKI I 15 AVDD 16 AVSS 17 AINA P P I 18 VREFP O 19 AINB I 20 VCO M O 21 AINC I 22 VREFN O 23 VTP I 24 VBT I M0035-E-01 CH A OUTPUT D8 CH A OUTPUT D7 Digital Supply(3.3V[TYP.]) Digital G round 0V CH A OUTPUT D6 CH A OUTPUT D5 CH A OUTPUT D4 CH A OUTPUT D3 CH A OUTPUT D2 CH A OUTPUT D1 CH A OUTPUT D0(LSB) Sampling Frequency SELECT Upper Lim it of Sam pling Clock(CKI) F requency is determ ined by this pin. Low : 15MHz m ode High : 20MHz m ode Always connect to High or Low. CHIP ENABLE(Power Down Control ) LOW :Normal Operating Mode High: Power down & All Di gital Output= High-Z CLO CK Input Input Pin for Sam pling Clock Analog Supply (3.3V[TYP.]) Analog Ground 0V ANALOG INPUT(CH A) VREF Voltage f or internal circuit Place 0.1uF C eram ic Cap. between AVSS. ANALOG INPUT(CH B) VREF Voltage f or internal circuit Place 0.1uF C eram ic Cap. between AVSS. ANALOG INPUT(CH C ) VREF Voltage f or internal circuit Place 0.1uF C eram ic Cap. between AVSS. VREF Top Voltage Input Pin[To set Analog Input Range] VIN Full Scale R ef erence pin. VREF Bottom Voltage Input Pin[To set Analog Input Range] VIN Zero Scale Ref erence pin. -3- 1999/03 ASAHI KASEI * [AK5483] Pin Descriptions PIN NO. Symbol T ype Description & F unction 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 M0035-E-01 AVDD DC0 DC1 DC2 DC3 DC4 DC5 DC6 DVSS D VDD DC7 DC8 DC9 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DA9 P O O O O O O O P P O O O O O O O O O O O O O O Analog Supply (3.3V[TYP.]) CH C OUTPUT D0(LSB) CH C OUTPU T D1 CH C OUTPU T D2 CH C OUTPU T D3 CH C OUTPU T D4 CH C OUTPU T D5 CH C OUTPU T D6 Digital Ground 0V Digital Supply(3.3V[TYP.]) CH C OUTPU T D7 CH C OUTPU T D8 CH C OUTPUT D9(M SB) CH B OUTPUT D0(LSB) CH B OUTPUT D1 CH B OUTPUT D2 CH B OUTPUT D3 CH B OUTPUT D4 CH B OUTPUT D5 CH B OUTPUT D6 CH B OUTPUT D7 CH B OUTPUT D8 CH B OUTPUT D9(M SB) CH A OUTPUT D9(M SB) -4- 1999/03 ASAHI KASEI [AK5483] ABSOLUTE MAXIMUM RATINGS AVSS,DVSS=0V,All voltages are with respect to GND Parameter Power Supply Voltage Symbol Conditions AVDD DVDD Voltage Difference Vdlt Input Current IIN Analog Input Voltage Range VINA (# 1) DVDD - AVDD Except Power Pins Ratings -0.3 ..... 6.0 -0.3 ..... 6.0 or (AVDD+0.3) 0.3 +-10 Units V V V V mA AVSS - 0.3 V ..... AVDD + 0.3 Digital Input Voltage VINL AVSS - 0.3 V [Input Pins] Digital Input Voltage ..... AVDD + 0.3 VONL (#2) AVSS - 0.3 V [Output Pins] Ambient Temperature .... AVDD + 0.3 TA Tstg -20 ..... +85 -40 .....+125 deg deg Storage Temperature (# 1) The higher voltage of 6.0V and AVDD + 0.3V specifies Max. value of DVDD absolute maximum rating. (# 2) The VONL limits the excess voltage applied to digital output pins. WARNING Operation at or beyond these limits may result in permanent damage to the device. Normal Operating Specifications are not guaranteed at these extremes. M0035-E-01 -5- 1999/03 ASAHI KASEI [AK5483] Recommended Operating Conditions 1.Power Supply Requirements (DVSS,AVSS=0V,(#1)) Parameter Supply Voltage [Analog] [Digital] Symbol AVDD DVDD Condition (#2) min 3.0 3.0 typ 3.3 3.3 max 3.6 AVDD Units V V (#1) All voltages are with respect to GND (#2) At start-up , power-on AVDD before(or at the same time to) DVDD power-on. 2.Reference Input Applicable Voltage to Top/Bottom Reference Voltage(TOP,BOTTOM is proportional to Power Supply Voltage[AVDD]. The Analog Input Range[Conversion D-range] is determined based on TOP & BOTTOM Voltage [which is applied to VTP/VBT pins] . Note that the AINFS[Analog Input Range] must satisfy the following range. Parameter Analog Input Range Symbol AINFS Reference Bottom Voltage VBTE Reference Top Voltage VTPE Reference Input Impedance ZTBE Conditions #1 #2 #2 VBT -VTP SPE C Values Unit min. typ. max. VDD/3 - VDD/30 VDD/3 VDD/3 + VDD/30 Vpp min. typ. max. 1.3 * VDD/3 - VDD/30 1.3 * VDD/3 1.3 * VDD/3 + VDD/30 V min. typ. max 2.3 * VDD/3 - VDD/30 2.3 * VDD/3 2.3 * VDD/3 + VDD/30 V min. typ. 100 KOHM (#1) : AINFS=VTPE - VBTE Note that AFINFS is not the ADC operating input voltage range (Analog Characteristics are not always guaranteed.) (#2) : Adjust both of these voltages[VBTE/VTPE] to satisfy the AINFS spec. regarding the voltage difference VTPE-VBTE. (Notice : Acceptable external VREF voltage varies according to the Power Supply Voltage[AVDD]. Example : In case of VDD=AVDD=DVDD=3.0V VBTE=1.20...1.398V VTPE=2.199...2.397V AINFS= 0.9 .... 1.08 Vpp M0035-E-01 -6- 1999/03 ASAHI KASEI [AK5483] Specifications 1) Analog Specifications (AVDD=DVDD=3.3V, VBT=1.43V,VTP=2.53V, Ta=25deg, Fs=20MHz @20MHz mode , Fs=15MHz @15MHz mode Signal frequency Fin=1MHz Signal level =-1dB , unless otherwise noted) Parameter Resolution Integral Nonlinearity[INL] Symbol RES INL Differential Nonlinearity[DNL] Offset Voltage DNL Conditions min typ +-1.5 max 10 +-2.5 Units BITS LSB +-0.6 +-1.0 LSB +30 +40 mV mV -55 dB KOHM pF EOB EOT TO VBT TO VTP Cross-talk Input Resistance Input Capacitance CT RIN CIN @Fs=20MHz(#2) @Fs=20MHz(#3) @Fs=20MHz -65 50 10 Input Bandwidth BW -3dB@20MHz 100 (#1) -30 -40 MHz (#1)Offset Voltage is the difference of Transition input voltage to All Zero [All One] and VBT[VTP]. (#2)Cross-talk[CT] is the isolation between each ADC. The value is specified as the cross talk from any one channel[Ain=1MHz ,-1dB] to the other two channels[no signal input]. (#3)Input Resistance[RIN] is specified as the equivalent impedance from Analog Input Pins[AINA,AINB,AINC] to ADC common voltage[center voltage between VTP & VBT]. RIN is proportional to 1/FS. M0035-E-01 -7- 1999/03 ASAHI KASEI [AK5483] 2)Power Supply (Ta=25 deg ;AVDD=DVDD=3.3V; VTP=2.53V,VBT=1.43V Parameter Analog Operating Current (@CEN=LOW) Symbol IA+ Digital Output Driver Operating Current (@CEN=LOW) ID+ Stand-by Current (@CEN=HIGH) IAS IDS Condition Fin=1MHz @Fs=15MHz(#3) @Fs=20MHz ) min Fin=1MHz (#1) @Fs=15MHz(#3) @Fs=20MHz Analog Digital typ max 45 55 60 70 mA mA 10 15 15 21 mA mA 0.1 0.1 mA mA (#2) Units (#1)Capacitor Loads [CL=10pF] are attached to all digital output pins[D0..D9]. Analog Input Signal 1MHz Sine Wave. (#2)The Stand-by Current is measured under *No Analog Input *CKI= Low fixed (#3)15MHz mode is selected by SEL=Low. 3)Timing Specifications (AVDD,DVDD=3.0V....3.6 V, AVSS,DVSS=0V, Ta=TAMIN.....TAMAX deg,CL70%]VDD [70%->30%]VDD (#1) 15MHz mode 20MHz mode 15MHz mode 20MHz mode min typ 0.5 0.5 66 50 max Units 15 20 MHz MHz ns ns ns ns % ns ns ns ns CLKIN ns ns ns 2 2 50 31 23 31 23 6 3 2 35 (#1)Acceptable DUTY should be calculated from clock HIGH/LOW period and operating Frequency(Fc). M0035-E-01 -8- 1999/03 ASAHI KASEI [AK5483] Timing Diagram 0.7A VD D CKI 0.3A VD D A N A LO G IN PU T N +6 N +5 N +1 N +4 N tap tdl1 SA M PLIN G PO IN T DIG ITAL O UTPU T N-6 N -5 N -2 0.7D VD D N-1 0.3D VD D N tdl2 tpd Clock Timing Chart tH 0.7AVD D 0.3AVD D tL tr tf tcyc 4)Digital DC Specifications (AVDD=DVDD=3.0...3.6V , AVSS=DVSS=0V, Ta=TAMIN...TAMAX deg Specified as static characteristics) Parameter High Input Voltage Symbol VIH Low Input Voltage VIL High Output Voltage Low Output Voltage High Level Input VOH VOL ILIKG IOH=-3mA IOL=3mA Current (CKI,CEN) HIGH-Z Output Current (DA0:9,DB0:9,DC0:9) IOZ CEN=HIGH M0035-E-01 Condition -9- min 0.7AVDD typ max Units V 0.3AVDD V 0.3DVDD +-10 V V uA 0.7DVDD +-10 uA 1999/03 ASAHI KASEI [AK5483] Theory of operation * Analog Input Range External Reference Voltage fed through VTP/VBT determine the analog input range of all three channels of 10 Bit AD converter. The Zero level of analog input(AINA,AINB,AINC) is VBT and the Full Scale is VTP. * Converted Digital Output Code The converted Digital Output Code is Straight Binary format. For Zero Scale(AIN=VBT), the output code is all zero. For Full Scale(AIN=VTP), the output code is all one. The deviation from these ideal voltage is expressed by Offset[EOB,EOT]. * Sampling Frequency Select Reduction of power consumption is realized for sampling frequency less than 15MHz. 20MHz mode : SEL=High Normal current is consumed to operate at Fc=20MHz. 15MHz mode ] : SEL=Low Current is reduced with restriction of Fcmax=15MHz. * Chip Enable Function By setting CEN=High, whole chip of AK5483 powers down. Under the power down state, all digital output are High-Impedance and Vref related circuit also powers down. The internal reference voltage is generated with input of CEN=LOW & supply of external VREF voltage. Depending on the state of external capacitors, some period is required to charge them. * CKI,Pipeline delay,Data Output Timing Feed A/D converter sampling clock through CKI pin. Rising edges of CKI track and hold the analog input signal. After 6clock pipeline delay, 10 bit digital output code is obtained. * Caution for Power Supply It is recommended to supply both AVDD and DVDD supply from single regulator. (Please observe absolute maximum rating spec. DVDD