AK5536VN

[AK5536] AK5536 6-Channel Differential 32-bit  ADC 1. General Description The AK553x series is a 32-bit, 768 kHz sampling, differential input A/D converter for digital audio systems. It achieves 111 dB dynamic range and 103 dB S/(N+D) while maintaining low power consumption performance. The AK5536 integrates a 6-channel A/D converter, suitable for mixers and multi-channel recorders. Four types of digital filters are integrated and selectable according to the sound quality preference. The AK5536 can be easily connected to a DSP by supporting TDM audio formats. Additionally, it supports DSD output up to 11.2MHz. The channel summation improves the dynamic range to 114 dB in 6-to-3 mode, to 117 dB in 4-to-1 mode and to 118 dB in 6-to-1 mode. 2. Features  Sampling Rate: 8 kHz-768 kHz  Input: Full Differential Inputs  S/(N+D): 103 dB  DR: 111 dB (6-to-3 mode: 114 dB, 4-to-1 mode: 117 dB, 6-to-1 mode: 118 dB)  S/N: 111 dB (6-to-3 mode: 114 dB, 4-to-1 mode: 117 dB, 6-to-1 mode: 118 dB)  Internal Filter: Four types of LPF, Digital HPF  Power Supply: 3.0-3.6 V (Analog), 1.7-1.98 V or 3.0-3.6 V (Digital)  Output Format: PCM mode: 24/32-bit MSB justified, I2S or TDM DSD mode: DSD Native 64, 128, 256 Maximized Slot Efficiency in TDM Mode by Optimal Data Placed Mode  Cascade TDM I/F: TDM512: fs= 48 kHz TDM256: fs= 96 kHz or 48 kHz TDM128: fs= 192 kHz, 96 kHz or 48 kHz  Operation Mode: Master Mode & Slave Mode  Detection Function: Input Overflow Flag  Serial Interface: 3-wire Serial and I2C μP I/F (Pin setting is also available)  Power Consumption: 142 mW (@AVDD= 3.3 V, TVDD= 3.3 V, fs= 48 kHz)  Package: 64-pin QFN 015099885-E-00 2016/03 -1- [AK5536] 3. Table of Contents General Description ............................................................................................................................ 1 Features .............................................................................................................................................. 1 Table of Contents................................................................................................................................ 2 Block Diagram..................................................................................................................................... 3 ■ Block Diagram.................................................................................................................................... 3 5. Pin Configurations and Functions ...................................................................................................... 4 ■ Pin Configurations ............................................................................................................................. 4 ■ Pin Functions ..................................................................................................................................... 5 ■ Handling of Unused Pin ..................................................................................................................... 7 6. Absolute Maximum Ratings ................................................................................................................ 8 7. Recommended Operation Conditions ................................................................................................ 8 8. Analog Characteristics ........................................................................................................................ 9 9. Filter Characteristics ......................................................................................................................... 10 ■ ADC Filter Characteristics (fs= 48 kHz) .......................................................................................... 10 ■ ADC Filter Characteristics (fs= 96 kHz) .......................................................................................... 12 ■ ADC Filter Characteristics (fs= 192 kHz) ........................................................................................ 14 ■ ADC Filter Characteristics (fs= 384 kHz) ........................................................................................ 16 ■ ADC Filter Characteristics (fs= 768 kHz) ........................................................................................ 17 10. DC Characteristics ........................................................................................................................ 18 11. Switching Characteristics .............................................................................................................. 19 ■ Timing Diagram ............................................................................................................................... 26 12. Functional Descriptions ................................................................................................................. 31 ■ Digital Core Power Supply ............................................................................................................... 31 ■ Output Mode .................................................................................................................................... 31 ■ Master Mode and Slave Mode ......................................................................................................... 31 ■ System Clock ................................................................................................................................... 31 ■ Audio Interface Format .................................................................................................................... 34 ■ Channel Summation (PCM Mode, DSD Mode) .............................................................................. 46 ■ Optimal Data Placement (PCM Mode, DSD Mode) ........................................................................ 46 ■ CH Power Down & Channel Summation Setting (PCM Mode, DSD Mode) .................................. 47 ■ Digital Filter Setting (PCM Mode) .................................................................................................... 52 ■ Digital HPF (PCM Mode) ................................................................................................................. 52 ■ Overflow Detection (PCM Mode, DSD Mode) ................................................................................. 52 ■ LDO .................................................................................................................................................. 53 ■ Reset ................................................................................................................................................ 53 ■ Power Up/Down Sequence ............................................................................................................. 54 ■ Operation Mode Control .................................................................................................................. 57 ■ Register Control Interface ................................................................................................................ 57 ■ Register Map .................................................................................................................................... 61 ■ Register Definitions .......................................................................................................................... 61 13. Recommended External Circuits .................................................................................................. 64 14. Package......................................................................................................................................... 67 ■ Outline Dimensions.......................................................................................................................... 67 ■ Material & Lead Finish ..................................................................................................................... 67 ■ Marking ............................................................................................................................................ 67 15. Ordering Guide .............................................................................................................................. 68 16. Revision History ............................................................................................................................ 68 IMPORTANT NOTICE ........................................................................................................................... 69 1. 2. 3. 4. 015099885-E-00 2016/03 -2- [AK5536] 4. Block Diagram VREFL3 VREFH3 VREFL2 VREFH2 VREFL1 VREFH1 ■ Block Diagram TVDD AIN1P Delta-Sigma Modulator VDD18 DVSS LDO Voltage Reference AIN1N LDOE Decimation Filter HPF DIF0/DSDSEL0 DIF1/DSDSEL1 AIN2P AIN2N AIN3P AIN3N Delta-Sigma Modulator Decimation Filter HPF Delta-Sigma Modulator Decimation Filter HPF Delta-Sigma Modulator Decimation Filter HPF Delta-Sigma Modulator Decimation Filter HPF BICK/DCLK LRCK/DSDOL1 TDMIN/DSDOR1 SDTO1/DSDOL2 SDTO2/DSDOR2 AIN4P AIN4N AIN5P AIN5N Serial Output Interface SDTO3/DSDOL3 DSDOR3 DP AIN6P AIN6N Delta-Sigma Modulator Decimation Filter HPF TDM0 TDM1 ODP AVDD1 AVSS1 PSN/CAD0_SPI CKS0/SDA/CDTI CKS1/CAD0_I2C/CSN CKS2/SCL/CCLK CKS3/CAD1 Controller AVDD2 I2C DCKS/HPFE OVF MSN PW0 PW1 PW2 SD/PMOD SLOW/DCKB TEST MCLK PDN AVSS2 Figure 1. Block Diagram 015099885-E-00 2016/03 -3- [AK5536] 5. Pin Configurations and Functions 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SD/PMOD SLOW/DCKB CKS3/CAD1 CKS2/SCL/CCLK CKS1/CAD0_I2C/CSN CKS0/SDA/CDTI OVF TESTO2 TESTO1 DSDOR3 SDTO3/DSDOL3 SDTO2/DSDOR2 SDTO1/DSDOL2 TDMIN/DSDOR1 LRCK/DSDOL1 BICK/DCLK ■ Pin Configurations 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 64QFN TOP VIEW Exposed Pad (Back Face) * 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 MSN PW2 PW1 PW0 PDN VDD18 DVSS TVDD MCLK TEST TESTIN6 TESTIN5 TESTIN4 TESTIN3 TESTIN2 TESTIN1 AVSS1 AVDD1 AIN3P AIN3N VREFL2 VREFH2 AIN4N AIN4P AIN5P AIN5N VREFH3 VREFL3 AIN6N AIN6P AVDD2 AVSS2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DIF0/DSDSEL0 DIF1/DSDSEL1 TDM0 TDM1 PSN/CAD0_SPI I2C DP DCKS/HPFE LDOE ODP AIN1P AIN1N VREFL1 VREFH1 AIN2N AIN2P * The exposed pad at back face of the package must be open or connected to the ground of the board. Figure 2. Pin Configurations 015099885-E-00 2016/03 -4- [AK5536] ■ Pin Functions No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name AVSS1 AVDD1 AIN3P AIN3N VREFL2 VREFH2 AIN4N AIN4P AIN5P AIN5N VREFH3 VREFL3 AIN6N AIN6P AVDD2 AVSS2 TESTIN1 TESTIN2 TESTIN3 TESTIN4 TESTIN5 TESTIN6 TEST MCLK I/O I I I I I I I I I I I I I I I I I I I I Function Analog Ground Pin(AIN1-4) Analog Power Supply Pin(AIN1-4), 3.0-3.6 V Channel 3 Positive Input Pin Channel 3 Negative Input Pin ADC Low Level Voltage Reference Input Pin ADC High Level Voltage Reference Input Pin Channel 4 Negative Input Pin Channel 4 Positive Input Pin Channel 5 Positive Input Pin Channel 5 Negative Input Pin ADC High Level Voltage Reference Input Pin ADC Low Level Voltage Reference Input Pin Channel 6 Negative Input Pin Channel 6 Positive Input Pin Analog Power Supply Pin(AIN5-6), 3.0-3.6 V Analog Ground Pin(AIN5-6) Test Input Pin1 Test Input Pin2 Test Input Pin3 Test Input Pin4 Test Input Pin5 Test Input Pin6 TEST Enable Pin. This pin is pull down by 100kΩ internally Master Clock Input Pin Digital I/O Buffers and LDO Power Supply Pin 1.7-1.98 V (LDOE pin= “L”) or 3.0-3.6 V (LDOE pin= “H”). Digital Ground Pin Digital Core Power Supply Pin, 1.7-1.98 V (LDOE pin= “L”) 25 TVDD - 26 DVSS I 27 VDD18 O LDO Stabilization Capacitor Connect Pin. (LDOE pin= “H”) 28 PDN I 29 PW0 30 PW1 31 PW2 I I I 32 MSN I I BICK 33 O DCLK O I LRCK 34 O DSDOL1 O Reset & Power Down Pin “L”: Reset & Power down, “H” : Normal operation Power Management Pin, Channel Summation select Pin Power Management Pin, Channel Summation select Pin Power Management Pin, Channel Summation select Pin Master/Slave Select Pin “L”: Slave Mode, “H” : Master Mode Audio Serial Data Clock Input Pin in PCM & Slave Mode. This pin is pulled down by 100 kΩ internally Audio Serial Data Clock Output Pin in PCM & Master Mode This pin is pulled down by 100 kΩ internally DSD Clock Output Pin in DSD Mode This pin is pulled down by 100 kΩ internally Channel Clock Input Pin in PCM & Slave Mode This pin is pulled down by 100 kΩ internally Channel Clock Output Pin in PCM & Master Mode This pin is pulled down by 100 kΩ internally Audio Serial Data Output Pin for AIN1 in DSD Mode This pin is pulled down by 100 kΩ internally 015099885-E-00 Power Down Status Hi-z & Pull Down with 500 Ω Hi-z Hi-z Hi-z Hi-z 2016/03 -5- [AK5536] No. Pin Name I/O TDMIN I DSDOR1 O SDTO1 DSDOL2 SDTO2 DSDOR2 SDTO3 DSDOL3 DSDOR3 TESTO1 TESTO2 OVF CKS0 SDA CDTI CKS1 CAD0_I2C CSN CKS2 SCL CCLK CKS3 CAD1 SLOW DCKB SD PMOD O O O O O O O O O O I I/O I I I I I I I I I I I I I 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DIF0 I DSDSEL0 I DIF1 I DSDSEL1 I 51 TDM0 I 52 TDM1 I 53 PSN I CAD0_SPI I 54 I2C I 55 DP I Function TDM Data Input Pin in PCM Mode This pin is pulled down by 100 kΩ internally Audio Serial Data Output Pin for AIN2 in DSD Mode This pin is pulled down by 100 kΩ internally Audio Serial Data Output Pin for AIN1 and AIN2 in PCM Mode Audio Serial Data Output Pin for AIN3 in DSD Mode Audio Serial Data Output Pin for AIN3 and AIN4 in PCM Mode Audio Serial Data Output Pin for AIN4 in DSD Mode Audio Serial Data Output Pin for AIN5 and AIN6 in PCM Mode Audio Serial Data Output Pin for AIN5 in DSD Mode Audio Serial Data Output Pin for AIN6 in DSD Mode Test Output Pin1 Test Output Pin2 Analog Input Over Flow Flag Output Pin Clock Mode Select Pin Control Data I/O Pin in I2C Bus Serial Control Mode Control Data Input Pin in 3-wire Serial Control Mode Clock Mode Select Pin Chip Address 0 Pin in I2C Bus Serial Control Mode Chip Select Pin in 3-wire Serial Control Mode Clock Mode Select Pin Control Data Clock Pin in I2C Bus Serial Control Mode Control Data Clock Pin in 3-wire Serial Control Mode Clock Mode Select Pin Chip Address 1 Pin in I2C Bus or 3-wire Serial Control Mode Slow Roll-OFF Digital Filter Select Pin in PCM Mode Polarity of DCLK Pin in DSD Mode Short Delay Digital Filter Select Pin in PCM Mode DSD Phase Modulation Mode Select Pin in DSD Mode Audio Data Format Select Pin in PCM Mode “L”: MSB justified, “H”: I2S DSD Sampling Rate Control Pin in DSD Mode Audio Data Format Select Pin in PCM Mode “L”: 24-bit Mode, “H”: 32-bit Mode DSD Sampling Rate Control Pin in DSD Mode TDM I/F Format Select Pin * This pin must be fixed to “L” when using DSD mode. TDM I/F Format Select Pin * This pin must be fixed to “L” when using DSD mode. Control Mode Select Pin (I2C pin = “H”) “L”:I2C Bus Serial Control Mode, “H” :Parallel Control Mode Chip Address 0 Pin in 3-wire Serial Control Mode (I2C pin = “L”) Control Mode Select Pin “L”: 3-wire Serial Control Mode “H”: I2C Bus Serial Control Mode or Parallel Control Mode DSD Mode Enable Pin “L”: PCM Mode, “H”: DSD Mode 015099885-E-00 Power Down Status Hi-z L L L L L L L Hi-Z Hi-Z L Hi-z - 2016/03 -6- [AK5536] No. Pin Name I/O Power Down Status Function High Pass Filter Enable Pin “L”: HPF Disable, “H”: HPF Enable DCKS I Master Clock Frequency Select at DSD Mode (DSD Only) LDO Enable Pin 57 LDOE I “L”: LDO Disable, “H”: LDO Enable This pin is pulled down by 100 kΩ internally. 58 ODP I Optimal Data Placement Mode Select Pin 59 AIN1P I Channel 1 Positive Input Pin 60 AIN1N I Channel 1 Negative Input Pin 61 VREFL1 I ADC Low Level Voltage Reference Input Pin 62 VREFH1 I ADC High Level Voltage Reference Input Pin 63 AIN2N I Channel 2 Negative Input Pin 64 AIN2P I Channel 2 Positive Input Pin Note 1. All digital input pins must not be allowed to float. 56 HPFE I - - ■ Handling of Unused Pin The unused I/O pins should be connected appropriately. 1. PCM Mode Classification Analog Digital Pin Name AIN1-6P, AIN1-6N VREFH1-3 VREFL1-3, TESTIN1-6 TDMIN, TEST SDTO1-3, OVF, TESTO1-2 Setting Open Connect to AVDD Connect to AVSS Connect to DVSS Open 2. DSD Mode Classification Pin Name AIN1-6P, AIN1-6N Analog VREFH1-3 VREFL1-3, TESTIN1-6 TDM0, TDM1, TEST Digital DSDOL1-3, DSDOR1-3, OVF TESTO1-2 Note 2. Unused channels must be powered down. 015099885-E-00 Setting Open Connect to AVDD Connect to AVSS Connect to DVSS Open 2016/03 -7- [AK5536] 6. Absolute Maximum Ratings (VSS= 0 V; Note 3) Parameter Symbol Min. Max. Unit AVDDam −0.3 6.0 V Power Analog (AVDD pin) Supplies: Digital Interface (TVDD pin) TVDDam −0.3 4.0 V Digital Core (VDD18 pin) (Note 4) VDD18am −0.3 2.5 V Input Current (Any Pin Except Supplies) IIN 10 mA Analog Input Voltage (AIN1-6P, AIN1-6N pins) VINA −0.3 AVDD+0.3 V Digital Input Voltage VIND −0.3 TVDD+0.3 V Ambient Temperature (Power applied) °C When the back tab is connected to VSS Ta −40 105 °C When the back tab is open Ta −40 70 Storage Temperature Tstg −65 150 °C Note 3. All voltages with respect to ground. Note 4. The 1.8 V LDO is off (LDOE pin = “L”) and an external power is supplied to the VDD18 pin. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operation Conditions (VSS= 0 V; Note 3) Parameter Symbol Min. Typ. Max. Unit Analog (AVDD pin) AVDD 3.0 3.3 3.6 V (LDOE pin= “L”) (Note 5) Power Digital Interface (TVDD pin) (Note 6) TVDD 1.7 1.8 1.98 V Supplies Digital Core (VDD18 pin) VDD18 1.7 1.8 1.98 V (LDOE pin= “H”) (Note 7) Digital Interface (TVDD pin) TVDD 3.0 3.3 3.6 V “H” voltage Reference (Note 8) VREFH1-3 3.0 3.3 3.6 V Voltage Reference “L” voltage reference (Note 9) VREFL1-3 AVSS V Note 3. All voltages with respect to ground. Note 5. TVDD pin must be powered up before or at the same time with the VDD18 pin when the LDOE pin = “L”. The power up sequence between AVDD pin and TVDD pin or between AVDD pin and VDD18 pin is not critical. Note 6. TVDD must not exceed VDD18±0.1 V when LDOE pin= “L”. Note 7. When LDOE pin = “H”, the internal LDO supplies 1.8 V (typ). The power up sequences between AVDD pin and TVDD pin is not critical. Note 8. VREFH1-3 must not exceed AVDD+0.1 V. Note 9. VREFL1-3 must be connected to AVSS. Analog Input Voltage is proportional to {(VREFH) – (VREFL)}. Vin (typ, @ 0dB) = 1.85  {(VREFH) – (VREFL)} / 3.3 [V]. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. 015099885-E-00 2016/03 -8- [AK5536] 8. Analog Characteristics (Ta= 25 C; AVDD= 3.3 V; TVDD= 3.3 V, fs= 48 kHz, BICK= 64fs; Signal Frequency= 1 kHz; 24-bit Data; Measurement frequency= 20 Hz-20 kHz at fs= 48 kHz, 40 Hz-40 kHz at fs= 96 kHz, 40 Hz-40 kHz at fs= 192 kHz, unless otherwise specified.) Parameter Min. Typ. Max. Unit Analog Input Characteristics: Resolution 32 bit Input Voltage (Note 10) Vpp 1.75 1.85 1.95 1 dBFS 103 dB 97 S/(N+D) fs= 48 kHz 89 dB 20 dBFS BW=20 kHz 49 dB 60 dBFS 1 dBFS 103 dB fs= 96 kHz 86 dB 20 dBFS BW= 40 kHz 46 dB 60 dBFS 1 dBFS 103 dB fs= 192 kHz 86 dB 20 dBFS BW= 40 kHz 46 dB 60 dBFS Not-Sum. mode 106 111 dB Dynamic Range 6-to-3 mode 114 dB 4-to-1 mode 117 dB (60 dBFS with A-weighted) 6-to-1 mode 118 dB Not-Sum. mode 106 111 dB S/N 6-to-3 mode 114 dB (A-weighted) 4-to-1 mode 117 dB 6-to-1 mode 118 dB Input Resistance These values will be doubled in DSD 64fs mode. 8.8 10.4 12.0 k (Values in DSD128 or DSD256 modes are as shown here) Interchannel Isolation 110 120 dB (AIN1↔AIN2, AIN3↔AIN4, AIN5↔AIN6) Interchannel Gain Mismatch 0 0.5 dB Power Supply Rejection (Note 11) 60 dB Power Supplies Power Supply Current Normal Operation (PDN pin = “H”, LDOE pin = “H”) mA AVDD + VREFHm (m=1-3) 29 38 mA TVDD (fs= 48 kHz) 14 19 mA TVDD (fs= 96 kHz) 24 32 mA TVDD (fs= 192 kHz) 21 28 Power Down mode (PDN pin = “L”) (Note 12) AVDD+TVDD 10 100 A Note 10. This value is (AINnP)(AINnN) that the ADC output becomes full-scale (n=1-6). Vin = 0.56  (VREFHmVREFLm) [Vpp]. (m=1-3) Note 11. PSRR is applied to AVDD, TVDD with 1 kHz, 20 mVpp sine wave. The VREFH1-3 are held to the fixed voltage. Note 12. All digital inputs are fixed to TVDD or TVSS. 015099885-E-00 2016/03 -9- [AK5536] 9. Filter Characteristics ■ ADC Filter Characteristics (fs= 48 kHz) (Ta= 40 - +105C; AVDD= 3.0-3.6 V, TVDD=1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin= “L”)) Parameter Symbol Min. Typ. Max. Unit Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 3) (SD pin= “L”, SLOW pin= “L”) Passband (Note 13) +0.001/0.06 dB PB 0 22.0 kHz 24.4 kHz 6.0 dB Stopband (Note 13) SB 27.9 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 20.0 kHz 0 1/fs GD Group Delay (Note 14) GD 19 1/fs Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 4) (SD pin= “L”, SLOW pin= “H”) Passband (Note 13) +0.001/0.076 dB PB 0 12.5 kHz 21.9 kHz 6.0 dB Stopband (Note 13) SB 36.5 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 20.0 kHz 0 1/fs GD Group Delay (Note 14) GD 7 1/fs Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER (Figure 5) (SD pin= “H”, SLOW pin= “L”) Passband (Note 13) PB 0 22.0 kHz +0.001/0.06 dB 24.4 kHz 6.0 dB Stopband (Note 13) SB 27.9 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 20.0 kHz 2.8 1/fs GD Group Delay (Note 14) GD 5 1/fs Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF (Figure 6) (SD pin= “H”,SLOW pin= “H”) Passband (Note 13) +0.001/0.076 dB PB 0 12.5 kHz 21.9 kHz 6.0 dB Stopband (Note 13) SB 36.5 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 20.0 kHz 1.2 1/fs GD Group Delay (Note 14) GD 5 1/fs Digital Filter (HPF): Frequency Response FR 1.0 Hz 3.0 dB 2.5 Hz 0.5 dB (Note 13) 6.5 Hz 0.1 dB Note 13. The Passband and Stopband Frequencies scale with fs. For Example, PB (+0.001 dB/0.06 dB) = 0.46  fs (SHARP ROLL-OFF). For Example, PB (+0.001 dB/0.076 dB) = 0.26  fs (SLOW ROLL-OFF). Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces. 015099885-E-00 2016/03 - 10 - [AK5536] Figure 3. SHARP ROLL-OFF (fs= 48 kHz) Figure 4. SLOW ROLL-OFF (fs= 48 kHz) Figure 5. SHORT DELAY SHARP ROLL-OFF (fs= 48 kHz) Figure 6. SHORT DELAY SLOW ROLL-OFF (fs= 48 kHz) 015099885-E-00 2016/03 - 11 - [AK5536] ■ ADC Filter Characteristics (fs= 96 kHz) (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD=1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin= “L”)) Parameter Symbol Min. Typ. Max. Unit Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 7) (SD pin= “L”, SLOW pin= “L”) 44.1 Passband (Note 13) +0.001/0.06 dB 0 kHz PB 48.8 kHz 6.0 dB Stopband (Note 13) SB 55.7 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0 1/fs GD Group Delay (Note 14) GD 19 1/fs Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 8) (SD pin= “L”, SLOW pin= “H”) 25 Passband (Note 13) +0.001/0.076 dB 0 kHz PB 43.8 kHz 6.0 dB Stopband (Note 13) SB 73 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0 1/fs GD Group Delay (Note 14) GD 7 1/fs Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF (Figure 9) (SD pin= “H”,SLOW pin= “L”) Passband (Note 13) +0.001/0.06 dB 0 44.1 kHz PB 48.8 kHz 6.0 dB Stopband (Note 13) SB 55.7 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 2.8 1/fs GD Group Delay (Note 14) GD 5 1/fs Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF (Figure 10) (SD pin=“H”, SLOW pin= “H”) Passband (Note 13) +0.001/0.076 dB 0 25 kHz PB 43.8 kHz 6.0dB Stopband (Note 13) SB 73 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 1.2 1/fs GD Group Delay (Note 14) GD 5 1/fs Digital Filter (HPF): Frequency Response FR 1.0 Hz 3.0 dB 2.5 Hz 0.5 dB (Note 13) 6.5 Hz 0.1 dB Note 13. The Passband and Stopband Frequencies scale with fs. For example, PB (+0.001 dB/0.06 dB) = 0.46  fs (SHARP ROLL-OFF). For example, PB (+0.001 dB/0.076 dB) = 0.26  fs (SLOW ROLL-OFF). Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces. 015099885-E-00 2016/03 - 12 - [AK5536] Figure 7. SHARP ROLL-OFF (fs= 96 kHz) Figure 8. SLOW ROLL-OFF (fs= 96 kHz) Figure 9. SHORT DELAY SHARP ROLL-OFF (fs= 96 kHz) Figure 10. SHORT DELAY SLOW ROLL-OFF (fs= 96 kHz) 015099885-E-00 2016/03 - 13 - [AK5536] ■ ADC Filter Characteristics (fs= 192 kHz) (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD=1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin= “L”)) Parameter Symbol Min. Typ. Max. Unit Digital Filter (Decimation LPF): SHARP ROLL-OFF (Figure 11) (SD pin=“L”, SLOW pin= “L”) 83.7 Passband (Note 13) +0.001/0.037 dB 0 kHz PB 100.2 kHz 6.0 dB Stopband (Note 13) SB 122.9 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0 1/fs GD Group Delay (Note 14) GD 15 1/fs Digital Filter (Decimation LPF): SLOW ROLL-OFF (Figure 12) (SD pin=“L”, SLOW pin= “H”) Passband (Note 13) +0.001/0.1 dB 0 31.5 kHz PB 75.2 kHz 6.0 dB Stopband (Note 13) SB 146 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0 1/fs GD Group Delay (Note 14) GD 8 1/fs Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER (Figure 13) (SD pin=“H”, SLOW pin= “L”) Passband (Note 13) +0.001/0.037 dB 0 83.7 kHz PB 100.2 kHz 6.0 dB Stopband (Note 13) SB 122.9 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0.3 1/fs GD Group Delay (Note 14) GD 6 1/fs Digital Filter (Decimation LPF): SHORT DELAY SLOW ROLL-OFF FILTER (Figure 14) (SD pin=“H”, SLOW pin= “H”) Passband (Note 13) +0.001/0.1 dB 0 31.5 kHz PB 75.2 kHz 6.0 dB Stopband (Note 13) SB 146 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz 0.4 1/fs GD Group Delay (Note 14) GD 6 1/fs Digital Filter (HPF): Frequency Response FR 1.0 Hz 3.0 dB 2.5 Hz 0.5 dB (Note 13) 6.5 Hz 0.1 dB Note 13. The Passband and Stopband Frequencies scale with fs. For Example, PB (+0.001 dB/0.037 dB) = 0.436  fs (SHARP ROLL-OFF). For Example, PB (+0.001 dB/0.1 dB) = 0.164  fs (SLOW ROLL-OFF). Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces. 015099885-E-00 2016/03 - 14 - [AK5536] Figure 11. SHARP ROLL-OFF (fs= 192 kHz) Figure 12. SLOW ROLL-OFF (fs= 192 kHz) Figure 13. SHORT DELAY SHARP ROLL-OFF (fs= 192 kHz) Figure 14. SHORT DELAY SLOW ROLL-OFF (fs= 192 kHz) 015099885-E-00 2016/03 - 15 - [AK5536] ■ ADC Filter Characteristics (fs= 384 kHz) (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD=1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin= “L”)) Parameter Symbol Min. Typ. Max. Unit Digital Filter (Decimation LPF) (Figure 15) (SD pin = “X”, SLOW pin = “X”) * It does not depend on the SD pin and Slow pin. Frequency Response 0.1 dB 81.75 kHz (Note 13) 1.0 dB 114 kHz FR 137.63 kHz 3.0 dB 157.2 kHz 6.0 dB Stopband (Note 13) SB 277.4 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz ΔGD 0 1/fs Group Delay (Note 14) GD 7 1/fs Note 13. The Passband and Stopband Frequencies scale with fs. Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces. Figure 15. Frequency Response (fs= 384 kHz) 015099885-E-00 2016/03 - 16 - [AK5536] ■ ADC Filter Characteristics (fs= 768 kHz) (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD=1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin= “L”)) Parameter Symbol Min. Typ. Max. Unit Digital Filter (Decimation LPF) (Figure 16) (SD pin = “X”, SLOW pin = “X”) * It does not depend on the SD pin and SLOW pin. Frequency Response 0.1 dB 26.25 kHz (Note 13) 1.0 dB 83.75 kHz FR 144.5 kHz 3.0 dB 203.1 kHz 6.0 dB Stopband (Note 13) SB 640.3 kHz Stopband Attenuation SA 85 dB Group Delay Distortion 0 - 40.0 kHz ΔGD 0 1/fs Group Delay (Note 14) GD 5 1/fs Note 13. The Passband and Stopband Frequencies scale with fs. Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the L channel MSB output timing of the SDTO. It may have an error of +1[1/fs] at maximum when outputting data via audio interfaces. Figure 16. Frequency Response (fs= 768 kHz) 015099885-E-00 2016/03 - 17 - [AK5536] 10. DC Characteristics (Ta= 40-105 C; AVDD= 3.0-3.6 V, VDD18= 1.7-1.98 V (LDOE pin=“L”)) Parameter Symbol Min. TVDD= 3.0-3.6 V (LDOE pin=”H”) High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout= 100 µA) Low-Level Output Voltage (except SDA pin: Iout= 100 µA) (SDA pin: Iout= 3 mA) TVDD= 1.7-1.98 V (LDOE pin=”L”) (Note 15) (Note 15) (Note 16) Typ. Max. Unit VIH VIL 70%TVDD - - 30%TVDD V V VOH TVDD0.5 - - V VOL VOL - - 0.5 0.4 V V (Note 17) High-Level Input Voltage (Note 15) VIH 80%TVDD V Low-Level Input Voltage (Note 15) VIL 20%TVDD V High-Level Output Voltage (Note 16) VOH TVDD0.3 V (Iout= 100 µA) Low-Level Output Voltage (Note 17) (except SDA pin: Iout= 100 µA) VOL 0.3 V (SDA pin: Iout= 3 mA) VOL 20%TVDD V Input Leakage Current Iin 10 A Note 15. MCLK, PDN, PW0-2, MSN, BICK (Slave Mode), LRCK (Slave Mode), TDMIN, SLOW/DCKB, SD/PMOD, CKS0/SDA (Write)/CDTI, CKS1/CAD_I2C/CSN, CKS2/SCL/CCLK, CKS3/CAD1, DIF0/DSDSEL0, DIF1/DSDSEL1, TDM0, TDM1, PSN/CAD0_SPI, I2C, DP, DCKS/HPFE, LDOE, ODP, TEST Note 16. BICK (Master Mode)/DCLK, LRCK (Master Mode)/DSDOL1, DSDOR1, SDTO1/DSDOL2, SDTO2/DSDOR2, SDTO3/DSDOL3, DSDOR3, OVF Note 17. Note.16 and SDA (Read) The external pull-up resistors should be connected to TVDD+0.3 V or less. 015099885-E-00 2016/03 - 18 - [AK5536] 11. Switching Characteristics (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), CL= 10 pF) Parameter Symbol Master Clock (MCLK)Timing (Figure 17, Figure 18) Frequency fCLK Duty Cycle dCLK LRCK Timing (Slave mode) (Figure 17) Normal mode (TDM1-0 bits = “00”) fs Frequency fsn Normal Speed mode fsd Double Speed mode fsq Quad Speed mode fso Oct speed mode fsh Hex speed mode Duty Duty Cycle TDM128 mode (TDM1-0 bits = “01”) fs Frequency fsn Normal Speed mode fsd Double Speed mode fsq Quad Speed mode tLRH High time tLRL Low time TDM256 mode (TDM1-0 bits = “10”) fs Frequency fsn Normal Speed mode fsd Double Speed mode tLRH High time tLRL Low time TDM512 mode (TDM1-0 bits = “11”) fs Frequency fsn Normal Speed mode tLRH High time tLRL Low time LRCK Timing (Master mode) (Figure 18) Normal mode (TDM1-0 bits = “00”) fs Frequency fsn Normal Speed mode fsd Double Speed mode fsq Quad Speed mode fso Oct speed mode fsh Hex speed mode Duty Duty Cycle TDM128 mode (TDM1-0 bits = “01”) fs Frequency fsn Normal Speed mode fsd Double Speed mode fsq Quad Speed mode tLRH High time TDM256 mode (TDM1-0 bits = “10”) fs Frequency fsn Normal Speed mode fsd Double Speed mode tLRH High time TDM512 mode (TDM1-0 bits = “11”) fs Frequency fsn Normal Speed mode tLRH High time Min. Typ. Max. Unit 2.048 45 - 49.152 55 MHz % 8 54 108 45 384 768 - 54 108 216 55 kHz kHz kHz kHz kHz % 8 54 108 1/128fs 1/128fs - 54 108 216 - kHz kHz kHz ns ns 8 54 1/256fs 1/256fs - 54 108 - kHz kHz ns ns 8 1/512fs 1/512fs - 54 - kHz ns ns 8 54 108 - 384 768 50 54 108 216 - kHz kHz kHz kHz kHz % 8 54 108 - 1/4fs 54 108 216 - kHz kHz kHz ns 8 54 - 1/8fs 54 108 - kHz kHz ns 8 - 1/16fs 54 - kHz ns Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5536 should be reset by the PDN pin or RSTN bit. 015099885-E-00 2016/03 - 19 - [AK5536] (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Slave mode) Normal mode (TDM1-0 bits = “00”) (8 kHz  fs  216 kHz) (Figure 19) (LDOE pin = “H”) BICK Period tBCK 1/128fsn ns Normal Speed mode tBCK 1/128fsd ns Double Speed mode tBCK 1/64fsq ns Quad Speed mode tBCKL 32 ns BICK Pulse Width Low tBCKH 32 ns BICK Pulse Width High tLRB 25 ns LRCK Edge to BICK “↑” (Note 19) tBLR 25 ns BICK “↑” to LRCK Edge (Note 19) tLRS 25 ns LRCK to SDTO (MSB) (Except I2S mode) tBSD 25 ns BICK “↓”to SDTO1/2/3 Normal mode (TDM1-0 bits = “00”) (8 kHz ≤ fs ≤ 216 kHz) (Figure 19) (LDOE pin = “L”) BICK Period tBCK 1/128fsn ns Normal Speed mode (8 kHz ≤ fs ≤ 48 kHz) tBCK 1/128fsd ns Double Speed mode (48 kHz ≤ fs ≤ 96 kHz) tBCK 1/64fsq ns Quad Speed mode (96 kHz ≤ fs ≤ 192 kHz) tBCKL 36 ns BICK Pulse Width Low tBCKH 36 ns BICK Pulse Width High tLRB 30 ns LRCK Edge to BICK “↑” (Note 19) tBLR 30 ns BICK “↑” to LRCK Edge (Note 19) tLRS 30 ns LRCK to SDTO (MSB) (Except I2S mode) tBSD 30 ns BICK “↓” to SDTO1/2/3 Normal mode (TDM1-0 bits = “00”) (fs = 384 kHz, 768 kHz) (Figure 20) BICK Period tBCK 1/64fso ns Oct Speed mode tBCK 1/48fsh ns Hex Speed mode tBCKL 12 ns BICK Pulse Width Low tBCKH 12 ns BICK Pulse Width High tLRB 12 ns LRCK Edge to BICK “↑” (Note 19) tBLR 12 ns BICK “↑” to LRCK Edge (Note 19) tBSDD 5 22 ns BICK “↑” to SDTO1/2/3 Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5536 should be reset by the PDN pin or RSTN bit. Note 19. BICK rising edge must not occur at the same time as LRCK edge. 015099885-E-00 2016/03 - 20 - [AK5536] (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Slave mode) (Figure 21) TDM128 mode (TDM1-0 bits = “01”) BICK Period tBCK 1/128fsn ns Normal Speed mode tBCK 1/128fsd ns Double Speed mode tBCK 1/128fsq ns Quad Speed mode tBCKL 14 ns BICK Pulse Width Low tBCKH 14 ns BICK Pulse Width High tLRB 14 ns LRCK Edge to BICK “↑” (Note 19) tBLR 14 ns BICK “↑” to LRCK Edge (Note 19) tBSDD 5 30 ns BICK “↑” to SDTO1/2 tSDH 5 ns TDMIN Hold Time tSDS 5 ns TDMIN Setup Time TDM256 mode (TDM1-0 bits = “10”) BICK Period tBCK 1/256fsn ns Normal Speed mode tBCK 1/256fsd ns Double Speed mode tBCKL 14 ns BICK Pulse Width Low tBCKH 14 ns BICK Pulse Width High tLRB 14 ns LRCK Edge to BICK “↑” (Note 19) tBLR 14 ns BICK “↑” to LRCK Edge (Note 19) tBSDD 5 30 ns BICK “↑” to SDTO1 tSDH 5 ns TDMIN Hold Time tSDS 5 ns TDMIN Setup Time TDM512 mode (TDM1-0 bits = “11”) BICK Period tBCK 1/512fsn ns Normal Speed mode tBCKL 14 ns BICK Pulse Width Low tBCKH 14 ns BICK Pulse Width High tLRB 14 ns LRCK Edge to BICK “↑” (Note 19) tBLR 14 ns BICK “↑” to LRCK Edge (Note 19) tBSDD 5 30 ns BICK “↑” to SDTO1 tSDH 5 ns TDMIN Hold Time tSDS 5 ns TDMIN Setup Time Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5536 should be reset by the PDN pin or RSTN bit. Note 19. BICK rising edge must not occur at the same time as LRCK edge. 015099885-E-00 2016/03 - 21 - [AK5536] (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), CL= 10 pF) Min. Typ. Max. Parameter Symbol Unit Audio Interface Timing (Master mode) (Figure 22) Normal mode (TDM1-0 bits = “00”) (8 kHz  fs  216 kHz) BICK Period tBCK 1/64fsn ns Normal Speed mode tBCK 1/64fsd ns Double Speed mode tBCK 1/64fsq ns Quad Speed mode dBCK 50 % BICK Duty tMBLR 20 20 ns BICK “↓” to LRCK Edge tBSD 20 ns BICK “↓”to SDTO1/2/3 20 Normal mode (TDM1-0 bits = “00”) (fs = 384kHz, 768 kHz) (LDOE pin = ”H”) BICK Period tBCK 1/64fso ns Oct speed mode tBCK 1/64fsh ns Hex speed mode dBCK 50 % BICK Duty tMBLR 4 4 ns BICK “↓” to LRCK Edge tBSD 4 ns BICK “↓” to SDTO1/2/3 4 Normal mode (TDM1-0 bits = “00”) (fs = 384 kHz,768 kHz) (LDOE pin = ”L”) BICK Period tBCK 1/64fso ns Oct speed mode tBCK 1/48fsh ns Hex speed mode dBCK 50 % BICK Duty tMBLR 5 5 ns BICK “↓” to LRCK Edge tBSD 5 ns BICK “↓” to SDTO1/2/3 5 Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5536 should be reset by the PDN pin or RSTN bit. 015099885-E-00 2016/03 - 22 - [AK5536] (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), CL= 10 pF) Min. Typ. Max. Parameter Symbol Unit Audio Interface Timing (Master mode) (Figure 22) TDM128 mode (TDM1-0 bits = “01”) BICK Period tBCK 1/128fsn ns Normal Speed mode tBCK 1/128fsd ns Double Speed mode tBCK 1/128fsq ns Quad Speed mode dBCK 50 % BICK Duty tMBLR 5 5 ns BICK “↓” to LRCK Edge tBSD 5 ns BICK “↓” to SDTO1/2 5 tSDH ns TDMIN Hold Time 5 tSDS ns TDMIN Setup Time 5 TDM256 mode (TDM1-0 bits = “10”) BICK Period tBCK 1/256fsn ns Normal Speed mode tBCK 1/256fsd ns Double Speed mode dBCK 50 % BICK Duty tMBLR 5 5 ns BICK “↓” to LRCK Edge tBSD 5 ns BICK “↓” to SDTO1 5 tSDH ns TDMIN Hold Time 5 tSDS ns TDMIN Setup Time 5 TDM512 mode (TDM1-0 bits = “11”) BICK Period tBCK 1/512fsn ns Normal Speed mode dBCK 50 % BICK Duty tMBLR 5 5 ns BICK “↓” to LRCK Edge tBSD 5 ns BICK “↓” to SDTO1 5 tSDH ns TDMIN Hold Time 5 tSDS ns TDMIN Setup Time 5 Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5536 should be reset by the PDN pin or RSTN bit. 015099885-E-00 2016/03 - 23 - [AK5536] (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing (Master mode) (Figure 23) DSD Audio Interface Timing (64fs mode, DSDSEL 1-0 bits = “00”) tDCK 1/64fs ns DCLK Period 144 tDCKL ns DCLK Pulse Width Low 144 tDCKH ns DCLK Pulse Width High tDDD 20 ns DCLK Edge to DSDOL/R (Note 20) 20 DSD Audio Interface Timing (128fs mode, DSDSEL 1-0 bits = “01”) tDCK 1/128fs ns DCLK Period 72 tDCKL ns DCLK Pulse Width Low 72 tDCKH ns DCLK Pulse Width High tDDD 10 ns DCLK Edge to DSDOL/R (Note 20) 10 DSD Audio Interface Timing (256fs mode, DSDSEL 1-0 bits = “10”) tDCK 1/256fs ns DCLK Period 36 tDCKL ns DCLK Pulse Width Low 36 tDCKH ns DCLK Pulse Width High tDDD 10 ns DCLK Edge to DSDOL/R (Note 20) 10 Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5536 should be reset by the PDN pin or RSTN bit. Note 20. tDDD is defined from a falling edge of DCLK “↓” to a DSDOL/R edge when DCKB bit = “0” and it is defined from a rising edge of DCLK “↑” to a DSDOL/R edge when DCKB bit = “1”. 015099885-E-00 2016/03 - 24 - [AK5536] (Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”), VDD18= 1.7-1.98 V (LDOE pin=“L”), CL= 10 pF) Parameter Symbol Min. Typ. Max. Unit Control Interface Timing (3-Wire Serial mode): (Figure 25) (Figure 26) tCCK 200 ns CCLK Period tCCKL 80 ns CCLK Pulse Width Low tCCKH 80 ns Pulse Width High tCDS 40 ns CDTI Setup Timing tCDH 40 ns CDTI Hold Timing tCSW 150 ns CSN “H” Time tCSS 50 ns CSN “↓” to CCLK “↑” tCSH 50 ns CCLK “↑” to CSN “↑” Control Interface Timing (I2C Bus mode): (Figure 27) fSCL 400 kHz SCL CLOCK Frequency tBUF 1.3 µs Bus Free Time Between Transmissions tHD STA 0.6 µs Start Condition Hold Tune (Prior to First Clock Pulse) tLow 1.3 µs Clock Low Time tHIGH 0.6 µs Clock High Time tSU STA 0.6 µs Setup Time for Repeated Start Condition tHD DAT 0 µs SDA Hold Time from SCL Falling (Note 21) tSU DAT 0.1 µs SDA Setup Time from SCL Rising tR 1.0 µs Rise Time of Both SDA and SCL Lines tF 0.3 µs Fall Time of Both SDA and SCL Lines tSU STO 0.6 µs Setup Time for Stop Condition tSP 0 50 ns Pulse Width of Spike Noise Suppressed by Input Filter Cb 400 pF Capacitive Load on Bus Power Down & Reset Timing (Figure 28) tPD 150 ns PDN Pulse Width (Note 22) tRPD 30 ns PDN Reject Pulse Width (Note 22) tPDV 583 1/fs PDN “↑” to SDTO1-4 valid (Note 23) Note 21. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 22. The AK5536 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L” for more than 150 ns for a certain reset. The AK5536 is not reset by the “L” pulse less than 30 ns. Note 23. This cycle is the number of LRCK rising edges from the PDN pin = “H”. 015099885-E-00 2016/03 - 25 - [AK5536] ■ Timing Diagram [1] PCM Mode 1/fCLK 50%TVDD MCLK tdCLKH tdCLKL dCLK=tdCLKHfs100 or tdCLKLfs100 1/fs 50%TVDD LRCK tLRH tLRL tBCK Duty=tLRHfs100 or tLRLfs100 VIH BICK VIL tBCKH tBCKL Figure 17. Clock Timing (Slave Mode) 1/fCLK 50%TVDD MCLK tCLKH tCLKL dCLK=tCLKHfCLK100 or tCLKLfCLK100 1/fs 50%TVDD LRCK Duty=tLRHfs100 tLRH tBCK 50%TVDD BICK tBCKH tBCKL dBCK=tBCKH/tBCK100 or tBCKL/tBCK100 Figure 18. Clock Timing (Master Mode) 015099885-E-00 2016/03 - 26 - [AK5536] VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD SDTO1/2/3 50%TVDD Figure 19. Audio Interface Timing (Normal Mode & Slave Mode: 8 kHz ≤ fs ≤ 216 kHz) VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSDD SDTO1/2/3 50%TVDD Figure 20. Audio Interface Timing (Normal & Slave Mode: fs=384 kHz, 768 kHz) VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSDD SDTO1/2/3 50%TVDD tSDS tSDH VIH TDMIN VIL Figure 21. Audio Interface Timing (TDM & Slave Mode) 015099885-E-00 2016/03 - 27 - [AK5536] LRCK 50%TVDD tMBLR 50%TVDD BICK tBSD 50%TVDD SDTO1/2/3 tSDS tSDH VIH TDMIN VIL Figure 22. Audio Interface Timing (Master Mode) [2] DSD Mode tDCK tDCKL tDCKH VOH DCLK VOL tDDD VOH DSDOL1-3 DSDOR1-3 VOL Figure 23. Audio Serial Interface Timing (Normal Mode, DCKB bit= “0” or DCKB pin= “L”) tDCK tDCKL tDCKH VOH DCLK VOL tDDD tDDD VOH DSDOL1-3 DSDOR1-3 VOL Figure 24. Audio Serial Interface Timing (Phase Modulation Mode, DCKB bit= “0” or DCKB pin= “L”) 015099885-E-00 2016/03 - 28 - [AK5536] [3] 3-Wire Serial Interface VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL Figure 25. WRITE Command Input Timing (3-wire Serial Mode) tCSW VIH CSN VIL tCSH VIH CCLK VIL CDTI D3 D2 D1 VIH D0 VIL Figure 26. WRITE Data Input Timing (3-wire Serial Mode) [4]I2C Interface VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Figure 27. I2C Bus Mode Timing 015099885-E-00 2016/03 - 29 - [AK5536] [5] Power-down Timing tPD VIH PDN VIL tPDV SDTO1/2/3 tRP D 50%TVDD Figure 28. Power-down & Reset Timing 015099885-E-00 2016/03 - 30 - [AK5536] 12. Functional Descriptions ■ Digital Core Power Supply The digital core of the AK5536 is operates off of a 1.8 V power supply. Normally, this voltage is generated by the internal LDO from TVDD (3.3 V) for digital interface. The internal LDO will be powered up by setting the LDOE pin = “H”. Set the LDOE pin to “L” and supply a 1.8 V power to the VDD18 pin externally when a 1.8 V is used as TVDD. ■ Output Mode The AK5536 is able to output either PCM or DSD data. The DP pin or DP bit select the output mode. Set the PW2 pin = PW1 pin = PW0 pin = “L” or RSTN bit = “0” or PW8-1 bits = “0H” to reset all channels when changing the PCM/DSD mode. The AK5536 outputs data from the SDTO1-3 pins by BICK and LRCK in PCM mode. DSD data are output from the DSDOL1-3 pins and DSDOR1-3 pins by DCLK in DSD mode. DP pin DP bit Interface L 0 PCM H 1 DSD Table 1 PCM/DSD Mode Control ■ Master Mode and Slave Mode The AK5536 requires a master clock (MCLK), an audio serial data clock (BICK) and an output channel clock (LRCK) in PCM mode. In this case, the LRCK frequency will be the sampling frequency. Both master and slave modes are available in PCM mode. In master mode, the AK5536 internally generates BICK and LRCK clocks from MCLK inputs and outputs them from the BICK pin and the LRCK pin. In slave mode, AK5536 operates in the input MCLK, BICK and LRCK. MCLK must be synchronized with BICK and LRCK but the phase is not important. The AK5536 is in master mode when the MSN pin = “H” and in slave mode when the MSN pin = “L”. The AK5536 requires a master clock (MCLK) in DSD mode. Slave mode is not available in DSD mode, only master mode is supported. ■ System Clock [1] PCM Mode The external system clocks, which are required to operate the AK5536, are MCLK, BICK and LRCK in PCM mode. MCLK frequency is determined based on LRCK frequency, according to the operation mode. Table 2, Table 3, Table 4 show MCLK frequencies correspond to the normal audio rate. Set the frequency ratio between Sampling frequency and MCLK by the CKS3-0 pins (Table 5) All channels must be reset when changing the clock mode or audio interface format by the CKS2-0 pins (bits), TDM1-0 pins (bits), DIF1-0 pins (bits) and the MSN pin. In parallel control mode, all channels will be reset by the PDN pin = “L” or PW2-0 pins = “LLL”. In serial control mode, all channels will be reset by RSTN bit = “0” or PW6-1 bits = “0H”. A stable clock must be supplied after releasing the reset. The AK5536 integrates a phase detection circuit for LRCK. If the internal timing becomes out of synchronization in slave mode, the AK5536 is reset automatically and the phase is resynchronized. The following sequence must be executed when synchronizing multiple AK5536’s. Stop all AK5536’s in reset status by setting the PDN pin = “L” → “H” after stopping the system clock. Make pin or register settings while all channels are in reset status. After that, input the same system clock to all AK5536’s. 015099885-E-00 2016/03 - 31 - [AK5536] 32fs 48fs 64fs 96fs 128fs MCLK 192fs 32 kHz N/A N/A N/A N/A N/A N/A 48 kHz N/A N/A N/A N/A N/A N/A 96 kHz N/A N/A N/A N/A N/A N/A 192 kHz N/A N/A N/A N/A 384 kHz N/A N/A fs 768 kHz 24.576 36.864 MHz MHz 24.576 36.864 MHz MHz N/A N/A 24.576 36.864 MHz MHz 256fs 384fs 512fs 768fs 1024fs 8.192 12.288 16.384 24.576 32.768 MHz MHz MHz MHz MHz 12.288 18.432 24.576 36.864 N/A MHz MHz MHz MHz 24.576 36.864 N/A N/A N/A MHz MHz N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A (N/A: Not Available) Table 2. System Clock Example (Slave Mode) 32fs 48fs 64fs 96fs 128fs MCLK 192fs 32 kHz N/A N/A N/A N/A N/A N/A 48 kHz N/A N/A N/A N/A N/A N/A 96 kHz N/A N/A N/A N/A N/A N/A 192 kHz N/A N/a N/A N/A fs 24.576 36.864 MHz MHz 24.576 36.864 49.152 768 kHz N/A MHz MHz MHz 384 kHz N/A N/A 24.576 36.864 MHz MHz 256fs 384fs 512fs 768fs 1024fs 8.192 12.288 16.384 24.576 32.768 MHz MHz MHz MHz MHz 12.288 18.432 24.576 36.864 N/A MHz MHz MHz MHz 24.576 36.864 N/A N/A N/A MHz MHz N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A (N/A: Not Available) Table 3. System Clock Example (Master Mode) 32fs 48fs 64fs 96fs 128fs MCLK 192fs 256fs 384fs 32 kHz N/A N/A N/A N/A N/A N/A N/A N/A 48 kHz N/A N/A N/A N/A N/A N/A N/A N/A 96 kHz N/A N/A N/A N/A N/A N/A 192 kHz N/A N/A N/A N/A 384 kHz N/A N/A fs 768 kHz 24.576 36.864 MHz MHz 24.576 36.864 MHz MHz NA N/A 24.576 36.864 MHz MHz 24.576 36.864 MHz MHz 512fs 768fs 1024fs 16.384 24.576 32.768 MHz MHz MHz 24.576 36.864 N/A MHz MHz N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A (N/A: Not Available) Table 4. System Clock Example (Auto Mode) 015099885-E-00 2016/03 - 32 - [AK5536] CKS3 pin(bit) CKS2 pin(bit) CKS1 pin(bit) CKS0 pin(bit) L(0) L(0) L(0) L(0) L(0) L(0) L(0) H(1) L(0) L(0) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) L(0) L(0) L(0) H(1) L(0) H(1) L(0) H(1) H(1) L(0) L(0) H(1) H(1) H(1) H(1) L(0) L(0) L(0) H(1) L(0) L(0) H(1) H(1) L(0) H(1) L(0) H(1) L(0) H(1) H(1) H(1) H(1) L(0) L(0) H(1) H(1) L(0) H(1) H(1) H(1) H(1) L(0) H(1) H(1) H(1) H(1) MSN pin L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L MCLK Frequency 128fs 24M 192fs 36M 256fs 12M 256fs 24M 384fs 36M 384fs 18M 512fs 24M 768fs 36M 64fs 24M 32fs 24M 96fs 36M 48fs 36M NA 64fs 49.1M 1024fs 32M Speed Mode fs Range Quad Speed 108 kHz  fs  216 kHz Quad Speed 108 kHz  fs  216 kHz Normal Speed 8 kHz  fs  54 kHz Double Speed 54 kHz  fs  108 kHz Double Speed 54 kHz  fs  108 kHz Normal Speed 8 kHz  fs  54 kHz Normal Speed 8 kHz  fs  54 kHz Normal Speed 8 kHz  fs  54 kHz Oct Speed fs = 384 kHz Hex Speed fs = 768 kHz Oct Speed fs = 384 kHz Hex Speed fs = 768 kHz NA Hex Speed fs = 768 kHz Normal Speed 8 kHz ≤ fs ≤ 32 kHz NA NA Auto H NA Table 5. Clock Mode (fs & MCLK Frequency) 015099885-E-00 8 kHz  fs  216 kHz fs = 384kHz, 768kHz NA 2016/03 - 33 - [AK5536] [2] DSD Mode The external clock, which is required to operate the AK5536, is MCLK in DSD mode. The AK5536 generates DCLK from MCLK inputs and DSD data outputs (DSDOL1-3 and DSDOR1-3) are synchronized with DCLK. The necessary MCLK frequencies are 512fs and 768fs (fs=32 kHz, 44.1 kHz, 48 kHz). MCLK frequency can be changed by the DCKS pin (bit). After exiting reset (PDN pin = “L” → “H”) upon power-up, the AK5536 is in power-down state until MCLK is input. DCKS pin (bit) MCLK Frequency L (0) 512fs H (1) 768fs Table 6. System Clock (DSD Mode) (default) The AK5536 supports 64fs, 128fs and 256fs DSD sampling frequencies (fs= 32 kHz 44.1 kHz, 48 kHz). DSDSEL1-0 pins (bits) control this setting (Table 7). DSDSEL1 pin (bit) L(0) L(0) H(1) H(1) DSDSEL0 pin (bit) L(0) H(1) L(0) H(1) Frequency DSD Sampling Frequency Mode fs=32 kHz fs=44.1 kHz fs=48 kHz 64fs 2.048 MHz 2.8224 MHz 3.072 MHz 128fs 4.096 MHz 5.6448 MHz 6.144 MHz 256fs 8.192 MHz 11.2896 MHz 12.288 MHz Reserved Reserved Reserved Table 7. DSD Sampling Frequency Select (default) ■ Audio Interface Format TDM1-0 pins(bits), DIF1-0 pins(bits), SLOW pin(bit) and SD pin(bit) settings should be changed when all channel are reset condition. [1] PCM Mode 48 types of audio interface format can be selected by the TDM1-0 pins (bits), MSN pin and DIF1-0 pins (bits) (Table 8, Table 9). In all formats the serial data is MSB-first, 2's complement format. In master mode, the SDTO1-3 is clocked out on the falling edge of BICK. Normal output in slave mode, the SDTO1-3 is clocked out on the falling edge of BICK if 8 kHz ≤ fs ≤ 216 kHz. In other conditions, the data is clocked out on the prior rising edge of BICK to compensate for some delay that renders the edge of data transition near BICK falling edge. Audio interface format is distinguished in four types: Normal mode, TDM128 mode, TDM256 mode and TDM512 mode are available. The TDM1-0 pins (bits) select these modes. In Normal mode (non TDM), AIN1 and AIN2 A/D converted data is output from the SDTO1 pin, AIN3 and AIN4 A/D converted data is output from the SDTO2 pin, AIN5 and AIN6 A/D converted data is output from the SDTO3 pin. The BICK frequency must be in the rage from 48fs to 128fs (fs= 48 kHz) in slave mode if the audio interface format is in normal output (non TDM) and the interface speed is in Normal, Double or Quad mode. Bit length of A/D data is 24-bit or 32-bit and it is selected by the DIF1 pin (bit). The BICK frequency must be set to 32fs, 48fs or 64fs in slave mode if the audio interface format is normal output (non TDM) and the interface speed is in OCT mode. Bit length of A/D data is determined by BICK frequency regardless of the DIF1 pin (bit) if the BICK frequency is 32fs or 48fs. It is 16-bit when the BICK frequency is 32fs and 24-bit when the BICK frequency is 48fs. When the BICK frequency is 64fs, A/D data can be selected between 24-bit and 32-bit by the DIF1 pin (bit). The BICK frequency must be set to 32fs or 48fs in slave mode if the audio interface format is normal output (non TDM) and the interface speed is in EXT mode. Bit length of A/D data is determined by BICK frequency regardless of the DIF1 pin (bit). It is 16-bit when the BICK frequency is 32fs and 24-bit when the BICK frequency is 48fs. 015099885-E-00 2016/03 - 34 - [AK5536] The BICK frequency will be 64fs in master mode if the audio interface format is normal output (non TDM) and the interface speed is Normal, Double or Quad mode. Data bit length can be selected from 24-bit and 32-bit by the DIF1 pin (bit). The MCLK frequency must be 64fs or 96fs in master mode if the audio interface format is normal output (non TDM) and the interface speed is OCT mode. The BICK frequency will be 64fs. Data bit length can be selected from 24-bit and 32-bit by the DIF1 pin (bit). The BICK frequency will be synchronized with the MCLK frequency in master mode if the audio interface format is normal output (non TDM) and the interface speed is HEX mode. The MCLK frequency must be 32fs, 48fs or 64fs. The bit length of A/D data is 16-bit when the MCLK frequency is 32fs, 24-bit when the MCLK frequency is 48fs and 24-bit or 32-bit can be selected by the DIF1 pin (bit) when the MCLK frequency is 64fs. The DIF0 pin selects the A/D data format between MSB justified and I2S Compatible. No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Multiplex Speed TDM1 TDM0 Mode Mode pin(bit) pin(bit) MSN Pin L Normal Double Quad L(0) L(0) H L Normal OCT HEX L(0) L(0) H DIF1 DIF0 SDTO pin(bit) pin(bit) L(0) L(0) 24-bit, MSB 2 L(0) H(1) 24-bit, I S H(1) L(0) 32-bit, MSB 2 H(1) H(1) 32-bit, I S L(0) L(0) 24-bit, MSB 2 L(0) H(1) 24-bit, I S H(1) L(0) 32-bit, MSB 2 H(1) H(1) 32-bit, I S * L(0) 16-bit, MSB 2 * H(1) 16-bit, I S * L(0) 24-bit, MSB 2 * H(1) 24-bit, I S L(0) L(0) 24-bit, MSB 2 L(0) H(1) 24-bit, I S H(1) L(0) 32-bit, MSB 2 H(1) H(1) 32-bit, I S * L(0) 16-bit, MSB 2 * H(1) 16-bit, I S * L(0) 24-bit, MSB 2 * H(1) 24-bit, I S L(0) L(0) 24-bit, MSB 2 L(0) H(1) 24-bit, I S H(1) L(0) 32-bit, MSB 2 H(1) H(1) 32-bit, I S LRCK Pol. I/O H/L I L/H I H/L I L/H I H/L O L/H O H/L O L/H O ↑ I ↓ I ↑ I ↓ I ↑ I ↓ I ↑ I ↓ I ↑ O ↓ O ↑ O ↓ O ↑ O ↓ O ↑ O ↓ O BICK Freq. 48-128fs 48-128fs 64-128fs 64-128fs 64fs 64fs 64fs 64fs 32fs 32fs 48fs 48fs 64fs 64fs 64fs 64fs 32fs 32fs 48fs 48fs 64fs 64fs 64fs 64fs I/O I I I I O O O O I I I I I I I I O O O O O O O O MCLK Freq. I/O 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 32-96fs I 32-96fs I 32-96fs I 32-96fs I 32-96fs I 32-96fs I 32-96fs I 32-96fs I 32fs I 32fs I 48fs I 48fs I 64-96fs I 64-96fs I 64-96fs I 64-96fs I Table 8. Audio Interface Format (Normal Mode) 015099885-E-00 2016/03 - 35 - [AK5536] No. Multiplex Speed TDM1 TDM0 Mode Mode pin(bit) pin(bit) 24 25 26 Normal 27 TDM128 Double 28 Quad 29 30 31 32 33 34 35 Normal TDM256 Double 36 37 38 39 40 41 42 43 TDM512 Normal 44 45 46 47 MSN pin L L(0) H(1) H L H(1) L(0) H L H(1) H(1) H DIF1 DIF0 pin(bit) pin(bit) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) L(0) L(0) L(0) H(1) H(1) L(0) H(1) H(1) SDTO 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S 24-bit, MSB 2 24-bit, I S 32-bit, MSB 2 32-bit, I S LRCK Edg. I/O ↑ I ↓ I ↑ I ↓ I ↑ O ↓ O ↑ O ↓ O ↑ I ↓ I ↑ I ↓ I ↑ O ↓ O ↑ O ↓ O ↑ I ↓ I ↑ I ↓ I ↑ O ↓ O ↑ O ↓ O BICK Freq. I/O 128fs I 128fs I 128fs I 128fs I 128fs O 128fs O 128fs O 128fs O 256fs I 256fs I 256fs I 256fs I 256fs O 256fs O 256fs O 256fs O 512fs I 512fs I 512fs I 512fs I 512fs O 512fs O 512fs O 512fs O MCLK Freq. I/O 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 128-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 256-1024fs I 512-1024fs I 512-1024fs I 512-1024fs I 512-1024fs I Table 9. Audio Interface Format (TDM Mode) 015099885-E-00 2016/03 - 36 - [AK5536] Cascade Connection in TDM Mode The AK5536 supports cascade connection in TDM mode. All A/D converted data of connected AK5536 are output from the SDTO1 pin of the last AK5536 by cascade connection. When the ODP pin = “L”, a cascade connection of two devices in TDM512 mode is supported. Figure 29 shows a connection example. When the ODP pin = “H”, a cascade connection of two up to sixteen devices is available. When using multiple devices in slave mode on cascade connection, internal operation timing of each device may differ for one MCLK cycle depending on MCLK and BICK input timings. To prevent this timing difference, BICK “↓” should be more than ± 10ns from MCLK “↑” as shown in Table 10. To realize this timing, BICK divided by two should be input on a falling edge of MCLK as shown in Figure 54 when MCLK=2xBICK (normal speed 1024fs mode). When MCLK=BICK (normal speed 512fs mode), MCLK and BICK should be input in-phase as shown in Figure 55 to satisfy the timing shown in Table 10. 256fs, 512fs or 1024fs AK5536 #1 MCLK 48kHz LRCK 512fs BICK 256fs, 512fs or 1024fs TDMIN 48kHz SDTO1 GND 512fs Slave mode BICK BICK SDTO1 GND AK5536 #2 TDMIN LRCK TDMIN LRCK Master mode AK5536 #2 MCLK AK5536 #1 MCLK MCLK 16ch TDM LRCK BICK SDTO1 TDMIN 16ch TDM SDTO1 Slave mode Slave mode TDM512 TDM512 Figure 29. Cascade Connection 015099885-E-00 2016/03 - 37 - [AK5536] LRCK 0 1 2 11 12 13 23 24 31 0 1 2 11 12 13 23 24 31 0 1 BICK(64fs) SDTO1-3 1 13 12 11 23 22 0 23 22 13 1 12 11 0 31 23: MSB, 0: LSB AIN1/3/5 Data AIN2/4/6 Data Figure 30. Mode 0/4 Timing (Normal Output, Normal/Double/Quad Speed Mode, MSB Justified, 24-bit) LRCK 0 1 2 3 22 23 24 25 29 30 31 0 1 2 3 22 23 24 25 29 30 31 0 1 BICK(64fs) SDTO1-3 23 22 2 1 0 23 22 2 1 0 23: MSB, 0: LSB AIN1/3/5 Data AIN2/4/6 Data Figure 31. Mode 1/5 Timing (Normal Output, Normal/Double/Quad Speed Mode, I2S Compatible, 24-bit) LRCK 0 1 2 11 12 13 20 21 31 0 1 2 12 13 14 24 25 31 0 1 BICK(64fs) SDTO1-3 12 11 22 20 19 31 30 1 0 31 30 22 12 11 20 19 1 0 31 31: MSB, 0: LSB AIN1/3/5 Data AIN2/4/6 Data Figure 32. Mode 2/6 Timing (Normal Output, Normal/Double/Quad Speed Mode, MSB Justified, 32-bit) LRCK 0 1 2 3 23 24 25 26 29 30 31 0 1 2 3 23 24 25 26 29 30 31 0 1 BICK(64fs) SDTO1-3 31 30 16 15 14 3 2 1 0 31 30 16 15 14 3 2 1 0 31: MSB, 0: LSB AIN1/3/5 Data AIN2/4/6 Data Figure 33. Mode 3/7 Timing (Normal Output, Normal/Double/Quad Speed Mode, I2S Compatible, 32-bit) 015099885-E-00 2016/03 - 38 - [AK5536] 32 BICK LRCK (Master) LRCK (Slave) BICK (32fs) SDTO1-3 (O) 0 15 14 9 8 7 6 1 0 15 14 9 8 7 6 1 AIN1/3/5 Data AIN2/4/6 Data 16 BICK 16 BICK 0 15 14 Figure 34. Mode 8/16 Timing (Normal Output, OCT/HEX Speed Mode, MSB Justified, 16-bit) 32 BICK LRCK (Master) LRCK (Slave) BICK (32fs) SDTO1-3 (O) 0 15 14 9 8 7 6 1 0 15 14 9 8 7 6 1 AIN1/3/5 Data AIN2/4/6 Data 16 BICK 16 BICK 0 15 14 Figure 35. Mode 9/17 Timing (Normal Output, OCT/HEX Speed Mode, I2S Compatible, 16-bit) 48 BICK LRCK (Master) LRCK (Slave) BICK (48fs) SDTO1-3 (O) 0 23 22 13 12 11 10 1 0 23 22 13 12 11 10 1 AIN1/3/5 Data AIN2/4/6 Data 24 BICK 24 BICK 0 23 22 Figure 36. Mode 10/18 Timing (Normal Output, OCT/HEX Speed Mode, MSB Justified, 24-bit) 48 BICK LRCK (Master) LRCK (Slave) BICK (48fs) SDTO1-3 (O) 0 23 22 13 12 11 10 1 0 23 22 13 12 11 10 1 AIN1/3/5 Data AIN2/4/6 Data 24 BICK 24 BICK 0 23 22 Figure 37. Mode 11/19 Timing (Normal Output, OCT/HEX Speed Mode, I2S Compatible, 24-bit) 015099885-E-00 2016/03 - 39 - [AK5536] 64 BICK LRCK (Master) LRCK (Slave) BICK (64fs) SDTO1-3 (O) 23 22 15 8 7 0 23 22 15 8 7 0 AIN1/3/5 Data AIN2/4/6 Data 32 BICK 32 BICK 23 22 Figure 38. Mode 12/20 Timing (Normal Output, OCT/HEX Speed Mode, MSB Justified, 24-bit) 64 BICK LRCK (Master) LRCK (Slave) BICK (64fs) SDTO1-3 (O) 23 22 15 8 7 0 23 22 15 8 7 0 AIN1/3/5 Data AIN2/4/6 Data 32 BICK 32 BICK 23 22 Figure 39. Mode 13/21 Timing (Normal Output, OCT/HEX Speed Mode, I2S Compatible, 24-bit) 64 BICK LRCK (Master) LRCK (Slave) BICK (64fs) SDTO1-3 (O) 0 31 30 17 16 15 14 1 0 31 30 17 16 15 14 1 AIN1/3/5 Data AIN2/4/6 Data 32 BICK 32 BICK 0 31 30 Figure 40. Mode 14/22 Timing (Normal Output, OCT/HEX Speed Mode, MSB Justified, 32-bit) 64 BICK LRCK (Master) LRCK (Slave) BICK (64fs) SDTO1-3 (O) 0 31 30 17 16 15 14 1 0 31 30 17 16 15 14 1 AIN1/3/5 Data AIN2/4/6 Data 32 BICK 32 BICK 0 31 30 Figure 41. Mode 15/23 Timing (Normal Output, OCT/HEX Speed Mode, I2S Compatible, 32-bit) 015099885-E-00 2016/03 - 40 - [AK5536] 128 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) SDTO2 (O) 23 22 0 23 22 0 23 22 0 23 22 0 Data 1 Data 2 Data 3 Data 4 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 23 22 0 Data 5 Data 6 32 BICK 32 BICK 23 22 SDTO3 (O) Figure 42. Mode 24/28 Timing (TDM128 Mode, MSB Justified, 24-bit) 128 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) SDTO2 (O) 23 22 0 23 22 0 23 22 0 23 22 0 Data 1 Data 2 Data 3 Data 4 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 Data 5 Data 6 32 BICK 32 BICK 23 22 23 22 SDTO3 (O) Figure 43. Mode 25/29 Timing (TDM128 Mode, I2S Compatible) 128 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) SDTO2 (O) 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 Data 1 Data 2 Data 3 Data 4 32 BICK 32 BICK 32 BICK 32 BICK 0 31 30 1 0 31 30 1 Data 5 Data 6 32 BICK 32 BICK 0 0 31 30 31 30 SDTO3 (O) Figure 44. Mode 26/30 Timing (TDM128 Mode, MSB Justified) 015099885-E-00 2016/03 - 41 - [AK5536] 128 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 0 31 30 SDTO2 (O) 1 0 31 30 1 0 31 30 1 0 31 30 1 Data 1 Data 2 Data 3 Data 4 32 BICK 32 BICK 32 BICK 32 BICK 0 31 30 1 0 31 30 1 Data 5 Data 6 32 BICK 32 BICK 0 0 31 30 31 30 SDTO3 (O) Figure 45. Mode 27/31 Timing (TDM128 Mode, I2S Compatible) 256 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 22 SDTO2-3 (O) Figure 46. Mode 32/36 Timing (TDM256 Mode, MSB Justified, 24-bit) 256 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 SDTO2-3 (O) Figure 47. Mode 33/37 Timing (TDM256 Mode, I2S Compatible, 24-bit) 015099885-E-00 2016/03 - 42 - [AK5536] 256 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 31 30 SDTO2-3 (O) Figure 48. Mode 34/38 Timing (TDM256 Mode, MSB Justified, 32-bit) 256 BICK LRCK (Master) LRCK (Slave) BICK (256fs) SDTO1 (O) 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 31 SDTO2-3 (O) Figure 49. Mode 35/39 Timing (TDM256 Mode, I2S Compatible, 32-bit) 512 BICK LRCK (Master) LRCK (Slave) BICK (512fs) SDTO1 (O) 23 22 0 23 33 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 #2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK SDTO2-3 (O) TDMIN (I) 23 22 (#1 SDTO1) #1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 32 BICK 23 22 0 31 30 32 BICK Figure 50. Mode 40/44 Timing (TDM512 Mode, MSB Justified, 24-bit) 015099885-E-00 2016/03 - 43 - [AK5536] 512 BICK LRCK (Master) LRCK (Slave) BICK (512fs) SDTO1 (O) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 #2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK SDTO2-3 (O) TDMIN (I) 23 22 (#1 SDTO1) #1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 22 32 BICK 0 23 32 BICK Figure 51. Mode 41/45 Timing (TDM512 Mode, I2S Compatible, 24-bit) 512 BICK LRCK (Master) LRCK (Slave) BICK (512fs) SDTO1 (O) 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 #2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK SDTO2-3 (O) TDMIN (I) 31 30 (#1 SDTO1) #1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK Figure 52. Mode 42/46 Timing (TDM512 Mode, MSB Justified, 32-bit) 512 BICK LRCK (Master) LRCK (Slave) BICK (512fs) SDTO1 (O) 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 #2 Data 1 #2 Data 2 #2 Data 3 #2 Data 4 #2 Data 5 #2 Data 6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 30 1 0 31 #1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data6 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK SDTO2-3 (O) TDMIN (I) 31 30 (#1 SDTO1) #1 Data 1 #1 Data 2 #1 Data 3 #1 Data 4 #1 Data 5 #1 Data 6 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 30 32 BICK 1 0 31 32 BICK Figure 53. Mode 43/47 Timing (TDM512 Mode, I2S Compatible, 32-bit) Parameter MCLK “↑” to BICK “↓” BICK “↓” to MCLK“↑” Symbol Min. tMCB tBIM 10 10 Typ. Max. Unit ns ns Table 10. TDM Mode Clock Timing 015099885-E-00 2016/03 - 44 - [AK5536] VIH MCLK VIL tMCB tBIM VIH BICK VIL Figure 54. Audio Interface Timing (Slave mode, TDM mode, MCLK=2×BICK) VIH MCLK VIL tMCB tBIM VIH VIL BICK Figure 55. Audio Interface Timing (Slave Mode, TDM Mode, MCLK=BICK) [2] DSD Mode DSD output is available only when the AK5536 is in Master mode. The DCLK frequency can be selected from 64fs, 128fs and 256fs by setting the DSDSEL1-0 pins (bits). The AK5536 enters Phase Modulation mode by setting PMOD pin = “H” or PMOD bit = “1”. It does not support Phase Modulation mode when the DCLK frequency is 256fs. DCKB bit controls DCLK polarity. DCLK (64fs, 128fs, 256fs) DCKB bit=”1” DCLK (64fs, 128fs, 256fs) DCKB bit=”0” DSDOL, DSDOR Normal D0 DSDOL,DSDOR Phase Modulation D0 D1 D1 D2 D1 D2 D3 D2 D3 Figure 56. DSD Mode Timing 015099885-E-00 2016/03 - 45 - [AK5536] ■ Channel Summation (PCM Mode, DSD Mode) Channel Summation function improves the dynamic range and S/N performance by averaging all A/D data of multiple-channel that the same signal is input. The AK5536 supports 6-to-3 mode, 4-to-1 mode, 6-to-1 mode. 6-to-3 mode (1.5-Stereo mode) Improve the dynamic range and S/N for 3 dB (2.5 dB in DSD mode) by averaging two channels. 4-to-1 mode (2-Mono mode) Improve the dynamic range and S/N for 6 dB (5 dB in DSD mode) by averaging four channels. In this mode, the data of other two channels are also averaged and output. 6-to-1 mode (Mono mode) Improve the dynamic range and S/N for 7 dB (6 dB in DSD mode) by averaging six channels. Not-Summation mode (3-Stereo mode) Normal mode that does not execute Summation is called as Not-Summation mode or 3-Stereo mode. Refer to the section “CH Power Down & Channel Summation mode” for details. ■ Optimal Data Placement (PCM Mode, DSD Mode) Assigned data to the SDTO1-3 slot is controlled by the ODP pin setting in parallel control mode. When the ODP pin = “L”, the data is output by Fixed Data Placement mode. Channel assignment of data slot is fixed regardless of enable/disenable of channel summation. For example, averaging data of two channels are output to both channel slots. When the ODP pin = “H”, the data is output by Optimal Data Placement mode that is uses data slot more efficiently. In Optimal Data Placement mode, there are no data redundant of channel summation, and the data is output in MSB justified. Therefore, the maximum number of connecting device in cascade connection will be increased. If the AK5536 is set to 6-to-3 mode (1.5-Stereo Mode), two devices can be connected in TDM256 mode, four devices can be connected in TDM512 mode. If the AK5536 is set to 4-to-1 mode (2-Mono Mode), two devices can be connected in TDM128 mode, four devices can be connected in TDM256 mode and eight devices can be connected in TDM512 mode. If the AK5536 is set to 6-to-1 mode (Mono Mode), four devices can be connected in TDM128 mode, eight devices can be connected in TDM256 mode and sixteen devices can be connected in TDM512 mode. In serial control mode, the data output is Optimal Data Placement mode regardless of the ODP pin setting. Refer to “CH Power Down & Channel Summation mode” for details. 015099885-E-00 2016/03 - 46 - [AK5536] ■ CH Power Down & Channel Summation Setting (PCM Mode, DSD Mode) [1] Parallel Control Mode The setting of the PW2-0 pins and the ODP pin controls the channel power-down and channel summation mode setting in parallel mode (Table 11-Table 16). The PDN pin must be set to “L” when changing the ODP pin and the PW2-0 pins. The power consumption of the device can be improved by setting unused channels to power-down state. In this case, the channel circuit that is powered down will be reset. When the ODP pin = “L”, the PW2-0 pins control channel power-down and 6-to-3 mode. In this mode, AIN1 and AIN2 channel data are summed digitally and output from the SDTO1 (DSDOL1 and DSDOR1) by dividing into half amplitude. In the same manner, AIN3 and AIN4 channel data are summed digitally and output from the SDTO2 (DSDOL2 and DSDOR2) by dividing into half amplitude. AIN5 and AIN6 channel data are summed digitally and output from the SDTO3 (DSDOL3 and DSDOR3) by dividing into half amplitude. Power ON/OFF PW2 PW1 PW0 pin pin pin Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 L L L OFF OFF OFF OFF OFF OFF L L H ON OFF ON ON ON ON L H L OFF ON ON ON ON ON L H H ON ON ON ON ON ON H L L OFF OFF ON ON ON ON H L H ON OFF ON ON ON ON H H L OFF ON ON ON ON ON H H H ON ON ON ON ON ON Table 11. Channel Power ON/OFF (Parallel Control Mode, ODP pin= “L”) PW2 pin L L L L H H H H PW1 pin L L H H L L H H Data on Slot PW0 pin Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 L All “0” All “0” All “0” All “0” All “0” H CH6 All “0” (CH3+4)/2 (CH3+4)/2 (CH1+2)/2 L All “0” CH5 (CH3+4)/2 (CH3+4)/2 (CH1+2)/2 H (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH3+4)/2 (CH1+2)/2 L All “0” All “0” CH4 CH3 CH2 H CH6 All “0” CH4 CH3 CH2 L All “0” CH5 CH4 CH3 CH2 H CH6 CH5 CH4 CH3 CH2 Table 12. Slot Data Assign (Parallel Control Mode, ODP pin= “L”) Slot 1 All “0” (CH1+2)/2 (CH1+2)/2 (CH1+2)/2 CH1 CH1 CH1 CH1 When the ODP pin = “H”, the AK5536 becomes optimal data placement mode and data slots can be used efficiently. The PW2-0 pins control power down, 6-to-3 mode, 4-to-1 mode and 6-to-1 mode. In 6-to-3 mode, AIN1 and AIN2 channel data are summed digitally and output from the SDTO1 (DSDOL1) of the slot1 by dividing into half amplitude. In the same manner, AIN3 and AIN4 channel data are summed digitally and output from the SDTO1 (DSDOR1) of the slot2 by dividing into half amplitude. AIN5 and AIN6 channel data are summed digitally and output from the SDTO2 (DSDOL2) of the slot3 by dividing into half amplitude. In 4-to-1 mode, AIN1 - AIN4 channel data are summed digitally and output from the SDTO1 (DSDOL1) of the slot1 by dividing into quarter amplitude. AIN5 – AIN6 channel data are summed digitally and output from the SDTO1 (DSDOR1) of the slot2 by dividing into half amplitude. In 6-to-1 mode, AIN1 – AIN6 channel data are summed digitally and output from the SDTO1 (DSDOL1) of the slot1 by dividing into 1/6 amplitude. 015099885-E-00 2016/03 - 47 - [AK5536] Power ON/OFF PW2 PW1 PW0 pin pin pin Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 L L L OFF OFF OFF OFF OFF OFF L L H ON ON ON ON ON ON L H L ON ON ON ON ON ON L H H ON ON ON ON ON ON H L L ON ON ON ON ON ON H L H ON ON ON ON ON ON H H L ON ON ON ON ON ON H H H ON ON ON ON ON ON Table 13. Channel Power ON/OFF (Parallel Control Mode, ODP pin= “H”) Data on Slot PW2 PW1 PW0 pin pin pin Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 L L L All “0” All “0” All “0” All “0” All “0” All “0” L L H All “0” All “0” All “0” All “0” (CH5+6)/2 (CH1+2+3+4)/4 L H L All “0” All “0” (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH1+2)/2 L H H All “0” All “0” All “0” All “0” All “0” (CH1+2+3+4+5+6)/6 H L L CH6 CH5 CH4 CH3 CH2 CH1 H L H All “0” All “0” All “0” All “0” (CH5+6)/2 (CH1+2+3+4)/4 H H L All “0” All “0” (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH1+2)/2 H H H All “0” All “0” All “0” All “0” All “0” (CH1+2+3+4+5+6)/6 Table 14. Slot Data Assign (Parallel Control Mode, ODP pin= “H”, Normal Output) Data on Slot PW2 PW1 PW0 pin pin pin Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 L L L All “0” All “0” All “0” All “0” All “0” All “0” L L H All “0” All “0” TDMIN TDMIN (CH5+6)/2 (CH1+2+3+4)/4 L H L All “0” All “0” (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH1+2)/2 L H H All “0” All “0” TDMIN TDMIN TDMIN (CH1+2+3+4+5+6)/6 H L L CH6 CH5 CH4 CH3 CH2 CH1 H L H All “0” All “0” TDMIN TDMIN (CH5+6)/2 (CH1+2+3+4)/4 H H L All “0” All “0” (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH1+2)/2 H H H All “0” All “0” TDMIN TDMIN TDMIN (CH1+2+3+4+5+6)/6 Table 15. Slot Data Assign (Parallel Control Mode, ODP pin= “H”, TDM128) Data on Slot PW2 PW1 PW0 pin pin pin Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 L L L All “0” All “0” All “0” All “0” All “0” All “0” L L H TDMIN TDMIN TDMIN TDMIN (CH5+6)/2 (CH1+2+3+4)/4 L H L TDMIN TDMIN (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH1+2)/2 L H H TDMIN TDMIN TDMIN TDMIN TDMIN (CH1+2+3+4+5+6)/6 H L L CH6 CH5 CH4 CH3 CH2 CH1 H L H TDMIN TDMIN TDMIN TDMIN (CH5+6)/2 (CH1+2+3+4)/4 H H L TDMIN TDMIN (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH1+2)/2 H H H TDMIN TDMIN TDMIN TDMIN TDMIN (CH1+2+3+4+5+6)/6 Table 16. Slot Data Assign (Parallel Control Mode, ODP pin= “H”, TDM256 & TDM512) 015099885-E-00 2016/03 - 48 - [AK5536] [2] Serial Control Mode In 3-wire serial mode or I2C mode, PW1-6 bits control the power of AIN1-6 channels independently. AINn channel is powered down when PWn bit = “0” (n=1-6) and AINn channel is in normal operation when PWn bit = “1”. The power-down channel is reset status and outputs all “0”. The channel summation is controlled by MONO1 and MONO2 bits. RSTN bit must be “0” when changing the setting of MONO1, MONO2 and PW1-6 bits. MONO2 bit 0 0 1 1 Data on Slot (Normal Output) MONO1 bit Slot6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 0 CH6 CH5 CH4 CH3 CH2 CH1 1 All “0” All “0” All “0” All “0” (CH5+6)/2 (CH1+2+3+4)/4 0 All “0” All “0” (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH1+2)/2 1 All “0” All “0” All “0” All “0” All “0” (CH1+2+3+4+5+6)/6 Table 17. Slot Data Assign (Serial Control mode, Normal Output & DSD mode) MONO2 MONO1 bit bit 0 0 0 1 1 0 1 1 Data on Slot (TDM128) Slot6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 CH6 CH5 CH4 CH3 CH2 CH1 All “0” All “0” TDMI TDMI (CH5+6)/2 (CH1+2+3+4)/4 All “0” All “0” (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH1+2)/2 All “0” All “0” TDMI TDMI TDMI (CH1+2+3+4+5+6)/6 Table 18. Slot Data Assign (Serial Control Mode, TDM128) Data on Slot (TDM256, TDM512) MONO2 MONO1 bit bit Slot6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 0 0 CH6 CH5 CH4 CH3 CH2 CH1 0 1 TDMI TDMI TDMI TDMI (CH5+6)/2 (CH1+2+3+4)/4 1 0 TDMI TDMI (CH5+6)/2 (CH5+6)/2 (CH3+4)/2 (CH1+2)/2 1 1 TDMI TDMI TDMI TDMI TDMI (CH1+2+3+4+5+6)/6 Table 19. Slot Data Assign (Serial Control Mode, TDM256 & TDM512) 015099885-E-00 2016/03 - 49 - [AK5536] ■ Data Slot Configuration [1] PCM Mode LRCK Period = 1/fs Normal Output SDTO1 pin Slot 1 Slot 2 SDTO2 pin Slot 3 Slot 4 SDTO3 pin Slot 5 Slot 6 LRCK Period = 1/fs TDM128 SDTO1 pin Slot 1 Slot 2 SDTO2 pin Slot 5 Slot 6 Slot 3 Slot 4 All ”0” All “0” SDTO3 pin LRCK Period = 1/fs TDM256 SDTO1 pin Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 SDTO2 pin All “0” SDTO3 pin All “0” All “0” LRCK Period = 1/fs TDM512 SDTO1 pin 1 2 3 4 5 6 All “0” SDTO2 pin All “0” SDTO3 pin All “0” TDMI Figure 57. Slot Assign in PCM Mode 015099885-E-00 2016/03 - 50 - [AK5536] [2] DSD Mode LRCK Period = 1/fs DSDOL1 pin Slot 1 DSDOR1 pin Slot 2 DSDOL2 pin Slot 3 DSDOR2 pin Slot 4 DSDOL3 pin Slot 5 DSDOR3 pin Slot 6 Figure 58. Slot Assign in DSD Mode 015099885-E-00 2016/03 - 51 - [AK5536] ■ Digital Filter Setting (PCM Mode) The AK5536 has four types of digital filters and they can be selected by SD pin (bit) and SLOW pin (bit). The filter setting is not available in OCT speed mode, HEX speed mode and DSD mode. So the setting of the digital filter is ignored. SD pin (bit) L (0) L (0) H (1) H (1) SLOW pin (bit) Filter L (0) Sharp Roll-off Filter H (1) Slow Roll-off Filter L (0) Short Delay Sharp Roll-off Filter H (1) Short Delay Slow Roll-off Filter Table 20. Digital Filter Setting ■ Digital HPF (PCM Mode) The AK5536 has a digital high-pass filter for DC offset (include internal offset) cancelation. The digital high-pass filter is enabled by setting the HPFE pin (bit) = “H (1)”. The cut-off frequency of the high-pass filter is fixed 1.0 Hz when fs= 48 kHz (Normal Speed mode), 96 kHz (Double Speed mode) or 192 kHz (Quad Speed mode). The high-pass filter is not available in OCT speed mode, HEX speed mode and DSD mode. So that the setting of the HPFE pin is ignored. The high pass-filter setting should be changed when all channels are reset condition. ■ Overflow Detection (PCM Mode, DSD Mode) [1] PCM Mode The AK5536 has an overflow detect function for the analog input. The OVF pin outputs “H” if one of AIN1 - 6 channels overflows (more than 0.3 dBFS). The OVF pin returns to “L” when analog input overflows are resolved. The OVF output for overflowed analog input has the same group delay as the ADC. [2] DSD Mode Overflow Detection (Error Detection Function) The OVF pin outputs “H” if any channel’s DSD modulators overflows. The OVF pin returns to “L” when overflows are resolved. 015099885-E-00 2016/03 - 52 - [AK5536] ■ LDO The voltage range of TVDD is from 1.7 V to 1.98 V or from 3.0 V to 3.6 V. Set ON/OFF of the LDO by the LDOE pin according to TVDD voltage (Table 21). The internal LDO is switched ON/OFF depending on TVDD voltage range. Additional Voltage Range LDOE PDN LDO VDD18 pin to TVDD pin L L OFF External Power Input 1.7-1.98 V 1.7-1.98 V L H OFF External Power Input 1.7-1.98 V 1.7-1.98 V H L OFF 3.0-3.6 V Pulled Down by 500  internally H H ON LDO Voltage Output 3.0-3.6 V Table 21. LDO Control [1] TVDD=1.7-1.98 V, LDO is OFF (LDOE pin = “L”) The internal LDO does not work properly when the TVDD voltage range is from 1.7 V to 1.98 V. Set the LDOE pin to “L” to switch OFF the LDO. A 1.7 V - 1.98 V is supplied from the VDD18 pin for internal logic circuits. The voltage difference between TVDD and VDD18 must be ±0.1 V or less. [2] TVDD=3.0-3.6 V, LDO is ON (LDOE pin = “H”) The internal LDO should be ON when the TVDD voltage range is from 3.0 V to 3.6 V. It will be the power supply for the internal logic circuit. The VDD18 pin will be a connection terminal for a stabilization capacitor. It is not possible to supply the power to external circuits from the VDD18 pin. ■ Reset The AK5536 must be reset upon power up or when changing the clock setting or clock frequency. It can be reset by the PDN pin or PW2-0 pins and RSTN bit or PW6-1 bits. 015099885-E-00 2016/03 - 53 - [AK5536] ■ Power Up/Down Sequence The AK5536 enters power-down mode by setting the PDN pin to “L”. Digital filters are reset at the same time. [1] PCM Mode In slave mode, internal power down signal (Internal PDN) is released by inputting MCLK, BICK and LRCK after setting the PDN pin to “H”. In master mode, The Internal PDN is released by inputting MCLK after setting the PDN pin to “H”. Initialization cycle starts when the Internal PDN is released. The output data of SDTO will be valid in 583 x 1/fs after exiting power-down mode in slave mode, it will be valid in 578 x 1/fs after exiting power-down mode in master mode. During initialization, the ADC digital outputs of both channels are in 2’s complement format and forced to “0”. The ADC outputs settle to data correspondent to the input signals after the end of initialization. This settling takes approximately the group delay time. Power PDN pin (1) VDD18 pin (2) Internal PDN (3) Internal State Power -down Initialize Normal Operation Power -down ADC In (Analog) GD (5) (5) GD (4) (4) ADC Out (Digital) Clock In MCLK,LRCK,BICK “0”data Don’t care Idle Noise Idle Noise “0”data Don’t care Figure 59. Power-Up/Down Sequence Example Notes (1) The PDN pin should be held to “L” for more than 150 ns after AVDD and TVDD are powered up. (2) a. LDOE pin = “H”, I2C pin = “H” and PSN pin = “H” (Parallel Mode): The internal LDO is powered up by releasing PDN pin to “H”. The Internal PDN is released by toggling MCLK for 16384times. b. LDOE pin = “H” and PSN pin = “L” (Register Mode): The internal LDO is powered up by releasing PDN pin to “H”. The internal PDN is released by toggling internal oscillator clock for 16384 times (max. 10 ms). c. LDOE pin = “L”: The internal PDN is released in 1 ms (max.) after releasing PDN pin to “H”. During this period, digital output and digital in/output pins may output an instantaneous pulse (max. 1 us). Therefore, referring the output of digital pins and data transmission with a device on the same 3-wire serial/I2C bus as the AK5536 should be avoided in this period to prevent system errors. (3) Initialization cycle is 583/fs in slave mode and 578/fs in master mode. (4) The ADC output data is “0” during initialization cycle and power-down mode. (5) The digital output corresponding to analog input has group delay (GD). 015099885-E-00 2016/03 - 54 - [AK5536] Internal PDN Release Sequence Figure 60. Internal PDN Release Sequence 015099885-E-00 2016/03 - 55 - [AK5536] [2] DSD Mode The Internal PDN is released by inputting MCLK after setting the PDN pin to “H”. PDN pin Internal PDN (1) MCLK In Don’t care Internal State Power-Down Don’t care Initialize Normal Operation Power-Down (2) ADC In (Analog) (6) (4) OVF-pin (5) (3) DSD Out (Digital) “L” (-full scale data) normal data abnormal data normal data “L” (-full scale data) Figure 61. DSD Operation Timing Notes: (1) The internal LDO is powered up by releasing PDN pin to “H”. The internal PDN is released by toggling internal oscillator clock for 16384 times (max. 10ms). The internal PDN is released in max. 1 ms after releasing PDN pin to “H”. Register writings become available when the internal PDN changes to “1”. During this period, digital output and digital in/output pins may output an instantaneous pulse (max. 1 us). Therefore, referring the output of digital pins and data transmission with a device on the same 3-wire serial/I2C bus as the AK5536 should be avoided in this period to prevent system errors. (2) Initialization operation will be completed in 583/fs. (3) DSD output pins output “L” (-full scale data) during power down and initializing operation. DSD output pins output full scale data during phase modulation mode, a reset sequence and a CH power down status. (4) The OVF pin outputs “H” when an excessive signal is input and overflow is detected at internal modulator. The OVF pin status will change after group delay period from the excessive input. (5) In the case above (4), the DSD output data will not be correct. (6) The OVF pin returns to “L” when the input signal settled to a normal state and overflow status of the internal modulator is resolved. The OVF pin status will change after group delay period from the normal input. 015099885-E-00 2016/03 - 56 - [AK5536] ■ Operation Mode Control Operation modes of the AK5536 are set by pins or registers. In parallel control mode, the operation mode is set by pin and register settings are invalid. Therefor the functions that needs register settings are not available in parallel control mode. For register accessing, 3-wire serial and I2C bus communications are available. This control mode of the AK5536 is selected by the I2C pin and the PSN pin. In serial control mode, register settings are prioritized so that all pin settings except the MSN pin setting are ignored. I2C pin L L H H PSN pin Control mode L 3-wire Serial H 3-wire Serial L I2C Bus H Parallel Table 22. Control Mode ■ Register Control Interface (1) 3-wire Serial Control Mode (I2C pin = “L”) The internal registers may be written through the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address, Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz (max). The internal registers are initialized by setting the PDN pin = “L”. In serial control mode, an internal timing circuit is reset by setting RSTN bit = “0” but register values are not initialized. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1=CAD1, C0=CAD0) READ/WRITE (Fixed to “1”, Write only) Register Address Control Data Figure 62. Control I/F Timing * The AK5536 does not support read commands in 3-wire serial control mode. * When the AK5536 is in power down mode (PDN pin = “L”), a writing into the control registers is prohibited. * The control data cannot be written when the CCLK rising edge is 15 times or less, or 17 times or more during CSN is “L”. 015099885-E-00 2016/03 - 57 - [AK5536] (2) I2C-bus Control Mode (I2C pin = “H” and PSN pin = “L”) The AK5536 supports the fast-mode I2C-bus (max: 400 kHz, Ver1.0). (2)-1. WRITE Operations Figure 63 shows the data transfer sequence of the I2C-bus control mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 69). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as “00100”. The next bits are CAD1-0 (device address bits). This bits identifies the specific device on the bus. The hard-wired input pins (CAD1-0 pins) set these device address bit (Figure 64). If the slave address matches that of the AK5536, the AK5536 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 70). R/W bit = “1” indicates that the read operation is to be executed. “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK5536. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 65). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 66). The AK5536 generates an acknowledge after each byte is received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 69). The AK5536 can perform more than one byte write operation per sequence. After receipt of the third byte the AK5536 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds “07H” prior to generating a stop condition, the address counter will “roll over” to “00H” and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 71) except for the START and STOP conditions. S T A R T SDA S S T O P R/W= “0” Slave Address 1st byte Sub Address(n) A C K 2nd byte Data(n) A C K Data(n+1) A C K 3rd byte Data(n+x) A C K A C K P A C K Figure 63. Data Transfer Sequence at the I2C-Bus Control Mode 0 0 1 0 0 CAD1 CAD0 R/W A1 A0 D1 D0 (CAD0 and CAD1 are set by pins) Figure 64. The First Byte 0 0 0 A4 A3 A2 Figure 65. The Second Byte D7 D6 D5 D4 D3 D2 Figure 66. Byte Structure After The Second Byte 015099885-E-00 2016/03 - 58 - [AK5536] (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK5536. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds “07H” prior to generating stop condition, the address counter will “roll over” to “00H” and the data of “00H” will be read out. The AK5536 supports two basic read operations: Current Address Read and Random Address Read. (2)-2-1. Current Address Read The AK5536 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK5536 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK5536 ceases transmission. S T A R T SDA S S T O P R/W= “1” Slave Address Data(n) A C K Data(n+1) A C K Data(n+2) A C K Data(n+x) A C K A C K P A C K Figure 67. Current Address Read (2)-2-2. Random Address Read The random read operation allows the master to access any memory location at random. Prior to issuing a slave address with the R/W bit =“1”, the master must execute a “dummy” write operation first. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit =“1”. The AK5536 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK5536 ceases transmission. S T A R T SDA S S T A R T R/W= “0” Slave Address Sub Address(n) A C K S A C K S T O P R/W= “1” Slave Address Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 68. Random Address Read 015099885-E-00 2016/03 - 59 - [AK5536] SDA SCL S P start condition stop condition Figure 69. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 70. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 71. Bit Transfer on the I2C-Bus 015099885-E-00 2016/03 - 60 - [AK5536] ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management1 1 1 PW6 PW5 PW4 PW3 PW2 PW1 01H Power Management2 0 0 0 0 0 MONO2 MONO1 RSTN 02H Control 1 0 CKS3 CKS2 CKS1 CKS0 DIF1 DIF0 HPFE 03H Control 2 0 TDM1 TDM0 0 0 0 0 0 04H Control 3 DP 0 0 0 0 0 SD SLOW 05H DSD 0 0 DCKS 0 PMOD DCKB DSDSEL1 DSDSEL0 06H TEST1 TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 07H TEST2 0 0 0 0 0 0 0 TRST Note 24. Data must not be written into addresses from “06H” to “1FH”. Note 25. The bits indicated as “0” must contain a “0” value. When RSTN bit is set to “0”, the internal digital filter and the control block are reset but the register values are not initialized. Note 26. When the PDN pin is set to “L”, all registers are initialized to their default values. ■ Register Definitions Addr Register Name 00H Power Management1 R/W Default D7 1 R/W 1 D6 1 R/W 1 D5 PW6 R/W 1 D4 PW5 R/W 1 D3 PW4 R/W 1 D5 0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D2 PW3 R/W 1 D1 PW2 R/W 1 D0 PW1 R/W 1 PW6-1: Power Down control for channel 6-1 0: Power OFF 1: Power ON (default) Addr Register Name 01H Power Management2 R/W Default D7 0 R/W 0 D6 0 R/W 0 D2 D1 D0 MONO2 MONO1 RSTN R/W R/W R/W 0 0 1 RSTN: Internal Timing Reset 0: Reset. All registers are not initialized. 1: Normal Operation (default) Internal clock timings are reset but registers are not reset. MONO2-1: Channel Summation mode Select (Table 17, Table 18, Table 19) 00: Not- Summation mode (default) 01: 4-to-1 mode 10: 6-to-3 mode 11: 6-to-1 mode 015099885-E-00 2016/03 - 61 - [AK5536] Addr Register Name 02H Control 1 R/W Default D7 0 R/W 0 D6 CKS3 R/W 0 D5 CKS2 R/W 0 D4 CKS1 R/W 0 D3 CKS0 R/W 0 D2 DIF1 R/W 0 D1 DIF0 R/W 0 D0 HPFE R/W 1 HPFE: High Pass Filter Enable 0: High Pass Filter OFF 1: High Pass Filter ON (default) When this bit is “1”, digital HPFs for all channels are ON. DIF1-0: Audio Data Interface Mode Select (Table 8, Table 9) Select A/D data bit length (24-bit/32-bit) and the format (MSB justified/ I2S Compatible) CKS3-0: Sampling Speed Mode and MCLK Frequency Select (Table 5) Select Sampling Speed and MCLK frequency. Addr Register Name 03H Control 2 R/W Default D7 0 R/W 0 D6 TDM1 R/W 0 D5 TDM0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D2 0 R/W 0 D1 0 R/W 0 D0 0 R/W 0 TDM1-0: TDM Modes Select (Table 9) Select the A/D data multiplex mode from Normal, TDM128, TDM256 and TDM512 modes. Addr Register Name 04H Control 3 R/W Default D7 DP R/W 0 D6 0 R/W 0 D5 0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D2 0 R/W 0 D1 SD R/W 0 D0 SLOW R/W 0 SLOW: Slow Roll-off Filter Select (Table 20) 0: Sharp Roll-off (default) 1: Slow Roll-off Select Roll-off characteristic of the digital filter. SD: Short Delay Select (Table 20) 0: Normal Delay (default) 1: Short Delay Select group delay of the digital filter. DP: DSD Mode Select 0: PCM Mode (default) 1: DSD Mode Select A/D Data Output Mode. 015099885-E-00 2016/03 - 62 - [AK5536] Addr Register Name 05H DSD R/W Default D7 0 R/W 0 D6 0 R/W 0 D5 DCKS R/W 0 D4 0 R/W 0 D3 PMOD R/W 0 D2 D1 D0 DCKB DSDSEL1 DSDSEL0 R/W R/W R/W 0 0 0 DSDSEL1-0: Select the Frequency of DCLK 00: 64fs (default) 01: 128fs 10: 256fs 11: Reserved DCKB: Polarity of DCLK 0: DSD data is output from DCLK Falling Edge (default) 1: DSD data is output from DCLK Rising Edge PMOD: DSD Phase Modulation Mode 0: Not Phase Modulation Mode (default) 1: Phase Modulation Mode DSD Output Phase Modulation Mode Enable DCKS: Master Clock Frequency Select at DSD Mode (DSD Only) 0: 512fs (default) 1: 768fs Addr 06H Register Name TEST1 R/W Default D7 TST7 RD 0 D6 TST6 RD 0 D5 TST5 RD 0 D4 TST4 RD 0 D3 TST3 RD 0 D2 TST2 RD 0 D1 TST1 RD 0 D0 TST0 RD 0 TST7-0: Test register. This register must be used as the default setting. Normal operation is not guaranteed if all bits are not “0”. Addr 07H Register Name TEST2 R/W Default D7 0 R/W 0 D6 0 R/W 0 D5 0 R/W 0 D4 0 R/W 0 D3 0 R/W 0 D2 0 R/W 0 D1 0 R/W 0 D0 TRST W 0 TRST: Test register. This register must be “0”. This register must be “0”. This register must be used as the default setting. Normal operation is not guaranteed if all bits are not “0”. 015099885-E-00 2016/03 - 63 - [AK5536] AIN1+ AIN1 Analog 3.3V + 20 100 0.1 TDM0 TDM1 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CKS3/CAD1 CKS2/SCL/CCLK CKS1/CAD0_I2C/CSN CKS0/SDA/CDTI OVF TESTO2 TESTO1 DSDOR3 SDTO3/DSDOL3 SDTO2/DSDOR2 SDTO1/DSDOL2 TDMIN/DSDOR1 LRCK/DSDOL1 BICK/DCLK DIF1/DSDSEL1 PSN/CAD0_SPI I2C DP HPFE/DCKS LDOE ODP AIN1P AIN1N VREFL1 VREFH1 AIN2N AIN2P MSN PW2 PW1 PW0 PDN VDD18 DVSS TVDD MCLK TEST TESTIN6 TESTIN5 TESTIN4 TESTIN3 TESTIN2 TESTIN1 AK5536 Top View 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Mode Setting Controller 0.1 4.7 + + 0.1 10 Digital 3.3V Mater Clock 0.1 + Analog 3.3V AIN6 AIN6+ 10 + 100 0.1 20 Analog 3.3V 100 0.1 + AIN4 AIN4+ AIN5+ AIN5 20 Analog 3.3V Analog 3.3V AIN3+ AIN3 + 10 0.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AIN2 AIN2+ DIF0/ DSDSEL0 Controller AVSS1 AVDD1 AIN3P AIN3N VREFL2 VREFH2 AIN4N AIN4P AIN5P AIN5N VREFH3 VREFL3 AIN6N AIN6P AVDD2 AVSS2 Mode Setting 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SD/PMOD 48 SLOW/DCKB 47 Mode Setting fs 64fs 13. Recommended External Circuits Figure 72 shows recommended external connection. Figure 72. Typical Connection Diagram Note 27. All digital input pins must not be allowed to float. 015099885-E-00 2016/03 - 64 - [AK5536] 1. Grounding and Power Supply Decoupling The AK5536 requires careful attention to power supply and grounding arrangements. Normally AVDD1/2 and TVDD are supplied from analog supply of the system. The power-up sequence between AVDD1/2 and TVDD are not critical when AVDD1/2 and TVDD are supplied separately. DVSS and AVSS1/2 must be connected to the same analog ground plane. System analog ground and digital ground should be wired separately and connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as possible to the supply pin. 2. Reference Voltage The differential voltage between the VREFH1-3 pins and the VREFL1-3 pins are the common voltage of A/D conversion. The VREFL1-3 pins are normally connected to AVSS. In order to remove a high frequency noise, connect a 20 Ω resistor between the VREFH1-3 pins and analog 3.3 V supply, and connect a 0.1 μF ceramic capacitor in parallel with an 100 μF electrolytic capacitor between the VREFH1-3 pins and the VREFL1-3 pins. Especially the ceramic capacitor should be connected as close as possible to the pin. All digital signals, especially clocks, should be kept away from the VREFH1-3 pins and VREFL1-3 pins in order to avoid unwanted noise coupling into the AK5536. 3. Analog Inputs The Analog input signal is differentially supplied into the modulator via the AINn+ and the AINn- pins (n= 1-6). The input voltage is the difference between the ALINn+ and ALINn- pins (n= 1-6). The full scale signal on each pin is nominally 1.85 V (typ). A voltage from AVSS1/2 to AVDD1/2 can be input to the AK5536. The output code format is two’s complement. The internal HPF removes DC offset (including DC offset by the ADC itself). The AK5536 requires a +3.3 V analog supply voltage. Any voltage which exceeds the upper limit of AVDD1/2+0.3 V and lower limit of AVSS1/20.3 V and any current beyond 10 mA for the analog input pins should be avoided. Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals at or beyond these limits. Use caution especially when using ±15 V for other analog circuits in the system. 015099885-E-00 2016/03 - 65 - [AK5536] 4. External Analog Circuit Examples Figure 73 shows an input buffer circuit example 1. (1st order HPF; fc= 0.70 Hz, 2nd order LPF; fc= 351 kHz, gain= 14.5 dB). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is 9.85 Vpp (AK5536: 1.85 Vpp Typ.). When using this circuit, analog characteristics at fs= 48 kHz is DR= 111 dB, S/(N+D)= 103 dB. The S/(N+D) characteristics of the AK5536 varies depending on DC bias current of the input signal. Set the DC bias voltage in a range from 0.48 x AVDD to 0.52 x AVDD for a better characteristic. * Film capacitors are recommended for the components shown as 15 nF and 1 nF in the figure below. 4.7k 4.7k Analog In 620 JP1 VP+ Vin- 68µ + 9.85Vpp Bias VP- 1n * 3.3k 10 + 1.85Vpp AK5536 AINn+ 100p NJM5534 NJM5534 XLR 15n * VA+ 620 10k Bias 10k JP2 68µ - + 10µ 1n * 3.3k Vin+ 0.1µ 10 + NJM5534 Bias VA=+3.3V VP=15V AK5536 AINn100p 1.85Vpp Figure 73. Input Buffer Example1 fin 1Hz 10Hz Frequency 1.77dB 0.02dB Response Table 23. Frequency Response of HPF fin 20kHz 40kHz 80kHz Frequency 0.00dB 0.00dB 0.00dB Response Table 24. Frequency Response of LPF 015099885-E-00 6.144MHz 49.68dB 2016/03 - 66 - [AK5536] 14. Package ■ Outline Dimensions 64-pin QFN (Unit mm) 9.00±0.15 A 0.40±0.10 8.75 B 64 49 48 48 1 33 16 6.15 8.75 9.00±0.15 1 64 49 16 33 32 17 0.10 M AB 0.25 +0.05 -0.07 .60 C0 X MA 32 0.50 17 6.15 +0.15 S 0.85 -0.05 +0.03 -0.02 0.08 0.02 0.20 S ■ Material & Lead Finish Package molding compound: Epoxy resin Lead frame material: Cu Terminal surface treatment: Solder (Pb free) plate ■ Marking AKM AK5536VN XXXXXXX 1 1) 2) 3) 4) Pin #1 indication Date Code : XXXXXXX (7 digits) Marketing Code: AK5536VN AKM Logo 015099885-E-00 2016/03 - 67 - [AK5536] 15. Ordering Guide 40 - 105 ºC 64-pin QFN Evaluation Board for AK5536 AK5536VN AKD5536 16. Revision History Date (Y/M/D) 16/03/16 Revision 00 Reason Page First Edition Contents 015099885-E-00 2016/03 - 68 - [AK5536] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 015099885-E-00 2016/03 - 69 -