[AK5704]
AK5704
Low-Power 4-ch 32-bit ADC with MIC-Amp
1. General Description
The AK5704 is a high performance analog front-end AD converter IC ideal for voice recognition, voice
control, and conferencing applications. The device has a built-in 4-ch 32-bit ADC and a low noise
microphone amplifier and extracts full performance of a high S/N microphone with low power
consumption by achieving dynamic range of 105dB. It is possible to support up to 16-ch microphone array
by connecting multiple AK5704’s. In addition, since it incorporates ultra-low power consumption voice
activity detection, power consumption during wait time is greatly reduced.
1.
2.
3.
4.
5.
6.
7.
8.
9.
2. Features
Recording Function
4-Channel Low Power 32-bit ADC
2-types Digital Filter (Low-latency [5/fs] Sharp Roll-off and Voice)
Single-ended Inputs or Full-differential Inputs
MIC Amplifier Gain: +30 dB to 0 dB, 3 dB step
2-output MIC Power Supplies: 2.8 V / 2.5 V / 1.8 V / Direct Mode Selectable
ADC Characteristics:
S/N, DR: 105 dB, THD+N: 90 dB, (Gain = 0 dB)
S/N, DR: 96 dB, THD+N: 86 dB, (Gain = +18 dB)
Excellent Power Supply Noise Reduction
PSRR: 60dB
Spurious Free Dynamic Range: 100dBc
4-Channel Digital MIC Interface
Programmable Phase Adjustment
Microphone Sensitivity Adjustment
Digital Voice Activity Detector
Programmable Digital Filter
Mixer
2nd order HPF and LPF
Digital ALC (Automatic Level Control): 4-ch Link Mode, 2-ch Mode
Digital Audio interface
Master/Slave mode
Sampling Frequency:
8 k, 11.025 k, 12 k, 16 k, 22.05 k, 24 k, 32 k, 44.1 k, 48 k, 88.2 k, 96 k,
176.4 k, 192 kHz
Interface Format
- 32/24/16-bit I2S/MSB justified, 16-bit PCM Short/Long Frame
- 4-ch TDM
- 8/12/16-ch Cascade TDM
Built-in PLL
Control I/F: I2C-bus (400kHz)
Operation Temperature Range: Ta = 40 to 85°C
Power Supply:
AVDD (ADC, MIC, PLL):
1.7 to 1.9 V or 3.0V to 3.6V
TVDD (Host & Audio I/F, LDO12): 1.65 to 3.6 V
Package: 28-pin QFN
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1.
2.
3.
4.
5.
6.
7.
8.
9.
3. Table of Contents
General Description .............................................................................................................................. 1
Features ................................................................................................................................................ 1
Table of Contents .................................................................................................................................. 2
Block Diagram ....................................................................................................................................... 4
Pin Configurations and Functions ......................................................................................................... 5
5.1.
Pin Configurations ................................................................................................................... 5
5.2.
Functions ................................................................................................................................. 6
5.3.
Handling of Unused Pin ........................................................................................................... 7
5.4.
Pin State In Power-down Mode ............................................................................................... 8
Absolute Maximum Ratings .................................................................................................................. 9
Recommended Operating Conditions .................................................................................................. 9
Electrical Characteristics .................................................................................................................... 10
8.1.
Microphone & ADC Analog Characteristics (AVDD=3.3V: AVDDL bit = “0”)........................ 10
8.2.
Microphone & ADC Analog Characteristics (AVDD=1.8V: AVDDL bit = “1”)........................ 12
8.3.
Power Supply Current ........................................................................................................... 14
8.4.
Power Consumption for Each Operation Mode..................................................................... 14
8.5.
ADC1/2 Short Delay Sharp Roll-off Filter (ADVF bit = “0”) ................................................... 15
8.6.
ADC1/2 Digital Filter for Voice (ADVF bit = “1”) .................................................................... 16
8.7.
DC Characteristics ................................................................................................................. 17
8.8.
Switching Characteristics ...................................................................................................... 18
Functional Descriptions ...................................................................................................................... 28
9.1.
Internal Pull-down Pin............................................................................................................ 28
9.2.
LDO Circuit ............................................................................................................................ 28
9.3.
System Clock ......................................................................................................................... 29
9.4.
PLL......................................................................................................................................... 30
9.5.
Audio Interface Format .......................................................................................................... 38
9.6.
Synchronization with audio system (SYNCDET) .................................................................. 46
9.7.
MIC/LINE Input ...................................................................................................................... 47
9.8.
Microphone Amplifier Gain .................................................................................................... 49
9.9.
Microphone Power ................................................................................................................. 50
9.10. MIC Input Start-Up Time........................................................................................................ 51
9.11. ADC1/2 Initialization Cycle .................................................................................................... 51
9.12. Mono/Stereo Mode ................................................................................................................ 52
9.13. Digital Microphone ................................................................................................................. 53
9.14. Digital Block ........................................................................................................................... 55
9.14.1.
Programmable Phase Adjustment .................................................................................. 56
9.14.2.
High Pass Filter (ADC1/2) ............................................................................................... 57
9.14.3.
ADC1/2 Digital Filter ........................................................................................................ 57
9.14.4.
Microphone Sensitivity Adjustment ................................................................................. 58
9.14.5.
Monaural (MIX) Selection ................................................................................................ 58
9.14.6.
High Pass Filter (HPF1/2) ............................................................................................... 59
9.14.7.
Low Pass Filter (LPF1/2) ................................................................................................. 59
9.14.8.
ALC Operation ................................................................................................................. 60
9.14.9.
Input Digital Volume (Manual Mode) ............................................................................... 65
9.14.10. ALC 4ch Link Mode Sequence........................................................................................ 66
9.15. Digital Voice Activity Detector ............................................................................................... 67
9.15.1.
VDLY ............................................................................................................................... 68
9.15.2.
HPF, LPF ......................................................................................................................... 68
9.15.3.
ABS.................................................................................................................................. 69
9.15.4.
NLD (Noise Level Detector) ............................................................................................ 70
9.15.5.
MAX ................................................................................................................................. 72
9.15.6.
MULT (X) ......................................................................................................................... 72
9.15.7.
Comparator (>) ................................................................................................................ 72
9.15.8.
Guard Timer .................................................................................................................... 73
9.15.9.
Interrupt Output (WINTN pin) .......................................................................................... 74
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9.15.10. Output Selector................................................................................................................ 74
9.16. I2C-bus Control Interface ...................................................................................................... 75
9.17. Register Map ......................................................................................................................... 78
9.18. Register Definition ................................................................................................................. 80
10. Recommended External Circuits ........................................................................................................ 94
11. Control Sequence ............................................................................................................................... 97
11.1. Clock Set Up .......................................................................................................................... 97
11.1.1.
PLL Master Mode ............................................................................................................ 97
11.1.2.
PLL Slave Mode (BCLK pin) ........................................................................................... 98
11.1.3.
PLL Slave Mode (MCKI pin) ............................................................................................ 99
11.1.4.
External Slave Mode ..................................................................................................... 100
11.1.5.
External Master Mode ................................................................................................... 101
11.2. Voice Activity Detection (1ch Mic) ....................................................................................... 102
11.3. Voice Activity Detection (4ch Mic) ....................................................................................... 103
11.4. Microphone Input Recording (4ch) ...................................................................................... 104
11.5. Stop of Clock ....................................................................................................................... 105
11.5.1.
PLL Master Mode .......................................................................................................... 105
11.5.2.
PLL Slave Mode (BCLK pin) ......................................................................................... 105
11.5.3.
PLL Slave Mode (MCKI pin) .......................................................................................... 105
11.5.4.
External Slave Mode ..................................................................................................... 106
11.5.5.
External Master Mode ................................................................................................... 106
11.6. Power Down ........................................................................................................................ 106
12. Package ............................................................................................................................................ 107
12.1. Outline Dimensions ............................................................................................................. 107
12.2. Material & Lead finish .......................................................................................................... 107
12.3. Marking ................................................................................................................................ 107
13. Ordering Guide ................................................................................................................................. 108
14. Revision History ................................................................................................................................ 108
IMPORTANT NOTICE ............................................................................................................................ 109
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4. Block Diagram
AVDD
VREF
VCOM
VSS1
SDA SCL
MPWR2
MIC
Power Supply
Control
Register
MPWR1
AIN1A+
/DMDAT1
CAD
PDN
PLL
MCKO
MCKI
AIN1AAIN1B+
/DMCLK1
Stereo
MIC
LRCK
ADC1 Delay HPF Sensitivity
Adj.
AIN1BAIN2A+
/DMDAT2
Mixer,
HPF, LPF,
ALC
Stereo
BCLK
Audio I/F
SDTO1
MIC
TDMIN
/SDTO2
ADC2 Delay HPF Sensitivity
Adj
AIN2AAIN2B+
/DMCLK2
TVDD
Digital VAD
for Voice Waku-up
AIN2B-
LDO12
VDD12
VSS2
WINTN
Figure 1. AK5704 Block Diagram
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5. Pin Configurations and Functions
5.1. Pin Configurations
15 VREF
16 VCOM
17 VSS1
18 AVDD
19 MPWR2
20 AIN2B-
AIN2B+
21 /DMCLK2
28-pin QFN
14 PDN
AIN2A- 22
AIN2A+
23
/DMDAT2
AIN1B- 24
13 TVDD
12 VSS2
AK5704
AIN1B+
25
/DMCLK1
AIN1A- 26
11 VDD12
Top View
10 MCKI
1
2
3
4
5
6
7
CAD
SCL
SDA
WINTN
SDTO1
TDMIN
/SDTO2
LRCK
AIN1A+
27
/DMDAT1
MPWR1 28
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MCKO
8
BCLK
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[AK5704]
5.2. Functions
No.
Pin Name
I/O
Protection
Diode
Function
1
CAD
I
I2C Chip Address Pin
2
SCL
I
I2C Serial Data Clock Pin
3
SDA
I/O
I2C Serial Data Input/Output Pin
4
WINTN
O
Interrupt Output Pin
5
SDTO1
O
Audio Serial Data Output 1 Pin
TDMIN
I
SDTO2
O
7
LRCK
I/O
Frame Sync Clock Pin
8
BCLK
I/O
Audio Serial Data Clock Pin
9
MCKO
O
Master Clock Output Pin
10
MCKI
I
Master Clock Input Pin
11
VDD12
-
12
13
VSS2
TVDD
-
6
14
PDN
I
15
VREF
O
16
VCOM
O
17
18
VSS1
AVDD
-
TDM Data Input Pin (Default)
(SDTO2E bit = “0”)
Audio Serial Data Output 2 Pin
(SDTO2E bit = “1”)
LDO12 (1.2 V) Output Pin
This pin must be connected to the VSS2 pin with a
2.2 μF ±50 % capacitor in series.
Digital Ground Pin
Digital I/F & LDO12 Power Supply Pin
Power down Pin
“L”: Power-down, “H”: Power-Up
Voltage Reference Pin
This pin must be connected to the VSS1 pin with a
2.2 μF ±50% Ceramic capacitor in series.
Common Voltage Output Pin
This pin must be connected to the VSS1 pin with a
2.2 μF ±50% Ceramic capacitor in series.
Analog Ground Pin
Analog Power Supply Pin
TVDD/
VSS2
TVDD/
VSS2
TVDD/
VSS2
TVDD/
VSS2
TVDD/
VSS2
TVDD/
VSS2
TVDD/
VSS2
TVDD/
VSS2
TVDD/
VSS2
TVDD/
VSS2
TVDD/
VSS2
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD/
VSS2
TVDD
AVDD/
VSS1
AVDD
AVDD/
VSS1
AVDD
AVDD/
19
MPWR2
O MIC Power Supply 2 Pin
VSS1
Note 1. Do not connect a load to the VDD12 pin, the VCOM pin and the VREF pin.
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Domain
AVDD
AVDD
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[AK5704]
No.
Pin Name
I/O
20
AIN2B-
I
AIN2B+
I
DMCLK2
O
AIN2A-
I
AIN2A+
I
DMDAT2
I
AIN1B-
I
AIN1B+
I
DMCLK1
O
AIN1A-
I
AIN1A+
I
DMDAT1
I
21
22
23
24
25
26
27
28
Note 2.
Function
Protection
Diode
Power
Domain
Negative Analog Input 2B Pin
AVDD/
VSS1
AVDD
Positive Analog Input 2B Pin
(DMIC2 bit = “0”)
Digital Microphone Clock Output 2 Pin
(DMIC2 bit = “1”)
AVDD/
VSS1
AVDD
Negative Analog Input 2A Pin
AVDD/
VSS1
AVDD
Positive Analog Input 2A Pin
(DMIC2 bit = “0”)
Digital Microphone Data Input 2 Pin
(DMIC2 bit = “1”)
AVDD/
VSS1
AVDD
Negative Analog Input 1B Pin
AVDD/
VSS1
AVDD
Positive Analog Input 1B Pin
(DMIC1 bit = “0”)
Digital Microphone Clock Output 1 Pin
(DMIC1 bit = “1”)
AVDD/
VSS1
AVDD
Negative Analog Input 1A Pin
AVDD/
VSS1
AVDD
Positive Analog Input 1A Pin
(DMIC1 bit = “0”)
Digital Microphone Data Input 1 Pin
(DMIC1 bit = “1”)
AVDD/
VSS1
AVDD
AVDD/
AVDD
VSS1
All input pins except analog input pins (AIN1A+, AIN1A−, AIN1B+, AIN1B−, AIN2A+, AIN2A−,
AIN2B+ and AIN2B− pins) should not be left floating.
MPWR1
O
MIC Power Supply 1 Pin
5.3. Handling of Unused Pin
The unused I/O pins must be connected appropriately.
Classification
Analog
Digital
Pin Name
MPWR1, MPWR2,
AIN1A+, AIN1A−, AIN1B+, AIN1B−
AIN2A+, AIN2A−, AIN2B+, AIN2B−
MCKO, WINTN, SDTO1
MCKI, TDMIN
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Setting
Open
Open and DMIC1 bit = “0”
Open and DMIC2 bit = “0”
Open
Connect to VSS2
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[AK5704]
5.4. Pin State In Power-down Mode
Register Power-down
Pin Name
I/O
Pin Power-down (PDN pin = “L”)
I
I
I/O
O
O
I
O
I/O
I/O
O
I
I
O
Hi-z
Hi-z
Hi-z
Hi-z
Pull-down to VSS2 by 49kΩ (typ.)
Pull-down to VSS2 by 49kΩ (typ.)
“L” (VSS2)
7
8
9
10
11
12
13
14
15
CAD
SCL
SDA
WINTN
SDTO1
TDMIN
SDTO2
LRCK
BCLK
MCKO
MCKI
VDD12
VSS2
TVDD
PDN
VREF
(PDN pin = “H”)
←
←
←
“H” (TVDD)
“L” (VSS2)
“L” (VSS2)
“L” (VSS2)
“L” (VSS2)
←
Normal Operation
←
←
16
VCOM
O
17
18
19
20
VSS1
AVDD
MPWR2
AIN2BAIN2B+
DMCLK2
AIN2AAIN2A+
DMDAT2
AIN1BAIN1B+
DMCLK1
AIN1AAIN1A+
DMDAT1
MPWR1
O
I
I
O
I
I
I
I
I
O
I
I
I
O
Pull-down to VSS2 by 49kΩ (typ.)
Pull-down to VSS2 by 49kΩ (typ.)
Pull-down to VSS2 by 49kΩ (typ.)
Hi-z
Pull-down to VSS2 by 700Ω (typ.)
Hi-z
Hi-z
Pull-down to VSS1 by 260Ω (typ.) @AVDD=3.3V
Pull-down to VSS1 by 265Ω (typ.) @AVDD=1.8V
Hi-z
Hi-z
Hi-z
←
Hi-z
←
Hi-z
←
Hi-z
←
Hi-z
←
Hi-z
←
Hi-z
←
Hi-z
←
No.
1
2
3
4
5
6
21
22
23
24
25
26
27
28
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←
←
←
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[AK5704]
6. Absolute Maximum Ratings
(VSS1 = VSS2 = 0 V; Note 3, Note 4)
Parameter
Symbol
Min.
Power
Analog
AVDD
−0.3
Supplies
Digital I/F & LDO12
TVDD
−0.3
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (Note 5)
VINA
−0.3
Digital Input Voltage
(Note 6)
VIND1
−0.3
Max.
4.3
4.3
±10
4.3
TVDD+0.3
or 4.3
AVDD+0.3
85
150
Unit
V
V
mA
V
V
(Note 7)
VIND2
V
−0.3
Ambient Temperature (powered applied)
Ta
−40
C
Storage Temperature
Tstg
−65
C
Note 3. All voltages are with respect to ground.
Note 4. VSS1 and VSS2 must be connected to the same analog ground plane.
Note 5. AIN1A+/-, AIN1B+/-, AIN2A+/-, AIN2B+/- pins
Note 6. MCKI, BCLK, LRCK, TDMIN, CAD, SCL, SDA, PDN pins; The maximum value is lower value
between “TVDD+0.3V” and “4.3V”.
Note 7. DMDAT1 and DMDAT2 pins
WARNING: Operation beyond these limits may results in permanent damage to the device. Normal
operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(VSS1 = VSS2 = 0 V; Note 8)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supplies
AVDDL
1.7
1.8
1.9
V
Analog
(Note 9)
AVDDH
3.0
3.3
3.6
V
Digital I/F & LDO12
TVDD
1.65
1.8
3.6
V
Note 8. All voltages are with respect to ground.
Note 9. The power-up sequence between AVDD and TVDD is not critical. The PDN pin must be “L”
upon power-up, and should be changed to “H” after all power supplies are supplied to avoid an
internal circuit error.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in datasheet.
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8. Electrical Characteristics
8.1. Microphone & ADC Analog Characteristics (AVDD=3.3V: AVDDL bit = “0”)
(Ta = 25C; AVDD = 3.3V, TVDD = 1.8 V; VSS1 = VSS2 = 0 V; Signal Frequency = 1 kHz; 24-bit Data; fs
= 48 kHz, BCLK = 64fs; Measurement Bandwidth = 20 Hz to 20 kHz; unless otherwise specified)
Parameter
Min.
Typ.
Max.
Unit
MIC Amplifier 1/2: AIN1A+/-, AIN1B+/-, AIN2A+/-, AIN2B+/- pins
Input Resistance
140
200
260
k
MIC-Amp 1/2 Gain
Gain Setting
0
+30
dB
Step Width
2
3
4
dB
MIC Power Supply: MPWR1/2 pins
MICL[1:0] bits = “00”
2.6
2.8
3.0
MICL[1:0] bits = “01”
2.3
2.5
2.7
Output Voltage (Note 10)
V
MICL[1:0] bits = “10”
1.7
1.8
1.9
MICL[1:0] bits = “11”
AVDD
Load Resistance
650
Load Capacitance
130
pF
MICL[1:0] bits = “00”
−111
Output Noise Level
MICL[1:0] bits = “01”
dBV
−112
(A-weighted)
MICL[1:0] bits = “10”
−116
PSRR (1kHz) (Note 11)
60
dB
Note 10. Output voltage setting of microphone power for MPWR1 and MPWR2 is common. The output
voltage is proportional to AVDD. MICL[1:0] bits = “00”: Typ. 2.8 x AVDD/3.3V, “01”: Typ. 2.5 x
AVDD/3.3V, “10”: Typ. 1.8 x AVDD/3.3V
When MICL[1:0] bits are “11”, MPWR1/2 output AVDD via internal switch (Switch ON
resistance: Typ. 37, Max. 62).
Note 11. PSRR is referred to all power supplies with 100mVpp sine wave.
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[AK5704]
Parameter
Min.
Typ.
Max.
Unit
ADC1/2 Analog Input Characteristics:
AIN1A+, AIN1B+, AIN2A+, AIN2B+ pins (Single-ended Input) → ADC1/2 → SDTO1/2
Resolution
32
Bits
0 dB
1.85
2.02
2.18
Vpp
Input Full Scale Voltage (Note 12)
+18 dB
0.255
Vpp
0 dB
dB
−90
fs = 48 kHz
BW = 20 kHz
+18 dB
dB
−86
−78
0 dB
dB
−90
fs = 96 kHz
THD+N
−1 dBFS
BW = 40 kHz
+18 dB
dB
−86
0 dB
dB
−90
fs = 192 kHz
BW = 40 kHz
+18 dB
dB
−86
0 dB
99
105
dB
Dynamic Range (−60 dBFS, A-weighted)
+18 dB
96
dB
0 dB
99
105
dB
S/N (A-weighted)
+18 dB
96
dB
0 dB
100
dB
Interchannel Isolation
+18 dB
80
100
dB
Interchannel Gain Mismatch
0
0.8
dB
0 dB
60
dB
PSRR (1kHz) (Note 13)
+18dB
60
dB
0 dB
100
dBc
Spurious Free Dynamic Range (10kHz)
(Note 14)
+18dB
100
dBc
ADC1/2 Analog Input Characteristics:
AIN1A+/-, AIN1B+/-, AIN2A+/-, AIN2B+/- pins (Differential Input) → ADC1/2 → SDTO1/2
Resolution
32
Bits
0 dB
1.85
2.02
2.18
Vpp
Input Full Scale Voltage (Note 12)
+18 dB
0.255
Vpp
0 dB
dB
−90
fs = 48 kHz
BW = 20 kHz
+18 dB
dB
−86
0
dB
dB
−90
fs = 96 kHz
THD+N
−1 dBFS
BW = 40 kHz
+18 dB
dB
−86
0 dB
dB
−90
fs = 192 kHz
BW = 40 kHz
+18 dB
dB
−86
0 dB
105
dB
Dynamic Range (−60 dBFS, A-weighted)
+18 dB
96
dB
0 dB
105
dB
S/N (A-weighted)
+18 dB
96
dB
0 dB
100
dB
Interchannel Isolation
+18 dB
100
dB
Interchannel Gain Mismatch
0
dB
0 dB
60
dB
PSRR (1kHz) (Note 13)
+18dB
60
dB
0 dB
100
dBc
Spurious Free Dynamic Range (10kHz)
(Note 14)
+18dB
100
dBc
Note 12. Input voltage is proportional to AVDD. Typ. 2.02 Vpp x AVDD/3.3V @ MIC-Amp Gain = 0 dB
Note 13. PSRR is referred to all power supplies with 100mVpp sine wave. It is the ratio based on
100mVpp (= −26.1dBFS) at the ADC output.
Note 14. SFDR is referred to AVDD with 100mVpp sine wave. It is the dynamic range based on full scale
(0 dBFS) at the ADC output.
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8.2. Microphone & ADC Analog Characteristics (AVDD=1.8V: AVDDL bit = “1”)
(Ta = 25C; AVDD = 1.8V, TVDD = 1.8 V; VSS1 = VSS2 = 0 V; Signal Frequency = 1 kHz; 24-bit Data; fs
= 48 kHz, BCLK = 64fs; Measurement Bandwidth = 20 Hz to 20 kHz; unless otherwise specified)
Parameter
Min.
Typ.
Max.
Unit
MIC Amplifier 1/2: AIN1A+/-, AIN1B+/-, AIN2A+/-, AIN2B+/- pins
Input Resistance
140
200
260
k
MIC-Amp 1/2 Gain
Gain Setting
0
+30
dB
Step Width
2
3
4
dB
MIC Power Supply: MPWR1/2 pins
Output Voltage (Note 15)
“11”
AVDD
V
Note 15. Output voltage setting of microphone power for MPWR1 and MPWR2 is common. The setting
of MICL[1:0] bits = "11" is only available.
When MICL[1:0] bits are “11”, MPWR1/2 output AVDD via internal switch (Switch ON
resistance: Typ. 37, Max. 62).
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[AK5704]
Parameter
Min.
Typ.
Max.
Unit
ADC1/2 Analog Input Characteristics:
AIN1A+, AIN1B+, AIN2A+, AIN2B+ pins (Single-ended Input) → ADC1/2 → SDTO1/2
Resolution
32
Bits
0 dB
1.01
1.10
1.19
Vpp
Input Full Scale Voltage (Note 16)
+18 dB
0.139
Vpp
0 dB
dB
−80
fs = 48 kHz
BW = 20 kHz
+18 dB
dB
−80
−72
0 dB
dB
−80
fs = 96 kHz
THD+N
−1 dBFS
BW = 40 kHz
+18 dB
dB
−80
0 dB
dB
−80
fs = 192 kHz
BW = 40 kHz
+18 dB
dB
−80
0 dB
95
101
dB
Dynamic Range (−60 dBFS, A-weighted)
+18 dB
91
dB
0 dB
95
101
dB
S/N (A-weighted)
+18 dB
91
dB
0 dB
100
dB
Interchannel Isolation
+18 dB
80
100
dB
Interchannel Gain Mismatch
0
0.8
dB
0 dB
60
dB
PSRR (1kHz) (Note 17)
+18dB
60
dB
0 dB
80
dBc
Spurious Free Dynamic Range (10kHz)
(Note 18)
+18dB
80
dBc
ADC1/2 Analog Input Characteristics:
AIN1A+/-, AIN1B+/-, AIN2A+/-, AIN2B+/- pins (Differential Input) → ADC1/2 → SDTO1/2
Resolution
32
Bits
0 dB
1.01
1.10
1.19
Vpp
Input Full Scale Voltage (Note 16)
+18 dB
0.139
Vpp
0 dB
dB
−80
fs = 48 kHz
BW = 20 kHz
+18 dB
dB
−80
0
dB
dB
−80
fs = 96 kHz
THD+N
−1 dBFS
BW = 40 kHz
+18 dB
dB
−80
0 dB
dB
−80
fs = 192 kHz
BW = 40 kHz
+18 dB
dB
−80
0 dB
101
dB
Dynamic Range (−60 dBFS, A-weighted)
+18 dB
91
dB
0 dB
101
dB
S/N (A-weighted)
+18 dB
91
dB
0 dB
100
dB
Interchannel Isolation
+18 dB
100
dB
Interchannel Gain Mismatch
0
dB
0 dB
60
dB
PSRR (1kHz) (Note 17)
+18dB
60
dB
0 dB
80
dBc
Spurious Free Dynamic Range (10kHz)
(Note 18)
+18dB
80
dBc
Note 16. Input voltage is proportional to AVDD. Typ. 1.10 Vpp x AVDD/1.8V @ MIC-Amp Gain = 0 dB
Note 17. PSRR is referred to all power supplies with 100mVpp sine wave. It is the ratio based on
100mVpp (= −20.8dBFS) at the ADC output.
Note 18. SFDR is referred to AVDD with 100mVpp sine wave. It is the dynamic range based on full scale
(0 dBFS) at the ADC output.
019000890-E-01
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[AK5704]
8.3. Power Supply Current
(Ta = 25C; AVDD = 3.3V or 1.8V, TVDD = 1.8 V; VSS1 = VSS2 = 0 V; unless otherwise specified)
Parameter
Min.
Typ.
Max.
Unit
Power Supply Current
Power Up (PDN pin = “H”, All circuits power-up, Note 19)
AVDD (AVDD=3.3V: AVDDL bit = “0”)
7.0
9.8
mA
AVDD (AVDD=1.8V: AVDDL bit = “1”)
5.3
mA
TVDD
2.4
3.4
mA
Power Up (PDN pin = “H”, LDO12 Enable, Other circuits power-down)
AVDD (AVDD=3.3V: AVDDL bit = “0”)
0.05
mA
AVDD (AVDD=1.8V: AVDDL bit = “1”)
0.05
mA
TVDD
0.15
mA
Power Down (PDN pin = “L”, Note 20)
AVDD + TVDD
4
20
μA
Note 19. PLL Master Mode, MCKI=16MHz, BCLK=64fs, fs=48kHz (PLD[15:0] bits = 0018H, PLM[15:0]
bits = 005FH, FS[3:0] bits = “1010”, CM[1:0] bits = “01”, PLS bit = “0”, MSN = BCKO = MCKOE
bit = “1”); All PMxx bits except PMDMxx bits are powered up.; MICL[1:0] bits = “00”
@AVDD=3.3V, MICL[1:0] bits = “11” @AVDD=1.8V; No signal input
Note 20. All digital input pins are fixed to each power supply pin, TVDD or VSS2.
8.4. Power Consumption for Each Operation Mode
(Ta = 25C; AVDD = 3.3V or 1.8V, TVDD = 1.8 V; VSS1 = VSS2 = 0 V; External Slave Mode, MCKI = 256
fs, BCLK = 64fs; No signal input, MPWR OFF)
AVDD
TVDD
Total Power
Mode
[mA]
[mA]
[mW]
3.3V
2.4
9.7
AIN1/2 → 2-ch ADC (fs = 48 kHz)
1.0
1.8V
2.0
5.4
3.3V
4.4
17.8
AIN1/2 → 2-ch ADC (fs = 96 kHz)
1.8
1.8V
3.7
9.9
3.3V
4.4
17.8
AIN1/2 → 2-ch ADC (fs = 192 kHz)
1.8
1.8V
3.7
9.9
3.3V
4.5
17.0
AIN1/2 → 4-ch ADC (fs = 48 kHz)
1.2
1.8V
4.0
9.4
3.3V
8.4
31.7
AIN1/2 → 4-ch ADC (fs = 96 kHz)
2.2
1.8V
7.1
16.7
3.3V
8.4
31.7
AIN1/2 → 4-ch ADC
2.2
(fs = 192 kHz, MCKI=128fs)
1.8V
7.1
16.7
3.3V
1.2
4.9
Voice Activity Detection Mode
0.5
(AIN1A → 1-ch ADC → VAD, fs = 16kHz)
1.8V
1.0
2.7
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[AK5704]
8.5. ADC1/2 Short Delay Sharp Roll-off Filter (ADVF bit = “0”)
(Ta = −40 to 85C; AVDD = 1.7 to 1.9V or 3.0 to 3.6 V; TVDD = 1.65 to 3.6 V; fs = 48kHz)
Parameter
Symbol
Min.
Typ.
Max.
Unit
ADC Digital Filter (Decimation LPF):
Passband (Note 21)
±0.16 dB
PB
0
18.8
kHz
20.0
kHz
−0.28 dB
22.8
kHz
−3.0 dB
Stopband (Note 21)
SB
28.4
kHz
Stopband Attenuation
SA
72
dB
Group Delay (Note 22)
GD
5.0
1/fs
Group Delay Distortion
2.4
1/fs
GD
ADC Digital Filter (HPF): HPFxC[1:0] bits = “00” (x=1, 2)
Frequency Response
FR
3.7
Hz
−3.0 dB
(Note 21)
Note 21. The passband and stopband frequencies scale with fs (sampling frequency). Each response
refers to that of 1kHz.
Note 22. This time is from the input of an analog signal to the A channel MSB output timing of SDTO1/2.
This time includes group delay of the HPF. The error of the delay at audio interface is within +1/8
[1/fs]. For the signal through the programmable filters, the group delay is increased by 1/fs.
(Ta = −40 to 85C; AVDD = 1.7 to 1.9V or 3.0 to 3.6 V; TVDD = 1.65 to 3.6 V; fs = 96kHz)
Parameter
Symbol
Min.
Typ.
Max.
ADC Digital Filter (Decimation LPF):
Passband (Note 21)
±0.16 dB
PB
0
37.6
40.0
−0.28 dB
45.6
−3.0 dB
Stopband (Note 21)
SB
56.8
Stopband Attenuation
SA
72
Group Delay (Note 22)
GD
5.0
Group Delay Distortion
2.4
GD
ADC Digital Filter (HPF): HPFxC[1:0] bits = “00” (x=1, 2)
Frequency Response
FR
7.4
−3.0 dB
(Note 21)
(Ta = −40 to 85C; AVDD = 1.7 to 1.9V or 3.0 to 3.6 V; TVDD = 1.65 to 3.6 V; fs = 192kHz)
Parameter
Symbol
Min.
Typ.
Max.
ADC Digital Filter (Decimation LPF):
Passband (Note 21)
±0.12 dB
PB
0
37
51
−1.0 dB
65
−3.0 dB
78
−6.0 dB
Stopband (Note 21)
SB
145.5
Stopband Attenuation
SA
72
Group Delay (Note 22)
GD
4.4
Group Delay Distortion
0
GD
ADC Digital Filter (HPF): HPFxC[1:0] bits = “00” (x=1, 2)
Frequency Response
FR
14.8
−3.0 dB
(Note 21)
019000890-E-01
Unit
kHz
kHz
kHz
kHz
dB
1/fs
1/fs
Hz
Unit
kHz
kHz
kHz
kHz
kHz
dB
1/fs
1/fs
Hz
2022/01
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[AK5704]
8.6. ADC1/2 Digital Filter for Voice (ADVF bit = “1”)
(Ta = −40 to 85C; AVDD = 1.7 to 1.9V or 3.0 to 3.6 V; TVDD = 1.65 to 3.6 V; fs = 8kHz)
Parameter
Symbol
Min.
Typ.
Max.
Voice Digital Filter
Passband (Note 21) -0.5dB to 0.5dB
PB
0
3.15
-3.0dB
3.35
Stopband (Note 21)
SB
4.0
Stopband Attenuation
SA
60
Group Delay (Note 22)
GD
15.2
Group Delay Distortion
GD
0
ADC Digital Filter (HPF): HPFxC[1:0] bits = “00” (x=1, 2)
Frequency Response
-3.0dB
FR
0.6
(Note 21)
(Ta = −40 to 85C; AVDD = 1.7 to 1.9V or 3.0 to 3.6 V; TVDD = 1.65 to 3.6 V; fs = 16kHz)
Parameter
Symbol
Min.
Typ.
Max.
Voice Digital Filter
Passband (Note 21) -0.5dB to 0.5dB
PB
0
6.3
-3.0dB
6.7
Stopband (Note 21)
SB
8.0
Stopband Attenuation
SA
60
Group Delay (Note 22)
GD
15.2
Group Delay Distortion
GD
0
ADC Digital Filter (HPF): HPFxC[1:0] bits = “00” (x=1, 2)
Frequency Response
-3.0dB
FR
1.2
(Note 21)
019000890-E-01
Unit
kHz
kHz
kHz
dB
1/fs
1/fs
Hz
Unit
kHz
kHz
kHz
dB
1/fs
1/fs
Hz
2022/01
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[AK5704]
8.7. DC Characteristics
(Ta = −40 to 85C; AVDD = 1.7 to 1.9V or 3.0 to 3.6 V; TVDD = 1.65 to 3.6 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Normal Pin (Note 23)
High-Level Input Voltage
VIH
70% TVDD
V
Low-Level Input Voltage
VIL
30% TVDD
V
VOH
V
High-Level Output Voltage (Iout = −200 μA)
TVDD −0.2
Low-Level Output Voltage
Except for SDA pin, Iout = 200 μA
VOL
0.2
V
SDA pin
VOL
0.4
V
2 V < TVDD 3.6 V (Iout = 3 mA)
VOL
20% TVDD
V
1.65 V TVDD 2 V (Iout = 2 mA)
Input Leakage Current (Note 24)
Iin
+5
μA
−5
Digital MIC Interface (DMDAT1/2 pin Input)
High-Level Input Voltage
VIH2
65% AVDD
V
Low-Level Input Voltage
VIL2
35% AVDD
V
Digital MIC Interface (DMCLK1/2 pin Output)
High-Level Output Voltage (Iout = −80 μA)
VOH2
AVDD −0.4
V
Low-Level Output Voltage (Iout = 80 μA)
VOL2
0.4
V
Input Leakage Current
Iin
−5
+5
μA
Note 23. MCKI, MCKO, BLK, LRCK, TDMIN/SDTO2, SDTO1, CAD, SCL, SDA, PDN, WINTN pins
Note 24. PSW1N = PSW2N bits = “1“
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[AK5704]
8.8. Switching Characteristics
(Ta = −40 to 85C; AVDD = 1.7 to 1.9V or 3.0 to 3.6 V; TVDD = 1.65 to 3.6 V; CL = 50 pF(MCKO, BCLK,
LRCK pins), 20 pF(SDTO1, SDTO2 pins); unless otherwise specified)
Parameter
Master Clock Input Timing
Input Frequency
Pulse Width Low
Pulse Width High
Master Clock Output Timing
Output Frequency
Duty Cycle (Note 25)
LRCK Frequency (Slave mode)
Normal mode (TDM[1:0] bits = “00”)
Frequency
Duty Cycle
TDM128 mode (TDM[1:0] bits = “01”)
Frequency
High Time
Low Time
TDM256 mode (TDM[1:0] bits = “10”)
Frequency
High time
Low time
TDM512 mode (TDM[1:0] bits = “11”)
Frequency
High Time
Low Time
BCLK Frequency (Slave mode)
Normal mode (TDM[1:0] bits = “00”)
Frequency (Note 26)
Symbol
Min.
Typ.
Max.
Unit
fMCK
tMCKL
tMCKH
0.256
0.4 / fMCK
0.4 / fMCK
-
27
-
MHz
ns
ns
fMCKO
dMCKO
-
50
24.576
-
MHz
%
fs
Duty
8
45
-
192
55
kHz
%
fs
tLRH
tLRL
8
1/128fs
1/128fs
-
192
-
kHz
ns
ns
fs
tLRH
tLRL
8
1/256fs
1/256fs
-
96
-
kHz
ns
ns
fs
tLRH
tLRL
8
1/512fs
1/512fs
-
48
-
kHz
ns
ns
1/tBCK
32fs
-
24.576M
or 512fs
-
BCLK Pulse Width Low
tBCKL
32
BCLK Pulse Width High
tBCKH
32
TDM128 mode (TDM[1:0] bits = “01”)
Frequency
1/tBCK
128fs
BCLK Pulse Width Low
tBCKL
16
BCLK Pulse Width High
tBCKH
16
TDM256 mode (TDM[1:0] bits = “10”)
Frequency
1/tBCK
256fs
BCLK Pulse Width Low
tBCKL
16
BCLK Pulse Width High
tBCKH
16
TDM512 mode (TDM[1:0] bits = “11”)
Frequency
1/tBCK
512fs
BCLK Pulse Width Low
tBCKL
16
BCLK Pulse Width High
tBCKH
16
Note 25. Divided by an even number.
Note 26. The maximum value is slower frequency between “24.576MHz” and “512fs”.
019000890-E-01
Hz
ns
ns
-
Hz
ns
ns
-
Hz
ns
ns
-
Hz
ns
ns
2022/01
- 18 -
[AK5704]
1/fMCK
VIH
MCKI
VIL
tMCKH
tMCKL
1/fMCKO
MCKO (Output)
50 %TVDD
Duty “dMCKO”
= tMCKOH / (1/fMCKO) x 100
tMCKOH
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
BCLK
VIL
tBCKH
tBCKL
Figure 2. System Clock (Slave Mode)
019000890-E-01
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[AK5704]
Parameter
LRCK Frequency (Master mode)
Normal mode (TDM[1:0] bits = “00”)
Frequency
Duty Cycle
TDM128 mode (TDM[1:0] bits = “01”)
Frequency
High Time
TDM256 mode (TDM[1:0] bits = “10”)
Frequency
High Time
TDM512 mode (TDM[1:0] bits = “11”)
Frequency
High Time
BCLK Frequency (Master mode)
Normal mode (TDM[1:0] bits = “00”)
Frequency (BCKO bit = “0”)
(BCKO bit = “1”)
BCLK Duty
TDM128 mode (TDM[1:0] bits = “01”)
Frequency
BCLK Duty
TDM256 mode (TDM[1:0] bits = “10”)
Frequency
BCLK Duty
TDM512 mode (TDM[1:0] bits = “11”)
Frequency
BCLK Duty
Symbol
Min.
Typ.
Max.
Unit
fs
Duty
8
-
50
192
-
kHz
%
fs
tLRH
8
-
1/4fs
192
-
kHz
ns
fs
tLRH
8
-
1/8fs
96
-
kHz
ns
fs
tLRH
8
-
1/16fs
48
-
kHz
ns
1/tBCK
1/tBCK
dBCK
-
32fs
64fs
50
-
Hz
Hz
%
1/tBCK
dBCK
-
128fs
50
-
Hz
%
1/tBCK
dBCK
-
256fs
50
-
Hz
%
1/tBCK
dBCK
-
512fs
50
-
Hz
%
1/fs
50%TVDD
LRCK
tLRH
Duty = tLRH x fs x 100
tBCK
50%TVDD
BCLK
tBCKH
tBCKL
Duty = tBCKH / tBCK x 100
tBCKL / tBCK x 100
Figure 3.System Clock (Master Mode)
019000890-E-01
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[AK5704]
Parameter
Symbol
Min.
Typ.
Audio Interface Timing (Slave mode)
Normal mode
(TDM[1:0] bits = “00”, DIF1 bit = “0”)
LRCK Edge to BCLK “↑” (Note 27)
tLRB
25
BCLK “↑” to LRCK Edge (Note 27)
tBLR
25
LRCK to SDTO (MSB) (Except I2S Mode)
tLRS
BCLK “↓” to SDTO1/2 (Note 28)
tBSD
PCM mode
(TDM[1:0] bits = “00” , DIF1 bit = “1”)
LRCK Edge to BCLK “↑” (Note 27)
tLRB
25
BCLK “↑” to LRCK Edge (Note 27)
tBLR
25
BCLK “↑” to SDTO1/2 (Note 27)
tBSDD
5
TDM128 mode (TDM[1:0] bits = “01”)
LRCK Edge to BCLK “↑” (Note 27)
tLRB
16
BCLK “↑” to LRCK Edge (Note 27)
tBLR
16
BCLK “↑” to SDTO1 (Note 27)
tBSDD
5
TDMIN Hold Time
tSDH
5
TDMIN Setup Time
tSDS
5
TDM256 mode (TDM[1:0] bits = “10”)
LRCK Edge to BCLK “↑” (Note 27)
tLRB
16
BCLK “↑” to LRCK Edge (Note 27)
tBLR
16
BCLK “↑” to SDTO1 (Note 27)
tBSDD
5
TDMIN Hold Time
tSDH
5
TDMIN Setup Time
tSDS
5
TDM512 mode (TDM[1:0] bits = “11”)
LRCK Edge to BCLK “↑” (Note 27)
tLRB
16
BCLK “↑” to LRCK Edge (Note 27)
tBLR
16
BCLK “↑” to SDTO1 (Note 27)
tBSDD
5
TDMIN Hold Time
tSDH
5
TDMIN Setup Time
tSDS
5
Note 27. When the polarity of BCLK is inverted, delay time starts from BCLK “↓”.
Note 28. When the polarity of BCLK is inverted, delay time starts from BCLK “↑”.
Max.
Unit
25
25
ns
ns
ns
ns
35
ns
ns
ns
35
-
ns
ns
ns
ns
ns
35
-
ns
ns
ns
ns
ns
35
-
ns
ns
ns
ns
ns
VIH
LRCK
VIL
tBLR
tLRB
VIH
BCLK
VIL
tLRS
tBSD
SDTO1/2
50%TVDD
Figure 4. Audio Interface Timing (Normal & Slave Mode: BCKP bit = “0”)
019000890-E-01
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[AK5704]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BCLK
VIL
tLRS
tBSD
SDTO1/2
50%TVDD
Figure 5. Audio Interface Timing (Normal & Slave Mode: BCKP bit = “1”)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BCLK
VIL
tBSDD
SDTO1/2
50%TVDD
Figure 6. Audio Interface Timing (PCM & Slave Mode: BCKP bit = “0”)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BCLK
VIL
tBSDD
SDTO1/2
50%TVDD
Figure 7. Audio Interface Timing (PCM & Slave Mode: BCKP bit = “1”)
019000890-E-01
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[AK5704]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BCLK
VIL
tBSDD
SDTO1
50%TVDD
tSDH
tSDS
VIH
TDMIN
VIL
Figure 8. Audio Interface Timing (TDM & Slave mode: BCKP bit = “0”)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BCLK
VIL
tBSDD
SDTO1
50%TVDD
tSDH
tSDS
VIH
TDMIN
VIL
Figure 9. Audio Interface Timing (TDM & Slave Mode: BCKP bit = “1”)
019000890-E-01
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[AK5704]
Min.
Typ.
Parameter
Symbol
Audio Interface Timing (Master mode)
Normal mode (TDM[1:0] bits = “00”)
BCLK “↓” to LRCK Edge (Note 29)
tMBLR
−20
BCLK “↓”to SDTO1/2 (Note 29)
tBSD
−20
TDM128 mode (TDM[1:0] bits = “01”)
BCLK “↓” to LRCK Edge (Note 29)
tMBLR
−10
BCLK “↓” to SDTO1/2 (Note 29)
tBSD
−10
TDMIN Hold Time
tSDH
5
TDMIN Setup Time
tSDS
5
TDM256 mode (TDM[1:0] bits = “10”)
−10
BCLK “↓” to LRCK Edge (Note 29)
tMBLR
BCLK “↓” to SDTO1 (Note 29)
tBSD
−10
TDMIN Hold Time
tSDH
5
TDMIN Setup Time
tSDS
5
TDM512 mode (TDM[1:0] bits = “11”)
BCLK “↓” to LRCK Edge (Note 29)
tMBLR
−10
BCLK “↓” to SDTO1 (Note 29)
tBSD
−10
TDMIN Hold Time
tSDH
5
TDMIN Setup Time
tSDS
5
Note 29. When the polarity of BCLK is inverted, delay time starts from BCLK “↑”.
LRCK
Max.
Unit
20
20
ns
ns
10
10
-
ns
ns
ns
ns
10
10
-
ns
ns
ns
ns
10
10
-
ns
ns
ns
ns
50%TVDD
tMBLR
50%TVDD
BCLK
tBSD
50%TVDD
SDTO1
tSDS
tSDH
VIH
TDMIN
VIL
Figure 10. Audio Interface Timing (Master mode: BCKP bit = “0”)
LRCK
50%TVDD
tMBLR
50%TVDD
BCLK
tBSD
50%TVDD
SDTO1
tSDS
tSDH
VIH
TDMIN
VIL
Figure 11. Audio Interface Timing (Master mode: BCKP bit = “1”)
019000890-E-01
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[AK5704]
Parameter
Symbol
Digital Audio Interface Timing: CL = 100 pF
DMCLK1/2 Output Timing
Period
tSCK
Rising Time
tSRise
Falling Time
tSFall
Duty Cycle
dSCK
Audio Interface Timing (DMCLK1/2, DMDAT1/2 pins)
DMDAT1/2 Setup Time
tDMS
DMDAT1/2 Hold Time
tDMH
Min.
Typ.
Max.
Unit
45
1/(64fs)
50
10
10
55
ns
ns
ns
%
50
0
-
-
ns
ns
tSCK
65%AVDD
DMCLKx
50%AVDD
35%AVDD
tSCKL
tSRise
tSFall
dSCK = 100 x tSCKL / tSCK
Figure 12. DMCLK1/2 Output Timing
VOH2
DMCLKx
VOL2
tDMS
tDMH
VIH2
DMDATx
Lch
@DCLKPx bit = “1”
VIL2
tDMS
tDMH
VIH2
DMDATx
VIL2
Rch
@DCLKPx bit = “1”
Figure 13. Audio Interface Timing
019000890-E-01
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[AK5704]
Parameter
Symbol
Min.
Typ.
Control Interface Timing: (Note 30)
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 31)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Capacitive Load on Bus
Cb
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
2
Note 30. I C-bus is a registered trademark of NXP B.V.
Note 31. Data must be held long enough to bridge the 300ns-transition time of SCL.
Max.
Unit
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
Start
Figure 14. I2C Bus Mode Timing
019000890-E-01
tSU:STO
Stop
2022/01
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[AK5704]
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power-down & Reset Timing
PDN Accept Pulse Width (Note 32)
tPDN
1
ms
PDN Reject Pulse Width (Note 32)
tRPD
50
ns
PMADxA/B bit = “1” to SDTOx valid (Note 33)
ADRST[2:0] bits = “000”
tPDV
1059
1/fs
ADRST[2:0] bits = “001”
tPDV
267
1/fs
ADRST[2:0] bits = “010”
tPDV
2115
1/fs
ADRST[2:0] bits = “011”
tPDV
531
1/fs
ADRST[2:0] bits = “100”
tPDV
4230
1/fs
ADRST[2:0] bits = “101”
tPDV
8
1/fs
ADRST[2:0] bits = “110”
tPDV
16
1/fs
ADRST[2:0] bits = “111”
tPDV
32
1/fs
PMDMxA/B bit = “1” to SDTOx valid (Note 34)
ADRST[2:0] bits = “000”
tPDV
1059
1/fs
ADRST[2:0] bits = “001”
tPDV
267
1/fs
ADRST[2:0] bits = “010”
tPDV
2115
1/fs
ADRST[2:0] bits = “011”
tPDV
531
1/fs
ADRST[2:0] bits = “100”
tPDV
4230
1/fs
ADRST[2:0] bits = “101”
tPDV
8
1/fs
ADRST[2:0] bits = “110”
tPDV
16
1/fs
ADRST[2:0] bits = “111”
tPDV
32
1/fs
Note 32. The PDN pin must held “L” for longer period the or equal to tPDN period. The AK5704 will not
be reset by the “L” pulse shorter than or equal to 50nsec.
Note 33. This is the count of LRCK “↑” from PMADxA/B bit = “1”.
Note 34. This is the count of LRCK “↑” from PMDMxA/B bit = “1”.
tPDN
PDN
VIL
tRPD
Figure 15. Power Down & Standby
PMADxA/B bit
PMDMxA/B bit
tPDV
SDTOx
50%TVDD
Figure 16. ADC1/2, DMIC1/2 Power Up Timing
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2022/01
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[AK5704]
9. Functional Descriptions
9.1. Internal Pull-down Pin
When the PDN pin = “H”, digital pins shown in Table 1 can set internal pull-down resistor to ON/OFF by
PSW0N, PSW1N, PSW2N bits. The pull-down resistor is ON and the control register is “0” at default
setting. The pull-down resistor setting should be made according to external conditions.
Table 1. Internal Pull-down Pin
Power
Control bit
Pin Name
I/O
Pin Name
Domain
(Note 35)
CAD
I
TVDD
DMCLK1
SCL
I
TVDD
DMDAT1
SDA
I/O
TVDD
DMCLK2
MCKI
I
TVDD
DMDAT2
MCKO
O
TVDD
PSW0N
BCLK
I/O
TVDD
PSW1N
LRCK
I/O
TVDD
PSW1N
TDMIN/SDTO2 I/O
TVDD
PSW2N
SDTO1
O
TVDD
PSW0N
PDN
I
TVDD
WINTN
O
TVDD
Note 35. “-”: There is no pull-down resistor.
I/O
O
I
O
I
Power
Domain
AVDD
AVDD
AVDD
AVDD
Control bit
(Note 35)
-
9.2. LDO Circuit
The PDN pin must be “L” upon power-up, and should be changed to “H” after all power supplies are
supplied. Then LDO12 will be powered up.
LDO12 has an overvoltage protection circuit. This overvoltage protection circuit powers the LDO12 down
when the power supply becomes unstable by an instantaneous power failure, etc. during operation. The
LDO12 circuit will not return to normal operation until being reset by the PDN pin (“L” → “H”) after
removing the problems.
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[AK5704]
9.3. System Clock
The AK5704 is operated by a clock generated by PLL or MCKI supplied from external. MCKI frequency
will be 128fs, 256fs, 512fs or 1024fs. The master clock is set by CM[1:0] bits (Table 3) and the sampling
frequency is set by FS[3:0] bits (Table 4). When changing the master clock or sampling frequency, set
PMAD1A/B = PMAD2A/B = PMDM1A/B = PMDM2A/B bits = “0” and VREF bit = “1”. If the clock is stopped
at PMADx bit = “1”, VREF bit should be set to “1”.
Table 2. Clock Mode Setting (x: Do not care, N/A: Not available)
PMPLL
bit
Mode
PLL Master Mode
1
MSN
bit
1
PLS
bit
0
PLL Slave Mode
(Clock Source:
MCKI pin)
1
0
0
PLL Slave Mode
(Clock Source:
BCLK pin)
1
0
1
EXT Master Mode
0
1
x
EXT Slave Mode
0
0
x
CM[1:0] bits
00
01
10
11
MCKI
pin
Input
BCLK pin
LRCK pin
Output
(Table 6)
Output
(Table 4)
Input
(≥ 32fs)
Input
(Table 4)
GND
Input
(Table 14,
Table 15)
Input
(Table 4)
Input
(Table 3)
Input
(Table 3)
Output
(Table 6)
Input
(≥ 32fs)
Output
(Table 4)
Input
(Table 4)
(Table 10,
Table 11,
Table 12,
Table 13)
Input
(Table 10,
Table 11,
Table 12,
Table 13)
Table 3. Setting of Master Clock Frequency
Master Clock Frequency Sampling Frequency Range
256fs
8 to 96 kHz
512fs
8 to 48 kHz
1024fs
8 to 24 kHz
128fs
176.4 to 192 kHz
019000890-E-01
MCKOE
bit
MCKO pin
0
“L” Output
1
Output
(Table 5)
1
Output
(Table 5)
0
1
0
1
0
1
“L” Output
Output
(Table 5)
“L” Output
N/A
“L” Output
N/A
(default)
2022/01
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[AK5704]
Table 4. Setting of Sampling Frequency (N/A: Not available)
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
8 kHz
0
0
0
1
11.025 kHz
0
0
1
0
12 kHz
0
0
1
1
N/A
0
1
0
0
16 kHz
0
1
0
1
22.05 kHz
0
1
1
0
24 kHz
0
1
1
1
N/A
1
0
0
0
32 kHz
1
0
0
1
44.1 kHz
1
0
1
0
48 kHz
(default)
1
0
1
1
N/A
1
1
0
0
88.2 kHz
1
1
0
1
96 kHz
1
1
1
0
176.4 kHz
1
1
1
1
192 kHz
Note 36. Sampling frequency has an error according to PLL division ratio. PLD[15:0], PLM[15:0] bits
should be set with accuracy.
9.4. PLL
The built-in PLL generates master clock for internal operation from the clock source input to the MCKI pin
or the BCLK pin. PLL starts to operate when PMPLL bit = “1”.
1. PLL Output Frequency (MCKO pin)
The PLL generates master clock for internal operation and outputs frequency below from the MCKO pin.
Table 5. MCKO Output
MCKO pin
Sampling Frequency
CM[1:0] bits
Range
MCKOE bit = “0” MCKOE bit = “1”
00
“L” Output
256fs
8 to 96 kHz
(default)
01
“L” Output
512fs
8 to 48 kHz
10
“L” Output
1024fs
8 to 24 kHz
11
“L” Output
128fs
176.4 to 192 kHz
Note 37. When CM[1:0] bits = “01”, fs=32kHz is not available. When CM[1:0] bits = “10”, fs=16kHz is not
available.
2. BCLK Output Frequency
When PLL Master Mode (MSN bit = “1”) is used, the following frequencies is output from the BCLK pin.
Table 6. BCLK Output (x: Do not care)
BCKO bit
BCLK pin
Sampling Frequency Range
0
32fs
8 to 192 kHz
(default)
00
1
64fs
8 to 192 kHz
01
x
TDM128fs
8 to 192 kHz
10
x
TDM256fs
8 to 96 kHz
11
x
TDM512fs
8 to 48 kHz
Note 38. When TDM[1:0] bits = “11”, the setting of CM[1:0] bits = “00” is not available.
TDM[1:0] bits
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2022/01
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[AK5704]
3. Internal Block Diagram of PLL
MCKI
60kHz
to 640kHz
1
(PLD+1)
BCLK
PLL Analog
PLLCLK
Reference
Divider
MCKO
Feedback
PLS
1
(PLM+1)
1
2
Figure 17. PLL Block Diagram
PLL clock source is selected by PLS bit.
Table 7. PLL Clock Source Select
PLS bit
Clock Source
0
MCKI pin
(default)
1
BCLK pin
(3-1) PLL Reference Clock Divider (PLD)
The PLL can set the division ratio of the reference clock in 16 bits. The input clock is used as PLL
reference clock by dividing by (PLDx + 1).
Table 8. PLL Reference Clock Divider
PLD[15:0] bits
Division Ratio
0000H
1
(default)
0001H to FFFFH
1/(PLD+1)
Note 39. The reference clock should be set in the range from 60kHz to 640kHz after divided by PLD.
(3-2) PLL Feedback Clock Divider (PLM)
The division ratio of feedback clock can be set freely in 16 bits. PLLCLK is divided by ((PLM+1) x 2) and
used as a PLL feedback clock. The feedback clock is fixed to “L” without dividing when PLM = 0000H.
Table 9. PLL Feedback Clock Divider
PLM[15:0] bits
Division Ratio
0000H
Clock Stop
(default)
0001H to FFFFH
1/((PLM+1) x 2)
4. Adaptive Frequencies
MCKI pin: 11.2896/22.5792MHz, 12.288/24.576MHz, 9.6/19.2MHz, 12/24MHz, 13/26MHz, 13.5/27MHz,
16MHz
BCLK pin: 32fs, 64fs, 128fs, 256fs, 512fs
fs:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz,
176.4kHz, 192kHz
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[AK5704]
5. Example of PLL Frequency Setting
5.1. PLL Reference Source: MCKI (PMPLL bit = “1”, MSN bit = “0”, “1”, PLS bit = “0”)
Table 10. PLL Frequency Setting Example (PLL reference source: MCKI) (1)
MCKI
[MHz]
11.2896
12.288
22.5792
24.576
12
Note 40.
fs
[kHz]
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
PLD
[15:0]
bits
PLM
[15:0]
bits
0092H
031FH
001FH
0092H
0092H
018FH
003FH
0092H
0018H
007FH
007CH
024BH
FS
[3:0]
bits
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
MCKO
Frequency
Error
CM[1:0] bits CM[1:0] bits CM[1:0] bits CM[1:0] bits
[ppm]
= “00”
= “01”
= “10”
= “11”
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
512fs
1024fs
0
256fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
512fs
1024fs
0
256fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
512fs
1024fs
0
256fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
0
128fs
0
“-”: Not available
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[AK5704]
Table 11. PLL Frequency Setting Example (PLL reference source: MCKI) (2)
MCKI
[MHz]
16
24
19.2
Note 41.
fs
[kHz]
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
PLD
[15:0]
bits
PLM
[15:0]
bits
0018H
005FH
007CH
01B8H
0031H
007FH
007CH
0125H
0031H
009FH
0031H
0092H
FS
[3:0]
bits
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
MCKO
Frequency
Error
CM[1:0] bits CM[1:0] bits CM[1:0] bits CM[1:0] bits
[ppm]
= “00”
= “01”
= “10”
= “11”
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
512fs
1024fs
0
256fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
512fs
1024fs
0
256fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
512fs
1024fs
0
256fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
0
128fs
0
“-”: Not available
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[AK5704]
Table 12. PLL Frequency Setting Example (PLL reference source: MCKI) (3)
MCKI
[MHz]
9.6
13
26
Note 42.
fs
[kHz]
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
PLD
[15:0]
bits
PLM
[15:0]
bits
000EH
005FH
0018H
0092H
0053H
018CH
0025H
00A4H
0144H
02FFH
004BH
00A4H
FS
[3:0]
bits
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
MCKO
Frequency
Error
CM[1:0] bits CM[1:0] bits CM[1:0] bits CM[1:0] bits
[ppm]
= “00”
= “01”
= “10”
= “11”
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
512fs
1024fs
0
256fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
7.750
256fs
512fs
1024fs
7.750
256fs
512fs
7.750
256fs
512fs
1024fs
7.750
256fs
7.750
256fs
512fs
7.750
256fs
7.750
128fs
7.750
256fs
512fs
1024fs
-11.189
256fs
512fs
1024fs
-11.189
256fs
512fs
-11.189
256fs
-11.189
128fs
-11.189
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
512fs
1024fs
0
256fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
-11.189
256fs
512fs
1024fs
-11.189
256fs
512fs
-11.189
256fs
-11.189
128fs
-11.189
“-”: Not available
019000890-E-01
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[AK5704]
Table 13. PLL Frequency Setting Example (PLL reference source: MCKI) (4)
MCKI
[MHz]
13.5
27
Note 43.
fs
[kHz]
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
PLD
[15:0]
bits
PLM
[15:0]
bits
00E0H
03FFH
00B5H
02F8H
00E0H
01FFH
0181H
0326H
FS
[3:0]
bits
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
MCKO
Frequency
Error
CM[1:0] bits CM[1:0] bits CM[1:0] bits CM[1:0] bits
[ppm]
= “00”
= “01”
= “10”
= “11”
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
512fs
1024fs
0
256fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
-3.504
256fs
512fs
1024fs
-3.504
256fs
512fs
-3.504
256fs
-3.504
128fs
-3.504
256fs
512fs
1024fs
0
256fs
512fs
1024fs
0
256fs
512fs
0
256fs
512fs
1024fs
0
256fs
0
256fs
512fs
0
256fs
0
128fs
0
256fs
512fs
1024fs
3.304
256fs
512fs
1024fs
3.304
256fs
512fs
3.304
256fs
3.304
128fs
3.304
“-”: Not available
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[AK5704]
5.2. PLL Reference Source: BCLK [Stereo Mode] (PMPLL bit = “1”, MSN bit = “0”, PLS bit = “1”, TDM[1:0]
bits = “00”)
Table 14. PLL Frequency Setting Example (PLL reference source: BCLK [Stereo Mode])
fs
[kHz]
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
Note 44.
BCLK
32fs
64fs
BCLK
[MHz]
PLD
[15:0]
bits
PLM
[15:0]
bits
FS
[3:0]
bits
0.256
0.384
0.512
0.768
1.024
1.536
3.072
6.144
0.3528
0.7056
1.4112
2.8224
5.6448
0.512
0.768
1.024
1.536
2.048
3.072
6.144
12.288
0.7056
1.4112
2.8224
5.6448
11.2896
0000H
0000H
0000H
0001H
0001H
0003H
0007H
000FH
0000H
0001H
0003H
0007H
000FH
0000H
0001H
0001H
0003H
0003H
0007H
000FH
001FH
0001H
0003H
0007H
000FH
001FH
00EFH
009FH
0077H
009FH
0077H
009FH
009FH
009FH
009FH
009FH
009FH
009FH
009FH
0077H
009FH
0077H
009FH
0077H
009FH
009FH
009FH
009FH
009FH
009FH
009FH
009FH
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
MCKO
CM[1:0] bits CM[1:0] bits CM[1:0] bits CM[1:0] bits
= “00”
= “01”
= “10”
= “11”
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
256fs
512fs
1024fs
256fs
256fs
512fs
256fs
128fs
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
256fs
128fs
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
256fs
512fs
1024fs
256fs
256fs
512fs
256fs
128fs
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
256fs
128fs
“-”: Not available
019000890-E-01
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[AK5704]
5.3. PLL Reference Source: BCLK [TDM Mode] (PMPLL bit = “1”, MSN bit = “0”, PLS bit = “1”, TDM[1:0]
bits = “01”, “10”, “11”)
Table 15. PLL Frequency Setting Example (PLL reference source: BCLK [TDM Mode])
fs
[kHz]
8
12
16
24
32
48
96
192
11.025
22.05
44.1
88.2
176.4
8
12
16
24
32
48
96
11.025
22.05
44.1
88.2
8
12
16
24
32
48
11.025
22.05
44.1
Note 45.
BCLK
128fs
256fs
512fs
BCLK
[MHz]
1.024
1.536
2.048
3.072
4.096
6.144
12.288
24.576
1.4112
2.8224
5.6448
11.2896
22.5792
2.048
3.072
4.096
6.144
8.192
12.288
24.576
2.8224
5.6448
11.2896
22.5792
4.096
6.144
8.192
12.288
16.384
24.576
5.6448
11.2896
22.5792
TDM
[1:0]
bits
01
10
11
PLD
[15:0]
bits
PLM
[15:0]
bits
FS
[3:0]
bits
0001H
0003H
0003H
0007H
0007H
000FH
001FH
003FH
0003H
0007H
000FH
001FH
003FH
0003H
0007H
0007H
000FH
000FH
001FH
003FH
0007H
000FH
001FH
003FH
0007H
000FH
000FH
001FH
001FH
003FH
000FH
001FH
003FH
0077H
009FH
0077H
009FH
0077H
009FH
009FH
009FH
009FH
009FH
009FH
009FH
009FH
0077H
009FH
0077H
009FH
0077H
009FH
009FH
009FH
009FH
009FH
009FH
0077H
009FH
0077H
009FH
0077H
009FH
009FH
009FH
009FH
0000
0010
0100
0110
1000
1010
1101
1111
0001
0101
1001
1100
1110
0000
0010
0100
0110
1000
1010
1101
0001
0101
1001
1100
0000
0010
0100
0110
1000
1010
0001
0101
1001
MCKO
CM[1:0] bits CM[1:0] bits CM[1:0] bits CM[1:0] bits
= “00”
= “01”
= “10”
= “11”
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
256fs
512fs
1024fs
256fs
256fs
512fs
256fs
128fs
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
256fs
128fs
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
256fs
512fs
1024fs
256fs
256fs
512fs
256fs
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
256fs
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
256fs
512fs
1024fs
256fs
256fs
512fs
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
-
“-”: Not available
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[AK5704]
9.5. Audio Interface Format
Audio interface formats are selectable with the MSN, TDM[1:0] and DIF[1:0] bits. In all modes the serial
data format is MSB first, 2’s complement. Audio interface formats can be used in both master and slave
modes. In master mode (MSN bit = “1”), the SDTO1/2 pins are clocked out on the falling edge (rising edge
when BCKP bit = “1”) of BCLK. Normal output in slave mode (TDM[1:0] bits = “00”, DIF[1:0] bits = “00”,
“01”, MSN bit = “0”), the SDTO1/2 pins are clocked out on the falling edge (rising edge when BCKP bit =
“1”) of BCLK. In other conditions (PCM and TDM Mode), the data is clocked out on the prior rising edge
(falling edge when BCKP bit = “1”) of BCLK to compensate for some delay that renders the edge of data
transition near BCLK falling edge. The TDMIN pin and SDTO2 pin are shared. SDTO2E bit is set to “1” to
enable the SDTO2 pin. BCLK edge polarity can be set by BCKP bit. SDTO data length is set by DLC[1:0]
bits.
Table 16. Audio Interface Format (Stereo Mode)
Mode
0
1
2
3
4
5
6
7
MSN bit
0
0
0
0
1
1
1
1
Mode
8
9
10
11
12
13
14
15
MSN bit
0
0
0
0
1
1
1
1
TDM[1:0] bits
00
00
00
00
00
00
00
00
DIF[1:0] bits
00
01
10
11
00
01
10
11
SDTO1/2 pin
I2S compatible
MSB justified
PCM Short Frame
PCM Long Frame
I2S compatible
MSB justified
PCM Short Frame
PCM Long Frame
BCLK
32fs
32fs
32fs
32fs
32fs or 64fs
32fs or 64fs
32fs or 64fs
32fs or 64fs
I
I
I
I
O
O
O
O
Figure
Figure 18
Figure 19
Figure 20
Figure 21
Figure 18
Figure 19
Figure 20
Figure 21
(default)
Table 17. Audio Interface Format (TDM128 Mode, N/A: Not available)
TDM[1:0] bits
01
01
01
01
01
01
01
01
DIF[1:0] bits
00
01
10
11
00
01
10
11
SDTO1 pin
I2S compatible
MSB justified
N/A
N/A
I2S compatible
MSB justified
N/A
N/A
BCLK
128fs
128fs
128fs
128fs
-
I
I
O
O
-
Figure
Figure 22
Figure 23
Figure 22
Figure 23
-
Note 46. MCKI frequency needs more than twice BCLK frequency in case of EXT Master Mode.
Table 18. Audio Interface Format (TDM256 Mode, N/A: Not available)
Mode
16
17
18
19
20
21
22
23
MSN bit
0
0
0
0
1
1
1
1
TDM[1:0] bits
10
10
10
10
10
10
10
10
DIF[1:0] bits
00
01
10
11
00
01
10
11
SDTO1 pin
I2S compatible
MSB justified
N/A
N/A
I2S compatible
MSB justified
N/A
N/A
BCLK
256fs
256fs
256fs
256fs
-
I
I
O
O
-
Figure
Figure 24
Figure 25
Figure 24
Figure 25
-
Note 47. MCKI frequency needs more than twice BCLK frequency in case of EXT Master Mode.
019000890-E-01
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[AK5704]
Table 19. Audio Interface Format (TDM512 Mode, N/A: Not available)
Mode
24
25
26
27
28
29
30
31
MSN bit
0
0
0
0
1
1
1
1
TDM[1:0] bits
11
11
11
11
11
11
11
11
DIF[1:0] bits
00
01
10
11
00
01
10
11
SDTO1 pin
I2S compatible
MSB justified
N/A
N/A
I2S compatible
MSB justified
N/A
N/A
BCLK
512fs
512fs
512fs
512fs
-
I
I
O
O
-
Figure
Figure 26
Figure 27
Figure 26
Figure 27
-
Note 48. MCKI frequency needs more than twice BCLK frequency in case of EXT Master Mode.
BCKP bit
0
1
Table 20. BCLK Edge
BCLK edge referenced to LRCK edge
Falling Edge
Rising Edge
(default)
Table 21. Data Length Setting (N/A: Not available)
DLC[1:0] bits
SDTO Data Length
00
24-bit Linear
(default)
01
16-bit Linear
10
32-bit Linear
11
N/A
Note 49. In TDM mode, the data width of 1SLOT is set 32-bits when SDTO data length is selected
24-bits or 32-bits. In TDM mode, the data width of 1SLOT is set 16-bits when SDTO data
length is selected 16-bits.
019000890-E-01
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[AK5704]
LRCK
BICK (32fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1/2
(16-bit)
Ach Data (MSB First)
Bch Data (MSB First)
Next Ach Data
Next Bch Data
Ach Data (MSB First)
“L”
Bch Data (MSB First)
“L”
LRCK
BICK (64fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1/2
(16-bit) “L”
(24-bit) “L”
(32-bit)
“L”
Ach Data (MSB First)
Ach Data (MSB First)
“L”
Bch Data (MSB First)
Bch Data (MSB First)
Figure 18. Mode 0/4 Timing (Normal mode, I2S Compatible)
LRCK
BICK (32fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1/2
(16-bit)
Ach Data (MSB First)
Bch Data (MSB First)
Next Ach Data
Next Bch Data
Ach Data (MSB First)
“L”
Bch Data (MSB First)
“L”
LRCK
BICK (64fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1/2
(16-bit) “L”
(24-bit) “L”
(32-bit)
Ach Data (MSB First)
“L”
Ach Data (MSB First)
Bch Data (MSB First)
“L”
Bch Data (MSB First)
Figure 19. Mode 1/5 Timing (Normal mode, MSB Justified)
019000890-E-01
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[AK5704]
LRCK
BICK (32fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1/2
(16-bit)
Ach Data (MSB First)
Bch Data (MSB First)
Next Ach Data
Next Bch Data
Ach Data (MSB First)
“L”
Bch Data (MSB First)
“L”
LRCK
BICK (64fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1/2
(16-bit) “L”
(24-bit) “L”
(32-bit)
Ach Data (MSB First)
“L”
“L”
Bch Data (MSB First)
Ach Data (MSB First)
Bch Data (MSB First)
Figure 20. Mode 2/6 Timing (Normal mode, PCM Short Frame)
LRCK(Slave)
“H” or “L”
“H” or “L”
LRCK(Master)
BICK (32fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1/2
(16-bit)
Ach Data (MSB First)
Bch Data (MSB First)
Next Ach Data
Next Bch Data
“H” or “L”
LRCK(Slave)
LRCK(Master)
BICK (64fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1/2
(16-bit) “L”
(24-bit) “L”
(32-bit)
Ach Data (MSB First)
“L”
Bch Data (MSB First)
Ach Data (MSB First)
Bch Data (MSB First)
Ach Data (MSB First)
“L”
Bch Data (MSB First)
Figure 21. Mode 3/7 Timing (Normal mode, PCM Long Frame)
019000890-E-01
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[AK5704]
128 BCLK
“H” or “L”
LRCK(Slave)
LRCK(Master)
BICK (128fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1 #2
(16-bit)
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC1
Bch
#2 Data
TDMIN
(SDTO1 #1)
“L”
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
Next
Data
#1 Data
ADC2
Ach
ADC2
Bch
Next
Data
“L”
#1 Data
SDTO1
(24-bit)
“L”
ADC1
Ach
“L”
ADC1
Bch
ADC1
Ach
(32-bit)
“L”
ADC1
Bch
ADC2
Ach
“L”
ADC2
Bch
ADC2
Ach
“L”
ADC2
Bch
Next
Data
Next
Data
Figure 22. Mode 8/12 Timing (TDM128 mode, I2S Compatible)
128 BCLK
“H” or “L”
LRCK(Slave)
LRCK(Master)
BICK (128fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1 #2
(16-bit)
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC1
Bch
#2 Data
TDMIN
(SDTO1 #1)
“L”
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
#1 Data
ADC2
Ach
ADC2
Bch
Next
Data
“L”
#1 Data
SDTO1
(24-bit)
(32-bit)
“L”
ADC1
Ach
ADC1
Ach
“L”
Next
Data
ADC1
Bch
ADC1
Bch
“L”
ADC2
Ach
ADC2
Ach
“L”
ADC2
Bch
“L”
Next
Data
Next
Data
ADC2
Bch
Figure 23. Mode 9/13 Timing (TDM128 mode, MSB Justified)
019000890-E-01
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[AK5704]
256 BCLK
“H” or “L”
LRCK(Slave)
LRCK(Master)
BICK (256fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1 #4
(16-bit)
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC1
Bch
#4 Data
TDMIN #4
(SDTO1 #3)
“L”
ADC1
Ach
ADC1
Bch
“L”
ADC1
Ach
“L”
ADC2
Bch
ADC1
Ach
ADC1
Bch
#3 Data
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC1
Bch
ADC1
Bch
“L”
ADC2
Ach
ADC2
Ach
ADC2
Bch
ADC2
Bch
“L”
ADC1
Ach
“L”
ADC1
Bch
“L”
ADC1
Bch
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
Next
Data
#1 Data
ADC2
Ach
ADC2
Bch
“L”
ADC1
Ach
“L”
ADC1
Bch
Next
Data
“L”
ADC2
Ach
“L”
#2 Data
TDMIN #2
(SDTO1 #1)
ADC1
Ach
#1 Data
ADC2
Bch
“L”
ADC2
Ach
#2 Data
#2 Data
#3 Data
SDTO1 #2
(24-bit)
ADC2
Ach
ADC2
Bch
“L”
“L”
Next
Data
#1 Data
ADC2
Ach
“L”
ADC2
Bch
Next
Data
“L”
#1 Data
SDTO1 #2
(32-bit)
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC1
Bch
#2 Data
TDMIN #2
(SDTO1 #1)
“L”
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
Next
Data
#1 Data
ADC2
Ach
ADC2
Bch
Next
Data
“L”
#1 Data
Figure 24. Mode 16/20 Timing (TDM256 mode, I2S Compatible)
256 BCLK
“H” or “L”
LRCK(Slave)
LRCK(Master)
BICK (256fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1 #4
(16-bit)
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC1
Bch
#4 Data
TDMIN #4
(SDTO1 #3)
“L”
ADC1
Ach
ADC1
Bch
“L”
ADC1
Ach
“L”
ADC2
Bch
ADC1
Ach
ADC1
Bch
#3 Data
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC1
Bch
#3 Data
SDTO1 #2
(24-bit)
ADC2
Ach
“L”
ADC2
Ach
ADC2
Ach
ADC2
Bch
“L”
ADC1
Ach
“L”
ADC1
Bch
“L”
ADC1
Bch
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
Next
Data
#1 Data
ADC2
Ach
ADC2
Bch
“L”
ADC1
Ach
“L”
ADC1
Bch
#2 Data
TDMIN #2
(SDTO1 #1)
ADC1
Ach
Next
Data
“L”
#1 Data
ADC2
Bch
“L”
ADC2
Bch
#2 Data
#2 Data
ADC1
Bch
ADC2
Ach
ADC2
Ach
“L”
“L”
ADC2
Bch
“L”
Next
Data
#1 Data
ADC2
Ach
“L”
ADC2
Bch
Next
Data
“L”
#1 Data
SDTO1 #2
(32-bit)
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
#2 Data
TDMIN #2
(SDTO1 #1)
“L”
ADC1
Ach
ADC1
Bch
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
Next
Data
#1 Data
ADC2
Ach
ADC2
Bch
“L”
Next
Data
#1 Data
Figure 25. Mode 17/21 Timing (TDM256 mode, MSB Justified)
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[AK5704]
512 BCLK
“H” or “L”
LRCK(Slave)
LRCK(Master)
BICK (512fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1 #4
(16-bit)
TDMIN #4
(SDTO1 #3)
“L”
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
#4 Data
“L”
ADC1
Ach
ADC1
Bch
ADC2
Ach
“L”
ADC1
Ach
ADC2
Bch
ADC2
Bch
ADC1
Ach
ADC1
Ach
ADC1
Bch
“L”
ADC2
Ach
“L”
ADC1
Bch
ADC2
Ach
ADC2
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC1
Bch
ADC2
Ach
“L”
ADC1
Bch
“L”
“L”
ADC1
Ach
ADC1
Bch
ADC2
Bch
“L”
ADC1
Ach
“L”
ADC1
Ach
“L”
ADC2
Ach
“L”
ADC2
Bch
“L”
ADC1
Ach
“L”
ADC1
Bch
“L”
#3 Data
ADC2
Ach
“L”
ADC2
Bch
“L”
ADC2
Bch
ADC1
Ach
“L”
ADC1
Bch
“L”
ADC2
Ach
“L”
ADC2
Bch
“L”
ADC1
Ach
“L”
ADC1
Bch
Next
Data
“L”
Next
Data
ADC1
Ach
ADC1
Bch
ADC2
Bch
ADC1
Ach
ADC2
Ach
ADC1
Bch
#3 Data
ADC2
Bch
“L”
ADC2
Bch
“L”
ADC1
Ach
“L”
ADC1
Bch
“L”
ADC2
Ach
“L”
ADC2
Ach
“L”
ADC2
Bch
“L”
Next
Data
#1 Data
“L”
ADC2
Bch
Next
Data
“L”
#1 Data
ADC2
Bch
ADC1
Ach
ADC1
Bch
#3 Data
ADC2
LAch
“L”
#2 Data
#2 Data
ADC2
Ach
ADC1
Bch
ADC2
Bch
ADC2
Bch
ADC1
Bch
#4 Data
“L”
ADC2
Ach
#1 Data
#3 Data
SDTO1 #4
(32-bit)
TDMIN #4
(SDTO1 #3)
ADC1
Ach
ADC1
Bch
#1 Data
#4 Data
TDMIN #4
(SDTO1 #3)
ADC1
Ach
#2 Data
#2 Data
ADC1
Bch
“L”
ADC2
Ach
#3 Data
#3 Data
SDTO1 #4
(24-bit)
ADC1
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC1
Bch
#2 Data
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC1
Bch
#2 Data
ADC2
Ach
ADC2
Bch
Next
Data
#1 Data
ADC2
Ach
ADC2
Bch
Next
Data
“L”
#1 Data
Figure 26. Mode24/28 Timing (TDM512 mode, I2S Compatible)
512 BCLK
“H” or “L”
LRCK(Slave)
LRCK(Master)
BICK (512fs)
BCKP bit = “0”
BCKP bit = “1”
SDTO1 #4
(16-bit)
TDMIN #4
(SDTO1 #3)
“L”
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
#4 Data
“L”
ADC1
Ach
ADC1
Bch
ADC2
Ach
“L”
ADC1
Ach
“L”
ADC2
Ach
ADC2
Bch
ADC1
Ach
#3 Data
ADC2
Bch
ADC1
Ach
#3 Data
SDTO1 #4
(24-bit)
ADC1
Bch
ADC1
Bch
“L”
ADC2
Ach
“L”
ADC2
Ach
ADC2
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
ADC2
Bch
ADC1
Bch
ADC2
Ach
“L”
“L”
ADC1
Bch
“L”
ADC2
Ach
ADC1
Ach
ADC1
Bch
ADC2
Ach
“L”
ADC1
Ach
ADC1
Ach
ADC1
Bch
ADC2
Ach
#3 Data
ADC2
Bch
ADC2
Bch
“L”
ADC1
Bch
“L”
ADC2
Ach
“L”
ADC2
Bch
“L”
ADC1
Ach
“L”
ADC1
Bch
“L”
#3 Data
“L”
ADC2
Bch
“L”
ADC1
Ach
ADC2
Bch
“L”
ADC1
Bch
“L”
ADC2
Ach
“L”
ADC2
Bch
“L”
ADC1
Ach
Next
Data
“L”
Next
Data
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC2
Ach
“L”
ADC2
Bch
“L”
ADC1
Ach
“L”
“L”
ADC1
Bch
“L”
ADC2
Ach
ADC1
Bch
“L”
ADC2
Ach
“L”
ADC2
Bch
“L”
Next
Data
#1 Data
“L”
ADC2
Bch
Next
Data
“L”
#1 Data
ADC2
Bch
ADC1
Ach
#3 Data
ADC2
Bch
“L”
#2 Data
#2 Data
#4 Data
“L”
ADC2
Ach
#1 Data
#3 Data
SDTO1 #4
(32-bit)
TDMIN #4
(SDTO1 #3)
ADC1
Ach
ADC1
Bch
#1 Data
#4 Data
TDMIN #4
(SDTO1 #3)
ADC1
Ach
#2 Data
#2 Data
ADC1
Bch
ADC1
Bch
ADC1
Bch
ADC2
Ach
ADC2
Bch
ADC1
Ach
#2 Data
ADC2
Bch
#2 Data
ADC1
Ach
ADC1
Bch
ADC2
Ach
ADC1
Bch
ADC2
Ach
ADC2
Bch
Next
Data
#1 Data
ADC2
Bch
“L”
Next
Data
#1 Data
Figure 27. Mode 25/29 Timing (TDM512 mode, MSB Justified)
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[AK5704]
Cascade Connection in TDM Mode
The AK5704 supports a cascade connection of four devices in TDM modes. Figure 28 shows a
connection example. All A/D converted data of connected AK5704’s is output from the SDTO1 pin of the
last AK5704 via cascade connection.
When the data length is 24-bits (DLC[1:0] bits = “00”) or 32-bits (DLC[1:0] bits = “10”), the AK5704
supports up to 4ch outputs in TDM128 mode, 8ch outputs in TDM256 mode and 16ch outputs in TDM512
mode (Figure 28).
When DLC[1:0] bits = “01”(16-bits), the AK5704 supports up to 8ch outputs in TDM128 mode, 16ch
outputs in TDM256 mode and 16ch outputs in TDM512 mode.
AK5704 #1
512fs
MCLK
~48kHz
LRCK
512fs
BICK
TDMIN
SDTO1
GND
Slave mode
AK5704 #1
256fs
MCLK
~96kHz
LRCK
256fs
BICK
AK5704 #2
TDMIN
MCLK
GND
SDTO1
BICK
Slave mode
AK5704 #3
TDMIN
LRCK
BICK
SDTO1
Slave mode
AK5704 #2
MCLK
TDMIN
LRCK
MCLK
8ch TDM
BICK
SDTO1
TDMIN
LRCK
SDTO1
Slave mode
Slave mode
AK5704 #4
TDM256
MCLK
TDMIN
LRCK
BICK
16ch TDM
SDTO1
Slave mode
TDM512
Figure 28. Cascade Connection
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[AK5704]
9.6. Synchronization with audio system (SYNCDET)
The AK5704 has a SYNCDET circuit for phase synchronization of the data output since it is assumed that
multiple AK5704’s will be used in TDM mode.
When the clock frequency is changed during operation, phase mismatch may occur between external
LRCK and data transferring clock that has the same frequency as the internal LRCK generated from
external LRCK. The SYNCDET circuit resets the internal counter and adjusts the phase between LRCK
and FsCLK automatically. Therefore, there’s a possibility that pop noise occurs.
To prevent pop noise, the following methods are recommended:
(1) Clock mode must be changed when PMAD1A/B = PMAD2A/B = PMDM1A/B = PMDM2A/B =
PMPFIL1 = PMPFIL2 bits = “0”.
(2) Stable clock must be supplied during operation (PDN pin = “H”).
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[AK5704]
9.7. MIC/LINE Input
The AK5704 supports both single-ended (Pseudo-Differential) and full-differential modes for analog
input. When MDIF1A, MDIF1B, MDIF2A, MDIF2B bits = “0” (default), each input pin is in single-ended
mode. When MDIF1A, MDIF1B, MDIF2A, MDIF2B bits = “1”, each input pin is in full-differential mode. In
single-ended mode, the signal should be input to the AINxA/B+ pins and the AINxA/B- pins should be
connected to the ground via a capacitor in series (Figure 29). All input pins are in single-ended mode
(MDIF1A = MDIF1B = MDIF2A = MDIF2B bits = “0”) and AINCOM bit = “1”, only one capacitor is
connected to the ground. AINxA/B- pins should be shorted all and connected to the ground via a capacitor
in series (Figure 31).
MDIF1A bit MDIF1B bit
0
0
0
1
1
0
1
1
Table 22. AIN1 Input Select
AIN1A
AIN1B
AIN1A+ pin (Single-ended)
AIN1B+ pin (Single-ended)
AIN1A+ pin (Single-ended)
AIN1B+/- pins (Full-differential)
AIN1A+/- pins (Full-differential)
AIN1B+ pin (Single-ended)
AIN1A+/- pins (Full-differential) AIN1B+/- pins (Full-differential)
MDIF2A bit MDIF2B bit
0
0
0
1
1
0
1
1
Table 23. AIN2 Input Select
AIN2A
AIN2B
AIN2A+ pin (Single-ended)
AIN2B+ pin (Single-ended)
AIN2A+ pin (Single-ended)
AIN2B+/- pins (Full-differential)
AIN2A+/- pins (Full-differential)
AIN2B+ pin (Single-ended)
AIN2A+/- pins (Full-differential) AIN2B+/- pins (Full-differential)
(default)
(default)
AK5704
MPWR1 pin
2.2k
AIN1A+ pin
MIC-Amp 1
AIN1A- pin
VSS1
Figure 29. Connection Example for Single-ended Microphone Input (AINCOM bit = “0”)
AK5704
MPWR1 pin
1k
MIC-Amp 1
AIN1A+ pin
AIN1A- pin
1k
VSS1
Figure 30. Connection Example for Full-differential Microphone Input
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[AK5704]
AK5704
MPWR1 pin
2.2k
MIC-Amp 1
AIN1A+ pin
AIN1A- pin
VSS1
2.2k
MIC-Amp 1
AIN1B+ pin
AIN1B- pin
VSS1
MPWR2 pin
2.2k
MIC-Amp 2
AIN2A+ pin
AIN2A- pin
VSS1
2.2k
MIC-Amp 2
AIN2B+ pin
AIN2B- pin
VSS1
VSS1
Figure 31. Connection Example for Single-ended Microphone Input (AINCOM bit = “1”)
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[AK5704]
9.8. Microphone Amplifier Gain
The AK5704 has gain amplifiers for microphone input. The gain of four microphone amplifiers can be
independently selected by MG1A[3:0], MG1B[3:0], MG2A[3:0] and MG2B[3:0] bits. The volume is
changed immediately by setting these bits.
AK5704
MIC-Amp 1 Ach
AIN1A+ pin
AIN1A- pin
ADC1 Ach
MG1A[3:0] bits
MIC-Amp 1 Bch
AIN1B+ pin
AIN1B- pin
ADC1 Bch
MG1B[3:0] bits
MIC-Amp 2 Ach
AIN2A+ pin
AIN2A- pin
ADC2 Ach
MG2A[3:0] bits
MIC-Amp 2 Bch
AIN2B+ pin
AIN2B- pin
ADC2 Bch
MG2B[3:0] bits
Figure 32. MIC Input Volume Setting
MG1A3 bit
MG1B3 bit
MG2A3 bit
MG2B3 bit
0
0
0
0
0
0
0
0
1
1
1
Table 24. MIC Amplifier 1/2 Gain (N/A: Not available)
MG1A2 bit
MG1A1 bit
MG1A0 bit
MG1B2 bit
MG1B1 bit
MG1B0 bit
Gain
MG2A2 bit
MG2A1 bit
MG2A0 bit
MG2B2 bit
MG2B1 bit
MG2B0 bit
0
0
0
0 dB
0
0
1
+3 dB
0
1
0
+6 dB
0
1
1
+9 dB
1
0
0
+12 dB
1
0
1
+15 dB
1
1
0
+18 dB
1
1
1
+21 dB
0
0
0
+24 dB
0
0
1
+27 dB
0
1
0
+30 dB
Others
N/A
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[AK5704]
9.9. Microphone Power
The AK5704 has two microphone power supplies. They can be powered up at the same time. Output
voltage of MPWR1/2 are common setting by MICL[1:0] bits. PMMPx bit controls output status. When
PMMPx bit is “1”, microphone power is output. When PMMPx bit is “0”, the MPWRx pin becomes
power-down state (Hi-Z). The load resistance is minimum 650Ω for each MPWR1/2 pin. Any capacitor
must not be connected directly to the MPWR1/2 pins. The AK5704 has a MIC power direct mode for the
MPWR1/2 pins. The AVDD voltage is directly output from the MPWR1/2 pin via the internal switch (ON
resistance: typ. 37Ω, max. 62Ω) by setting MICL[1:0] bits = “11”. In MIC power direct mode (MICL[1:0] bits
= “11”), PMMP1/2 bit controls ON/OFF of the internal switch. This power-up timer will not work in MIC
power direct mode.
Set MICL[1:0] bits before power-on of the corresponding MPWR pin (there is no time limitation). When a
MPWR pin is ON, the setting of corresponding MICL[1:0] bits should not be changed.
When using a microphone power, the power-up sequence below should be followed to reduce DC offset
(pop noise).
1. MIC Power ON
2. MIC Amplifier/ADC ON
Table 25. MIC Power Output Voltage
MICL[1:0] bits
MPWR1/2 Output Level (Typ.)
00
2.8 V
(default)
01
2.5 V
10
1.8 V
11
Direct Mode (AVDD)
Note 50. When AVDD=1.7~1.9V, the setting of MICL[1:0] bits = "11" is only available.
Table 26. MIC Power Output Status
PMMP1/2 bits
MPWR1/2 pins
0
Hi-z
(default)
1
Output
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[AK5704]
9.10.
MIC Input Start-Up Time
The microphone input circuit can be powered-up/down by PMAIN1A/B and PMAIN2A/B bits. The
initialization cycle starts by setting PMAINxA/B bit to “1”. An acceleration circuit, which shortens the
charging time of an input capacitor, starts operation when the microphone input circuit is powered up. The
initialization cycle can be set by AIRST[2:0] bits (Table 27) and this setting is common for all channels.
Although it depends on the condition of microphone characteristic and external circuit, the initialization
cycle should be set to longer than 13.7 ms when a capacitor for AC-coupling is 1 µF ± 50%. The
initialization cycle should be set to longer than 6.8 ms when a capacitor for AC-coupling is 0.47 µF ± 50%.
AIRST[2:0] bits
000
001
010
011
100
101
110
111
9.11.
Table 27. AINxA/B Start-Up Time (N/A: Not available)
Start-Up Time
Cycle
fs = 16 kHz fs = 48 kHz fs = 96 kHz fs = 192 kHz
656/fs
41.0ms
13.7ms
6.8ms
3.4ms
164/fs
10.3ms
3.4ms
1.7ms
0.9ms
1312/fs
82.0ms
27.3ms
13.7ms
6.8ms
328/fs
20.5ms
6.8ms
3.4ms
1.7ms
2624/fs
164ms
54.7ms
27.3ms
13.7ms
128/fs
8.0ms
N/A
256/fs
16.0ms
N/A
512/fs
32.0ms
N/A
(default)
ADC1/2 Initialization Cycle
The ADC1/2 enters an initialization cycle after PMAD1A, PMAD1B, PMAD2A or PMAD2B bit is changed
from “0” to “1” when all of these bits are “0”. The initialization cycle time is set by ADRST[2:0] bits (Table
28). During the initialization cycle, the ADC1/2 digital data output of both channels are forced to “0” in 2’s
complement. The ADC output reflects the analog input signal after the initialization cycle is complete.
When using a digital microphone, the initialization cycle is the same as ADC’s.
Note 51. The initial data of ADC1/2 has offset data that depends on the condition of the microphone and
the cut-off frequency of HPF. If this offset is not small, make initialization cycle longer or do not
use the initial data of ADC1/2.
Table 28. ADC1/2 Initialization Cycle (N/A: Not available)
Initialization Cycle
ADRST[2:0] bits
Cycle
fs = 16 kHz fs = 48 kHz fs = 96 kHz fs = 192 kHz
000
1059/fs
66.2ms
22.1ms
11.0ms
5.5ms
(default)
001
267/fs
16.7ms
5.6ms
2.8ms
1.4ms
010
2115/fs
132.2ms
44.1ms
22.0ms
11.0ms
011
531/fs
33.2ms
11.1ms
5.5ms
2.8ms
100
4230/fs
528.8ms
88.1ms
44.1ms
22.0ms
101
8/fs
0.5ms
N/A
110
16/fs
1.0ms
N/A
111
32/fs
2.0ms
N/A
Note 52. When ADRST[2:0] bits = “101” and “110”, the initial data includes unstable data. The initial
data of ADC1/2 (the length of Group Delay of ADC Digital Filter) should not be used.
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[AK5704]
9.12.
Mono/Stereo Mode
MONON bit and PMAD1A/B bits set mono/stereo operation of the ADC1. MONON bit and PMAD2A/B bits
set mono/stereo operation of the ADC2. When changing ADC operation and analog/digital microphone,
PMAD1A/B (PMAD2A/B) and PMDM1A/B (PMDM2A/B) bits must be set “0” at first. When DMIC1 bit is =
“0”, PMDM1A/B bit settings are ignored. When DMIC2 bit = “0”, PMDM2A/B bits setting are ignored.
When DMIC1 bit is = “1”, PMAD1A/B bit settings are ignored. When DMIC2 bit = “1”, PMAD2A/B bits
setting are ignored.
Table 29. ADC1 Mono/Stereo Select (Analog Microphone) (x: Do not care)
MONON bit PMAD1A bit PMAD1B bit
ADC1 Ach data
ADC1 Bch data
x
0
0
“0” data
“0” data
(default)
0
0
1
“0” data
AIN1B Input Signal
0
1
0
AIN1A Input Signal
“0” data
1
0
1
AIN1B Input Signal AIN1B Input Signal
1
1
0
AIN1A Input Signal AIN1A Input Signal
x
1
1
AIN1A Input Signal AIN1B Input Signal
Table 30. ADC2 Mono/Stereo Select (Analog Microphone) (x: Do not care)
MONON bit PMAD2A bit PMAD2B bit
ADC2 Ach data
ADC2 Bch data
x
0
0
“0” data
“0” data
(default)
0
0
1
“0” data
AIN2B Input Signal
0
1
0
AIN2A Input Signal
“0” data
1
0
1
AIN2B Input Signal AIN2B Input Signal
1
1
0
AIN2A Input Signal AIN2A Input Signal
x
1
1
AIN2A Input Signal AIN2B Input Signal
MONON bit
x
0
0
1
1
x
MONON bit
x
0
0
1
1
x
Table 31. DMIC1 Mono/Stereo Select (Digital Microphone) (x: Do not care)
ADC1 Ach data
ADC1 Bch data
PMDM1A bit PMDM1B bit
0
0
“0” data
“0” data
0
1
“0” data
DMIC1 Bch Input Signal
1
0
“0” data
DMIC1 Ach Input Signal
0
1
DMIC1 Bch Input Signal DMIC1 Bch Input Signal
1
0
DMIC1 Ach Input Signal DMIC1 Ach Input Signal
1
1
DMIC1 Ach Input Signal DMIC1 Bch Input Signal
Table 32. DMIC2 Mono/Stereo Select (Digital Microphone) (x: Do not care)
ADC2 Ach data
ADC2 Bch data
PMDM2B bit
0
0
“0” data
“0” data
0
1
“0” data
DMIC2 Bch Input Signal
1
0
“0” data
DMIC2 Ach Input Signal
0
1
DMIC2 Bch Input Signal DMIC2 Bch Input Signal
1
0
DMIC2 Ach Input Signal DMIC2 Ach Input Signal
1
1
DMIC2 Ach Input Signal DMIC2 Bch Input Signal
(default)
PMDM2A bit
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[AK5704]
9.13.
Digital Microphone
1. Connection to Digital Microphone
When DMIC1 bit is set to “1”, the AIN1A+ pin and the AIN1B+ pin become the DMDAT1 (digital
microphone data input) pin and the DMCLK1 (digital microphone clock supply) pin, respectively. When
DMIC2 bit is set to “1”, the AIN2A+ pin and the AIN2B+ pin become the DMDAT2 (digital microphone data
input) pin and the DMCLK2 (digital microphone clock supply) pin, respectively. DMCLK2 is the same
clock (64fs) as DMCLK1.
The same power supply as AVDD must be provided to the digital microphone. The Figure 33 and Figure
34 show stereo/mono connection examples. By dividing the master clock to 64fs with divider, the
DMCLK1 (DMCLK2) signal is output from the AK5704, and the digital microphone outputs 1bit data,
which is generated by Modulator, to DMDAT1 (DMDAT2). PMDM1A/B (PMDM2A/B) bits control power
up/down of the digital block (Decimation Filter and HPF). PMAD1A/B (PMDM2A/B) bits settings do not
affect the digital microphone power management. The DCLKE1 (DCLKE2) bit controls ON/OFF of the
output clock from the DMCLK1 (DMCLK2) pin. When the AK5704 is power-up (PDN pin = “H”), external
pull-down resistor (R) should be connected to the DMDAT1 (DMDAT2) pin to avoid floating state. Note
that when using the digital microphone it does not support quad speed mode (fs ≥ 128 kHz).
AVDD
VDD
AMP
AK5704
DMCLK1
(64fs)
CODEC Master Clock
Divider
100 k
Modulator
DMDAT1
Ach
Decimation
Filter
HPF
ADC1 Output Data
R
VDD
AMP
Modulator
Bch
Figure 33. Connection Example of Stereo Digital Microphone (DMIC1 bit = “1”)
AVDD
AK5704
VDD
AMP
DMCLK1
(64fs)
100 k
Modulator
DMDAT1
Ach
CODEC Master Clock
Divider
Decimation
Filter
HPF
ADC1 Output Data
R
Figure 34. Connection Example of Monaural Digital Microphone (DMIC1 bit = “1”)
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[AK5704]
2. Interface
The input data channel of the DMDAT1 (DMDAT2) pin is set by DCLKP1 (DCLKP2) bit. When DCLKP1
(DCLKP2) bit = “0”, Ach data is input to the Decimation Filter if DMCLK1 (DMCLK2) signal = “L”, Bch data
is input if DMCLK1 (DMCLK2) signal = “H”. When DCLKP1 (DCLKP2) bit = “1”, Bch data is input to the
Decimation Filter if DMCLK1 (DMCLK2) signal = “L”, Ach data is input if DMCLK1 (DMCLK2) signal = “H”.
The DMCLK1 (DMCLK2) pin outputs “L” when DCLKE1 (DCLKE2) bit = “0”. DMCLK supports only 64fs
and outputs same frequency. The DMCLK1 (DMCLK2) pin outputs 64fs clock when DCLKE1 (DCLKE2)
bit = “1”. In this case, necessary clocks must be supplied to the AK5704 for ADC operation. The output
data through “the Decimation and Digital Filters” is the negative full-scale with 0% 1’s density of 1bit
output data and positive full-scale with the 100% 1’s density of 1bit output data.
Table 33. Digital MIC Data Input/Output Timing
DCLKP1/2 bit
DMCLK1/2 pin= “H”
DMCLK1/2 pin= “L”
0
B ch
A ch
1
A ch
B ch
(default)
DMCLK1/2 (64fs)
DMDAT1/2 (Ach)
Valid
Data
Valid
Data
Valid
Data
DMDAT1/2 (Bch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 35. Digital MIC Data Input/Output Timing (DCLKP1/2 bit = “0”)
DMCLK1/2 (64fs)
DMDAT1/2 (Ach)
DMDAT1/2 (Bch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 36. Digital MIC Data Input/Output Timing (DCLKP1/2 bit = “1”)
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[AK5704]
9.14.
Digital Block
The digital block consists of the blocks shown in Figure 37. When PMPFIL1 bit = “1”, the programmable
filter 1 consisting of MIX1, HPF1, LPF1 and ALC1 is powered up. When PMPFIL1 and PMPFIL2 bits =
“1”, the programmable filter 2 consisting of MIX2, HPF2, LPF2 and ALC2 is powered up. When PFTHR1,
PFTHR2 bit = “1”, the MIX1/2 output data bypasses HPF1/2 and LPF1/2 and is input to ALC1/2. When
PFSDO1, PFSDO2 bit = “0”, the output data of MIC sensitivity Adjustment bypasses programmable filter
1/2 and outputs to SDTO1/2.
PMAD1A/B bit or
PMDM1A/B bit
PMAD2A/B bit or
PMDM2A/B bit
ADC2
ADC1
DLY1A/B[5:0] bits
DLY2A/B[5:0] bits
(Delay)
1st Order
HPFAD1N bit
HPFC1 bit
HPFAD2N bit
HPFC2 bit
HPF
MIC Sensitivity
Adjustment
MS1A/B[7:0] bits
MS2A/B[7:0] bits
PMPFIL1 bit
(Delay)
1st Order
HPF
MIC Sensitivity
Adjustment
PMPFIL2 bit
MIX1
MIX1 bit
2nd Order
HPF11/2 bits
HPF21/2 bits
HPF1
2nd Order
LPF11/2 bits
LPF21/2 bits
LPF1
“0”
PFTHR1 bit
“1”
“0”
“1”
VADSEL bit
ALC1
ALC1 bit
MIX2
MIX2 bit
HPF2
2nd Order
LPF2
“0”
PFTHR2 bit
ALC2 bit
ALC4 bit
(Volume)
2nd Order
“1”
ALC2
(Volume)
PMVAD bit
“0”
“1”
VADOE bit
“0”
VADO
(VDLY)
VAD
“1”
“1”
PFSDO1 bit
SDTO1
(1)
(2)
(3)
(4)
(5)
(6)
(7)
“0”
PFSDO2 bit
WINTN pin
SDTO2
ADC1/2: Includes the Digital Filter (LPF) and the Programmable Phase Adjustment.
HPF: High Pass Filter for ADC.
MIC Sensitivity Adjustment: Microphone Sensitivity Adjustment.
MIX1/2: Mixer for Monaural Selection.
HPF1/2: 2nd order High Pass Filter.
LPF1/2: 2nd order Low Pass Filter.
ALC1/2(Volume): Digital Volume with ALC Function.
Figure 37. Digital Block Path Select
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[AK5704]
9.14.1. Programmable Phase Adjustment
Output data is independently delayed in state of 64/fs (1/32fs) before the Decimation Filter to adjust the
phase shift of each 4ch analog inputs into 4ch ADC. Setting resolution of delay amount is 1/64fs (1/32fs)
and setting range is from 1/64fs (1/32fs) to 64/64fs (32/32fs). Delay function of AIN1A channel, AIN1B
channel, AIN2A channel and AIN2B channel are independently controlled ON/OFF by DLY1AE bit,
DLY1BE bit, DLY2AE bit and DLY2BE bits, respectively. When DLYxxE bit = “0”, data delay is disable.
When DLYxxE bit = “1”, data delay is enable.
DLY1A[5:0] bits:
DLY1B[5:0] bits:
DLY2A[5:0] bits:
DLY2B[5:0] bits:
Setting the amount of delay for AIN1A channel.
Setting the amount of delay for AIN1B channel.
Setting the amount of delay for AIN2A channel.
Setting the amount of delay for AIN2B channel.
64fs or 32fs
Modulator
Delay
1fs
AIN1B Input
Decimation
Filter
DLY1AE bit, DLY1A5-0 bits
64fs or 32fs
Decimation
Modulator
Delay
Filter
1fs
AIN2A Input
DLY1BE bit, DLY1B5-0 bits
64fs or 32fs
Decimation
Modulator
Delay
Filter
1fs
AIN2B Input
DLY2AE bit, DLY2A5-0 bits
64fs or 32fs
Decimation
Modulator
Delay
Filter
AIN1A Input
1fs
DLY2BE bit, DLY2B5-0 bits
Figure 38. Programmable Phase Adjustment
Table 34. Programmable Phase Adjustment Setting (N/A: Not available)
Delay
DLY1A[5:0] bits
DLY1B[5:0] bits
Except
fs=176.4kHz,
DLY2A[5:0] bits
fs=176.4kHz,
192kHz
DLY2B[5:0] bits
192kHz
00H
1/64fs
1/32fs
(default)
01H
2/64fs
2/32fs
02H
3/64fs
3/32fs
:
:
:
1FH
32/64fs
32/32fs
:
:
:
3DH
62/64fs
N/A
3EH
63/64fs
N/A
3FH
64/64fs
N/A
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9.14.2. High Pass Filter (ADC1/2)
A digital High Pass Filter (HPF) is integrated for DC offset cancellation of the ADC input. The cut-off
frequencies (fc) of the HPF are set by HPF1C[1:0] bits (ADC1), HPF2C[1:0] bits (ADC2). HPFAD1N,
HPFAD2N bit controls the ON/OFF of the each HPF (HPF ON is recommended). It is proportional to the
sampling frequency (fs) and the default value is 3.7Hz (@fs = 48kHz).
HPF1C[1:0] bits
HPF2C[1:0] bits
00
01
10
11
Table 35. ADC1/2 HPF Cut-off Frequency
fc
fs = 16 kHz
fs = 48 kHz
fs = 96 kHz fs = 192 kHz
1.2 Hz
3.7 Hz
7.4 Hz
14.8 Hz
(default)
4.9 Hz
14.8 Hz
29.6 Hz
59.2 Hz
19.7 Hz
59.2 Hz
118.4 Hz
236.8 Hz
0.31 Hz
0.93 Hz
1.85 Hz
3.7 Hz
The cut-off frequencies during initialization cycle will be high (Table 36) at FSTHPFAD1N =
FSTHPFAD2N bit = “0” (default). When FSTHPFAD1N = FSTHPFAD2N bit = “1”, the setting of
HPF1C[1:0] and HPF2C[1:0] bits are valid.
Table 36. ADC1/2 HPF Cut-off Frequency at Initialization Cycle (x: Do not care)
FSTHPFAD1N bit HPF1C[1:0] bits
fs =
fs =
fs =
fs =
FSTHPFAD2N bit HPF2C[1:0] bits
16 kHz
48 kHz
96 kHz
192 kHz
0
xx
59.2 Hz
118.4 Hz 236.8 Hz 473.6 Hz (default)
00
1.2 Hz
3.7 Hz
7.4 Hz
14.8 Hz
01
4.9 Hz
14.8 Hz
29.6 Hz
59.2 Hz
1
10
19.7 Hz
59.2 Hz
118.4 Hz 236.8 Hz
11
0.31 Hz
0.93 Hz
1.85 Hz
3.7 Hz
9.14.3. ADC1/2 Digital Filter
The AK5704 has two types digital filter for ADC1/2 (Table 37). Short delay sharp roll-off filter or voice filter
of ADC1/2 can be selected by ADVF bit. When voice filter is selected by ADVF bit = “1”, the maximum
sampling frequency (fs) is 48kHz. If ADVF bit = “1” and the sampling frequency of ADC1/2 is 96kHz or
192kHz, the short delay sharp roll-off filter is selected automatically.
Table 37. ADC1/2 Digital Filter Selection
ADVF bit
Digital Filter
0
Short Delay Sharp Roll-Off Filter (default)
1
Voice Filter
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9.14.4. Microphone Sensitivity Adjustment
The AK5704 has linear microphone sensitivity adjustment function including mute controlled by
MS1A/B[7:0], MS2A/B[7:0] bits to adjust the variation of the microphone sensitivity input to the AIN1A/B
and AIN2A/B pins. MS1A/B[7:0], MS2A/B[7:0] bits must be set when PMAD1A/B, PMAD2A/B bits = “0”.
MS1A[7:0] bits:
MS1B[7:0] bits:
MS2A[7:0] bits:
MS2B[7:0] bits:
Adjusting the microphone sensitivity for AIN1A channel.
Adjusting the microphone sensitivity for AIN1B channel.
Adjusting the microphone sensitivity for AIN2A channel.
Adjusting the microphone sensitivity for AIN2B channel.
Table 38. Microphone Sensitivity Adjustment
MS1A[7:0] bits
MS1B[7:0] bits
MS2A[7:0] bits
MS2B[7:0] bits
00H
01H
02H
:
7EH
7FH
80H
81H
82H
:
FDH
FEH
FFH
MS_DATA
GAIN (dB)
Calculation
0
1
2
:
126
127
128
129
130
:
253
254
255
Mute
-42.144
-36.124
:
-0.137
-0.068
0.000
+0.068
+0.135
:
+5.918
+5.952
+5.987
-
20 log10(MS_DATA/128) (default)
9.14.5. Monaural (MIX) Selection
ADC1/2 output data can be mixed to monaural by controlling MIX1/2 bits. ALC (ALC1/2 or ALC4 bit = “1”)
or digital volume (ALC1/2 = ALC4 bits = “0”) operates for the data in Table 39.
MIXx bit
0
1
Table 39. ADCx Monaural (MIX) Selection (x=1, 2)
MONON bit
Ach Output Data
Bch Output Data
0
ADCx Ach
ADCx Bch
1
ADCx Ach
ADCx Bch
0
(ADCx Ach+ADCx Bch)/2
“0” data
1
(ADCx Ach+ADCx Bch)/2 (ADCx Ach+ADCx Bch)/2
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9.14.6. High Pass Filter (HPF1/2)
This is composed with double 1st order HPF. The coefficient of HPF11/2 (HPF21/2) is set by FH1A[15:0],
FH1B[15:0] bits (FH2A[15:0], FH2B[15:0] bits). HPF11/2 bits (HPF21/2 bits) control ON/OFF of the
HPF11/2 (HPF21/2). When the HPF11/2 (HPF21/2) is OFF, the audio data passes this block by 0dB gain.
The coefficient must be set when HPF11/2 = HPF21/2 bits = “0”. The HPF11/2 (HPF21/2) starts operation
4/fs (max) after when HPF11/2 = HPF21/2 bits = “1” is set.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 53)
HPF: FHxA[15:0] bits =A, FHxB[15:0] bits =B
(MSB=FHxA15, FxB15; LSB=FHxA0, FHxB0)
1 / tan (fc/fs)
1 − 1 / tan (fc/fs)
A=
,
B=
1 + 1 / tan (fc/fs)
1 + 1 / tan (fc/fs)
Transfer Function
1 − z −1
H(z) = A
1 + Bz −1
The cut-off frequency must be set as bellow.
fc/fs 0.000029 (fc min = 5.6Hz at 192kHz)
9.14.7. Low Pass Filter (LPF1/2)
This is composed with double 1st order LPF. The coefficient of LPF11/2 (LPF21/2) is set by FL1A[15:0],
FL1B[15:0] bits (FL2A[15:0], FL2B[15:0] bits). LPF11/2 bits (LPF21/2 bits) control ON/OFF of the
LPF11/2 (LPF21/2). When the LPF11/2 (LPF21/2) is OFF, the audio data passes this block by 0dB gain.
The coefficient must be set when LPF11/2 = LPF21/2 bits = “0”. The LPF11/2 (LPF21/2) starts operation
4/fs (max) after when LPF11/2 = LPF21/2 bits = “1” is set.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 53)
LPF: FLxA[15:0] bits =A, FLxB[15:0] bits =B
(MSB=FLxA15, FLxB15; LSB=FLxA0, FLxB0)
1
1 − 1 / tan (fc/fs)
A=
, B=
1 + 1 / tan (fc/fs)
1 + 1 / tan (fc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
The cut-off frequency must be set as bellow.
0.0125 ≤ fc/fs < 0.5 (fc min = 2.4kHz at 192kHz)
Note 53. [Translation the filter coefficient calculated by the equations above from real number to binary
code (2’s complement)]
X = (Real number of filter coefficient calculated by the equations above) x 215
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9.14.8. ALC Operation
The ALC (Automatic Level Control) is operated by ALC1 (2ch) block when ALC1 bit is “1” and operated by
ALC2 (2ch) block when ALC2 bit is “1”. In this case, both Ach and Bch VOL values are changed together.
When ALC4 bit = “0” and ALC1 = ALC2 bits = “1”, ALC of ADC1 and ADC2 are independently operated.
When ALC4 bit = “1” regardless of ALC1 and ALC2 bits, ALC is operated for all 4ch of the ADC1 and
ADC2. In this case, the VOL value is always changed in common with all channels. 4ch Link ALC is
operated by the register setting of ADC1 (LMTH1[1:0], RGAIN1[2:0], REF1[7:0], RFST1[1:0] and
ATTLIM1 bits). In this case, ALC setting of ADC2 (LMTH2[1:0], RGAIN2[2:0], REF2[7:0] and RFST2[1:0]
bits) is invalid, but ATTLIM2 bit should be set to “0”.
The ALC block consists of these blocks shown below. ALC limiter detection level and ALC recovery wait
counter reset level are monitored at Level Detection 2 block after EQ block. The Level Detection 1 block
also monitors clipping detection level (+0.53dBFS). ALC limiter gives priority to Level Detection 1.
ALC
Control
Level
Detection 2
EQ
Level
Detection 1
Output
Input
Volume
Figure 39. ALC Block
The polar (fc1) and the zero-point (fs2) frequencies of EQ block are dependent on the sampling frequency.
The coefficient is changed automatically according to the sampling frequency range setting. When
ALCEQ bit is OFF (ALCEQ bit = “1”), the level detection is not executed on EQ block.
Table 40. ALCEQ Frequency Setting
Sampling Frequency
Polar Frequency
Zero-point Frequency
Range
(fc1)
(fc2)
150Hz @ fs=8kHz
100Hz @ fs=8kHz
8kHz fs 12kHz
150Hz @ fs=16kHz
100Hz @ fs=16kHz
12kHz < fs 24kHz
150Hz @ fs=48kHz
100Hz @ fs=48kHz
24kHz < fs 48kHz
150Hz @ fs=96kHz
100Hz @ fs=96kHz
48kHz < fs 96kHz
150Hz @ fs=192kHz
100Hz @ fs=192kHz
96kHz < fs 192kHz
fs: Sampling frequency
fc1: Polar frequency
fc2: Zero-point frequency
K/20
A = 10
1 − 1 / tan (fc1/fs)
1 + 1 / tan (fc2/fs)
x
, B=
1 + 1 / tan (fc1/fs)
K/20
, C = 10
1 + 1 / tan (fc1/fs)
1 − 1 / tan (fc2/fs)
x
1 + 1 / tan (fc1/fs)
Transfer function
A + Cz −1
H(z) =
1 + Bz −1
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[ALCEQ: First order zero pole high pass filter]
Gain
[dB]
0dB
-3.5dB
150Hz
(fc1)
100Hz
(fc2)
Frequency
[Hz]
Note 54. Black: Diagrammatic Line, Red: Actual Line
Figure 40. ALCEQ Frequency Response (fs = 48kHz)
1. ALC Limiter Operation
During 2ch Link ALC limiter operation, when either A or B channel output level exceeds the ALC limiter
detection level (Table 42), the VOL1/2 value (same value for both A and B) is attenuated automatically
according to the output level (Table 43). During 4ch Link ALC limiter operation, when either A or B
channel output level of ADC1 or ADC2 exceeds the ALC limiter detection level (Table 42), the VOL1/2
value (same value for both A and B) is attenuated automatically according to the output level (Table 43).
This attenuation is repeated for sixteen times once ALC limiter operation is executed.
After completing the attenuate operation, unless ALC operation is changed to manual mode, the
operation repeats when the input signal level exceeds ALC limiter detection level.
When ATTLMT1/2 bit = “1”, VOL value is attenuated to 0dB if the volume is over ALC limiter detection
level. In this case, attenuation under 0dB is not executed. The reference level and the input digital volume
must be set to a value more than 0dB. When ATTLMT1/2 bit = “0” (default), normal attenuation is
executed without volume limitation. When ALC 4ch Link Mode is selected (ALC4 bit = “1”), it is controlled
by ATTLIM1 bit and ATTLIM2 bit should be set to “0”.
Table 41. ALC Mode (x: Do not care)
ALC4 ALC2 ALC1
ALC2
ALC1
Mode
bit
bit
bit
Operation
Operation
0
0
0
0
Manual
Manual
(default)
1
0
0
1
Manual
2ch Link
2
0
1
0
2ch Link
Manual
3
0
1
1
2ch Link
2ch Link
4
1
x
x
4ch Link
Note 55. ALC4 bit must be set when ALC1 = ALC2 bits = “0” or PMAD1A = PMAD1B = PMAD2A =
PMAD2B bits = “0”. When ALC4 bit = “1”, only either ADC1 or ADC2 must not be power down.
Table 42. ALC Limiter Detection Level/ Recovery Counter Reset Level
LMTH1[1:0] bits
LMTH2[1:0] bits
00
01
10
11
ALC Limiter Detection Level
ALC Recovery Counter Reset Level
ALC Output −2.5dBFS
ALC Output −4.1dBFS
ALC Output −6.0dBFS
ALC Output −8.5dBFS
−2.5dBFS > ALC Output −4.1dBFS
−4.1dBFS > ALC Output −6.0dBFS
−6.0dBFS > ALC Output −8.5dBFS
−8.5dBFS > ALC Output −12dBFS
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Table 43. ALC Limiter ATT Step
Output Level
+0.53dBFS Output Level (Level Detection 1)
–1.16dBFS EQ Output Level (Level Detection 2) < +0.53dBFS
LM-LEVEL EQ Output Level (Level Detection 2) < –1.16dBFS
ATT Step [dB]
0.38148
0.06812
0.02548
2. ALC Recovery Operation
ALC recovery operation waits for the WTM[1:0] bits (Table 44) to be set after completing ALC limiter
operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 42) during
the wait time, ALC recovery operation is executed. The VOL value is automatically incremented by the
setting value of RGAIN1/2[2:0] bits (Table 45) up to the set reference level (Table 46) in every sampling.
When the VOL value exceeds the reference level (REF values), the VOL values are not increased. The
recovery speed gets slower when the VOL peak level exceeds -12dBFS to make the recovery speed for
low VOL level faster relatively.
When
“ALC recovery waiting counter reset level Output Signal < ALC limiter detection level”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level > Output Signal”,
the waiting timer of ALC recovery operation starts.
ALC operations correspond to the impulse noise. When FRN bit = “0”, the impulse noise is input, the ALC
recovery operation becomes faster than a normal recovery operation. When large noise is input to a
microphone instantaneously, the quality of small level in the large noise can be improved by this fast
recovery operation. The speed of fast recovery operation is set by RFST1/2[1:0] bits (Table 47). Limiter
amount of Fast recovery is set by FRATT[1:0] bits (Table 48). When FRN bit = “1”, the fast recovery does
not operate though the impulse noise is input.
Table 44. ALC Recovery Operation Waiting Period
WTM[1:0] bits ALC Recovery Cycle
128/fs
(default)
00
512/fs
01
2048/fs
10
8192/fs
11
Table 45. ALC Recovery Gain Step
RGAIN1[2:0] bits
Gain Change
GAIN Step [dB]
RGAIN2[2:0] bits
Timing
000
0.00212
1/fs
001
0.00106
1/fs
010
0.00106
4/fs
011
0.00106
8/fs
100
0.00106
16/fs
101
0.00106
32/fs
110
0.00106
64/fs
111
0.00106
128/fs
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Table 46. Reference Level of ALC Recovery Operation
REF1[7:0] bits
GAIN [dB]
Step
REF2[7:0] bits
F1H
+36.0
E0H
+35.625
EFH
+35.25
:
:
E1H
+30.0
(default)
:
:
0.375 dB
92H
+0.375
91H
0.0
90H
–0.375
:
:
06H
–52.125
05H
–52.5
04H ~ 00H
MUTE
Table 47. Fast Recovery Speed Setting (FRN bit = “0”)
RFST1[1:0] bits
Fast Recovery Gain Step
RFST2[1:0] bits
[dB]
00
0.000265
(default)
01
0.00106
10
0.00424
11
0.01696
Table 48. Fast Recovery Reference Volume Attenuation Step
ATT Step [dB]
ATT Switch Timing
FRATT[1:0] bits
-0.00106
4/fs
(default)
00
-0.00106
16/fs
01
-0.00106
64/fs
10
-0.00106
256/fs
11
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3. Example of ALC Setting
Table 49 shows the examples of the ALC setting.
Register Name
LMTH1/2[1:0]
WTM[1:0]
REF1/2[7:0]
IV1A/B[7:0],
IV2A/B[7:0]
RGAIN1/2[2:0]
RFST1/2[1:0]
ALCEQN
ALC1/2
Table 49. Example of the ALC Setting
fs=16kHz
Comment
Data Operation
Limiter detection Level
01
−4.1dBFS
Recovery waiting period
01
32ms
Maximum gain at recovery operation
E1H
+30dB
fs=48kHz
Data
Operation
01
−4.1dBFS
10
42.7ms
E1H
+30dB
Gain of IVOL
E1H
+30dB
E1H
+30dB
Recovery GAIN
Fast Recovery GAIN
ALC EQ disable
ALC enable
001
11
0
1
0.00106dB
0.01696dB
Enable
Enable
010
10
0
1
0.00106dB(4/fs)
0.00424dB
Enable
Enable
4. Example of registers set-up sequence of ALC operation
The following registers must not be changed during ALC operation. These bits must be changed after
ALC operation is stopped by ALC1/2 = ALC4 bits = “0”.
・FRN, WTM[1:0], FRATT[1:0], ALCEQN, LMTH1/2[1:0], RFST1/2[1:0] and RGAIN1/2[2:0] bits
The reference level can be changed during ALC operation. If the reference level is reduced the volume
level is changed by soft transition in 0.02548dB/fs step. The volume is also changed by soft transition to
the IVOL setting value (IV1A/B[7:0], IV2A/B[7:0] bits) until manual mode starts after ALCx bit is set to “0”.
Do not change the REF value during soft transition when REF1/2[7:0] bits are set to 00H (MUTE).
When changing ALC operation channels, finish all ALC operations at first (ALC4 = ALC2 = ALC1 bits=
“0”) and write ALCx bit = “1”. In this case, ALCx bit writing must be made with an interval of 2/fs. It is
recommended that ALC operation is enabled after transition time since the volume changes to the IVOL
setting value by soft transition when ALC operation is finished.
The reference level and IVOL must be set to a value more than 0dB when ATTLMT1/2 bits = “1”.
Example:
Recovery Wait Time = 42.7ms@48kHz
ALCEQN bit = “0”
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
Fast Recovery Step = 0.00424 dB
Recovery Gain = 0.00106 dB (4/fs)
ALC1 bit = “1”
Manual Mode
WR (WTM[1:0], ALCEQN)
WR (IV1A/B[7:0])
(1) Addr=26H Data=42H
* The value of IVOL should be
the same or smaller than REF’s
(2) Addr=27H,28H, Data=E1H
WR (REF1[7:0])
(3) Addr=29H, Data=E1H
WR (LMTH1[1:0], RFST1[1:0], RGAIN1[2:0])
(4) Addr=2AH, Data=A9H
WR (ALC1 = “1”)
(5) Addr=25H, Data=01H
ALC Operation
Figure 41. ALC Operation Setting Sequence
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9.14.9. Input Digital Volume (Manual Mode)
The input digital volume becomes manual mode when ALC4 = ALC2 = ALC1 bits= “0”. This mode is used
in the cases shown below.
1. After exiting reset state, when setting up the registers for ALC operation (LMTH1/2 bits and etc.)
2. When the registers for ALC operation (Limiter period, Recovery period and etc.) are changed.
For example; when the sampling frequency is changed.
3. When IVOL is used as a manual volume control.
IV1A/B[7:0] and IV2A/B[7:0] bits set the gain of the digital input volume (Table 50). 1Ach and 1Bch
volumes are set individually by IV1A[7:0] and IV1B[7:0] bits when IVOL1C bit = “0”. IV1A[7:0] bits control
both 1Ach and 1Bch volumes together when IVOL1C bit = “1”. 2Ach and 2Bch volumes are set
individually by IV2A[7:0] and IV2B[7:0] bits when IVOL2C bit = “0”. IV2A[7:0] bits control both 2Ach and
2Bch volumes together when IVOL2C bit = “1”. This volume control has a soft transition function at
0.09375dB/fs (IVTM[1:0] bits = “01”). Therefore, no switching noise occurs during the transition. When
IVTM[1:0] bits = “01”, it takes 944/fs from F1H(+36dB) to 05H(-52.5dB). The volume is muted after
transitioned to -72dB (208/fs) in the period set by IVTM[1:0] bits when changing the volume from 05H
(-52.5dB) to 00H (MUTE). When IV1A/B[7:0] bits and IV2A/B[7:0] bits are set in series, should be set at
soft transition time interval.
If IV1A/B[7:0] or IV2A/B[7:0] bits are written during PMPFIL1/2 bits = “0”, IVOL operation starts with the
written values after PMPFIL1/2 bits are changed to “1”.
Table 50. Input Digital Volume Setting
IV1A/B[7:0] bits
GAIN [dB]
Step
IV2A/B[7:0] bits
F1H
+36.0
E0H
+35.625
EFH
+35.25
:
:
E1H
+30.0
:
:
0.375 dB
92H
+0.375
91H
0.0
(default)
90H
–0.375
:
:
06H
–52.125
05H
–52.5
04H ~ 00H
MUTE
IVTM[1:0] bits
00
01
10
11
Table 51. Transition Time Setting of Input Digital Volume
Transition Time from F1H to 05H (IV1A/B[7:0], IV2A/B[7:0] bits)
Setting
fs=16kHz
fs=48kHz
fs=96kHz
fs=192kHz
236/fs
14.8ms
4.9ms
2.5ms
1.2ms
944/fs
59ms
19.7ms
9.8ms
4.9ms
1888/fs
118ms
39.3ms
19.7ms
9.8ms
3776/fs
236ms
78.7ms
39.3ms
19.7ms
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ALC1/2 bits
ALC1/2 Status
“0”
“1”
“0”
Disable
Enable
Disable
IV1/2A7-0 bits
E1H(+30dB)
IV1/2B7-0 bits
C6H(+20dB)
Internal IV1/2A
E1H(+30dB)
Internal IV1/2B
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
(1)
E1(+30dB)
(2)
E1(+30dB) --> F1(+36dB)
C6H(+20dB)
Figure 42. Example of IVOL value during 2ch ALC (ALC4 bit = “0”)
(1) The IV1A and IV2A value becomes the start value if the IV1A and IV1B, IV2A and IV2B are different
when an ALC operation starts. The wait time from ALC1/2 bits = “1” to ALC operation start by
IV1/2A[7:0] bits is at most recovery time (WTM[1:0] bits).
(2) Writing to IV1A/B and IV2A/B registers is ignored during ALC operation. After ALC is disabled, the
IVOL changes to each IV1A/B or IV2A/B value by soft transition. When ALC is enabled again, ALC1/2
bits should be set to “1” with an interval more than soft transition time after ALC1/2 bit = “0”.
9.14.10. ALC 4ch Link Mode Sequence
Figure 43 shows the 4ch Link ALC Mode sequence at ALC1 = ALC2 bits = “0”, when ALC4 bit = “0” → “1”.
(3)
ALC4 bit
PMPFIL1 bit
(5)
(1)
(7)
(2)
PMPFIL2 bit
ALC1 bit
ALC2 bit
ADC1 Operation Power Down
ADC2 Operation Power Down
(6)
(4)
(4)
(4)
(4)
Manual Mode
Manual Mode
4ch Link ALC
4ch Link ALC
Manual Mode
Manual Mode
Power Down
Power Down
Figure 43. 4ch Link ALC Mode Sequence (ALC4 bit = “1”)
(1) Programmable Filter 1 is powered up by PMPFIL1 bit is changed from “0” to “1”.
(2) Programmable Filter 2 is powered up by PMPFIL2 bit is changed from “0” to “1”.
(3) Both ADC1 and ADC2 start ALC operation together (4ch Link ALC) by changing ALC4 bit from “0” to
“1”. At this point the start value of ALC is Ach of ADC1 (IV1A[7:0] bits).
(4) When ALC4 bit = “1”, ALC1 bit and ALC2 bit become invalid. But ALC1 and ALC2 bits should be “0”,
when ALC4 bit is changed.
(5) When ALC4 bit = “1” → “0”, ADC1 and ADC2 become Manual Mode. 2ch link mode can also be set
without stopping operation by setting ALC1 and ALC2 bits = “1”.
(6) Programmable Filter 2 is powered down by PMPFIL2 bit is changed from “1” to “0”.
(7) Programmable Filter 1 is powered down by PMPFIL1 bit is changed from “1” to “0”.
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9.15.
Digital Voice Activity Detector
The AK5704 has a Voice Activity Detector (VAD) function. VAD operation requires to supply MCKI input
and to operate an analog microphone and ADC or a digital microphone.
By setting each parameter, an interrupt signal is output to the WINTN pin for the external DSP (SoC) in
response to the voice input from MIC. Then, the voice input from MIC is output to the SDTO1 pin.
AVDD
MCKI
(e.g. 4.096MHz)
MPWR1
Analog
MIC
MUX
Voice
Activity
Detector
ADC
DSP
or
SoC
Interrupt WINTN
Signal
Digital
Filter
Buffer
SDTO1
or
Digital
MIC
PDM
-
DCLK
Keyword verification
Voice Recognition
Figure 44. Voice Activity Detector System Block Diagram
VAD is a function to detect a large sound in ambient noise. VAD has a delay circuit to save speech data
prior to the point which the voice is detected.
Programmable Filter 1
AIN1A
AIN1B
AIN2A
AIN2B
VAD Block
PFTHR1 bit
ADC
HPF
1A
VADINS[1:0] bits
VDLYO[15:0]
ALC1
(IVOL)
HPF1, LPF1
VDLY
16bits
Input Sel
VADSEL bit
Output
Selector
VAHPF
VALPF
VADO
Serial Data
IIRO[17:0]
18bits
ABS
Comparator
VDET Guard VON
>
Timer
ABS[16:0]
17bits
NLD
NL[16:0]
MINTH[16:0] bits
NLX[16:0]
MAX
THX[16:0]
MULT(X)
NLDTH[11:0] bits
Figure 45. Voice Activity Detector Block Diagram
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Input signal to ADC1 is selected by VADINS[1:0] bits, and the corresponding microphone input circuit is
powered up by setting PMAINx bit = “1”. When the ADC1 and the Programmable Filter 1 are powered up
by setting PMAD1A = PMPFIL1 bits = “1”, a signal is input to the VAD circuit.
Table 52. ADC1 Input Signal Select
VADINS[1:0] bits
ADC1 Input Signal
00
AIN1A
(default)
01
AIN1B
10
AIN2A
11
AIN2B
VAD circuit is powered up by setting PMVAD bit = “1”. When the VAD is powered down, NLD (Noise Level
Detector) is also reset the leaning data by resetting the VAD circuit. The default value of NLD part is zero.
Each register related to VAD should be set during PMVAD bit = “0” (Do not change the set value during
operation.)
Table 53. Voice Activity Detector Power Management
PMVAD bit
VAD Operation
0
Power down (Reset)
(default)
1
Normal operation
Input signal to VAD circuit is selected by VADSEL bit.
Table 54. Select Input Signal for VAD
VADSEL bit
Input Signal for VAD
0
ADC output
(default)
1
HPF/LPF output
9.15.1. VDLY
VDLY block outputs the signal according to VDLYO[15:0] bits which is delayed input data. These data are
used when the speech data which is before voice detection is necessary for subsequent process. SRAM
is used to create delay. SRAM size is 2048word x 16bit. The ON/OFF control of VDLY block is selectable
by DLYE bit. Non-delay data is output when this function is disabled. SRAM is initialized when the reset is
released.
Table 55. VAD Delay Setting
DLYE bit
Amount of Delay
0
No-delay
2048 sample
1
(128ms @ fs=16kHz)
(default)
9.15.2. HPF, LPF
In addition to 2nd order HPF and LPF of Programmable Filter 1, 2nd order HPF and LPF are built in for
VAD. After passing through HPF and LPF, the output value IIRO [17: 0] is input to the ABS section of the
next stage.
High Pass Filter (VAHPF)
This is composed with double 1st order HPF. The coefficient of VAHPF1/2 is set by VFHA[15:0],
VFHB[15:0] bits. VAHPF1 bit (VAHPF2 bit) control ON/OFF of the VAHPF1 (VAHPF2). When the
VAHPF1 (VAHPF2) is OFF, the audio data passes this block by 0dB gain. The coefficient must be set
when VAHPF1 = VAHPF2 bits = “0”. The VAHPF1 (VAHPF2) starts operation 4/fs (max) after when
VAHPF1 = VAHPF2 bits = “1” is set.
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fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 56)
VAHPF: VFHA[15:0] bits =A, VFHB[15:0] bits =B
(MSB=VFHA15, VFHB15; LSB=VFHA0, VFHB0)
1 / tan (fc/fs)
1 − 1 / tan (fc/fs)
A=
,
B=
1 + 1 / tan (fc/fs)
1 + 1 / tan (fc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
The cut-off frequency must be set as bellow.
fc/fs 0.000029 (fc min = 5.6Hz at 192kHz)
Low Pass Filter (VALPF)
This is composed with double 1st order LPF. The coefficient of VALPF1/2 is set by VFLA[15:0],
VFLB[15:0] bits. VALPF1 bit (VALPF2 bit) control ON/OFF of the VALPF1 (VALPF2). When the VALPF1
(VALPF2) is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when
VALPF1 = VALPF2 bits = “0”. The VALPF1 (VALPF2) starts operation 4/fs (max) after when VALPF1 =
VALPF2 bits = “1” is set. When HPF3RD bit is set to “1”, VALPF1 can be changed to HPF. In this case,
the coefficient setting is followed VFHA[15:0] and VFHB[15:0] bits.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 56)
VALPF: VFLA[15:0] bits =A, VFLB[15:0] bits =B
(MSB=VFLA15, VFLB15; LSB=VFLA0, VFLB0)
1
1 − 1 / tan (fc/fs)
A=
, B=
1 + 1 / tan (fc/fs)
1 + 1 / tan (fc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
The cut-off frequency must be set as bellow.
0.0125 ≤ fc/fs < 0.5 (fc min = 2.4kHz at 192kHz)
Note 56. [Translation the filter coefficient calculated by the equations above from real number to binary
code (2’s complement)]
X = (Real number of filter coefficient calculated by the equations above) x 215
9.15.3. ABS
ABS simply calculates an absolute value.
1. If most significant bit of sign bit is 0, all bit except for most significant bit will be directly output.
2. If most significant bit of sign bit is 1, all bit except for most significant bit will be added +1 after bit
inverting and output.
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9.15.4. NLD (Noise Level Detector)
NLD (Noise Level Detector) detects a noise level of the input signal.
Average 1
Average 2
Peakhold
Capture
T2=T1/2^AT
T1=fs / (PT+1)
更新条件
input
sync
T1
max
1/2^N
T2
1/2
T2
NL[16:0]
Figure 46. Noise Level Detector Block Diagram
The peak value is calculated according to the setting of PT[7:0] bits in the Peak-hold stage.
PT[7:0] bits
N
00H
:
07H
:
1FH
:
FFH
Table 56. Peak Value Setting
Update Rate
Calculating Period [μs]
Number of Samples
T1 [Hz]
@ fs=16kHz
N+1
fs/(N+1)
62.5 * (N+1)
1
fs
62.5
:
:
:
8
fs/8
500
:
:
:
32
fs/32
2,000
:
:
:
256
fs/256
16,000
(default)
The peak value is calculated according to the setting of AT[3:0] bits in the Average1 and Average2 stage.
AT[3:0]
bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Average1
Number of
Samples
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
Table 57. Average of Peak Value Setting
Average 1 Average 2
Total
Update Rate
Shift
Number of Number of
T2 [Hz]
Amount N
Samples
Samples
0
2
2
T1/1
1
2
4
T1/2
2
2
8
T1/4
3
2
16
T1/8
4
2
32
T1/16
5
2
64
T1/32
6
2
128
T1/64
7
2
256
T1/128
0
2
512
T1/256
1
2
1024
T1/512
2
2
2048
T1/1024
3
2
4096
T1/2048
4
2
8192
T1/4096
5
2
16384
T1/8192
6
2
32768
T1/16384
7
2
65536
T1/32768
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NL (Noise Level) update execution is determined in the Capture stage. In the following condition, NL is
updated.
(Noise level reaches to the voice level unless stopping NLD during speech detection. To prevent this,
noise level is updated in this condition.)
(When VON becomes “1” due to a false detection by sudden increase of noise level, NLD stops
updating. To prevent this, noise level is updated in this condition.)
* 0xFFFF samples is default setting (VONT bit = “0”). When VONT bit is set to “1”, the number of
samples is changed to 0x7FFF (2.048s@16kHz).
NL Limiter Function
When NL increases following the input signal, there is a possibility that voice activity cannot be detected
depending on the setting of NLDTH[11:0] bits. It is an optional function considering such a situation. It can
prevent a sudden increase of noise level according to the data limit by NLLIM[1:0] bits at the next NL
update.
Table 58. Noise Level Limiter Value Setting
Noise Level Limiter Value
NLLIM[1:0] bits
at Next NL Update
00
No-limit
(default)
01
+2dB
10
+3dB
11
+4dB
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9.15.5. MAX
The minimum noise level is set to MINTH[16:0] bits (unsigned). A larger value of MINTH[16:0] bits
(unsigned) and NL[16:0] bits (output level of NLD block, unsigned) is output to NLX[16:0] bits.
This setting can prevent the NLD reacts sensitively in a quiet environment.
Table 59. Minimum Noise Level Setting
MINTH[16:0] bits Minimum Noise Level [dBFS]
N
20*log(N/2^17)
00000H
-∞
:
:
0001FH
-72.2
(default)
:
:
00048H
-65.2
:
:
10000H
-6.0
:
:
1FFFFH
0
9.15.6. MULT (X)
The speech detection threshold level (THX[16:0] bits) is calculated by multiplying noise level threshold
(NLDTH[11:0] bits) by ambient noise level (NLX[16:0] bits) which is determined according to NLD and
MAX blocks. Multiplication result outputs 17-bit data. If multiplication result is greater than 17-bit full scale,
output data is saturated to 0x1FFFF.
Table 60. Noise Level Threshold
NLDTH[11:0] bits
Noise Level Threshold [dB]
N
20*log(N/2^7)
000H
-∞
:
:
080H
+0.0
:
:
200H
+12.0
:
:
7EDH
+24.0
:
:
FFFH
+30.1
(default)
9.15.7. Comparator (>)
In case of output value of ABS block > THX[16:0] bits, the comparator outputs VDET = “H”.
In case of output value of ABS block THX[16:0] bits, the comparator outputs VDET = “L”.
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9.15.8. Guard Timer
The output condition of VON = "H" can be limited by ONGT[7:0] bits which define a number of
continuous detection times of VDET = "H".
OFFGT[7:0] bits which define a number of continuous detection times of VDET = “L” can set a
determined period that keeps VON = "H" after VON = "L" detection.
Table 61. On Guard Timer Setting
OFFGT[7:0]
bits
N
00H
:
0FH
:
FFH
ONGT[7:0] bits
VON↑ Condition
A Number of VDET= “H”
N
00H
01H
02H
:
FFH
N+1
1
2
3
:
256
(default)
Table 62. Off Guard Timer Setting
VON↓ Condition
Time @ fs = 16kHz [ms]
A Number of VDET = “L”
(N+1)*2^8
0.0625 * (N+1)*2^8
256
16
:
:
4,096
256
:
:
65,536
4096
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9.15.9. Interrupt Output (WINTN pin)
The WINTN pin holds “H” output when voice activity is not detected (VON = “L”). When the voice activity
is detected (VON = “H”), the WINTN pin output is changed to “L”.
9.15.10. Output Selector
VADO output is selectable by setting VAS[2:0] bits or VBS[2:0] bits. VAS[2:0] bits determine Ach output,
and VBS[2:0] bits determine Bch output.
When VADOE bit is set to “1”, VADO is started to output from the SDTO1 pin. (When VADOE bit = “0”
(default), the data of ADC1 or Programmable Filter 1 is output from SDTO1 pin.)
Table 63. Output Selector Setting
VAS[2:0] bits
Ach Output [15:0]
VBS[2:0] bits
Bch Output [15:0]
000
VDLYO[15:0]
VON=0: 0x0000
001
VON=1: VDLYO[15:0]
VON=0: 0x0000
010
VON=1: 0x2710 (10000dec)
011
NL[16:1]
100
ABS[16:1]
101
THX[16:1]
110
IIRO[17:2]
VDET=0: 0x0000
111
VDET=1: 0x2710 (10000dec)
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9.16.
I2C-bus Control Interface
The AK5704 supports the fast-mode I2C Bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins
must be connected to (TVDD+0.3)V or less.
1. WRITE Operation
Figure 47 shows the data transfer sequence for the I2C Bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 53). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant six bits of the slave
address are fixed as “001000” (Figure 48). If the slave address matches that of the AK5704, the AK5704
generates an acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
(Figure 54). A R/W bit value of “1” indicates that the read operation is to be executed, and “0” indicates
that the write operation is to be executed.
The second byte consists of the control register address of the AK5704. The format is MSB first, and
those most significant 1bit is fixed to zero (Figure 49). The data after the second byte contains control
data. The format is MSB first, 8bits (Figure 50). The AK5704 generates an acknowledge after each byte is
received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to
HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 53).
The AK5704 can perform more than one byte write operation per sequence. After receipt of the third byte
the AK5704 generates an acknowledge and awaits the next data. The master can transmit more than one
byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data
packet the internal address counter is incremented by one, and the next data is automatically taken into
the next address. The address counter will “roll over” to 00H and the previous data will be overwritten if
the address exceeds “46H” prior to generating a stop condition.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (Figure 55) except for the
START and STOP conditions.
S
T
A
R
T
SDA
S
S
T
O
P
R/W="0"
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 47. Data Transfer Sequence at I2C Bus Mode
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0
0
0
A6
D7
D6
1
0
0
0
(CAD must match with CAD pin.)
Figure 48. The First Byte
CAD
R/W
A5
A4
A3
A2
Figure 49. The Second Byte
A1
A0
D5
D4
D3
D2
Figure 50. The Third Byte
D1
D0
2. READ Operation
Set the R/W bit = “1” for the READ operation of the AK5704. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. The address counter
will “roll over” to 00H and the data of 00H will be read out if the address exceeds “46H” of Register map
prior to generating a stop condition.
The AK5704 supports two basic read operations: CURRENT ADDRESS READ and RANDOM
ADDRESS READ.
2-1. CURRENT ADDRESS READ
The AK5704 has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address
with R/W bit “1”, the AK5704 generates an acknowledge, transmits 1-byte of data to the address set by
the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates a stop condition instead, the AK5704 ceases the transmission.
S
T
A
R
T
SDA
S
S
T
O
P
R/W="1"
Slave
Address
Data(n)
A
C
K
Data(n+1)
MA
AC
SK
T
E
R
Data(n+2)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S K
T
E
R
MA
AC
SK
T
E
R
P
MN
AA
SC
T K
E
R
Figure 51. Current Address Read
2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing
the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit “1”. The AK5704 then generates an acknowledge, 1 byte of data and increments
the internal address counter by 1. If the master does not generate an acknowledge but generates a stop
condition instead, the AK5704 ceases the transmission.
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S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
S
T
O
P
R/W="1"
Slave
S Address
A
C
K
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
P
MN
A A
SC
T K
E
R
Figure 52. Random Address Read
SDA
SCL
S
P
start condition
stop condition
Figure 53. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 54. Acknowledge (I2C Bus)
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 55. Bit Transfer (I2C Bus)
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9.17.
Addr
Register Map
Register Name
D7
D6
D5
D4
D3
D2
D1
0
PSW2N
D0
00H
Flow Control
0
SDTO2E
MSN
AVDDL
PSW1N
PSW0N
01H
Power Management 1
PMVCM
PMPLL
PMMP2
PMMP1
PMAIN2B PMAIN2A
PMAIN1B
PMAIN1A
02H
Power Management 2
PMDM2B PMDM2A PMDM1B
PMDM1A
PMAD2B PMAD2A
PMAD1B
PMAD1A
AIRST[2:0]
PMVAD
PFSDO2
PFSDO1
PMPFIL2
PMPFIL1
MDIF1A
AINCOM
MONON
03H
Power Management 3
MIC Input & MIC Power
04H
Setting
05H
MIC Amplifier 1 Gain
MDIF2B
MDIF2A
MG1A[3:0]
MG2B[3:0]
MG2A[3:0]
MIC Amplifier 2 Gain
07H
Digital MIC Setting
0
DCLKP2
08H
Clock Mode Select
0
0
0
0
0AH
PLL Ref CLK Divider 1
MICL[1:0]
MG1B[3:0]
06H
09H PLL CLK Source Select
MDIF1B
DCLKE2
DMIC2
0
DCLKP1
0
0
CM[1:0]
BCKO
DCLKE1
DMIC1
FS[3:0]
MCKOE
PLS
0
PLD[15:8]
0BH
PLL Ref CLK Divider 2
PLD[7:0]
0CH
PLL FB CLK Divider 1
PLM[15:8]
0DH
PLL FB CLK Divider 2
PLM[7:0]
0EH
Audio I/F Format
0
BCKP
0FH
Phase Adjustment 1A
DLY1AE
0
DLY1A[5:0]
10H
Phase Adjustment 1B
DLY1BE
0
DLY1B[5:0]
11H
Phase Adjustment 2A
DLY2AE
0
DLY2A[5:0]
12H
Phase Adjustment 2B
DLY2BE
0
13H
ADC High Pass Filter
0
14H
Digital Filter Select
ADVF
15H
MIC Sensitivity Adj. 1A
16H
MIC Sensitivity Adj.1B
MS1B[7:0]
17H
MIC Sensitivity Adj.2A
MS2A[7:0]
18H
MIC Sensitivity Adj.2B
MS2B[7:0]
19H
Filter 1 Select
PFTHR1
1AH
Filter 2 Select
PFTHR2
0
0
MIX2
1BH
VAD Setting 1
VALPF2
VALPF1
VAHPF2
VAHPF1
1CH
VAD Setting 2
1DH
VAD Setting 3
1EH
VAD Setting 4
MINTH[15:8]
1FH
VAD Setting 5
MINTH[7:0]
20H
VAD Setting 6
21H
VAD Setting 7
NLDTH[7:0]
22H
VAD Setting 8
ONGT[7:0]
23H
VAD Setting 9
OFFGT[7:0]
24H
VAD Setting 10
DLC[1:0]
TDM[1:0]
DIF[1:0]
DLY2B[5:0]
ADRST[2:0]
0
0
0
0
HPF2C[1:0]
FSTHPF FSTHPF
VREFH
AD2N
AD1N
MS1A[7:0]
MIX1
LPF12
HPF1C[1:0]
HPFAD2N HPFAD1N
LPF11
HPF12
HPF11
LPF22
LPF21
HPF22
HPF21
HPF3RD
VADSEL
DLYE
VADOE
0
0
MINTH16
PT[7:0]
VADINS[1:0]
NLLIM[1:0]
0
AT[3:0]
VONT
NLDTH[11:8]
VBS[2:0]
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Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
25H
ALC Select
FRN
ATTLIM2
ATTLIM1
0
0
ALC4
ALC2
ALC1
26H
ALC Control 1
0
ALCEQN
IVTM[1:0]
27H Input Digital Volume 1A
IV1A[7:0]
28H Input Digital Volume 1B
IV1B[7:0]
29H ALC1 Reference Level
REF1[7:0]
2AH
ALC1 Control
IVOL1C
RGAIN1[2:0]
2BH Input Digital Volume 2A
IV2A[7:0]
2CH Input Digital Volume 2B
IV2B[7:0]
2DH ALC2 Reference Level
REF2[7:0]
2EH
ALC2 Control
2FH
HPF1 Coefficient A
IVOL2C
RGAIN2[2:0]
FH1A[15:8]
30H
HPF1 Coefficient A
FH1A[7:0]
31H
HPF1 Coefficient B
FH1B[15:8]
32H
HPF1 Coefficient B
FH1B[7:0]
33H
LPF1 Coefficient A
FL1A[15:8]
34H
LPF1 Coefficient A
FL1A[7:0]
35H
LPF1 Coefficient B
FL1B[15:8]
36H
LPF1 Coefficient B
FL1B[7:0]
37H
HPF2 Coefficient A
FH2A[15:8]
38H
HPF2 Coefficient A
FH2A[7:0]
39H
HPF2 Coefficient B
FH2B[15:8]
3AH
HPF2 Coefficient B
FH2B[7:0]
3BH
LPF2 Coefficient A
FL2A[15:8]
3CH
LPF2 Coefficient A
FL2A[7:0]
3DH
LPF2 Coefficient B
FL2B[15:8]
3EH
LPF2 Coefficient B
FL2B[7:0]
3FH
VAHPF Coefficient A
VFHA[15:8]
40H
VAHPF Coefficient A
VFHA[7:0]
41H
VAHPF Coefficient B
VFHB[15:8]
42H
VAHPF Coefficient B
VFHB[7:0]
43H
VALPF Coefficient A
VFLA[15:8]
44H
VALPF Coefficient A
VFLA[7:0]
45H
VALPF Coefficient B
VFLB[15:8]
46H
VALPF Coefficient B
VFLB[7:0]
FRATT[1:0]
WTM[1:0]
RFST1[1:0]
LMTH1[1:0]
RFST2[1:0]
LMTH2[1:0]
Note 57. Register values are initialized by setting the PDN pin to “L”.
Note 58. It is prohibited to write “1” to the bits indicated as “0“.
Note 59. Writing access to 47H ~ 7FH is prohibited.
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9.18.
Addr
00H
Register Definition
Register Name
Flow Control
R/W
Default
D7
0
R/W
0
D6
SDTO2E
R/W
0
D5
MSN
R/W
0
D4
AVDDL
R/W
0
D3
0
R/W
0
D2
PSW2N
R/W
0
D1
PSW1N
R/W
0
D0
PSW0N
R/W
0
PSW2N/1N/0N: Pull-down Resistance Disable bits (Table 1)
0: Pull-down Enable (Typ. 49 k) (default)
1: Pull-down Disable
AVDDL: AVDD Internal Operation Mode
0: 3.3V Operation (default)
1: 1.8V Operation
MSN: Master/Slave Setting (Table 16, Table 17, Table 18, Table 19)
0: Slave Mode (default)
1: Master Mode
SDTO2E: SDTO2 Enable
0: Disable (TDMIN pin: Default)
1: Enable (SDTO2 pin)
Addr
01H
Register Name
Power Management 1
R/W
Default
D7
PMVCM
R/W
0
D6
PMPLL
R/W
0
D5
PMMP2
R/W
0
D4
PMMP1
R/W
0
D3
D2
D1
D0
PMAIN2B PMAIN2A PMAIN1B PMAIN1A
R/W
R/W
R/W
R/W
0
0
0
0
PMAIN1A/B: Power Management of AIN1A/B Inputs
0: Power down (default)
1: Power up
PMAIN2A/B: Power Management of AIN2A/B Inputs
0: Power down (default)
1: Power up
PMMP1/2: Power Management of MPWR1/2 (Table 26)
0: Power down: Hi-Z (default)
1: Power up
PMPLL: Power Management of PLL
0: Power down (default)
1: Power up
PMVCM: Power Management of VCOM
0: Power down (default)
1: Power up
After setting AVDDL bit, VCOM must be powered up (PMVCM bit = “1”).
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Addr
02H
Register Name
Power Management 2
R/W
Default
D7
D6
D5
D4
D3
PMDM2B PMDM2A PMDM1B PMDM1A PMAD2B
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
D2
PMAD2A
R/W
0
D1
PMAD1B
R/W
0
D0
PMAD1A
R/W
0
PMAD1A/B: Power Management of MIC-Amp 1 & ADC1 Ach/Bch (Table 29)
0: Power down (default)
1: Power up
PMAD2A/B: Power Management of MIC-Amp 2 & ADC2 Ach/Bch (Table 30)
0: Power down (default)
1: Power up
PMDM1A/B: Input Signal Select with Digital Microphone 1 (Table 31)
0: Power Down (default)
1: Power Up
ADC1 digital block is powered-down by PMDM1A = PMDM1B bits = “0” when selecting a digital
microphone input (DMIC1 bit = “1”).
PMDM2A/B: Input Signal Select with Digital Microphone 2 (Table 32)
0: Power Down (default)
1: Power Up
ADC2 digital block is powered-down by PMDM2A = PMDM2B bits = “0” when selecting a digital
microphone input (DMIC2 bit = “1”).
Addr
03H
Register Name
Power Management 3
R/W
Default
D7
D6
AIRST[2:0]
R/W
000
D5
D4
PMVAD
R/W
0
D3
PFSDO2
R/W
0
D2
PFSDO1
R/W
0
D1
D0
PMPFIL2 PMPFIL1
R/W
R/W
0
0
PMPFIL1: Power Management of Programmable Filter 1
0: Power down (default)
1: Power up
PMPFIL2: Power Management of Programmable Filter 2
0: Power down (default)
1: Power up @ PMPFIL1 bit = “1” (PMPFIL2 does not power up, when PMPFIL1 bit = “0”.)
PFSDO1/2: SDTO1/2 Output Signal Select
0: ADC output (default)
1: Programmable Filter or VAD output
PMVAD: Power Management of Voice Activity Detector (Table 53)
0: Power down (default)
1: Power up
AIRST[2:0]: AIN1/2 Initialization Cycle Setting (Table 27)
Default: “000” (656/fs)
This is a common setting for AIN1A/B and AIN2A/B.
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Addr
04H
Register Name
MIC Input & MIC Power
Setting
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
MDIF2B
MDIF2A
MDIF1B
MDIF1A
AINCOM
MONON
MICL[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
00
MICL1[1:0]: MIC Power (MPWR1/2 pins) Output Voltage Setting (Table 25)
Default: “00” (Typ. 2.8 V)
MONON: ADC Digital Output Mode Setting (Table 29, Table 30, Table 31, Table 32, Table 39)
0: Ach or Bch output (Default)
1: Ach and Bch output
AINCOM: COM Input Setting for Single-ended Input Mode
0: COM Separation (Default)
1: COM Contact (AIN1A-, AIN1B-, AIN2A-, AIN2B- pins)
MDIF1A/B: AIN1A/B Input Setting (Table 22)
0: Single-ended Input (AIN1A+ pin, AIN1B+ pin: Default)
1: Full-differential Input (AIN1A+/- pins, AIN1B+/- pins)
MDIF2A/B: AIN2A/B Input Setting (Table 23)
0: Single-ended Input (AIN2A+ pin, AIN2B+ pin: Default)
1: Full-differential Input (AIN2A+/- pins, AIN2B+/- pins)
Addr
05H
Register Name
MIC Amplifier 1 Gain
R/W
Default
D7
D6
D5
MG1B[3:0]
R/W
0110
D4
D3
D2
D1
MG1A[3:0]
R/W
0110
D0
D3
D2
D1
MG2A[3:0]
R/W
0110
D0
MG1A/B[3:0]: MIC-Amp 1 Ach/Bch Analog Volume (Table 24)
Default: “0110” (+18 dB)
Addr
06H
Register Name
MIC Amplifier 2 Gain
R/W
Default
D7
D6
D5
MG2B[3:0]
R/W
0110
D4
MG2A/B[3:0]: MIC-Amp 2 Ach/Bch Analog Volume (Table 24)
Default: “0110” (+18 dB)
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Addr
07H
Register Name
Digital MIC Setting
R/W
Default
D7
0
R/W
0
D6
DCLKP2
R/W
0
D5
DCLKE2
R/W
0
D4
DMIC2
R/W
0
D3
0
R/W
0
D2
DCLKP1
R/W
0
D1
DCLKE1
R/W
0
D0
DMIC1
R/W
0
D2
D1
D0
DMIC1: Digital Microphone 1 Connection Select
0: Analog Microphone (default)
1: Digital Microphone (DMCLK1, DMDAT1 pins)
DCLKE1: DMCLK1 pin Output Clock Control
0: “L” Output (default)
1: 64fs Output
DCLKP1: DMDAT1 pin Data Latching Edge Select (Table 33)
0: Ach data is latched on the DMCLK1 rising edge (“”). (default)
1: Ach data is latched on the DMCLK1 falling edge (“”).
DMIC2: Digital Microphone 2 Connection Select
0: Analog Microphone (default)
1: Digital Microphone (DMCLK2, DMDAT2 pins)
DCLKE2: DMCLK2 pin Output Clock Control
0: “L” Output (default)
1: 64fs Output
DCLKP2: DMDAT2 pin Data Latching Edge Select
0: Ach data is latched on the DMCLK2 falling edge (“”). (default)
1: Ach data is latched on the DMCLK2 falling edge (“”).
Addr
08H
Register Name
Clock Mode Select
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
D4
D3
CM[1:0]
R/W
00
FS[3:0]
R/W
1010
FS[3:0]: Sampling Frequency Setting
(Table 4, Table 10, Table 11, Table 12, Table 13, Table 14, Table 15)
Default: “1010” (fs = 48kHz)
CM[1:0]: CODEC Master Clock Select
(Table 3, Table 5, Table 10, Table 11, Table 12, Table 13, Table 14, Table 15)
Default: “00” (256fs)
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Addr
Register Name
09H PLL CLK Source Select
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
BCKO
R/W
0
D4
MCKOE
R/W
0
D3
0
R/W
0
D2
0
R/W
0
D1
PLS
R/W
0
D0
0
R/W
0
D2
D1
D0
D2
D1
D0
PLS: PLL Clock Source Select (Table 7)
0: MCKI pin (default)
1: BCLK pin
MCKOE: Master Clock Output Enable (Table 5)
0: Disable (“L” output: Default)
1: Enable
BCKO: BCLK Output Frequency Select at Master Mode (Table 6, Table 14)
0: 32fs (default)
1: 64fs
Addr
0AH
0BH
Register Name
PLL Ref CLK Divider 1
PLL Ref CLK Divider 2
R/W
Default
D7
D6
D5
D4
D3
PLD[15:8]
PLD[7:0]
R/W
00H
PLD[15:0]: PLL Reference Clock Divider Setting (Table 8)
Default: 0000H
Addr
0CH
0DH
Register Name
PLL FB CLK Divider 1
PLL FB CLK Divider 2
R/W
Default
D7
D6
D5
D4
D3
PLM[15:8]
PLM[7:0]
R/W
00H
PLM[15:0]: PLL Feedback Clock Divider Setting (Table 9)
Default: 0000H
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Addr
0EH
Register Name
Audio I/F Format
R/W
Default
D7
0
R/W
0
D6
BCKP
R/W
0
D5
D4
DLC[1:0]
R/W
00
D3
D2
TDM[1:0]
R/W
00
D1
D0
DIF[1:0]
R/W
00
DIF[1:0]: Audio I/F Format Setting (Table 16, Table 17, Table 18, Table 19)
Default: “00” (I2S compatible)
TDM[1:0]: TDM Mode Setting (Table 6, Table 16, Table 17, Table 18, Table 19)
Default: “00” (Stereo Mode)
DLC[1:0]: Data Length Setting (Table 21)
Default: “00” (24-bit Linear)
BCKP: BCLK Edge Setting (Table 20)
0: Falling (default)
1: Rising
Addr
0FH
10H
11H
12H
Register Name
Phase Adjustment 1A
Phase Adjustment 1B
Phase Adjustment 2A
Phase Adjustment 2B
R/W
Default
D7
DLY1AE
DLY1BE
DLY2AE
DLY2BE
R/W
0
D6
0
0
0
0
R/W
0
D5
D4
D3
D2
DLY1A[5:0]
DLY1B[5:0]
DLY2A[5:0]
DLY2B[5:0]
R/W
000000
D1
D0
DLYxA/B[5:0]: Programmable Phase Adjustment Setting (x=1, 2) (Table 34Table 21)
Default: “00H” (1/64fs)
DLYxA/BE: Programmable Phase Adjustment Enable (x=1, 2)
0: Disable (default)
1: Enable
Addr
13H
Register Name
ADC high Pass Filter
R/W
Default
D7
0
R/W
0
D6
D5
ADRST[2:0]
R/W
000
D4
D3
D2
HPF2C[1:0]
R/W
00
D1
D0
HPF1C[1:0]
R/W
00
HPF1/2C[1:0]: HPF1/2 Cut-off Frequency Setting (Table 35)
Default: “00” (3.7Hz @ fs = 48kHz)
ADRST[2:0]: ADC1/2 Initialization Cycle Setting (Table 28)
Default: “000” (1059/fs)
This is a common setting for ADC1 and ADC2.
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Addr
Register Name
D7
D6
D5
14H
Digital Filter Select
ADVF
0
0
R/W
0
R/W
0
R/W
0
R/W
Default
D4
FSTHPF
AD2N
R/W
0
D3
FSTHPF
AD1N
R/W
0
D2
VREFH
R/W
0
D1
D0
HPFAD2N HPFAD1N
R/W
0
R/W
0
HPFAD1N: HPF Control for ADC1
0: ON (default)
1: OFF
When HPFAD1N bit is “0”, the settings of HPF1C[1:0] bits are enabled. When HPFAD1N bit is “1”,
the audio data passes the HPFAD1 block by 0dB gain.
When PMAD1A bit = “1” or PMAD1B bit = “1” (PMDM1A bit = “1” or PMDM1B bit = “1”), set
HPFAD1N bit to “0”.
HPFAD2N: HPF Control for ADC2
0: ON (default)
1: OFF
When HPFAD2N bit is “0”, the settings of HPF2C[1:0] bits are enabled. When HPFAD2N bit is “1”,
the audio data passes the HPFAD2 block by 0dB gain.
When PMAD2A bit = “1” or PMAD2B bit = “1” (PMDM2A bit = “1” or PMDM2B bit = “1”), set
HPFAD2N bit to “0”.
VREFH: VREF Mode Setting
0: Normal Operation (default)
1: Provide the same power supply as AVDD to VREF pin
When the clock is stopped during normal operation, set VREFH bit to “1”.
FSTHPFADxN: ADCx HPF Cut-off Frequency Setting during Initialization Cycle (x=1, 2) (Table 36)
0: The cut-off frequencies during initialization cycle will be high. (default)
1: The setting of HPFxC[1:0] bits are valid.
ADVF: ADC1/2 Digital Filter Mode Select (Table 37)
0: Short Delay Sharp Roll-Off Filter (default)
1: Voice Filter
This is a common setting for ADC1 and ADC2.
Addr
15H
16H
17H
18H
Register Name
MIC Sensitivity Adj.1A
MIC Sensitivity Adj.1B
MIC Sensitivity Adj.2A
MIC Sensitivity Adj.2B
R/W
Default
D7
D6
D5
D4
D3
MS1A[7:0]
MS1B[7:0]
MS2A[7:0]
MS2B[7:0]
R/W
80H
D2
D1
D0
MSxA/B[7:0]: ADCx Ach/Bch Microphone Sensitivity Adjustment (x=1, 2) (Table 38)
Default: “80H” (0dB)
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Addr
19H
1AH
Register Name
Filter 1 Select
Filter 2 Select
R/W
Default
D7
PFTHR1
PFTHR2
R/W
0
D6
0
0
R/W
0
D5
0
0
R/W
0
D4
MIX1
MIX2
R/W
0
D3
LPF12
LPF22
R/W
0
D2
LPF11
LPF21
R/W
0
D1
HPF12
HPF22
R/W
0
D0
HPF11
HPF21
R/W
0
HPFx1/2: HPFx Control (x=1, 2)
0: Disable (default)
1: Enable
When HPFx1/2 bit is “1”, the settings of FHxA[15:0] and FHxB[15:0] bits are enabled. When HPFx1/2
bit is “0”, the audio data passes the HPFx1/2 block by is 0dB gain. (x=1, 2)
LPFx1/2: LPFx Control (x=1, 2)
0: Disable (default)
1: Enable
When LPFx1/2 bit is “1”, the settings of FLxA[15:0] and FlxB[15:0] bits are enabled. When LPFx1/2
bit is “0”, the audio data passes the LPFx1/2 block by is 0dB gain. (x=1, 2)
MIXx: ADCx Mixer Setting (x=1, 2) (Table 39)
0: Through (default)
1: Mix ((Ach + Bch)/2)
PFTHRx: HPFx, LPFx Through Select (x=1, 2)
0: HPFx, LPFx Path (default)
1: Through Path
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Addr
1BH
Register Name
VAD Setting 1
R/W
Default
D7
VALPF2
R/W
0
D6
VALPF1
R/W
0
D5
VAHPF2
R/W
0
D4
VAHPF1
R/W
0
D3
HPF3RD
R/W
0
D2
VADSEL
R/W
0
D1
DLYE
R/W
0
D0
VADOE
R/W
0
VADOE: VADO Output Signal Select
0: ADC1 or Programmable Filter 1 output (default)
1: VADO output
DLYE: VAD Input Data Delay Setting (Table 55)
0: No Delay (default)
1: 2048 Samples (128ms @ fs=16kHz)
VADSEL: Input signal Select for VAD (Table 54)
0: ADC output (default)
1: HPF/LPF output
HPF3RD: HPF Setting for VALPF1
0: Use VALPF1 as LPF (default)
1: Use VALPF1 as HPF (3rd order HPF combined with VAHPF1/2)
VAHPF1/2: VAHPF1/2 Control
0: Disable (default)
1: Enable
When VAHPF1, VAHPF2 and HPF3RD bit = “1”, the settings of VFHA[15:0] and VFHB[15:0] bits are
enabled. When VAHPF1 bit is “0” (VAHPF2 bit = “0”), the audio data passes the VAHPF1 (VAHPF2)
block by is 0dB gain.
VALPF1/2: VALPF1/2 Control
0: Disable (default)
1: Enable
When VALPF1/2 bit is “1”, the settings of VAFLA[15:0] and VAFLB[15:0] bits are enabled. When
VALPF1 bit is “0” (VALPF2 bit = “0”), the audio data passes the VALPF1 (VALPF2) block by is 0dB
gain.
Addr
1CH
Register Name
VAD Setting 2
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
PT[7:0]
R/W
07H
PT[7:0]: Noise Level Detector Peak Value Setting (Table 56)
Default: 07H, Number of Sample = 8
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Addr
1DH
1EH
1FH
Register Name
VAD Setting 3
VAD Setting 4
VAD Setting 5
R/W
Default
D7
D6
VADINS[1:0]
D5
D4
D3
NLLIM[1:0]
0
MINTH[15:8]
MINTH[7:0]
R/W
00001FH
D2
0
D1
0
D0
MINTH16
MINTH[16:0]: Minimum Noise Level Setting (Table 59)
Default: 0001FH, -72.2dB
NLLIM[1:0]: Rising Limit Select at NL Update (Table 58)
Default: 00, No limit
VADINS[1:0]: VAD Input Path Select (Table 54)
Default: 00 (AIN1A)
Addr
20H
21H
Register Name
VAD Setting 6
VAD Setting 7
R/W
Default
D7
D6
D5
D4
D3
D2
D1
NLDTH[11:8]
D0
D4
D3
ONGT[7:0]
OFFGT[7:0]
R/W
010FH
D2
D1
D0
D4
D2
D1
VAS[2:0]
R/W
000
D0
AT[3:0]
NLDTH[7:0]
R/W
7200H
AT[3:0]: Noise Level Detector Average Value Setting (Table 57)
Default: “0111”, Number of Sample = 256
NLDTH[11:0]: Noise Level Threshold (Table 60)
Default: 200H, +12.0dB
Addr
22H
23H
Register Name
VAD Setting 8
VAD Setting 9
R/W
Default
D7
D6
D5
ONGT[7:0]: On Guard Timer Setting (Table 61)
Default: 01H, 2 times
OFFGT[7:0]: Off Guard Timer Setting (Table 62)
Default: 0FH, 4096/fs (256ms)
Addr
24H
Register Name
VAD Setting 10
R/W
Default
D7
VONT
R/W
0
D6
D5
VBS[2:0]
R/W
000
D3
0
R/W
0
VAS[2:0], VBS[2:0]: Output Selector Setting (Table 63)
Default: “000”, VDLYO[15:0]
VONT: NL Non-updated Time Setting at VON Detection
Default: “0”, 4s@fs=16kHz
“1”, 2s@fs=16kHz
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Addr
25H
Register Name
ALC Select
R/W
Default
D7
FRN
R/W
0
D6
ATTLIM2
R/W
0
D5
ATTLIM1
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D2
ALC4
R/W
0
D1
ALC2
R/W
0
D0
ALC1
R/W
0
ALCx: ALCx Enable (x=1, 2) (Table 41)
0: ALCx Disable (default)
1: ALCx Enable
ALC4: ALC 4ch Link Enable (Table 41)
0: ALC 4ch Link Disable (default)
1: ALC 4ch Link Enable
ATTLIMx: ALCx ATT Limiter Enable (x=1, 2)
0: ATT Limiter Disable (default)
1: ATT Limiter Enable
When ALC 4ch Link Mode is selected (ALC4 bit = “1”), it is controlled by ATTLIM1 bit and ATTLIM2
bit should be set to “0”.
FRN: Fast Recovery Disable
0: Fast Recovery Enable (default)
1: Fast Recovery Disable
Addr
26H
Register Name
ALC Control 1
R/W
Default
D7
D6
IVTM[1:0]
R/W
01
D5
0
R/W
0
D4
ALCEQN
R/W
0
D3
D2
FRATT[1:0]
R/W
00
D1
D0
WTM[1:0]
R/W
00
WTM[1:0]: ALC Recovery Waiting Period (Table 44)
Default: 00 (128fs)
FRATT[1:0]: Fast Recovery Reference Volume Attenuation Step (Table 48)
Default: 00 (-0.00106dB: 4/fs)
ALCEQN: ALCEQ Disable
0: ALCEQ Enable (default)
1: ALCEQ Disable
IVTM[1:0]: Input Digital Volume Soft Transition Time Setting (Table 51)
Default: 01 (944/fs)
Addr
Register Name
27H Input Digital Volume 1A
28H Input Digital Volume 1B
R/W
Default
D7
D6
D5
D4
D3
IV1A[7:0]
IV1B[7:0]
R/W
91H
D2
D1
D0
D4
D3
REF1[7:0]
R/W
E1H
D2
D1
D0
IVxA/B[7:0]: Digital Input Volume (x=1, 2) (Table 50)
Default: “91H” (0dB)
Addr
29H
Register Name
ALC1 Reference Level
R/W
Default
D7
D6
D5
REF1[7:0]: Reference Value at ALC Recovery Operation (Table 46)
Default: “E1H” (+30dB)
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Addr
2AH
Register Name
ALC1 Control
R/W
Default
D7
IVOL1C
R/W
1
D6
D5
RGAIN1[2:0]
R/W
000
D4
D3
D2
RFST1[1:0]
R/W
00
D1
D0
LMTH1[1:0]
R/W
00
LMTH1[1:0]: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 42)
Default: 00
RFST1[1:0]: ALC Fast Recovery Speed (Table 47)
Default: 00 (0.000265dB)
RGAIN1[2:0]: ALC Recovery Gain Step (Table 45)
Default: 000 (0.00212dB)
IVOL1C: Input Digital Volume Control Mode
0: Independent
1: Dependent (default)
When IVOL1C bit = “1”, IV1A[7:0] bits control both Ach and Bch volume levels, while register values
of IV1A[7:0] bits are not written to IV1B[7:0] bits.
Addr
Register Name
2BH Input Digital Volume 2A
2CH Input Digital Volume 2B
R/W
Default
D7
D6
D5
D4
D3
IV2A[7:0]
IV2B[7:0]
R/W
91H
D2
D1
D0
D5
D4
D3
REF2[7:0]
R/W
E1H
D2
D1
D0
IV2A/B[7:0]: Digital Input Volume (Table 50)
Default: “91H” (0dB)
Addr
2DH
Register Name
ALC2 Reference Level
R/W
Default
D7
D6
REF2[7:0]: Reference Value at ALC Recovery Operation (Table 46)
Default: “E1H” (+30dB)
Addr
2EH
Register Name
ALC2 Control
R/W
Default
D7
IVOL2C
R/W
1
D6
D5
RGAIN2[2:0]
R/W
000
D4
D3
D2
RFST2[1:0]
R/W
00
D1
D0
LMTH2[1:0]
R/W
00
LMTH2[1:0]: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 42)
Default: 00
RFST2[1:0]: ALC Fast Recovery Speed (Table 47)
Default: 00 (0.000265dB)
RGAIN2[2:0]: ALC Recovery Gain Step (Table 45)
Default: 000 (0.00212dB)
IVOL2C: Input Digital Volume Control Mode
0: Independent
1: Dependent (default)
When IVOL2C bit = “1”, IV2A[7:0] bits control both Ach and Bch volume levels, while register values
of IV2A[7:0] bits are not written to IV2B[7:0] bits.
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Addr
2FH
30H
31H
32H
Register Name
HPF1 Coefficient A
HPF1 Coefficient A
HPF1 Coefficient B
HPF1 Coefficient B
R/W
Default
D7
D6
D5
D4
D3
FH1A[15:8]
FH1A[7:0]
FH1B[15:8]
FH1B[7:0]
R/W
D2
D1
D0
FH1A[15:0] bits = 7EC1H, FH1B[15:0] bits = 827DH
FH1A[15:0], FH1B[15:0]: HPF1 Coefficient
Default: FH1A[15:0] bits = 7EC1H, FH1B[15:0] bits = 827DH (fc=150Hz@fs=48kHz)
Addr
33H
34H
35H
36H
Register Name
LPF1 Coefficient A
LPF1 Coefficient A
LPF1 Coefficient B
LPF1 Coefficient B
R/W
Default
D7
D6
D5
D4
D3
FL1A[15:8]
FL1A[7:0]
FL1B[15:8]
FL1B[7:0]
R/W
00H
D2
D1
D0
D5
D4
D3
FH2A[15:8]
FH2A[7:0]
FH2B[15:8]
FH2B[7:0]
R/W
D2
D1
D0
FL1A[15:0], FL1B[15:0]: LPF1 Coefficient
Default: 0000H
Addr
37H
38H
39H
3AH
Register Name
HPF2 Coefficient A
HPF2 Coefficient A
HPF2 Coefficient B
HPF2 Coefficient B
R/W
Default
D7
D6
FH2A[15:0] bits = 7EC1H, FH2B[15:0] bits = 827DH
FH2A[15:0], FH2B[15:0]: HPF2 Coefficient
Default: FH2A[15:0] bits = 7EC1H, FH2B[15:0] bits = 827DH (fc=150Hz@fs=48kHz)
Addr
3BH
3CH
3DH
3EH
Register Name
LPF2 Coefficient A
LPF2 Coefficient A
LPF2 Coefficient B
LPF2 Coefficient B
R/W
Default
D7
D6
D5
D4
D3
FL2A[15:8]
FL2A[7:0]
FL2B[15:8]
FL2B[7:0]
R/W
00H
D2
D1
D0
D5
D4
D3
VFHA[15:8]
VFHA[7:0]
VFHB[15:8]
VFHB[7:0]
R/W
D2
D1
D0
FL2A[15:0], FL2B[15:0]: LPF2 Coefficient
Default: 0000H
Addr
3FH
40H
41H
42H
Register Name
VAHPF Coefficient A
VAHPF Coefficient A
VAHPF Coefficient B
VAHPF Coefficient B
R/W
Default
D7
D6
VFHA[15:0] bits = 78DFH, VFHB[15:0] bits = 8E42H
VFHA[15:0], VFHB[15:0]: VAHPF Coefficient
Default: VFHA[15:0] bits = 78DFH, VFHB[15:0] bits = 8E42H (fc=300Hz@fs=16kHz)
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Addr
43H
44H
45H
46H
Register Name
VAPF Coefficient A
VAHF Coefficient A
VAPF Coefficient B
VAPF Coefficient B
R/W
Default
D7
D6
D5
D4
D3
VFLA[15:8]
VFLA[7:0]
VFLB[15:8]
VFLB[7:0]
R/W
00H
D2
D1
D0
VFLA[15:0], VFLB[15:0]: VALPF Coefficient
Default: 0000H
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10. Recommended External Circuits
Figure 56 and Figure 57 show the system connection diagrams. An evaluation board (AKD5704) is
available for fast evaluation as well as suggestions for peripheral circuitry.
Power Supply
1.71.9V
or 3.0~3.6V
Analog Ground
0.1u
2.2k
2.2u
1u
19
18
17
16
15
MPWR2
AVDD
VSS1
VCOM
VREF
22 AIN2A-
20
1u
AIN2B-
21
MIC4
PDN
14
TVDD
13
VSS2
12
VDD12
11
26 AIN1A-
MCKI
10
27 AIN1A+
MCKO
9
BCLK
8
23 AIN2A+
1u
AK5704
1u
25 AIN1B+
10u
2.2u
Top View
1u
MIC1
Power Supply
1.653.6V
0.1u
24 AIN1BMIC2
Digital Ground
2.2u
AIN2B+
2.2k
2.2k
1u
1u
MIC3
DMDAT
10u
1u
CAD
SCL
SDA
WINTN
SDTO1
TDMIN
/SDTO2
LRCK
1
2
3
4
5
6
7
28 MPWR1
2.2k
DSP
or
SoC
100k
“H” (TVDD)
or “L” (VSS2)
R
R
µP
Note:
- VSS1 and VSS2 of the AK5704 must be distributed separately from the ground of external controllers.
- All digital input pins must not be allowed to float.
- Negative input pins must be connected to VSS1 with same value capacitor in series.
- SCL, SDA pins must be pulled-up by the resistor (R).
- If WINTN pin is used, WINTN pin is a Hi-Z state at power-down. WINTN pin should be pulled-up to
TVDD by the resistor (about 100kΩ) externally to avoid the floating state.
Figure 56. System Connection Diagram (Single-ended Input, EXT Slave Mode)
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Power Supply
1.71.9V
or 3.0~3.6V
Analog Ground
0.1u
1k
2.2u
1u
19
18
17
16
15
MPWR2
AVDD
VSS1
VCOM
VREF
22 AIN2A-
20
1u
AIN2B-
21
MIC4
MIC3
PDN
14
TVDD
13
VSS2
12
VDD12
11
26 AIN1A-
MCKI
10
27 AIN1A+
MCKO
9
BCLK
8
23 AIN2A+
1u
Power Supply
1.653.6V
0.1u
24 AIN1B-
AK5704
1u
MIC2
Digital Ground
2.2u
1u
AIN2B+
1k
1u
1k
DMDAT
10u
25 AIN1B+
10u
2.2u
Top View
1u
1u
1k
CAD
SCL
SDA
WINTN
SDTO1
TDMIN
/SDTO2
LRCK
2
3
4
5
6
7
28 MPWR1
1k
1
1k
1k
1k
MIC1
DSP
or
SoC
100k
“H” (TVDD)
or “L” (VSS2)
R
R
µP
Note:
- VSS1 and VSS2 of the AK5704 must be distributed separately from the ground of external controllers.
- All digital input pins must not be allowed to float.
- SCL, SDA pins must be pulled-up by the resistor (R).
- If WINTN pin is used, WINTN pin is a Hi-Z state at power-down. WINTN pin should be pulled-up to
TVDD by the resistor (about 100kΩ) externally to avoid the floating state.
Figure 57. System Connection Diagram (Full-differential Input, EXT Slave Mode)
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1. Grounding and Power Supply Decoupling
The AK5704 requires careful attention to power supply and grounding arrangements. AVDD is usually
supplied from the system’s analog supply, and TVDD is supplied from the system’s digital power supply.
If AVDD and TVDD are supplied separately, the power-up sequence is not critical. The PDN pin should be
held “L” when power supplies are tuning on. The PDN pin is allowed to be “H” after all power supplies are
applied and settled.
1) Power-up
・The PDN pin should be held “L” when power supplies are turning on. The AK5704 can be reset by
keeping the PDN pin “L” for 1ms or longer after all power supplies are applied and settled. When the
PDN pin = “H”, LDO12 powers up and outputs a regulated voltage (typ. 1.2V) from the VDD12 pin.
LDO12 is supplied to the digital core. The VDD12 pin must be connected to the VSS2 pin with a
2.2μF ±50% ceramic capacitor in series. No load current may be drawn from the VDD12 pin.
2) Power-down
・Each of power supplies can be powered OFF after the PDN pin is set to “L”.
VSS1 and VSS2 of the AK5703 should be connected to the analog ground plane. System analog ground
and digital ground should be wired separately and connected together as close as possible to where the
supplies are brought onto the printed circuit board. Decoupling capacitors should be as close the power
supply pins as possible. Especially, the small value ceramic capacitor is to be closest.
2. Reference Voltage
VREF is an analog reference voltage output from the VREF pin. This pin must be connected to the VSS1
pin with a 2.2μF ±50% ceramic capacitor in series. VCOM is a signal ground of this chip. A 2.2F ±50%
capacitor attached to the VSS1 pin eliminates the effects of high frequency noise. This capacitor should
be placed as near as possible to the AK5704. No load current may be drawn from the VREF pin and the
VCOM pin. All signals, especially clocks, should be kept away from the VREF pin and the VCOM pin in
order to avoid unwanted coupling into the AK5704.
3. Analog Inputs
The analog inputs are single-ended or full-differential and input resistance is 200k (typ). The input signal
range scales with nominally 2.02 x AVDD/3.3 Vpp (typ) (@ MIC-Amp Gain = 0dB), centered around the
internal signal ground (0.5 x AVDD). Usually the input signal is AC coupled with a capacitor. The cut-off
frequency is fc = 1/(2RC). The ADC output data format is 2’s complement. The DC offset including the
ADC’s own DC offset is removed by the internal HPF (fc=1.23Hz@ HPF1/2C[1:0] bits = “00”, fs=16kHz).
An AINx- pin must be connected to VSS1 via a capacitor with the same capacitance as the AINx+ pin
when single-ended input.
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11. Control Sequence
11.1.
Clock Set Up
When the AK5704 is in operation, the clocks must be supplied.
11.1.1. PLL Master Mode
Example:
Power Supply
PDN pin
≥1ms
Audio I/F Format: I2S, 24-bit
Input Master Clock Frequency: 12MHz
Output BCLK Frequency: 64fs
MCKO: Enable (256fs)
Sampling Frequency: 48kHz
(1)
VDD12 pin
Flow Control
≥1ms
(1) Power Supply & PDN pin = “L” → “H”
(2)
(Addr:00H)
(2) Addr:00H, Data:67H
Addr:01H, Data:80H
Addr:08H, Data:0AH
Addr:09H, Data:30H
Addr:0AH, Data:00H
Addr:0BH, Data:18H
Addr:0CH, Data:00H
Addr:0DH, Data:7FH
Addr:0EH, Data:00H
PMVCM bit
(Addr:01H, D7)
Clock Mode Select
(Addr:08H)
PLL CLK Source Select
(Addr:09H)
PLL Ref CLK Divider 1, 2
(Addr:0AH, 0BH)
(3)Addr:01H, Data:C0H
PLL FB CLK Divider 1, 2
(Addr:0CH, 0DH)
Audio I/F Format
(4)MCKI Input
(Addr:0EH)
PMPLL bit
(Addr:01H, D6)
≥ 5ms
(3)
MCKO, BCLK and LRCK output
(4)
MCKI pin
Input
3ms (max)
BCLK pin
LRCK pin
Output
3ms (max)
MCKO pin
(6)
(5)
(8)
Output
(7)
Figure 58. Clock Set Up Sequence (1)
(1) After Power Up: PDN pin “L” → “H”
“L” time of 1ms or more is needed to reset the AK5704. After the PDN pin = “H”, wait time of 1ms
or more is needed to power up VDD12.
(2) Power Up VCOM and VREF: PMVCM bit = “0” → “1”
PSW0N, PSW1N, FS[3:0], CM[1:0], MSN, PLS, PLLMD, MCKOE, BCKO, PLD[15:0], PLM[15:0],
DIF[1:0], TDM[1:0], DLC[1:0], BCKP and SDTO2E bits must be set during this period.
VCOM and VREF must first be powered-up before the other block operates. Power up time is
5.0ms (max) when the capacitance of an external capacitor for the VCOM and the VREF pin is
2.2μF ±50% each.
In case of using MCKO output: MCKOE bit = “1”
In case of not using MCKO output: MCKOE bit = “0”
(3) Power Up PLL: PMPLL bit = “0” → “1”
(4) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source,
and PLL lock time is 3ms (max).
(5) BCLK pin and LRCK pin output “L” during this period.
(6) The AK5704 starts outputting BCLK and LRCK clocks after the PLL becomes stable. Then normal
operation starts.
(7) The invalid frequency is output from the MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from the MCKO pin after the PLL is locked if MCKO bit = “1”.
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11.1.2. PLL Slave Mode (BCLK pin)
Example:
Power Supply
PDN pin
Audio I/F Format: I2S, 24-bit
PLL Reference Clock: BCLK
Input BCLK Frequency: 64fs
Sampling Frequency: 48kHz
(1)
≥1ms
VDD12 pin
Flow Control
(1) Power Supply & PDN pin = “L” → “H”
≥1ms
(2)
(Addr:00H)
(2) Addr:00H, Data:47H
Addr:01H, Data:80H
Addr:08H, Data:0AH
Addr:09H, Data:02H
Addr:0AH, Data:00H
Addr:0BH, Data:07H
Addr:0CH, Data:00H
Addr:0DH, Data:9FH
Addr:0EH, Data:00H
PMVCM bit
(Addr:01H, D7)
Clock Mode Select
(Addr:08H)
PLL CLK Source Select
(Addr:09H)
PLL Ref CLK Divider 1, 2
(Addr:0AH, 0BH)
(3)Addr:01H, Data:C0H
PLL FB CLK Divider 1, 2
(Addr:0CH, 0DH)
(4)BCLK Input
Audio I/F Format
(Addr:0EH)
PMPLL bit
(Addr:01H, D6)
≥ 5ms
(3)
Internal Clock start
(4)
BCLK pin
Internal Clock
Input
3ms (max)
(5)
Figure 59. Clock Set Up Sequence (2)
(1) After Power Up: PDN pin “L” → “H”
“L” time of 1ms or more is needed to reset the AK5704. After the PDN pin = “H”, wait time of 1ms
or more is needed to power up VDD12.
(2) Power Up VCOM and VREF: PMVCM bit = “0” → “1”
PSW0N, PSW1N, FS[3:0], CM[1:0], MSN, PLS, PLLMD, PLD[15:0], PLM[15:0], DIF[1:0], TDM[1:0],
DLC[1:0], BCKP and SDTO2E bits must be set during this period.
VCOM and VREF must first be powered-up before the other block operates. Power up time is
5.0ms (max) when the capacitance of an external capacitor for the VCOM and the VREF pin is
2.2μF ±50% each.
(3) Power Up PLL: PMPLL bit = “0” → “1”
(4) PLL starts after PMPLL bit changes from “0” to “1” and PLL reference clock is supplied from BCLK
pin. The time until PLL is locked and the clock is supplied to internal circuits is 3ms (max).
(5) The AK5704 starts normal operation after the PLL became stable and the internal clock is
generated.
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11.1.3. PLL Slave Mode (MCKI pin)
Example:
Power Supply
Audio I/F Format: I2S, 24-bit
PLL Reference Clock: MCKI (12MHz)
MCKO: Enable (256fs)
BCLK Frequency: 64fs
Sampling Frequency: 48kHz
(1)
≥1ms
PDN pin
VDD12 pin
Flow Control
≥1ms
(1) Power Supply & PDN pin = “L” → “H”
(2)
(Addr:00H)
(2) Addr:00H, Data:47H
Addr:01H, Data:80H
Addr:08H, Data:0AH
Addr:09H, Data:10H
Addr:0AH, Data:00H
Addr:0BH, Data:18H
Addr:0CH, Data:00H
Addr:0DH, Data:7FH
Addr:0EH, Data:00H
PMVCM bit
(Addr:01H, D7)
Clock Mode Select
(Addr:08H)
PLL CLK Source Select
(Addr:09H)
PLL Ref CLK Divider 1, 2
(Addr:0AH, 0BH)
(3)Addr:01H, Data:C0H
PLL FB CLK Divider 1, 2
(Addr:0CH, 0DH)
Audio I/F Format
(4)MCKI Input
(Addr:0EH)
PMPLL bit
(Addr:01H, D6)
≥ 5ms
(3)
MCKO output start
(4)
MCKI pin
Input
BCLK and LRCK input start
3ms (max)
(5)
MCKO pin
Output
(6)
(7)
BCLK pin
LRCK pin
Input
Figure 60. Clock Set Up Sequence (3)
(1) After power Up: PDN pin “L” → “H”
“L” time of 1ms or more is needed to reset the AK5704. After the PDN pin = “H”, wait time of 1ms
or more is needed to power up VDD12.
(2) Power Up VCOM and VREF: PMVCM bit = “0” → “1”
PSW0N, PSW1N, FS[3:0], CM[1:0], MSN, PLS, PLLMD, MCKOE, PLD[15:0], PLM[15:0], DIF[1:0],
TDM[1:0], DLC[1:0], BCKP and SDTO2E bits must be set during this period.
VCOM and VREF must first be powered-up before the other block operates. Power up time is
5.0ms (max) when the capacitance of an external capacitor for the VCOM and the VREF pin is
2.2μF ±50% each.
(3) Power Up PLL: PMPLL bit = “0” → “1”
(4) PLL starts after PMPLL bit changes from “0” to “1” and PLL reference clock is supplied from MCKI
pin. The time until PLL is locked and starts normal output is 3ms (max).
(5) The normal clock is output from the MCKO pin after the PLL became stable.
(6) The invalid frequency is output from the MCKO pin during this period.
(7) BCLK and LRCK clocks must be synchronized with MCKO clock.
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11.1.4. External Slave Mode
Example:
Power Supply
Audio I/F Format: I2S, 24-bit
Input Master Clock Frequency: 256fs
Input BCLK Frequency: 64fs
Sampling Frequency: 48kHz
(1)
≥1ms
PDN pin
VDD12 pin
Flow Control
≥1ms
(1) Power Supply & PDN pin = “L” → “H”
(2)
(Addr:00H)
(2) Addr:00H, Data:47H
Addr:01H, Data:80H
Addr:08H, Data:0AH
Addr:09H, Data:00H
Addr:0EH, Data:00H
PMVCM bit
(Addr:01H, D7)
Clock Mode Select
(Addr:08H)
PLL CLK Source Select
(Addr:09H)
(3)MCKI, BCLK, LRCK Input
Audio I/F Format
(Addr:0EH)
≥5ms
(3)
MCKI pin
Input
BCLK pin
LRCK pin
Input
Figure 61. Clock Set Up Sequence (4)
(1) After Power Up: PDN pin “L” → “H”
“L” time of 1ms or more is needed to reset the AK5704. After the PDN pin = “H”, wait time of 1ms
or more is needed to power up VDD12.
(2) Power Up VCOM and VREF: PMVCM bit = “0” → “1”
PSW0N, PSW1N, FS[3:0], CM[1:0], MSN, DIF[1:0], TDM[1:0], DLC[1:0], BCKP and SDTO2E bits
must be set during this period.
VCOM and VREF must first be powered-up before the other block operates. Power up time is
5.0ms (max) when the capacitance of an external capacitor for the VCOM and the VREF pin is
2.2μF ±50% each.
(3) Normal operation starts after the MCKI, BCLK and LRCK are supplied.
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11.1.5. External Master Mode
Power Supply
PDN pin
Example:
(1)
≥1ms
Audio I/F Format: I2S, 24-bit
Input Master Clock Frequency: 12.288MHz
Output BCLK Frequency: 64fs
Sampling Frequency: 48kHz
VDD12 pin
Flow Control
≥1ms
(1) Power Supply & PDN pin = “L” → “H”
(3)
(Addr:00H)
(4)
(2)MCKI input
PMVCM bit
(Addr:01H, D7)
(3) Addr:00H, Data:67H
Addr:08H, Data:0AH
Addr:0EH, Data:00H
Addr:09H, Data:20H
Clock Mode Select
(Addr:08H)
Audio I/F Format
(Addr:0EH)
MSN, BCKO bits
(Addr:09H, D0,D5)
BCLK, LRCK output
(2)
MCKI pin
Input
BCLK pin
LRCK pin
Output
(4) Addr:01H, Data:80H
Figure 62. Clock Set Up Sequence (5)
(1) After Power Up: PDN pin “L” → “H”
“L” time of 1ms or more is needed to reset the AK5704. After the PDN pin = “H”, wait time of 1ms
or more is needed to power up VDD12.
(2) MCKI is supplied.
(3) After SW0N, PSW1N, FS[3:0], CM[1:0], DIF[1:0], TDM[1:0], DLC[1:0], BCKP and SDTO2E bits are
set, MSN and BCKO bits should be set to “1”.
Then BCLK and LRCK are output.
(4) Power Up VCOM and VREF: PMVCM bit = “0” → “1”
VCOM and VREF must first be powered-up before the other block operates. Power up time is
5.0ms (max) when the capacitance of an external capacitor for the VCOM and the VREF pin is
2.2μF ±50% each.
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11.2.
Voice Activity Detection (1ch Mic)
S Audio I/F Format: I2S, 16-bit
Sampling Frequency: 16kHz
MIC AMP Gain: +18dB
VAHPF1/2: On
AIRST[2:0] bits
PFSDO1/2 bit 000,00
(Addr:03H, D7-5,D3-2)
MIC-amp Gain
(Addr:05H, D3-0)
Example:
(1) Addr:03H, Data:CCH
110,11
(1)
(2) Addr:05H, Data:66H
0110
0110
(2)
(3)
PMAIN1A bit
PMMP1 bit
(Addr:01H, D4,D0)
ADC HPF Setting
(Addr:13H)
(10)
> 16.0ms
(4) Addr:13H, Data:71H
00H
(5) Addr:14H, Data:80H
71H
(4)
Digital Filter Select
(Addr:14H, D7)
00H
(6) Addr:1BH, Data:30H
Addr:1CH, Data:07H
Addr:1DH, Data:00H
Addr:1EH, Data:00H
Addr:1FH, Data:1FH
Addr:20H, Data:72H
Addr:21H, Data:00H
Addr:22H, Data:01H
Addr:23H, Data:0FH
Addr:24H, Data:00H
80H
(5)
VAD Setting
(Addr:1B-24H)
xx…..x
xx…..x
(6)
Filter Co-ef
(Addr:3F-42H)
PMAD1A bit
(3) Addr:01H, Data:91H
xx…..x
xx…..x
(7) (8)
(Addr:02H, D0)
(7) Addr: 3FH ~ 42H
PMVAD bit
PMPFIL1 bit
(8) Addr:02H, Data:01H
Addr:03H, Data:DDH
(Addr:03H, D4,D0)
SDTO1 pin
Initialize
40/fs
Data (ADC1A)
(9) WINTN pin “H” → “L”
SDTO2 pin
(9)
WINTN pin
VAD Standby
Data Output
Detect
(10) Addr:02H, Data:00H
Addr:03H, Data:CCH
Addr:01H, Data:80H
Figure 63. Voice Activity Detection (1ch Mic) Sequence
This sequence is an example of VAD setting at fs=16kHz. At first, clocks should be supplied according to
“Clock Set Up” sequence.
(1) Set Up AIN Initialization Cycle and Signal Path: AIRST[2:0] bits = “110” (256/fs), PFSDO1/2 bits =
“1”
(2) Set Up Microphone Amp Gain: MG1A[3:0] bits = “0110” (+18dB)
(3) Power Up Microphone Power 1 and Microphone Amp 1A: PMAIN1A = PMMP1 bits = “1”
The initialization cycle time of AIN1A is 256/fs=16ms @ fs=16kHz.
(4) Set Up ADC1 Initialization Cycle: ADRST[2:0] bits = “111” (32/fs)
Set Up HPF1 Cut-off Frequency: HPF1C[1:0] bits = “01” (fc = 4.9Hz)
(5) Set Up ADC Digital Filter: ADVF bit = “1” (Voice Filter)
(6) Set Up VAD:
VAHPF1 = VAHPF2 bits = “1”, PT[7:0] bits = 07H, MINTH[16:0] bits = 0001FH, AT[3:0] bits = “0111”,
NLDTH[11:0] bits = 200H, ONGT[7:0] bits = 01H, OFFGT[7:0] bits = 0FH, VAS[2:0] = VBS[2:0] bits
= “000”
(7) Set Up Coefficient of VAHPF1/2 (Addr: 3FH ~ 42H)
(8) Power Up ADC1, VAD and Programmable Filter 1:
PMAD1A = PMVAD = PMPFIL1 bits = “0” → “1”
The initialization cycle time of ADC is 32/fs=2ms @ fs=16kHz.
(9) Voice Activity Detection: WINTN pin = “H” → “L”
When the voice activity is detected, the WINTN pin changes from “H” to “L”. The “L” period is
256/fs=16ms @fs = 16kHz(min.).
(10) Power Down ADC1, VAD and Programmable Filter 1:
PMAD1A = PMVAD = PMPFIL1 bits = “1” → “0”
Power Down Microphone Power 1 and Microphone 1A: PMAIN1A = PMMP1 bits = “1” → “0”
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11.3.
Voice Activity Detection (4ch Mic)
Example:
S Audio I/F Format: I2S, 16-bit
Sampling Frequency: 16kHz
MIC AMP Gain: +18dB
VAHPF1/2: On
AIRST[2:0] bits
PFSDO1/2 bit 000,00
(Addr:03H, D7-5,D3-2)
MIC-amp Gain
(Addr:05H, 06H)
(1) Addr:03H, Data:CCH
110,11
(1)
66H
(2) Addr:05H, Data:66H
Addr:06H, Data:66H
66H
(2)
(3)
PMAIN1A/B bits
PMAIN2A/B bits
PMMP1/2 bits
(10)
> 16.0ms
(4) Addr:13H, Data:75H
(Addr:01H)
ADC HPF Setting
(Addr:13H)
00H
(5) Addr:14H, Data:80H
75H
(4)
Digital Filter Select
(Addr:14H, D7)
00H
(6) Addr:1BH, Data:30H
Addr:1CH, Data:07H
Addr:1DH, Data:00H
Addr:1EH, Data:00H
Addr:1FH, Data:1FH
Addr:20H, Data:72H
Addr:21H, Data:00H
Addr:22H, Data:01H
Addr:23H, Data:0FH
Addr:24H, Data:00H
80H
(5)
VAD Setting
(Addr:1B-24H)
xx…..x
xx…..x
(6)
Filter Co-ef
(Addr:3F-42H)
PMAD1A/B bit
PMAD2A/B bits
xx…..x
xx…..x
(7) (8)
(7) Addr: 3FH ~ 42H
(Addr:02H, D3-0)
PMVAD bit
PMPFIL1/2 bit
(8) Addr:02H, Data:0FH
Addr:03H, Data:DFH
(Addr:03H, D4,D1-0)
SDTO1 pin
Initialize
40/fs
Data (ADC1A/B)
SDTO2 pin
Data (ADC2A/B)
(9)
WINTN pin
(3) Addr:01H, Data:BFH
Detect
VAD Standby
Data Output
(9) WINTN pin “H” → “L”
(10) Addr:02H, Data:00H
Addr:03H, Data:CCH
Addr:01H, Data:80H
Figure 64. Voice Activity Detection (4ch Mic) Sequence
This sequence is an example of VAD setting at fs=16kHz. At first, clocks should be supplied according to
“Clock Set Up” sequence.
(1) Set Up AIN Initialization Cycle and Signal Path: AIRST[2:0] bits = “110” (256/fs), PFSDO1/2 bits =
“1”
(2) Set Up Microphone Amp Gain (Addr = 05H, 06H)
(3) Power Up Microphone Power 1/2, Microphone Amp 1A/B and Microphone Amp 2A/B: PMAIN1A/B
= PMAIN2A/B = PMMP1/2 bits = “1”
The initialization cycle time of AIN1/2 is 256/fs=16ms @ fs=16kHz.
(4) Set Up ADC1/2 Initialization Cycle: ADRST[2:0] bits = “111” (32/fs)
Set Up HPF1/2 Cut-off Frequency: HPF1/2C[1:0] bits = “01” (fc = 4.9Hz)
(5) Set Up ADC Digital Filter: ADVF bit = “1” (Voice Filter)
(6) Set Up VAD:
VAHPF1 = VAHPF2 bits = “1”, PT[7:0] bits = 07H, MINTH[16:0] bits = 0001FH, AT[3:0] bits = “0111”,
NLDTH[11:0] bits = 200H, ONGT[7:0] bits = 01H, OFFGT[7:0] bits = 0FH, VAS[2:0] = VBS[2:0] bits
= “000”
(7) Set Up Coefficient of VAHPF1/2 (Addr: 3FH ~ 42H)
(8) Power Up ADC1/2, VAD and Programmable Filter 1/2:
PMAD1A/B = PMAD2A/B = PMVAD = PMPFIL1/2 bits = “0” → “1”
The initialization cycle time of ADC is 32/fs=2ms @ fs=16kHz.
(9) Voice Activity Detection: WINTN pin = “H” → “L”
When the voice activity is detected, the WINTN pin changes from “H” to “L”. The “L” period is
256/fs=16ms @fs = 16kHz(min.).
(10) Power Down ADC1/2, VAD and Programmable Filter 1/2:
PMAD1A/B = PMAD2A/B = PMVAD = PMPFIL1/2 bits = “1” → “0”
Power Down Microphone Power 1/2, Microphone 1A/B and Microphone Amp 2A/B:
PMAIN1A/B = PMAIN2A/B = PMMP1/2 bits = “1” → “0”
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11.4.
Microphone Input Recording (4ch)
AIRST[2:0] bits
PFSDO1/2 bit 000,00
(Addr:03H, D7-5,D3-2)
MIC-amp Gain
(Addr:05H, 06H)
Example:
000,11
Sampling Frequency: 48kHz
MIC AMP Gain: +18dB
ALC setting Refer to Table 39
HPF1/2, LPF1/2: On
(1)
66H
66H
(1) Addr:03H, Data:0CH
(2)
(3)
PMAIN1A/B bits
PMAIN2A/B bits
PMMP1/2 bits
> 13.7ms
(2) Addr:05H, Data:66H
Addr:06H, Data:66H
(Addr:01H)
Filter Select
(Addr:19H, 1AH, D3-0)
0101
0000
(3) Addr:01H, Data:BFH
(4)
ALC Control 1
(Addr:26H)
(4) Addr:19H, Data:05H
Addr:1AH, Data:05H
46H
40H
(5)
Input Digital Volume
(Addr:27H)
E1H
91H
(5) Addr:26H, Data:46H
(6)
ALC Ref. Level
(Addr:29H)
(6) Addr:27H, Data:E1H
E1H
E1H
(7)
ALC1 Control
(Addr:2AH)
(7) Addr:29H, Data:E1H
E1H
80H
(8)
Filter Co-ef
(Addr:2F-3EH)
(8) Addr:2AH, Data:A9H
xx…..x
xx…..x
(9) Addr: 2FH ~ 3EH
(9)
ALC4 Select
(Addr:25H, D2)
(10) Addr:25H, Data:04H
(10)
ALC4 State
ALC4 Enable
ALC4 Disable
PMAD1A/B bits
PMAD2A/B bits
ALC4 Disable
(12) (13)
(11)
Recording
(Addr:02H, D3-0)
PMPFIL1/2 bits
(Addr:03H, D1-0)
SDTO1/2 pins
State
(11) Addr:02H, Data:0FH
Addr:03H, Data:0FH
(12) Addr:02H, Data:00H
Addr:03H, Data:0CH
1059/fs
“L” Output
Initialize
Normal State
“L” Output
(13) Addr:25H, Data:00H
Figure 65. MIC Input Recording Sequence
This sequence is an example of ALC setting at fs=48kHz. For changing the parameter of ALC, please
refer to “Example of ALC Setting”. At first, clocks should be supplied according to “Clock Set Up”.
(1) Set Up AIN Initialization Cycle and Signal Path: AIRST[2:0] bits = “000” (656/fs), PFSDO1/2 bits =
“1”
(2) Set Up Microphone Amp Gain (Addr = 05H, 06H)
(3) Power Up Microphone Power 1/2, Microphone Amp 1A/B and Microphone Amp 2A/B: PMAIN1A/B
= PMAIN2A/B = PMMP1/2 bits = “1”
The initialization cycle time of AIN2A/B is 656/fs=13.7ms @ fs=48kHz.
(4) HPF1/2 and LPF1/2 ON/OFF Setting (Addr = 19H, 1AH)
(5) Set Up WTM[1:0], FRATT1[1:0] and ALCEQN bits (Addr = 26H)
(6) Set Up IVOL Value at ALC Operation start: IV1A[7:0] bits (Addr = 27H)
(7) Set Up REF Value: REF1[7:0] bits (Addtr = 29H)
(8) Set Up LMTH1[1:0], RFST1[1:0] and RGAIN1[2:0] bits (Addr = 29H)
(9) Set Up Coefficient of HPF1/2 and LPF1/2 (Addr: 2FH ~ 3EH)
(10) Set Up ALC4 and ATTLMT1 bits (Addr = 25H)
(11) Power Up ADC1/2: PMAD1A/B = PMAD2A/B bits = “0” → “1”
Power Up Programmable Filter 1/2: PMPFIL2 = PMPFIL2 bits = “0” → “1”
The initialization cycle time of ADC is 1059/fs=22.1ms @ fs=48kHz. ADC outputs “0” data during
the initialization cycle. The ALC operation starts from IVOL value of (6).
(12) Power Down ADC1/2: PMAD1A/B = PMAD2A/B bits = “1” → “0”
Power Down Programmable Filter 1/2: PMPFIL2 = PMPFIL2 bits = “1” → “0”
(13) ALC4 Disable: ALC4 bit = “1” → “0”
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11.5.
Stop of Clock
11.5.1. PLL Master Mode
Example:
(1)
Audio I/F Format: I2S
Input Master Clock Frequency: 12MHz
Output BCLK Frequency: 64fs
PMPLL bit
(Addr:01H, D6)
(2)
MCKOE bit
(Addr:09H, D4)
(1) Addr:01H, Data:80H
“0” or “1”
(2) Addr:09H, Data:25H
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 66. Clock Stopping Sequence (1)
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO output: MCKOE bit = “1” → “0”
(3) Stop an external master clock.
11.5.2. PLL Slave Mode (BCLK pin)
(1)
PMPLL bit
Example:
(Addr:01H, D6)
Audio I/F Format: I2S
PLL Reference Clock: BCLK
Input BCLK Frequency: 64fs
(1) Addr:01H, Data:80H
(2)
External BCLK
Input
(2)
External LRCK
(2) Stop the external clocks
Input
Figure 67. Clock Stopping Sequence (2)
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BCLK and LRCK clocks.
11.5.3. PLL Slave Mode (MCKI pin)
Example:
(1)
Audio I/F Format: I2S
PLL Reference Clock: MCKI
Input BCLK Frequency: 64fs
PMPLL bit
(Addr:01H, D6)
(2)
(1) Addr:01H, Data:80H
MCKOE bit
(Addr:09H, D4)
(2) Addr:09H, Data:04H
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 68. Clock Stopping Sequence (3)
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO output: MCKOE bit = “1” → “0”
(3) Stop an external master clock.
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11.5.4. External Slave Mode
(1)
External MCKI
Example:
Input
Audio I/F Format: I2S
Input Master Clock Frequency: 256fs
Input BCLK Frequency: 64fs
(1)
External BCLK
Input
(1) Stop the external clocks
(1)
External LRCK
Input
Figure 69. Clock Stopping Sequence (4)
(1) Stop the external MCKI, BCLK and LRCK clocks.
11.5.5. External Master Mode
(1)
External MCKI
BCLK
Example:
Input
Output
“H” or “L”
Audio I/F Format: I2S
Input Master Clock Frequency: 256fs
Output BCLK Frequency: 64fs
(1) Stop the external clocks
LRCK
Output
“H” or “L”
Figure 70. Clock Stopping Sequence (5)
(1) Stop an external master clock. BCLK and LRCK are fixed to “H” or “L”.
11.6.
Power Down
Power supply current cannot be shut down by stopping clocks and setting PMVCM bit = “0”. Power supply
current can be shut down (typ. 4A) by stopping clocks and setting the PDN pin = “L”. When the PDN pin
= “L”, all registers are initialized.
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12. Package
12.1.
Outline Dimensions
28-pin QFN
0.75 ± 0.05
B
15
21
14
22
8
Exposed
Pad
28
7
A
1
0 ~ 0.05
4.00 ± 0.10
(0.20)
0.40
0.20 ± 0.05
0.07 M C A B
0.40 ± 0.10
(0.30)
2.60 ± 0.10
4.00 ± 0.10
2.60 ± 0.10
C0.35
0.08 C
(Unit: mm)
* The exposed pad on the bottom surface of the package should be connected to the ground.
C
12.2.
Material & Lead finish
Package molding compound: Epoxy Resin, Halogen (Br and Cl) free
Lead frame material: Cu Alloy
Pin surface treatment: Solder (Pb free) plate
12.3.
Marking
5704
XXXX
1
XXXX: Date code (4 digits)
Pin #1 indication
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13. Ordering Guide
AK5704EN
AKD5704
−40 ~ +85°C 28-pin QFN (0.4mm pitch)
AK5704 Evaluation Board
14. Revision History
Date (Y/M/D)
19/02/20
22/01/31
Revision
00
01
Reason
First Edition
Error
Correction
Page
Contents
102
Description
Addition
103
Control Sequence
Voice Activity Detection (1ch Mic) sequence
and figure were changed.
Control Sequence
Voice Activity Detection (4ch Mic) sequence
was added.
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IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third party
with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the
aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other
transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations in
which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or
related technology or any information contained in this document, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws
and regulations. The Products and related technology may not be used for or incorporated into
any products or systems whose manufacture, use, or sale is prohibited under any applicable
domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws
and regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as
a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without
prior written consent of AKM.
Rev.1
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