ASAHI KASEI
[AK6480C/81]
AK6480C/81C
8Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY
READ/WRITE NON-VOLATILE MEMORY
- Wide VCC (1.8V to 5.5V) operation
- 8192 bits: 512 × 16 organization
ONE CHIP MICROCOMPUTER INTERFACE
- Interface with one chip microcomputer’s serial communication port directly
LOW POWER CONSUMPTION
- 0.8µA Max. (Standby mode)
HIGH RELIABILITY
- Endurance
- Data Retention
: 1000K cycles/Address
: 10 years
SPECIAL FEATURES
- 8 word Page Write Mode
- High speed operation ( fMAX=5MHz: VCC=4.5V to 5.5V )
- Automatic write cycle time-out with auto-ERASE (5ms Max.)
- Automatic address increment (READ)
- Ready/ Busy status signal
- Software and Hardware controlled write protection
IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package (SOP, SSOP, MSOP, SON)
DO
DATA
REGISTER
DI
INSTRUCTION
REGISTER
INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATION
16
ADD.
BUFFERS
R/W AMPS
AND
AUTO ERASE
16
DECODER
EEPROM
8192bit
512 ×16
CS
VPP SW
SK
VREF
RESET
VPP
GENERATOR
RDY/BUSY
Block diagram
DAS04E-00
2005/03
- 1 -
ASAHI KASEI
[AK6480C/81]
General Description
The AK6480C/81C is a 8192bit, serial, read/write, non-volatile memory device fabricated using an
advanced CMOS EEPROM technology. The AK6480C/81C has 8192bits of memory organized
into 512 registers of 16 bits each. The AK6480C/81C can operate full function under wide
operating voltage range from 1.8V to 5.5V. The charge up circuit is integrated for high voltage
generation that is used for write operation.
The AK6480C/81C can connect to the serial communication port of popular one chip
microcomputer directly (3 line negative clock synchronous interface). At write operation,
AK6480C/81C takes in the write data from data input pin (DI) to a register synchronously with
rising edge of input pulse of serial clock pin ( SK ). And at read operation, AK6480C/81C takes
out the read data from a register to data output pin (DO) synchronously with falling edge of SK .
The AK6480C/81C has 5 instructions such as READ, WRITE, PAGE WRITE, WREN (write enable)
and WRDS (write disable). Each instruction is organized by op-code block (8bits), address block
(8bits) and data (8bits x 2). When input level of SK pin is high level and input level of chip
select ( CS ) pin is changed from high level to low level, AK6480C/81C can receive the
instructions.
Special features of the AK6480C/81C include : automatic write time-out with auto-ERASE,
Ready/ Busy status signal output and ultra-low standby power mode when deselected ( CS
=high).
Software and Hardware controlled write protection
The AK6480C/81C has 2 (hardware and software) write protection functions.
After power on or after execution of WRDS (write disable) instruction, execution of WRITE
instruction will be disabled. This write protection condition continues until WREN instruction is
executed or VCC is removed from the part.
Execution of READ instruction is independent of both WREN and WRDS instructions.
Reset pin should be low level when WRITE instruction is executed. When the Reset pin is high
level, the WRITE instruction is not executed.
Ready/ Busy status signal
During the automatic write time-out period ( Busy status), the AK6480C/81C can't accept the
other instructions. The AK6480C/81C has 2 functions to know the Busy status from exterior.
The RDY/ BUSY pin indicates the Busy status regardless of the CS pin status. The
RDY/ BUSY pin outputs the low level regardless of the CS pin status during Busy status.
Except the above status, this pin outputs high level.
Also the DO pin indicates the Busy status. When input level of SK pin is low level and input
level of CS pin is changed from high level to low level, the AK6480C/81C is in the status output
mode and the DO pin indicates the Ready/ Busy status. The Ready/ Busy status outputs on
DO pin until CS pin is changed from low level to high level, or first bit ("1") of op-code of next
instruction is given to the part. Except when the device is in the status output mode or outputs
data, the DO pin is in the high impedance state.
DAS04E-00
2005/03
- 2 -
ASAHI KASEI
[AK6480C/81]
Type of Products
Model
AK6480CF
Temp.Range
-40°C to 85°C
VCC
1.8V to 5.5V
Package
8pin Plastic SOP
AK6480CM
-40°C to 85°C
1.8V to 5.5V
8pin Plastic SSOP
AK6480CH
-40°C to 85°C
1.8V to 5.5V
8pin Plastic MSOP
AK6480CL
-40°C to 85°C
1.8V to 5.5V
8pin Plastic SON
AK6481CM
-40°C to 85°C
1.8V to 5.5V
8pin Plastic SSOP
AK6481CH
-40°C to 85°C
1.8V to 5.5V
8pin Plastic MSOP
Pin Arrangement
AK6480CF
AK6480CM/81CM
RDY/BUSY
1
8
RESET
VCC
2
7
GND
CS
3
6
DO
SK
4
5
DI
CS
SK
DI
DO
8pin SOP
1
2
3
4
VCC
RDY/BUSY
RESET
GND
8pin SSOP
AK6480CH/81CH
CS
SK
DI
DO
8
7
6
5
1
2
3
4
8
7
6
5
AK6480CL
VCC
RDY/BUSY
RESET
GND
CS
SK
DI
DO
1
2
3
4
8pin MSOP
8
7
6
5
VCC
RDY/BUSY
RESET
GND
8pin SON
Pin Function
Pin name
CS
SK
DI
DO
RESET
RDY/BUSY
VCC
GND
Functions
Chip Select input
Serial Clock input
Serial Data input
Serial Data output
RESET input
RDY/BUSY output
Power Supply
Ground
DAS04E-00
2005/03
- 3 -
ASAHI KASEI
[AK6480C/81]
Pin Description
CS (Chip Select)
When SK is high level and CS is changed from high level to low level, AK6480C/81C can
receive the instructions. CS should be kept low level while receiving op-code, address and
data and while outputting data. If CS is changed to high level during the above period,
AK6480C/81C stops the instruction execution. When SK is low and CS is changed from
high level to low level, AK6480C/81C will be in status output mode. The CS need not be low
level during the automatic write time-out period ( Busy status).
SK (Serial Clock)
The SK clock pin is the synchronous clock input for input/output data. At write operation,
AK6480C/81C takes in the write data from data input pin (DI) synchronously with rising edge of
input pulse of serial clock pin ( SK ). And at read operation, AK6480C/81C takes out the read
data to data output pin (DO) synchronously with falling edge of SK . The SK clock is not
needed during the automatic write time-out period ( Busy status), the status output period and
when the device isn't selected ( CS = high level).
DI (Data Input)
The op-code, address and write data is input to the DI pin.
DO (Data Output)
The DO pin outputs the read data and status signal and will be high impedance except for this
timing.
RDY/ BUSY (Ready/ Busy status)
This pin outputs the internal programming status. When the AK6480C/81C is in the automatic
write time-out period, this pin outputs the low level ( Busy status), and outputs the high level
except for this timing.
RESET (Reset)
The AK6480C/81C stops executing the write instruction when the RESET pin is high level. The
RESET pin should be low level while the write instruction input period and the page write
instruction input period and the automatic write time-out period. If the RESET pin is high level
while the automatic write time-out period, the AK6480C/81C stops execution of internal
programming and the device returns to ready status. In this case the word data of the specified
address will be incomplete. When inputting the new instruction after RESET, the CS pin
should be set to high level. The read, write enable and write disable instructions are not affected
by RESET pin status.
VCC (Power Supply)
GND (Ground)
DAS04E-00
2005/03
- 4 -
ASAHI KASEI
[AK6480C/81]
Functional Description
The AK6480C/81C has 5 instructions such as READ, WRITE, Page Write, WREN (write enable)
and WRDS (write disable). Each instruction is organized by op-code block (8bits), address block
(8bits) and data (8bits x 2). When input level of SK pin is high level and input level of chip
select ( CS ) pin is changed from high level to low level, AK6480C/81C can receive the
instructions.
When the instructions are executed consecutively, the CS pin should be brought to high level for
a minimum of 250ns(tCS) between consecutive instruction cycle.
Instruction Set For AK6480C
Instruction
WRITE
Page Write
READ
WREN
WRDS
(WRAL)
1
1
1
1
1
1
Op-Code
0 1 0 0 1 0 A8
0 1 1 0 1 0 A8
0 1 0 1 0 0 A8
0100011
0100000
0101111
Address
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
X X X X X X X X
X X X X X X X X
X X X X X X X X
Data
D15 – D0
D15 – D0
D15 – D0
D15 – D0
X: don't care
Instruction Set For AK6481C
Instruction
WRITE
Page Write
READ
WREN
WRDS
(WRAL)
1
1
1
1
1
1
Op-Code
0 1 0 0 1 0 A0
0 1 1 0 1 0 A0
0 1 0 1 0 0 A0
0100011
0100000
0101111
Address
A1 A2 A3 A4 A5 A6 A7 A8
A1 A2 A3 A4 A5 A6 A7 A8
A1 A2 A3 A4 A5 A6 A7 A8
X X X X X X X X
X X X X X X X X
X X X X X X X X
Data
D0 – D15
D0 – D15
D0 – D15
D0 – D15
X: don't care
(Note) The WRAL instruction is used for factory function test only.
instruction.
DAS04E-00
User can't use this
2005/03
- 5 -
ASAHI KASEI
[AK6480C/81]
Write
The write instruction is followed by 16 bits of data to be written into the specified address. After
the 32nd rising edge of SK to read D0 in, the AK6480C/81C will be put into the automatic write
time-out period. During the automatic write time-out period ( Busy status) and while entering
write instruction, the RESET pin should be low level. If the RESET pin is set to high level during
the automatic write time-out period, the AK6480C/81C stops execution of internal programming
and the device returns to ready status. In this case the word data of the specified address will be
incomplete. When inputting the new instruction after RESET, the CS pin should be set to high
level. When the RESET pin is kept at high level, the write is not executed. This becomes write
protection function.
The CS pin need not be high level during automatic write time-out period ( Busy status).
RESET
CS
SK
DI
1
2
1
3
0
4
1
5
0
6
0
7
1
8
0
9
A8
10
A7
15
A6
A1
16
17
18
A0 D15 D14
30
31
32
D2 D1 D0
Hi-Z
DO
tE/W
RDY/
BUSY
WRITE (AK6480C)
RESET
CS
SK
DI
DO
1
2
1
3
0
4
1
5
0
6
0
7
1
8
0
9
A0
A1
10
15
A2
A7
16
A8
17
D0
18
D1
30
31
32
D13 D14 D15
Hi-Z
tE/W
RDY/
BUSY
WRITE (AK6481C)
Page Write
AK6480C/81C has Page Write mode, which can write the data within 8 words with one
programming cycle. The input data sent to the shift register within 8 words. After the instruction
input, the internal programming cycle starts when CS pin changes low to high. After the
instructions are inputted, CS pin should change low to high after the last data bit (D0,
AK6481C: D15) inputs and before next SCK clock rises. Page Write function can start only at this
timing.
After the receipt of each word, the three lower order address pointer bits internally incremented by
one. The higher order seven bits of the word address remains constant. When the highest
address is reached ”XX XXXX X111”, the address counter rolls over to address ”XX XXXX X000”
allowing the page write cycle to be continued indefinitely.
If AK6480C/81C is transmitted more than 8 words, the address counter will ”roll over” and the
previously written data will be overwritten. When AK6480C/81C is transmitted 10 words, ninth
word will be overwritten to first word, and tenth word will be overwritten to second word.
During the automatic write time-out period ( Busy status) and while entering Page Write
DAS04E-00
2005/03
- 6 -
ASAHI KASEI
[AK6480C/81]
instruction, the RESET pin should be low level. If the RESET pin is set to high level during the
automatic write time-out period, the AK6480C/81C stops execution of internal programming and
the device returns to ready status. In this case the word data of the specified address will be
incomplete. When inputting the new instruction after RESET, the CS pin should be set to high
level. When the RESET pin is kept at high level, the Page Write is not executed. This becomes
write protection function.
The CS pin need not be high level during automatic write time-out period ( Busy status).
RESET
CS
1
SK
2
3
4
5
6
7
8
9
10
15
16
17
18
30
31
32
Data(n)
DI
1
0
1
1
0
1
0
A8
A7
A6
A1
A0
D15 D14
D2
D1
D0
Hi-Z
DO
RDY/
BUSY
RESET
CS
SK
33
34
46
DI
D15 D14
47
48
Data(n+1)
Data(n+7)
D2
D1
D0
D15
D0
D15 D14
D2
D1
D0
Hi-Z
DO
tE/W
RDY/
BUSY
PAGE WRITE (AK6480C)
RESET
CS
1
SK
DI
2
1
3
0
4
1
5
1
6
0
7
1
8
0
9
A0
10
A1
15
A2
16
A7
A8
17
18
D0
D1
30
31
32
データ(n)
D13 D14 D15
Hi-Z
DO
RDY/
BUSY
RESET
CS
SK
33
34
46
47
48
データ(n+1)
DI
DO
D0
D1
データ(n+7)
D13 D14 D15
D0
D15
D0
D1
D13 D14 D15
Hi-Z
tE/W
RDY/
BUSY
PAGE WRITE (AK6481C)
DAS04E-00
2005/03
- 7 -
ASAHI KASEI
[AK6480C/81]
Read
The read instruction is the only instruction which outputs serial data on the DO pin. When the
17th falling edge of SK is received , the DO pin will come out of high impedance state and shift
out the data from D15 (AK6481C: D0) first in descending order which is located at the address
specified in the instruction.
The data in the next address can be read sequentially by continuing to provide clock. The
address automatically cycles to the next higher address after the 16bit data shifted out. When the
highest address is reached (A8-A0 : 1 1111 1111), the address counter rolls over to address
(A8-A0 : 0 0000 0000) allowing the read cycle to be continued indefinitely.
CS
SK
1
DI
2
1
3
0
4
1
5
0
6
1
7
0
0
8
9
A8
A7
15
10
A6
A1
16
18
32
33
34
48
A0
Hi-Z
DO
17
D15 D14
D0 D15 D14
RDY/
BUSY
D0
"H"
* The data in the next address can be read sequentially by continuing to provide clock.
*
READ (AK6480C)
CS
SK
1
DI
2
1
3
0
4
1
5
0
6
1
7
0
0
8
9
A0
A1
15
10
A2
A7
16
18
32
33
34
48
A8
Hi-Z
DO
17
D0 D1
D15 D0 D1
RDY/
BUSY
D15
"H"
* The data in the next address can be read sequentially by continuing to provide clock.
*
READ (AK6481C)
WREN / WRDS ( Write Enable and Write Disable )
When VCC is applied to the part, it powers up in the programming disable (WRDS) state.
Programming must be preceded by a programming enable (WREN) instruction. Programming
remains enabled until a programming disable (WRDS) instruction is executed or VCC is removed
from the part. The programming disable instruction is provided to protect against accidental data
disturb. Execution of a read instruction is not affected by both WREN and WRDS instructions.
CS
SK
DI
DO
1
2
1
3
0
4
1
5
0
6
0
7
8
0
9
X
WREN=11
WRDS=00
10
11
X
X
12
X
13
X
14
X
15
X
16
17
18
X
Hi-Z
SK pulses exceeding 17 are ignored.
WREN / WRDS
DAS04E-00
2005/03
- 8 -
ASAHI KASEI
[AK6480C/81]
Absolute Maximum Ratings
Parameter
Power Supply
All Input Voltages
with Respect to Ground
Ambient storage temperature
Symbol
VCC
VIO
Tst
Min.
-0.6
-0.6
Max.
+6.5
VCC+0.6
Unit
V
V
-65
+150
°C
Stress above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to
absolute maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter
Power Supply
Ambient Operating Temperature
Symbol
VCC
Ta
DAS04E-00
Min.
1.8
-40
Max.
5.5
+85
Unit
V
°C
2005/03
- 9 -
ASAHI KASEI
[AK6480C/81]
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS
( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter
Symbol
Condition
Min.
Max.
Unit
Current Dissipation
ICC1
VCC=5.5V,tSKP=200ns
*1
2.5
mA
(WRITE)
ICC2
VCC=2.5V,tSKP=400ns
*1
2.0
mA
ICC3
VCC=1.8V,tSKP=1.0µs
*1
1.5
mA
Current Dissipation
ICC4
VCC=5.5V,tSKP=200ns
*1
1.0
mA
(READ,WREN,
ICC5
VCC=2.5V,tSKP=400ns
*1
0.2
mA
WRDS)
ICC6
VCC=1.8V,tSKP=1.0µs
*1
0.1
mA
Current Dissipation
(Standby)
ICCS
VCC=5.5V
*2
0.8
µA
Input High Voltage
VIH1
VIH2
Input Low Voltage
VIL1
VIL2
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V
0.7×VCC
VCC+0.5
V
0.8×VCC
VCC+0.5
V
0
0.3×VCC
V
0
0.2×VCC
V
VOH1
2.5V ≤ VCC ≤ 5.5V
IOH=-50µA
VCC-0.3
V
VOH2
1.8V ≤ VCC < 2.5V
IOH=-50µA
VCC-0.3
V
VOL1
2.5V ≤ VCC ≤ 5.5V
IOL=1.0mA
0.4
V
VOL2
1.8V ≤ VCC < 2.5V
IOL=0.1mA
0.4
V
Input Leakage
CS , SK ,DI,RESET
ILI
VCC=5.5V, VIN=5.5V
±1.0
µA
Output Leakage
ILO
VCC=5.5V
VOUT=5.5V, CS=VCC
±1.0
µA
Output High Voltage
Output Low Voltage
*1 : VIN=VIH/VIL, DO=RDY/ BUSY =Open
*2 : CS =VCC, SK /DI/RESET=VCC/GND, DO= RDY/ BUSY =Open
DAS04E-00
2005/03
- 10 -
ASAHI KASEI
[AK6480C/81]
(2) A.C. ELECTRICAL CHARACTERISTICS
( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter
Symbol
SK Cycle Time
tSKP1
tSKP2
tSKP3
SK Pulse Width
tSKW1
tSKW2
tSKW3
CS Setup Time
tCSS1
tCSS2
CS Hold Time
tCSH1
tCSH2
SK Setup Time
tSKSH/L1
tSKSH/L2
Condition
Min.
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 4.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 4.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 4.5V
Max.
Unit
200
ns
400
ns
1.0
µs
100
ns
200
ns
500
ns
40
ns
80
ns
40
ns
80
ns
40
ns
80
ns
RESET Setup Time
tRESS
0
ns
RESET Hold Time
tRESH
0
ns
Data Setup Time
tDIS1
40
ns
80
ns
200
ns
40
ns
80
ns
200
ns
tDIS2
tDIS3
Data Hold Time
tDIH1
tDIH2
tDIH3
DO pin Output delay
tPD1
tPD2
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
CL=100pF
*3
60
ns
*3
150
ns
*3
300
1
ns
µs
5
ms
RDY/BUSY pin Output delay
tPD3
tPD
Selftimed Programming Time
tE/W
Write Recovery Time
tRC
100
ns
Min CS High Time
tCS
250
ns
DO High-Z Time
tOZ
Endurance
*4
500
5.5V, 25°C, Page Write
*3 : CL=100pF
*4 : These parameters are not 100% tested.
DAS04E-00
1,000,000
ns
E/W
cycles /
Address
These are the sample value.
2005/03
- 11 -
ASAHI KASEI
[AK6480C/81]
Synchronous Data Timing
tRESS
RESET
tCS
tCSS
CS
tSKP
tSKSH
tSKW
SK
1
tSKW
2
3
tDIS
DI
tDIH
1
0
1
Hi-Z
DO
tRC
RDY/
BUSY
Instruction Input
CS
"H"
tSKP
"L"
tSKW
SK
tSKW
15
16
tDIS
18
tDIH
A1
/A7
DI
17
A0
/A8
tPD
RDY/
BUSY
D15
/D0
Hi-Z
DO
tPD
D14
/D1
"H"
"L"
Upper:AK6480C, Lower:AK6481C
Data Output (READ)
DAS04E-00
2005/03
- 12 -
ASAHI KASEI
[AK6480C/81]
CS
SK
31
32
DI
tOZ
D1
/D14
DO
RDY/
BUSY
D0
/D15
"H"
"L"
Upper:AK6480C, Lower:AK6481C
Data Output (READ)
tRESH
RESET
CS
tCSH
SK
DI
DO
30
31
D2
/D13
32
D1
/D14
D0
/D15
Hi-Z
tPD
tE/W
RDY/
BUSY
Upper:AK6480C, Lower:AK6481C
WRITE Ready / Busy Signal Output (RDY/ BUSY pin)
DAS04E-00
2005/03
- 13 -
ASAHI KASEI
[AK6480C/81]
tRESH
RESET
CS
tCSH
tSKH
SK
D1
/D14
DI
D0
/D15
Hi-Z
DO
tPD
tE/W
RDY/
BUSY
Upper:AK6480C, Lower:AK6481C
PAGE WRITE Ready / Busy Signal Output (RDY/ BUSY pin)
tCS
CS
tSKSL
SK
DI
tPD
DO
RDY/
BUSY
tOZ
BUSY
READY
BUSY
READY
Ready/ Busy Signal Output (DO pin)
DAS04E-00
2005/03
- 14 -
IMPORTANT NOTICE
These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use,
except with the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support and maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or
damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that part in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and reliability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
工商网监
湘ICP备2023018690号
