[AK7735]
AK7735
Dual DSP with 4chADC + 4chDAC + 4chSRC
1. General Description
The AK7735 is a highly integrated digital signal processor, including a 24-bit stereo ADC with MIC gain
amplifiers, a 24-bit stereo ADC with input selector, two 32-bit stereo DACs, 2 stereo sampling rate
convertors supporting the sampling frequency up to 192kHz and dual DSPs for Audio/HF process. Each
DSP has 3072step/fs (when fs=48kHz) parallel processing power. As the AK7735 is a RAM based DSP,
it is freely programmable for user requirements, such as acoustic effects and proprietary high
performance hands-free function. The AK7735 is available in a 48-pin LQFP package.
2.
Features
□ Dual DSP: (DSP1 and DSP2 have the same specification. Memory areas are shared by them)
- Word length:
28-bit (Simple floating point supported)
- Instruction cycle:
Max. 6.8ns (3072fs at fs=48kHz)
- Multiplier:
24 x 24 → 48-bit (Double precision arithmetic available)
- Divider:
24 / 24 → 24-bit (Floating point normalization function)
- ALU:
52-bit Arithmetic Operation (with 4bits overflow margin)
- Program RAM:
4096-word x 36-bit
- Coefficient RAM:
6144-word x 24-bit
- Data RAM:
4096-word x 28-bit
- Delay RAM:
12288-word x 28-bit
- JX pins (Interrupt)
- Independent Power Management Function for DSP1, DSP2
□ ADC1: 24-bit Stereo ADC with MIC Gain Amplifiers
- Sampling Frequency: fs = 8kHz ~ 192kHz
- Channel Independent Analog Gain Amplifiers (0~18dB(2dB Step), 18~36dB(3dB Step))
- Differential Input or Single-ended Input
- ADC Characteristics
S/N: 106dB (fs=48kHz, Differential Input, MIC Gain=0dB)
- Channel Independent Digital Volume Control (24dB～-103dB, 0.5dB Step, Mute)
- Digital HPF for DC Offset Cancelling
- Low Noise MIC Power Output: 1ch
- 4 types of Digital Filter for Sound Color Selection
□ ADC2: 24-bit Stereo ADC with Input Selector
- Sampling Frequency: fs = 8kHz ~ 192kHz
- Analog Input Selector: Differential Input x1 or Single-ended Input x2,
- ADC Characteristics
S/N: 106dB (fs=48kHz, Differential Input)
- Channel Independent Digital Volume (24dB ~ -103dB, 0.5dB Step, Mute)
- Digital HPF for DC Offset Cancelling
- 4 types of Digital Filter for Sound Color Selection
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[AK7735]
□ DAC: Advanced 32bit DAC
- 2ch x 2
- Sampling Frequency: fs = 8kHz ~ 192kHz
- Single-ended Output
- DAC Characteristics
S/N: 108dB (fs=48kHz)
- Channel Independent Digital Volume Control (12dB ~ -115dB, 0.5dB Step, Mute)
- 4 types of Digital Filter for Sound Color Selection
□ SRC:
- 2ch x 2
- FSI = 8kHz ~ 192kHz, FSO = 8kHz ~ 192kHz (FSO/FSI = 0.167 ~ 6.0)
□ Digital Interfaces
- Digital Input Port x 4 (Max 32ch, in TDM mode)
- Digital Output Port x 4 (Max 32ch, in TDM mode)
- Independent LRCK/BICK port x 3
- Data Format: MSB 32, 24bit / LSB 24, 20, 16bit / I2S
- PCM Short / Long Frame Supported
- TDM Format Supported (Max:8ch / 256fs, fs=96kHz)
□ PLL Circuit
□ μP Interface: SPI(Max 6MHz) / I2C(400kHz Fast Mode, 1MHz Fast Mode Plus)
□ Power Supply:
Analog: AVDD: 3.0V ~ 3.6V (Typ. 3.3V)
Digital: LVDD: 3.0V ~ 3.6V (Typ. 3.3V) (3.3V → 1.2V regulator integrated)
I/F
VDD33: 3.0V ~ 3.6V (Typ. 3.3V)
TVDD: 1.7V ~ 3.6V (Typ. 3.3V)
□Operating Temperature Range:
AK7735VQ: Ta = -40 ~ 85C
AK7735EQ: Ta = -20 ~ 85C
□Package: 48-pin LQFP (7mm x 7mm, 0.5mm pitch)
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[AK7735]
3.
1.
2.
3.
4.
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8.
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10.
11.
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12.
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13.
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Table of Contents
General Description .......................................................................................................................... 1
Features ............................................................................................................................................ 1
Table of Contents .............................................................................................................................. 3
Block Diagrams ................................................................................................................................. 5
Block Diagram ................................................................................................................................... 5
DSP Block Diagram........................................................................................................................... 6
Pin Configurations and Functions ..................................................................................................... 7
Pin Configurations ............................................................................................................................. 7
Pin Functions..................................................................................................................................... 8
Handling of Unused Pins..................................................................................................................11
Internal Pulled-down Pins Status .....................................................................................................11
Power-down Status of Output Pins ................................................................................................. 12
Absolute Maximum Ratings ............................................................................................................ 13
Recommended Operating Conditions ............................................................................................ 13
Electrical Characteristics................................................................................................................. 14
Analog Characteristics .................................................................................................................... 14
Power Consumption ........................................................................................................................ 19
Digital Filter Characteristics ............................................................................................................ 20
ADC Block ....................................................................................................................................... 20
DAC Block ....................................................................................................................................... 24
SRC Block ....................................................................................................................................... 28
DC Characteristics .......................................................................................................................... 30
Switching Characateristics .............................................................................................................. 31
System Clock .................................................................................................................................. 31
Power Down .................................................................................................................................... 31
Serial Data Interface (SDIN1 ~ SDIN4, SDOUT1 ~ SDOUT4) ....................................................... 32
SPI Interface.................................................................................................................................... 35
I2C Interface..................................................................................................................................... 37
Functional Descriptions................................................................................................................... 38
System Clock .................................................................................................................................. 38
Audio HUB ....................................................................................................................................... 40
Audio Data Path Setting .................................................................................................................. 46
Power-up Sequence ........................................................................................................................ 64
VREG (Internal Circuit Drive Regulator) ......................................................................................... 65
Power-down and Reset ................................................................................................................... 66
RAM Clear ....................................................................................................................................... 68
STO pin Output Status .................................................................................................................... 69
μP Interface Setting and Pin Statuses ............................................................................................ 70
SPI Interface.................................................................................................................................... 71
I2C Interface..................................................................................................................................... 85
Simple Write Error Check ................................................................................................................ 90
DSP Block ....................................................................................................................................... 91
Analog Input Block .......................................................................................................................... 94
ADC Block ....................................................................................................................................... 97
DAC Block ..................................................................................................................................... 102
SRC Block ..................................................................................................................................... 107
Register Map ..................................................................................................................................113
Register Definitions ........................................................................................................................116
Recommended External Circuits .................................................................................................. 135
Connection Diagram ..................................................................................................................... 135
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■ Peripheral Circuit ........................................................................................................................... 137
14. Package ........................................................................................................................................ 139
■ Outline Dimensions ....................................................................................................................... 139
■ Material and Lead Finish ............................................................................................................... 139
■ Marking .......................................................................................................................................... 140
15. Ordering Guide.............................................................................................................................. 141
16. Revision History ............................................................................................................................ 141
IMPORTANT NOTICE ........................................................................................................................ 142
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4.
■
Block Diagrams
Block Diagram
Figure 1. Block Diagram
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■
DSP Block Diagram
Pointer
CP0, CP1
DP0, DP1
Coefficient RAM
DLP0, DLP1
Data RAM
Delay RAM
4096w x 28Bit max
2048w Unit
6144×24Bit max
2048w Unit
OFREG
64w x 14Bit
12288w x 28Bit max
4096w Unit
CBUS(24Bit)
DBUS(28Bit)
Micon I/F
MPX24
MPX24
Control
Serial I/F
Program RAM
X
DEC
Y
Multiply
24×24 → 48Bit
4096w×36Bit max
2048w Unit
PC
Stack : 8 Level(max)
28Bit
48Bit
TMP 12×28Bit
PTMP(LIFO) 6×28Bit
MUL
DBUS
2 x 24Bit DIN6
SHIFT
52Bit
2 x 24Bit DIN5
48Bit
A
2 x 24Bit DIN4
2 x 24Bit DIN3
B
ALU
2 x 24Bit DIN2
52Bit
2 x 24Bit DIN1
Overflow Margin: 4Bit
2 x 32Bit DOUT6
52-Bit
2 x 32Bit DOUT5
2 x 32Bit DOUT4
DR0 3
2 x 32Bit DOUT3
52Bit
2 x 32Bit DOUT2
Over Flow Data
Generator
2 x 32Bit DOUT1
28bit x fifo16 DTMP
(Connection between DSP1/2)
Division 2424→24
Peak Detector
Figure 2. DSP Block Diagram
Note
* 1. Coefficient RAM, Data RAM, Delay RAM, Program RAM areas are shared by DSP1 and DSP2 and
the sizes are configurable by control registers.
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[AK7735]
5. Pin Configurations and Functions
AIN1R/INP2
37
INN1
38
AIN1L/INP1
39
MPREF
40
MPWR
41
SI/I2CFIL
SCLK/SCL
SO/SDA
26
25
30
27
LVDD
31
PDN
AIN2RN/AIN4R
32
28
AIN2RP/AIN3R
33
AVDRV
AIN2LN/AIN4L
34
29
AIN2LP/AIN3L
35
DVSS3
INN2
36
Configurations
LVDD
TVDD
AK7735
（Top View）
AVDD
24
CSN
23
STO/RDY/SDOUT2
22
-
DVSS2
21
-
TVDD
20
SDOUT1/RDY
19
BICK1
AVDD
-
42
AVSS
-
43
18
LRCK1
VCOM
44
17
SDIN1
VREFH
45
16
BICK2/JX2
VREFL
46
15
LRCK2/JX1
AOUT1R
47
14
SDIN2/JX0
AOUT1L
48
13
XTO
1
2
3
4
5
6
7
8
9
- 10
- 11
12
AOUT2L
TESTI
LRCK3
SDOUT4/GPO2
BICK3
SDOUT3/CLKO/GPO1
SDIN3/JX3
SDIN4
DVSS1
VDD33
XTI
VDD33
AOUT2R
■ Pin
016014707-E-00
input
output
in/out
-
power
2016/12
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[AK7735]
■ Pin
Functions
No.
Pin Name
I/O
1
AOUT2R
O
2
AOUT2L
O
3
TESTI
I
4
9
10
11
LRCK3
SDOUT4
GPO2
BICK3
SDOUT3
CLKO
GPO1
SDIN3
JX3
SDIN4
DVSS1
VDD33
12
XTI
I
13
XTO
O
SDIN2
JX0
LRCK2
JX1
BICK2
JX2
SDIN1
LRCK1
BICK1
SDOUT1
RDY
TVDD
DVSS2
I
I
I/O
I
I/O
I
I
I/O
I/O
O
O
-
5
6
7
8
14
15
16
17
18
19
20
21
22
I/O
O
O
I/O
O
O
O
I
I
I
-
Supply
Power
Function
DAC2 Rch Analog Output Pin
This pin outputs “Hi-Z” during power-down state.
DAC2 Lch Analog Output Pin
This pin outputs “Hi-Z” during power-down state.
Test Input Pin
It must be tied “L”.
LR Channel Select Clock 3 Pin
Serial Data Output 4 Pin
GPO Output 2 Pin (GPO Output of DSP2)
Serial Bit Clock 3 Pin
Serial Data Output 3 Pin
Master Clock Output Pin
GPO Output 1 Pin (GPO Output of DSP1)
Serial Data Input 3 Pin
External Conditional Jump Input 3 Pin
Serial Data Input 4 Pin
Digital Ground 1 Pin 0V
Digital I/F Power Supply Pin 3.0~3.6V (typ.3.3V)
Crystal Oscillator Input Pin
When using a crystal oscillator, connect it between XTI and XTO.
When not using XTI pin, leave this pin open.
Crystal Oscillator Output Pin
When using a crystal oscillator, connect it between XTI and XTO.
When not using a crystal oscillator, leave this pin open.
Serial Data Input 2 Pin
External Conditional Jump Input 0 Pin
LR Channel Select Clock 1 Pin
External Conditional Jump Input 1 Pin
Serial Bit Clock 2 Pin
External Conditional Jump Input 2 Pin
Serial Data Input 1 Pin
LR Channel Select Clock 1 Pin
Serial Bit Clock 1 Pin
Serial Data Output 1 Pin
RDY Signal Output Pin
Digital I/F Power Supply Pin 1.7~3.6V (typ.3.3V)
Digital Ground 2 Pin 0V
016014707-E-00
AVDD
AVDD
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
-
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[AK7735]
No.
23
Pin Name
I/O
STO
O
RDY
SDOUT2
O
O
I
24
CSN
I
SO
O
25
SDA
I/O
SCLK
SCL
SI
I
I
I
I2CFIL
I
28
PDN
I
29
AVDRV
O
30
31
DVSS3
LVDD
-
26
27
Supply
Power
Function
Status Output Pin
This pin outputs “L” during power-down state.
RDY Signal Output Pin
Serial Data Output 2 Pin
SPI Mode
SPI I/F Chip Select Pin
During power-down state or when SPI I/F is not in use, leave this
pin “H” level.
2
I C Mode
I2C I/F Chip Address Pin
This pin must be pulled up or pulled down.
Serial Data Output Pin for SPI I/F
This pin outputs “Hi-Z” during power-down state.
This pin must be pulled up or pulled down.
Serial Data In/Output Pin for I2C I/F
This pin outputs “Hi-Z” during power-down state.
Serial Data Clock Input Pin for SPI I/F
Serial Data Clock Input Pin for I2C I/F
Serial Data Input Pin for SPI I/F
I2C I/F Mode Select Input Pin
I2CFIL = “L”: Fast Mode (400kHz)
I2CFIL = “H”: Fast Mode Plus (1MHz) (should be fixed to TVDD2)
Power-down Pin
Use this pin to power down the AK7735.
The PDN pin should be held “L” when power is supplied.
VREG Output Pin
Connect a 2.2uF(±30%) ceramic capacitor between this pin and
DVSS3. Do not connect this pin to an external circuit.
Digital Ground 3 Pin 0V
Digital Core Power Supply Pin 3.0~3.6V (typ.3.3V)
016014707-E-00
TVDD
TVDD
TVDD
TVDD
TVDD
TVDD
LVDD
-
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[AK7735]
No.
Pin Name
I/O
Supply
Power
Function
AIN2RN
AIN4R
AIN2RP
AIN3R
AIN2LN
AIN4L
AIN2LP
AIN3L
INN2
AIN1R
INP2
INN1
AIN1L
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC2 Rch Inverted Differential Input 2 Pin
ADC2 Rch Single-ended Input 4 Pin
ADC2 Rch Non-inverted Differential Input 2 Pin
ADC2 Rch Single-ended Input 3 Pin
ADC2 Lch Inverted Differential Input 2 Pin
ADC2 Lch Single-ended Input 4 Pin
ADC2 Lch Non-inverted Differential Input 2 Pin
ADC2 Lch Single-ended Input 3 Pin
ADC1 Rch Inverted Differential Input 2 Pin
ADC1 Rch Single-ended Input 1 Pin
ADC1 Rch Non-inverted Differential Input 2 Pin
ADC1 Lch Inverted Differential Input 1 Pin
ADC1 Lch Single-ended Input 1 Pin
INP1
I
40
MPREF
O
41
MPWR
O
42
43
AVDD
AVSS
-
44
VCOM
O
45
VREFH
I
46
VREFL
I
47
AOUT1R
O
48
AOUT1L
O
ADC1 Lch Non-inverted Differential Input 1 Pin
Ripple Filter Pin for Microphone Power Supply
Connect a 1uF ceramic capacitor between this pin and AVSS.
Do not connect this pin to an external circuit.
Power Supply Output Pin for Microphone
This pin outputs “Hi-Z” during power-down state.
Analog Power Supply Pin 3.0~3.6V (typ.3.3V)
Analog Ground Pin 0V
Analog Common Voltage Output Pin
Connect a 2.2uF ceramic capacitor between this pin and AVSS.
Do not connect this pin to an external circuit.
This pin outputs “L” during power-down state.
Analog High-level Reference Voltage Input Pin
Connect this pin to AVDD.
Analog Low-level Reference Voltage Input Pin
Connect this pin to AVSS.
DAC1 Rch Analog Output Pin
This pin outputs “Hi-Z” during power-down state.
DAC1 Lch Analog Output Pin
This pin outputs “Hi-Z” during power-down state.
32
33
34
35
36
37
38
39
016014707-E-00
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
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[AK7735]
■ Handling
of Unused Pins
Unused I/O pins must be connected appropriately.
Classification
Analog
Digital
■
Pin Name
MPREF, MPWR, AIN1L/INP1, INN1, AIN1R/INP2, INN2,
AIN2LP/AIN3L, AIN2LN/AIN4L, AIN2RP/AIN3R,
AIN2RN/AIN4R, AOUT1L, AOUT1R, AOUT2L, AOUT2R
XTI, XTO, SDOUT1/RDY, STO/RDY/SDOUT2,
SDOUT3/CLKO/GPO1, SDOUT4/GPO2
SDIN4, SDIN3/JX3, SDIN2/JX0, SDIN1, LRCK1, BICK1,
LRCK2/JX1, BICK2/JX2, LRCK3, BICK3, TESTI
Table 1. Handling of Unused Pins
Setting
Open
Open
Connect to DVSS1/DVSS2
Internal Pulled-down Pins Status
No.
Pin Name
3
18
19
15
16
4
6
20
23
7
5
29
TESTI
LRCK1
BICK1
LRCK2/JX1
BICK2/JX2
LRCK3
BICK3
SDOUT1/RDY
STO/RDY/SDOUT2
SDOUT3/CLKO/GPO1
SDOUT4/GPO2
AVDRV
Power Down Status
PDN pin = “L”
Power Down Release
PDN pin = “H”
(Slave mode)
Pulled-down (25kΩ)
Pulled-down (25kΩ)
Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ)
Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ)
Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ)
Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ)
Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ)
Pulled-down (50kΩ) Input (Pulled-down) (46 kΩ)
Pulled-down (50kΩ)
Output
Pulled-down (50kΩ)
Output
Pulled-down (50kΩ)
Output
Pulled-down (50kΩ)
Output
Pulled-down (70Ω)
Output
Table 2. Internal Pulled-down Pins Status
Power Down Release
PDN pin = “H”
(Master mode)
Pulled-down (25kΩ)
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Note
* 2. Typical resistance value when LVDD=TVDD=VDD33=3.3V.
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[AK7735]
■ Power-down
No
44
40
41
Status of Output Pins
Pin Name
VCOM
MPREF
MPWR
I/O
O
O
O
Power-down Status
“L” Output
“L” Output
“Hi-Z” Output
No
4
6
25
Pin Name
LRCK3
BICK3
SO/SDA
I/O
I/O
I/O
I/O
48 AOUT1L
O “Hi-Z” Output
20 SDOUT1/RDY
O
47 AOUT1R
O “Hi-Z” Output
23 STO/RDY/SDOUT2
O
2
AOUT2L
O “Hi-Z” Output
7
SDOUT3/CLKO/GPO1
O
1
AOUT2R
O “Hi-Z” Output
5
SDOUT4/GPO2
O
18 LRCK1
I/O Input
13 XTO
O
19 BICK1
I/O Input
29 AVDRV
O
15 LRCK2/JX1
16 BICK2/JX2
I/O Input
I/O Input
Power-down Status
Input
Input
“Hi-Z” Output
“L” Output
(Pulled-down)
“L” Output
(Pulled-down)
“L” Output
(Pulled-down)
“L” Output
(Pulled-down)
“Hi-Z” Output
“L” Output
(Pulled-down)
Table 3. Power-down Status of Output Pins
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[AK7735]
6.
Absolute Maximum Ratings
(AVSS=DVSS1=DVSS2=DVSS3=0V * 3)
Parameter
Symbol
Min.
Max.
Unit
Power Supplies
Analog
AVDD
-0.3
4.3
V
Digital1(Core)
LVDD
-0.3
4.3
V
Digital2(I/F)
TVDD
-0.3
4.3
V
Digital3(I/F)
VDD33
-0.3
4.3
V
Difference (AVSS, DVSS1, DVSS2, DVSS3) * 3
ΔGND
-0.3
0.3
V
mA
Input Current (except power supply pins)
IIN
±10
－
Analog Input Voltage * 4
VINA
-0.3
(AVDD+0.3) or 4.3
V
Digital Input Voltage * 5
VIND1
-0.3
(TVDD+0.3) or 4.3
V
Digital Input Voltage * 6
VIND2
-0.3
(VDD33+0.3) or 4.3
V
Ambient Temperature (AK7735VQ)
Ta
-40
85
C
Ambient Temperature (AK7735EQ)
Ta
-20
85
C
Storage Temperature
Tstg
-65
150
C
Notes
* 3. All voltages are with respect to ground. AVSS and DVSS1-3 must be connected to the same ground.
* 4. The maximum analog input voltage is smaller value between (AVDD+0.3)V and 4.3V.
* 5. The maximum digital input voltage of SDIN1, SDIN2/JX0, LRCK1, BICK1, LRCK2/JX1, BICK2/JX2,
PDN, SCLK/SCL, CSN and SI/I2CFIL pins is smaller value between (TVDD+0.3)V and 4.3V.
* 6 . The maximum digital input voltage of SDIN3/JX3, SDIN4, LRCK3, BICK3, TESTI and XTI pins is
smaller value between (VDD33+0.3)V and 4.3V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal
operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS=DVSS1=DVSS2=DVSS3=0V * 3)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supplies
Analog
AVDD
3.0
3.3
3.6
V
Digital1(Core)
LVDD
3.0
3.3
3.6
V
Digital2(I/F)
TVDD
1.7
3.3
3.6
V
Digital3(I/F)
VDD33
3.0
3.3
3.6
V
Difference1
AVDD – LVDD
-0.1
0
0.1
V
Difference2
AVDD – VDD33
-0.1
0
0.1
V
Difference3
LVDD – VDD33
-0.1
0
0.1
V
Difference4
LVDD – TVDD
-0.1
V
Notes
* 7. The power-up sequence with AVDD, DVDD, TVDD and VDD33 is not critical. The PDN pin should
be held “L” when power is supplied. The PDN pin is allowed to be “H” after all power supplies are
applied and settled.
* 8. Do not turn off the power supply of the AK7735 with the power supply of the peripheral device turned
on. When using the I2C interface, pull-up resistors of SDA and SCL pins should be connected to
TVDD or less voltage.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
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[AK7735]
8.
■
Electrical Characteristics
Analog Characteristics
1. MIC AMP
(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; AVSS=DVSS1=DVSS2=DVSS3=0V;
ADC1VL/R bits=“0”)
Parameter
Min.
Typ.
Input Impedance
14
20
MGNL[3:0]bits=0h, MGNR[3:0]bits=0h
-1
0
MGNL[3:0]bits=1h, MGNR[3:0]bits=1h
1
2
MGNL[3:0]bits=2h, MGNR[3:0]bits=2h
3
4
MGNL[3:0]bits=3h, MGNR[3:0]bits=3h
5
6
MGNL[3:0]bits=4h, MGNR[3:0]bits=4h
7
8
MGNL[3:0]bits=5h, MGNR[3:0]bits=5h
9
10
MIC
MGNL[3:0]bits=6h, MGNR[3:0]bits=6h
11
12
AMP
MGNL[3:0]bits=7h, MGNR[3:0]bits=7h
13
14
Gain
MGNL[3:0]bits=8h, MGNR[3:0]bits=8h
15
16
MGNL[3:0]bits=9h, MGNR[3:0]bits=9h
17
18
MGNL[3:0]bits=Ah, MGNR[3:0]bits=Ah
20
21
MGNL[3:0]bits=Bh, MGNR[3:0]bits=Bh
23
24
MGNL[3:0]bits=Ch, MGNR[3:0]bits=Ch
26
27
MGNL[3:0]bits=Dh, MGNR[3:0]bits=Dh
29
30
MGNL[3:0]bits=Eh, MGNR[3:0]bits=Eh
32
33
MGNL[3:0]bits=Fh, MGNR[3:0]bits=Fh
35
36
Max.
26
1
3
5
7
9
11
13
15
17
19
22
25
28
31
34
37
2. MIC Bias Output
(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; AVSS=DVSS1=DVSS2=DVSS3=0V;
Measurement Frequency =20Hz~20kHz)
Parameter
Min.
Typ.
Max.
Output Voltage * 9
2.3
2.5
2.7
MIC Bias
Load Resistance
2
Load Capaitance
30
Output Noise (A-weighted)
-114
-108
Note
* 9. Output voltage is proportional to AVDD (0.76 x AVDD).
016014707-E-00
Unit
kΩ
dB
Unit
V
kΩ
pF
dBV
2016/12
- 14 -
[AK7735]
3. MIC AMP + ADC1
(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; AVSS=DVSS1=DVSS2=DVSS3=0V; Signal Frequency
=1kHz; 24bit Data; BICK=64fs; @fs=48kHz, Measurement Frequency BW=20Hz ~ 20kHz;
@fs=96kHz,192kHz, BW=20Hz ~ 40kHz; ADC1VL/R bits=“0”; MGNL/R[3:0] bits=0h (0dB); Differential
Input, Unless otherwise specified.)
Parameter
Resolution
Differential Input
Differential Input
Differential Input
Single-ended Input
Input Full Scale
Single-ended Input
Voltage * 11
Single-ended Input
fs=48kHz * 13
fs=48kHz * 14
fs=96kHz * 13
S/(N+D)
(-1dBFS)
fs=96kHz * 14
fs=192kHz * 13
fs=192kHz * 14
fs=48kHz (A-weighted)
fs=48kHz (A-weighted)
fs=96kHz
Dynamic Range
(-60dBFS)
fs=96kHz
fs=192kHz
fs=192kHz
fs=48kHz (A-weighted)
fs=48kHz (A-weighted)
fs=96kHz
S/N
fs=96kHz
fs=192kHz
fs=192kHz
Inter-Channel Isolation
Channel Gain Mismatch
CMRR
* 16
Input Full Scale
Voltage * 10
MIC AMP
+ ADC1
* 13
* 14
* 15
* 13
* 14
* 15
* 13
* 14
* 13
* 14
* 13
* 14
* 13
* 14
* 13
* 14
* 13
* 14
* 12
Min.
Typ.
±2.1
±0.264
±2.55
2.1
0.264
2.55
85
±2.3
±0.290
±2.83
2.3
0.290
2.83
95
87
92
84
92
84
106
95
99
89
99
89
106
95
99
89
99
89
105
0.0
80
98
98
90
60
Max.
Unit
24
Bit
±2.5
±0.315 Vpp
±3.11
2.5
0.315 Vpp
3.11
dB
dB
dB
0.3
dB
dB
dB
Notes
* 10. INP1, INN1, INP2 and INN2 pins
* 11. AIN1L and AIN1R pins
* 12. Inter-channel isolation with -1dBFS signal input.
* 13. ADC1VL/R bits = “0”, MGNL/R[3:0] bits = 0h (0dB). Input full-scale voltage is proportional to AVDD
(0.7 x AVDD).
* 14. ADC1VL/R bits = “0”, MGNL/R[3:0] bits = 9h (+18dB). Input full-scale voltage is proportional to
AVDD (0.088 x AVDD).
* 15. ADC1VL/R bits = “1”, MGNL/R[3:0] bits = 0h (0dB). Input full-scale voltage is proportional to AVDD
(0.86 x AVDD).
* 16. Common mode rejection ratio when inputting 1kHz, 100mVpp sine wave to both differential inputs.
The value refers to the case when input a 1kHz, ±100mVpp sine wave as differential input.
016014707-E-00
2016/12
- 15 -
[AK7735]
4. ADC2
(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; AVSS=DVSS1=DVSS2=DVSS3=0V; Signal Frequency
=1kHz; 24bit Data; BICK=64fs; @fs=48kHz, Measurement Frequency BW=20Hz ~ 20kHz;
@fs=96kHz,192kHz, BW=20Hz ~ 40kHz; ADC2VL/R bits=“0”; Differential Input, Unless otherwise
specified.)
Parameter
Resolution
Input Impedance
Input Full Scale
Voltage * 17
Input Full Scale
Voltage * 18
ADC2
Differential Input
* 19
Differential Input
* 20
Single-ended Input * 19
Single-ended Input * 20
fs=48kHz
S/(N+D) (-1dBFS)
fs=96kHz
fs=192kHz
fs=48kHz (A-weighted)
Dynamic Range
fs=96kHz
(-60dBFS)
fs=192kHz
fs=48kHz (A-weighted)
S/N
fs=96kHz
fs=192kHz
Inter-Channel Isolation * 12
Channel Gain Mismatch
CMRR
* 16
Min.
Typ.
14
±2.1
±2.55
2.1
2.55
85
20
±2.3
±2.83
2.3
2.83
95
92
92
106
99
99
106
99
99
105
0.0
80
98
98
90
Max.
24
26
±2.5
±3.11
2.5
3.11
60
Notes
* 17. AIN2LP, AIN2LN, AIN2RP and AIN2RN pins
* 18. AIN3L, AIN3R, AIN4L and AIN4R pins
* 19. ADC2VL/R bits = “0”. Input full-scale voltage is propotional to AVDD (0.7 x AVDD).
* 20. ADC2VL/R bits = “1”. Input full-scale voltage is propotional to AVDD (0.86 x AVDD).
016014707-E-00
Unit
bit
kΩ
Vpp
Vpp
dB
dB
dB
0.3
dB
dB
dB
2016/12
- 16 -
[AK7735]
5. DAC
(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; AVSS=DVSS1=DVSS2=DVSS3=0V; Signal Frequency
=1kHz; 32bit Data; BICK=64fs; @fs=48kHz, Measurement Frequency BW=20Hz ~ 20kHz;
@fs=96kHz,192kHz, Measurement Frequency BW=20Hz ~ 40kHz)
Parameter
Min.
Typ.
Max.
Unit
Resolution
32
bit
Output Voltage
* 21
2.55
2.83
3.11
Vpp
fs=48kHz
80
91
S/(N+D)
fs=96kHz
89
dB
(0dBFS)
fs=192kHz
89
fs=48kHz (A-weighted)
100
108
Dynamic Range
fs=96kHz
101
dB
DAC1
(-60dBFS)
DAC2
fs=192kHz
101
fs=48kHz (A-weighted)
100
108
S/N
fs=96kHz
101
dB
fs=192kHz
101
Inter-Channel Isolation (fin=1kHz)
* 22
90
110
dB
Channel Gain Mismatch
0.0
0.7
dB
Load Resistance
* 23
10
kΩ
Load Capaitance
30
pF
Notes
* 21. The output voltage when 0dBFS signal input. The output voltage is proportional to AVDD (0.86 x
AVDD).
* 22. Inter-channel isolation between each DAC of Lch and Rch with 0dBFS signal input. (AOUT1L and
AOUT1R, and AOUT2L and AOUT2R)
* 23. to AC load
016014707-E-00
2016/12
- 17 -
[AK7735]
6. SRC
(Ta=25C; AVDD=LVDD=TVDD=VDD33=3.3V; AVSS=DVSS1=DVSS2=DVSS3=0V; Signal Frequency
=1kHz; 24bit Data; Measurement Frequency BW=20Hz ~ FSO/2)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Resolution
24
bit
Input Sample Rate
FSI
8
192
kHz
Output Sample Rate
FSO
8
192
kHz
THD+N (Input=1kHz, 0dBFS)
Audio Mode
(SRCFAUD bit = “1”, SRCFEC bit = “0”)
FSO/FSI=192kHz/48kHz
FSO/FSI=44.1kHz/48kHz
FSO/FSI=48kHz/88.2kHz
FSO/FSI=48kHz/96kHz
FSO/FSI=44.1kHz/96kHz
FSO/FSI=48kHz/192kHz
FSO/FSI=8kHz/48kHz
SRC
Voice Mode
(SRCFAUD bit = “0”, SRCFEC bit = “0”)
FSO/FSI=24kHz/32kHz
FSO/FSI=16kHz/24kHz
FSO/FSI=24kHz/44.1kHz
FSO/FSI=16kHz/44.1kHz
FSO/FSI=8kHz/32kHz
Dynamic Range (Input=1kHz, -60dBFS)
Audio Mode
(SRCFAUD bit = “1”, SRCFEC bit = “0”)
FSO/FSI=192kHz/48kHz
FSO/FSI=44.1kHz/48kHz
FSO/FSI=48kHz/88.2kHz
FSO/FSI=48kHz/96kHz
FSO/FSI=44.1kHz/96kHz
FSO/FSI=48kHz/192kHz
FSO/FSI=8kHz/48kHz
Voice Mode
(SRCFAUD bit = “0”, SRCFEC bit = “0”)
FSO/FSI=24kHz/32kHz
FSO/FSI=16kHz/24kHz
FSO/FSI=24kHz/44.1kHz
FSO/FSI=16kHz/44.1kHz
FSO/FSI=8kHz/32kHz
Dynamic Range
(Input=1kHz, -60dBFS, A-weighted)
FSO/FSI=44.1kHz/48kHz
Ratio between Input and Output Sample Rate
016014707-E-00
FSO/FSI
0.167
-122
-125
-122
-133
-116
-133
-130
dB
dB
dB
dB
dB
dB
dB
-95
-98
-78
-69
-130
dB
dB
dB
dB
dB
132
136
136
135
136
136
130
dB
dB
dB
dB
dB
dB
dB
134
137
132
128
130
dB
dB
dB
dB
dB
137
6
dB
-
2016/12
- 18 -
[AK7735]
■ Power
Consumption
(Ta=25C; AVDD=LVDD=VDD33=3.0~3.6V(Typ=3.3V, Max=3.6V); TVDD=1.7~3.6V(Typ=3.3V,
Max=3.6V); AVSS=DVSS1=DVSS2=DVSS3=0V; fs=192kHz; BICK=64fs; Master Mode;
SDOUT1~4/LRCK1~3/BICK1~3=Output; CL=20pF)
Parameter
Symbol
Min.
Typ.
Max.
Unit
AVDD
23
33
mA
LVDD
55
98
mA
Power-Up * 24
(PDN pin = “H”)
TVDD
4
6
mA
VDD33
5
8
mA
AVDD
0.01
mA
LVDD
0.01
mA
Power-Down
(PDN pin = “L”)
TVDD
0.01
mA
VDD33
0.01
mA
Note
* 24. The current of LVDD changes depending on the system frequency and contents of DSP program.
016014707-E-00
2016/12
- 19 -
[AK7735]
9.
Digital Filter Characteristics
■
ADC Block
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V)
1. Sharp Roll-Off Filter (ADSD bit = “0”, ADSL bit = “0”)
fs=48kHz
Parameter
SHARP ROLL-OFF
Passband * 25
0dB ~ -0.06dB
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~20kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
fs=96kHz
Parameter
SHARP ROLL-OFF
Passband * 25
0dB ~ -0.06dB
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~40kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
fs=192kHz
Parameter
SHARP ROLL-OFF
Passband * 25
0dB ~ -0.04dB
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~40kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
22.1
0
20
kHz
kHz
kHz
dB
1/fs
1/fs
0.9
Hz
23.7
27.8
85.0
FR
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
44.2
0
20
kHz
kHz
kHz
dB
1/fs
1/fs
1.9
Hz
47.5
55.6
85.0
FR
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
83.7
0
16
kHz
kHz
kHz
dB
1/fs
1/fs
3.8
Hz
96.0
122.9
85.0
FR
016014707-E-00
2016/12
- 20 -
[AK7735]
2. Slow Roll-Off Filter (ADSD bit = “0”, ADSL bit = “1”)
fs=48kHz
Parameter
SLOW ROLL-OFF
Passband * 25
0dB ~ -0.074dB
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~20kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
fs=96kHz
Parameter
SLOW ROLL-OFF
Passband * 25
0dB ~ -0.074dB
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~40kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
fs=192kHz
Parameter
SLOW ROLL-OFF
Passband * 25
0dB ~ -0.1dB
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~40kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
12.5
0
8
kHz
kHz
kHz
dB
1/fs
1/fs
0.9
Hz
19.2
36.5
85.0
FR
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
25
0
8
kHz
kHz
kHz
dB
1/fs
1/fs
1.9
Hz
38.5
73.0
85.0
FR
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
31.1
0
9
kHz
kHz
kHz
dB
1/fs
1/fs
3.8
Hz
62.3
145.9
85.0
FR
016014707-E-00
2016/12
- 21 -
[AK7735]
3. Short Delay Sharp Roll-Off Filter (ADSD bit = “1”, ADSL bit = “0”)
fs=48kHz
Parameter
SHORT DELAY SHARP ROLL-OFF
0dB ~ -0.06dB
Passband * 25
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~20kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
fs=96kHz
Parameter
SHORT DELAY SHARP ROLL-OFF
0dB ~ -0.06dB
Passband * 25
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~40kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
fs=192kHz
Parameter
SHORT DELAY SHARP ROLL-OFF
0dB ~ -0.04dB
Passband * 25
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~40kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
22.1
6
kHz
kHz
kHz
dB
1/fs
1/fs
0.9
Hz
23.7
27.8
85.0
2.6
FR
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
44.2
6
kHz
kHz
kHz
dB
1/fs
1/fs
1.9
Hz
47.5
55.6
85.0
2.6
FR
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
83.7
7
kHz
kHz
kHz
dB
1/fs
1/fs
3.8
Hz
96.0
122.9
85.0
0.2
FR
016014707-E-00
2016/12
- 22 -
[AK7735]
4. Short Delay Slow Roll-Off Filter (ADSD bit = “1”, ADSL bit = “1”)
fs=48kHz
Parameter
SHORT DELAY SLOW ROLL-OFF
0dB ~ -0.074dB
Passband * 25
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~20kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
fs=96kHz
Parameter
SHORT DELAY SLOW ROLL-OFF
0dB ~ -0.074dB
Passband * 25
-3.0dB
Stopband * 25
Stopband Attenuation
Group Delay Distortion : 0Hz~40kHz
Group Delay * 26
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
12.5
6
kHz
kHz
kHz
dB
1/fs
1/fs
0.9
Hz
19.2
36.5
85.0
2.6
FR
Symbol
Min.
PB
PB
SB
SA
GD
GD
0
Typ.
Max.
Unit
25
6
kHz
kHz
kHz
dB
1/fs
1/fs
1.9
Hz
38.5
73.0
85.0
2.6
FR
fs=192kHz
Parameter
Symbol
Min.
Typ.
Max.
Unit
SHORT DELAY SLOW ROLL-OFF
0dB ~ -0.1dB
PB
0
31.1
kHz
Passband * 25
-3.0dB
PB
63.2
kHz
Stopband * 25
SB
145.9
kHz
Stopband Attenuation
SA
85.0
dB
Group Delay Distortion : 0Hz~40kHz
GD
0.5
1/fs
Group Delay * 26
GD
7
1/fs
ADC Digital Filter(HPF)
Frequency Response
-3.0dB
FR
3.8
Hz
Notes
* 25. The passband and stopband frequencies are proportional to fs (sampling rate). High-pass filter
characteristics are not included. A reference value of each gain amplitude is the maximum value of
frequency response.
* 26. Delay time caused by the digital filter calculation. This time is measured from an analog signal input
until 24-bit data of both channels are set into the output register. It includes group delay by HPF.
016014707-E-00
2016/12
- 23 -
[AK7735]
■ DAC
Block
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V)
1. Sharp Roll-Off Filter (DASD bit = “0”, DASL bit = “0”)
fs=48kHz
Parameter
SHARP ROLL-OFF
Passband * 27
0.05dB
3.0dB
Passband Ripple * 28
Stopband * 27
Stopband Attenuation * 30, * 31
Group Delay * 29
Digital Filter + SCF + SMF * 30
Frequency Response : 0 20.0kHz
fs=96kHz
Parameter
SHARP ROLL-OFF
Passband * 27
0.05dB
3.0dB
Passband Ripple * 28
Stopband * 27
Stopband Attenuation * 30, * 31
Group Delay * 29
Digital Filter + SCF + SMF * 30
Frequency Response : 0 40.0kHz
fs=192kHz
Parameter
SHARP ROLL-OFF
Passband * 27
0.05dB
3.0dB
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
Max.
Unit
21.7
kHz
kHz
dB
kHz
dB
1/fs
23.4
-0.0032
26.3
80.0
0.0032
27.3
-0.3
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
0.1
dB
Max.
Unit
43.5
kHz
kHz
dB
kHz
dB
1/fs
46.8
-0.0032
52.5
80.0
0.0032
27.3
-0.5
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
0.1
dB
Max.
Unit
87.0
kHz
kHz
dB
kHz
dB
1/fs
93.6
Passband Ripple * 28
-0.0032
0.0032
Stopband * 27
105.0
Stopband Attenuation * 30, * 31
80.0
Group Delay * 29
27.3
Digital Filter + SCF + SMF * 30
Frequency Response : 0 80.0kHz
-1.9
0.1
dB
Notes
* 27. The passband and stopband frequencies are proportional to fs (sampling rate).
“PB = 0.4535 fs, SB = 0.546 fs”
* 28. Pass-band gain amplitude of double over sampling filter at the first step of Interpolator.
* 29. Delay time caused by the digital filter calculation. This time is measured from setting of the
16/20/24/32-bit impulse data to the input registers to output of the analog peak signal.
* 30. The output level with a 1kHz, 0dB sine wave input is defined as 0dB.
* 31. Band width of Stopband Attenuation ranges from 0Hz to fs.
016014707-E-00
2016/12
- 24 -
[AK7735]
2. Slow Roll-Off Filter (DASD bit = “0”, DASL bit = “1”)
fs=48kHz
Parameter
SLOW ROLL-OFF
Passband * 32
0.05dB
3.0dB
Passband Ripple * 28
Stopband * 32
Stopband Attenuation * 30, * 31
Group Delay * 29
Digital Filter + SCF + SMF * 30
Frequency Response : 0 20.0kHz
fs=96kHz
Parameter
SLOW ROLL-OFF
Passband * 32
0.05dB
3.0dB
Passband Ripple * 28
Stopband * 32
Stopband Attenuation * 30, * 31
Group Delay * 29
Digital Filter + SCF + SMF * 30
Frequency Response : 0 40.0kHz
fs=192kHz
Parameter
SLOW ROLL-OFF
Passband * 32
0.05dB
3.0dB
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
Max.
Unit
8.8
kHz
kHz
dB
kHz
dB
1/fs
19.8
-0.043
42.7
73.0
0.043
6.8
-5.0
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
0.1
dB
Max.
Unit
17.7
kHz
kHz
dB
kHz
dB
1/fs
39.5
-0.043
85.3
73.0
0.043
6.8
-5.2
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
0.1
dB
Max.
Unit
35.5
kHz
kHz
dB
kHz
dB
1/fs
79.0
Passband Ripple * 28
-0.043
0.043
Stopband * 32
171.0
Stopband Attenuation * 30, * 31
73.0
Group Delay * 29
6.8
Digital Filter + SCF + SMF * 30
Frequency Response : 0 80.0kHz
-5.9
0.1
Note
* 32. The passband and stopband frequencies are proportional to fs (sampling rate).
“PB = 0.185 fs, SB = 0.888 fs”
016014707-E-00
dB
2016/12
- 25 -
[AK7735]
3. Short Delay Sharp Roll-Off Filter (DASD bit = “1”, DASL bit = “0”)
fs=48kHz
Parameter
SHORT DELAY SHARP ROLL-OFF
0.05dB
Passband * 27
3.0dB
Passband Ripple * 28
Stopband * 27
Stopband Attenuation * 30, * 31
Group Delay * 29
Digital Filter + SCF + SMF * 30
Frequency Response : 0 20.0kHz
fs=96kHz
Parameter
SHORT DELAY SHARP ROLL-OFF
0.05dB
Passband * 27
3.0dB
Passband Ripple * 28
Stopband * 27
Stopband Attenuation * 30, * 31
Group Delay * 29
Digital Filter + SCF + SMF * 30
Frequency Response : 0 40.0kHz
fs=192kHz
Parameter
SHORT DELAY SHARP ROLL-OFF
0.05dB
Passband * 27
3.0dB
Passband Ripple * 28
Stopband * 27
Stopband Attenuation * 30, * 31
Group Delay * 29
Digital Filter + SCF + SMF * 30
Frequency Response : 0 80.0kHz
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
Max.
Unit
21.7
0.0031
kHz
kHz
dB
kHz
dB
1/fs
0.1
dB
Max.
Unit
43.5
kHz
kHz
dB
kHz
dB
1/fs
23.4
-0.0031
26.3
80.0
6.3
-0.3
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
46.8
-0.0031
52.5
80.0
0.0031
6.3
-0.5
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
0.1
dB
Max.
Unit
87.0
kHz
kHz
dB
kHz
dB
1/fs
93.6
-0.0031
105.0
80.0
0.0031
6.3
-1.9
016014707-E-00
0.1
dB
2016/12
- 26 -
[AK7735]
4. Short Delay Slow Roll-Off Filter (DASD bit = “1”, DASL bit = “1”)
fs=48kHz
Parameter
SHORT DELAY SLOW ROLL-OFF
0.05dB
Passband * 33
3.0dB
Passband Ripple * 28
Stopband * 33
Stopband Attenuation * 30, * 31
Group Delay * 29
Digital Filter + SCF + SMF * 30
Frequency Response : 0 20.0kHz
fs=96kHz
Parameter
SHORT DELAY SLOW ROLL-OFF
0.05dB
Passband * 33
3.0dB
Passband Ripple * 28
Stopband * 33
Stopband Attenuation * 30, * 31
Group Delay * 29
Digital Filter + SCF + SMF * 30
Frequency Response : 0 40.0kHz
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
Max.
Unit
12.0
kHz
kHz
dB
kHz
dB
1/fs
21.1
-0.05
41.5
82.0
0.05
5.3
-4.8
Symbol
Min.
PB
PB
PR
SB
SA
GD
0
Typ.
0.1
dB
Max.
Unit
24.2
kHz
kHz
dB
kHz
dB
1/fs
42.1
-0.05
83.0
82.0
0.05
5.3
-5.0
0.1
fs=192kHz
Parameter
Symbol
Min.
Typ.
Max.
SHORT DELAY SLOW ROLL-OFF
0.05dB
PB
0
48.4
Passband * 33
3.0dB
PB
84.3
Passband Ripple * 28
PR
-0.05
0.05
Stopband * 33
SB
165.9
Stopband Attenuation * 30, * 31
SA
82.0
Group Delay * 29
GD
5.3
Digital Filter + SCF + SMF * 30
Frequency Response : 0 80.0kHz
-5.7
0.1
Note
* 33. The passband and stopband frequencies are proportional to fs (sampling rate).
“PB = 0.252 fs, SB = 0.864 fs”
016014707-E-00
dB
Unit
kHz
kHz
dB
kHz
dB
1/fs
dB
2016/12
- 27 -
[AK7735]
■ SRC
Block
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V )
1. Audio Mode (SRCFAUD bit = “1”, SRCFEC bit = “0”)
Parameter
-0.01dB
-0.01dB
-0.01dB
Passband -0.01dB
-0.01dB
-0.01dB
-0.50dB
Stopband
Passband Ripple
0.980 ≤
0.900 ≤
0.533 ≤
0.490 ≤
0.450 ≤
0.225 ≤
0.167 ≤
0.980 ≤
0.900 ≤
0.533 ≤
0.490 ≤
0.450 ≤
0.225 ≤
0.167 ≤
0.225 ≤
0.167 ≤
0.450 ≤
0.167 ≤
FSO/FSI ≤ 6.000
FSO/FSI < 0.990
FSO/FSI < 0.909
FSO/FSI < 0.539
FSO/FSI < 0.495
FSO/FSI < 0.455
FSO/FSI < 0.227
FSO/FSI ≤ 6.000
FSO/FSI < 0.990
FSO/FSI < 0.909
FSO/FSI < 0.539
FSO/FSI < 0.495
FSO/FSI < 0.455
FSO/FSI < 0.227
FSO/FSI ≤ 6.000
FSO/FSI < 0.227
FSO/FSI ≤ 6.000
FSO/FSI < 0.455
Symbol
PB
PB
PB
PB
PB
PB
PB
SB
SB
SB
SB
SB
SB
SB
PR
PR
SA
SA
Min.
0
0
0
0
0
0
0
0.5417FSI
0.5021FSI
0.2974FSI
0.2812FSI
0.2604FSI
0.1802FSI
0.0970FSI
Typ.
Max.
0.4583FSI
0.4167FSI
0.2182FSI
0.2177FSI
0.1948FSI
0.1312FSI
0.0658FSI
±0.01
±0.50
95.2
Stopband
Attenuation
85.0
Group Delay * 34
67
GD
(Ts=1/fs)
(55/FSI+12/FSO)
Note
* 34. This value is SRC block only. It is the time from a rising edge of input LRCK after data is input to a
rising edge of output LRCK just before the data is output when there is no phase difference
between input and output LRCK.
016014707-E-00
2016/12
- 28 -
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
Ts
[AK7735]
2. Voice Mode (SRCFAUD bit = “0”, SRCFEC bit = “0”)
Passband
Parameter
-0.01dB
-0.01dB
-0.50dB
-0.50dB
-0.50dB
-0.50dB
-0.50dB
-0.50dB
Stopband
Passband Ripple
Stopband
Attenuation
0.980 ≤ FSO/FSI ≤ 6.000
0.900 ≤ FSO/FSI < 0.990
0.711 ≤ FSO/FSI < 0.910
0.653 ≤ FSO/FSI < 0.718
0.450 ≤ FSO/FSI < 0.660
0.327 ≤ FSO/FSI < 0.455
0.225 ≤ FSO/FSI < 0.330
0.167 ≤ FSO/FSI < 0.227
0.980 ≤ FSO/FSI ≤ 6.000
0.900 ≤ FSO/FSI < 0.990
0.711 ≤ FSO/FSI < 0.910
0.653 ≤ FSO/FSI < 0.718
0.450 ≤ FSO/FSI < 0.660
0.327 ≤ FSO/FSI < 0.455
0.225 ≤ FSO/FSI < 0.330
0.167 ≤ FSO/FSI < 0.227
0.900 ≤ FSO/FSI ≤ 6.000
0.167 ≤ FSO/FSI ≤ 0.910
0.900 ≤ FSO/FSI ≤ 6.000
0.653 ≤ FSO/FSI < 0.909
0.450 ≤ FSO/FSI ≤ 0.660
0.167 ≤ FSO/FSI < 0.455
Symb
ol
PB
PB
PB
PB
PB
PB
PB
PB
SB
SB
SB
SB
SB
SB
SB
SB
PR
PR
SA
SA
SA
SA
Group Delay * 34
(Ts=1/fs)
Min.
Typ.
0
0
0
0
0
0
0
0
0.5417FSI
0.5021FSI
0.3735FSI
0.3320FSI
0.2490FSI
0.1660FSI
0.1248FSI
0.0970FSI
Max.
Unit
0.4583FSI
0.4167FSI
0.3420FSI
0.3007FSI
0.2230FSI
0.1417FSI
0.1018FSI
0.0658FSI
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
dB
dB
±0.01
±0.50
95.2
90.0
70.0
60.0
67
(55/FSI+12/FSO)
GD
Ts
3. Echo Canceller Mode (SRCFEC bit = “1”)
Parameter
Passband
-0.01dB
Stopband
Passband Ripple
Stopband
Attenuation
Group Delay * 34
(Ts=1/fs)
0.167 ≤ FSO/FSI ≤ 6.000
0.167 ≤ FSO/FSI ≤ 6.000
0.167 ≤ FSO/FSI ≤ 6.000
Symbol
PB
SB
PR
Min.
0
0.5417FSI
0.167 ≤ FSO/FSI ≤ 6.000
SA
95.2
GD
016014707-E-00
Typ.
Max.
0.4583FSI
±0.01
dB
67
(55/FSI+12/FSO)
Ts
2016/12
- 29 -
Unit
kHz
kHz
dB
[AK7735]
10. DC Characteristics
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
High-Level Input Voltage 1 * 35
VIH1
75%TVDD
V
Low-Level Input Voltage 1 * 35
VIL1
25%TVDD
V
High-Level Input Voltage 2 * 36
VIH2
75%VDD33
V
Low-Level Input Voltage 2 * 36
VIL2
25%VDD33
V
SCL, SDA High-Level Input Voltage
VIH3
70%TVDD
V
SCL, SDA Low-Level Input Voltage
VIL3
30%TVDD
V
TVDD-0.3
V
VOH1
High-Level Output Voltage Iout= -100A * 37
0.3
V
VOL1
Low-Level Output Voltage Iout=100A * 37
VDD33-0.3
V
VOH2
High-Level Output Voltage Iout= -100A * 38
0.3
V
VOL2
Low-Level Output Voltage Iout=100A * 38
Fast Mode
TVDD ≥ 2.0V (Iout=3mA)
VOL3
0.4
V
TVDD < 2.0V (Iout=3mA)
VOL3
20%TVDD
V
SDA Low-Level
Output Voltage
Fast Mode Plus
TVDD ≥ 2.0V (Iout=20mA)
VOL3
0.4
V
TVDD < 2.0V (Iout=3mA)
VOL3
20%TVDD
V
Input Leak Current * 39
Iin
±10
A
Input Leak Current, Pulled down pins
Iid
66
A
Power Down
* 40, * 42
Input Leak Current, Pulled down pins
Iid
72
A
Power Down Release * 41, * 42
132
Input Leak Current, TESTI pin
Iid
A
17
Input Leak Current, XTI pin
lix
A
Notes
* 35. SDIN1, SDIN2/JX0, LRCK1, BICK1, LRCK2/JX1, BICK2/JX2, PDN, SCLK/SCL, CSN and
SI/I2CFIL pins. The SCL pin is not included.
* 36. SDIN3/JX3, SDIN4, LRCK3, BICK3, TESTI and XTI pins
* 37. SDOUT1/RDY, STO/RDY/SDOUT2 and SO/SDA pins. The SDA pin is not included.
* 38. SDOUT3/CLKO/GPO1 pin and SDOUT4/GPO2 pin
* 39. Except internal pulled-down pins and the XTI pin.
* 40. When the AK7735 is powered down (PDN pin = “L”), the pull down resistors of LRCK1, BICK1,
LRCK2/JX1, BICK2/JX2, LRCK3 and BICK3 pins is 50kΩ (Typ. @3.3V).
* 41. When the AK7735 is powered up (PDN pin = “H”), the pull down resistors of LRCK1, BICK1,
LRCK2/JX1, BICK2/JX2, LRCK3 and BICK3 pins is 46kΩ (Typ. @3.3V).
* 42. Leak current in case of inputting 3.3V when LVDD=TVDD=VDD33=3.3V.
016014707-E-00
2016/12
- 30 -
[AK7735]
11. Switching Characateristics
■ System
Clock
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V; CL=20pF)
Parameter
Symbol
Min.
Typ.
Max.
XTI Input Timing
a) X’tal Oscillator
Input Frequency
fXTI
11.2896
18.432
b) XTI Clock Input
Duty Cycle
40
50
60
Input Frequency
fXTI
0.256
24.576
CLKO Output Timing
Output Frequency
fCLKO
2.048
24.576
Duty Cycle
dCLKO
50
LRCK/BICK Input Timing (Slave Mode)
LRCK Input Timing
Frequency
fs
8
192
BICK Input Timing
Frequency * 43
fBCLK
0.256
24.576
Pulse Width Low
tBCLKL
0.4 / fBCLK
Pulse Width High
tBCLKH
0.4 / fBCLK
LRCK/BICK Output Timing (PLL Master Mode)
LRCK Output Timing
Frequency
fs
8
192
Pulse Width High
PCM Mode
tLRCKH
1/fBCLK
Except PCM Mode
tLRCKH
50
BICK Output Timing
Frequency * 43
fBCLK
0.256
24.576
Duty
dBCLK
50
Note
* 43. Required to meet the following expression: fBCLK ≥ 2 x fs x (Input/Output Data Length).
■ Power
Unit
MHz
%
MHz
MHz
%
kHz
MHz
ns
ns
kHz
ns
%
MHz
%
Down
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V)
Parameter
Symbol
Min.
Typ.
Max.
PDN Pulse Width * 44
tRST
600
Note
* 44. The PDN pin must be “L” when power up the AK7735.
Unit
ns
PDN
tRST
VIL1
Figure 3. Reset Timing
016014707-E-00
2016/12
- 31 -
[AK7735]
■ Serial
Data Interface (SDIN1 ~ SDIN4, SDOUT1 ~ SDOUT4)
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V; CL=20pF)
Parameter
Symbol Min.
Typ.
Max. Unit
Slave Mode
Delay Time from BICK “↑” to LRCK * 45
tBLRD
10
ns
Delay Time from LRCK to BICK “↑” * 45
tLRBD
10
ns
Serial Data Input Latch Setup Time
tBSIDS
10
ns
Serial Data Input Latch Hold Time
tBSIDH
5
ns
Delay Time from BICK “↓” to Serial Data Output * 46
tBSOD1
20
ns
Delay Time from BICK “↑”to Serial Data Output * 45, * 47 tBSOD2
5
30
ns
Master Mode
32, 48, 64,
BICK Frequency
fBCLK
fs
128, 256
BICK Duty Cycle
50
%
Delay Time from BICK “↓” to LRCK * 46
tMBL
-10
10
ns
Serial Data Input Latch Setup Time
tBSIDS
10
ns
Serial Data Input Latch Hold Time
tBSIDH
10
ns
Delay Time from BICK “↓” to Serial Data Output * 46, * 47 tBSOD
10
ns
Notes
* 45. It is measured from BICK “↓” when the BICK polarity is inverted by setting BCKPx bit = “1”.
* 46. It is measured from BICK “↑” when the BICK polarity is inverted by setting BCKPx bit = “1”.
* 47. Set SDOPHx bit to “1” and the data from SDOUTx pin is output based on BICK “↑” when BICK
speed is more than 12.288MHz such as when using TDM256 mode with 96kHz sampling
frequency or TDM128 mode with 192kHz sampling frequency in slave mode. SDOPHx bit must be
set to “0” in master mode.
016014707-E-00
2016/12
- 32 -
[AK7735]
1. Slave Mode
LRCK(I)
tBLRD
VIH
VIL
D
D
tLRBD
D
BICK(I)
tBSIDS
D
D
tBSIDH
SDIN1~4
VIH
VIL
VIH
VIL
D
Figure 4. Serial Interface Input Timing in Slave Mode
D
VIH
VIL
LRCK(I)
tBLRD
tLRBD
D
BICK(I)
VIH
VIL
tBSOD1
tBSOD1
D
D
50%TVDD
50%VDD33
SDOUT1~4
Figure 5. Serial Interface Output Timing in Slave Mode (SDOPHx bit = “0”)
VIH
VIL
LRCK(I)
tBLRD
tLRBD
D
BICK(I)
VIH
VIL
tBSOD2
D
tBSOD2
D
SDOUT1~4
50%TVDD
50%VDD33
Figure 6. Serial Interface Output Timing in Slave Mode (SDOPHx bit = “1”)
016014707-E-00
2016/12
- 33 -
[AK7735]
2. Master Mode
50%TVDD
50%VDD33
LRCK(O)
tMBL
tMBL
50%TVDD
50%VDD33
D
BICK(O)
tBSIDS
tBSIDH
SDIN1~4
VIH
VIL
D
Figure 7. Serial Interface Input Timing in Master Mode
LRCK(O)
50%TVDD
50%VDD33
BICK(O)
50%TVDD
50%VDD33
tBSOD
D
tBSOD
D
50%TVDD
50%VDD33
SDOUT1~4
Figure 8. Serial Interface Output Timing in Master Mode (SDOPHx bit = “0”)
016014707-E-00
2016/12
- 34 -
[AK7735]
■ SPI
Interface
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V; CL=20pF)
1. SPI Low Speed Mode
Parameter
μP Interface Signal
SCLK Frequency * 49
SCLK Low-level Width
SCLK High-level Width
Microcontroller → AK7735
CSN High-level Width
From CSN “↑” to PDN “↑”
From PDN “↑” to CSN “↓”
From CSN “↓” to SCLK “↓”
From SCLK “↑” to CSN “↑”
SI Latch Setup Time
SI Latch Hold Time
AK7735 → Microcontroller
Delay Time from SCLK “↓” to SO Output
SO Output Hold Time from SCLK “↑” * 48
Symbol
Min.
fSCLK
tSCLKL
tSCLKH
Typ.
Max.
Unit
3.0
160
160
MHz
ns
ns
tWRQH
tRST
tIRRQ
tWSC
tSCW
tSIS
tSIH
300
360
1
300
480
120
120
ns
ns
ms
ns
ns
ns
ns
tSOS
tSOH
120
120
ns
ns
2. SPI High Speed Mode
Parameter
Symbol
Min.
Typ.
Max.
Unit
μP Interface Signal
SCLK Frequency * 49
fSCLK
6
MHz
SCLK Low-level Width
tSCLKL
72
ns
SCLK High-level Width
tSCLKH
72
ns
Microcontroller → AK7735
CSN High-level Width
tWRQH
150
ns
From CSN “↑” to PDN “↑”
tRST
180
ns
From PDN “↑” to CSN “↓”
tIRRQ
1
ms
From CSN “↓” to SCLK “↓”
tWSC
150
ns
From SCLK “↑” to CSN “↑”
tSCW
240
ns
SI Latch Setup Time
tSIS
60
ns
SI Latch Hold Time
tSIH
60
ns
AK7735 → Microcontroller
Delay Time from SCLK “↓” to SO Output
tSOS
60
ns
SO Output Hold Time from SCLK “↑” * 48
tSOH
60
ns
Notes
* 48. Except when writing the 24th bit (8 bits command + 16 bits address) of the command code. This will
be the 8th bit (8 bits command) with “write preparation data read command (24H, 25H, 26H and
27H)”.
* 49. Dummy command writing for switching to SPI interface from I2C interface and control register
access can always be made in SPI high speed mode (Max. 6MHz). DSP RAM area can be
accessed in SPI low speed mode (Max. 3MHz) in clock reset state (CKRESETN bit = “0”) and can
also be accessed in SPI high speed mode (Max. 6MHz) when PLL is locked (CKRESETN bit = “1”
and PLL is locked). It is necessary to set DLRDY bit to “1” when accessing to the DSP RAM area
while PLL is unlocked (Figure 47).
016014707-E-00
2016/12
- 35 -
[AK7735]
VIH1
VIL1
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
VIH1
PDN
VIL1
VIH1
CSN
VIL1
tRST
tIRRQ
Figure 9. SPI Interface Timing 1
VIH1
VIL1
tWRQH
CSN
VIH1
SI
VIL1
tSIS
tSIH
VIH1
VIL1
SCLK
tWSC
tSCW
tWSC
tSCW
Figure 10. SPI Interface Timing 2 (Microcontroller → AK7735)
VIH1
VIL1
SCLK
50%TVDD
SO
tSOS
tSOH
Figure 11. SPI Interface Timing 3 (AK7735 → Microcontroller)
016014707-E-00
2016/12
- 36 -
[AK7735]
■ I2C
Interface
(Ta=-40 ~ 85C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD=1.7~3.6V; VDD33=3.0~3.6V;
AVSS=DVSS1=DVSS2=DVSS3=0V)
1. I2C: Fast Mode
Parameter
I2C Timing
SCL clock frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first Clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed By Input Filter
Capacitive load on bus
2. I2C: Fast Mode Plus
Parameter
I2C Timing
SCL clock frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first Clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed By Input Filter
Capacitive load on bus
Symbol
Min.
Typ.
Max.
Unit
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
-
400
0.3
0.3
50
400
kHz
s
s
s
s
s
s
s
s
s
s
ns
pF
Symbol
Min.
Typ.
Max.
Unit
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
0.5
0.26
0.5
0.26
0.26
0
0.05
0.26
0
-
-
1
0.12
0.12
50
550
MHz
s
s
s
s
s
s
s
s
s
s
ns
pF
VIH3
SDA
VIL3
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH3
SCL
VIL3
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
2
Figure 12. I C Interface Timing
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[AK7735]
12. Functional Descriptions
■ System
Clock
1. PLL Mode
The AK7735 has a PLL circuit to generate an internal operation clock. An input pin for the PLL reference
clock is selected by REFSEL[1:0] bits. REFMODE[4:0] bits set the frequency of the reference clock. A
reference clock input pin and the reference clock frequency must be changed during clock reset
(CKRESETN bit = “0”).
Use of Crystal
Oscillator
XTI
Available
BICK1
N/A
BICK2
N/A
BICK3
N/A
Table 4. PLL Reference Clock Input Pin Select
Mode
REFSEL[1:0] bits
0
1
2
3
00
01
10
11
Reference Clock Input Pin
(default)
Input Frequency
48kHz base
44.1kHz base
0
00000
256kHz
235.2kHz
(default)
1
00001
384kHz
352.8kHz
2
00010
512kHz
470.4kHz
3
00011
768kHz
705.6kHz
4
00100
1.024MHz
940.8kHz
5
00101
1.152MHz
1.0584MHz
6
00110
1.536MHz
1.4112MHz
7
00111
2.048MHz
1.8816MHz
8
01000
2.304MHz
2.1168MHz
9
01001
3.072MHz
2.8224MHz
10
01010
4.096MHz
3.7632MHz
11
01011
4.608MHz
4.2336MHz
12
01100
6.144MHz
5.6448MHz
13
01101
8.192MHz
7.5264MHz
14
01110
9.216MHz
8.4672MHz
15
01111
12.288MHz
11.2896MHz (X’tal available)
16
10000
18.432MHz
16.9344MHz (X’tal available)
17
10001
24.576MHz
22.5792MHz
Others
N/A
N/A
N/A
Table 5. PLL Reference Clock Frequency Setting (N/A: Not Available)
Mode
REFMODE[4:0] bits
The PLL block multiplies an input clock which is set by REFMODE[4:0] bits directly and generates a
147.456MHz/135.4752MHz master clock (PLLMCLK) for internal operation.
48kHz base
44.1kHz base
Master Clock
(PLLMCLK)
147.456MHz
135.4752MHz
Table 6. Internal Operation Master Clock
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[AK7735]
1-1. XTI Input
When using a crystal oscillator, connect it between XTI pin and XTO pin. Only 11.2896MHz, 12.288MHz,
16.9344MHz and 18.432MHz crystal oscillators are available. When using an external clock, the external
clock must be input to the XTI pin and the XTO pin must be open. The XTI pin should also be open when
not using XTI input.
XTI
XTI
ExternalClock
Clock
External
XTO
AK7735
XTO
Figure 13. Using Crystal Oscillator
AK7735
Figure 14. Using External System Clock
1-2. BICK Input
A stable BICK of single frequency is required when using clock input from BICKx (x=1~3) pin as
reference clock.
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[AK7735]
■
Audio HUB
1. Audio HUB
Audio HUB provides simultaneous data transmitting and flexible path configuration for various audio
sources by setting sample rate converters, input/output ports that support TDM mode and registers.
Therefore the AK7735 is able to support various use cases of audio systems.
2. Definition of Clock Sync Domain
The AK7735 has four Clock Sync Domains (Figure 15). Reference clocks (LRCKSDx, BICKSDx, x=1~4)
are output according to each register settings. The internal audio data and input/output data of the
AK7735 must be synchronized with one of these four Clock Sync Domains.
When MSNx bit =“0”, clocks from input pins (LRCKx pin/BICKx pin) are selected as reference clock of
clock sync domain 1~3. When MSNx bit = “1”, internal dividing clocks (MLRCKx/MBICKx) are selected
as reference clock of clock sync domain 1~3. For clock sync domain 4, internal dividing clocks
(MBICK4/MLRCK4) are selected as reference clock (BICKSD4/LRCKSD4) (Table 7).
Clock Sync Domain
Sync Domain x
(x=1 ~ 3)
MSNx bit
Reference Clock
MSNx = 0
Clocks from Input Pins (BICKx pin/LRCKx pin)
Internal Dividing Clocks (MBICKx/MLRCKx)
Reference clock is generated internally by CKSx[2:0],
BDVx[9:0] and SDVx[2:0] bits settings.
Internal Dividing Clocks (MBICK4/MLRCK4)
Reference clock is generated internally by CKS4[2:0],
BDV4[9:0] and SDV4[2:0] bits settings.
Table 7. Reference Clock of Clock Sync Domain
MSNx = 1
Sync Domain 4
LRCK1(pin Input)
BICK1(pin Input)
PLLMCLK
BICK1~3 pin
LRCKSD1
BICKSD1
CKS1[2:0]
XTI pin
DIV
MBICK1
BDV1[9:0]
p
MSN1
DIV
MLRCK1
SDV1[2:0]
LRCK2(pin Input)
BICK2(pin Input)
CKS2[2:0]
/
BDV2[9:0]
/
LRCKSD2
BICKSD2
SDV2[2:0]
MSN2
LRCK3(pin Input)
BICK3(pin Input)
CKS3[2:0]
/
BDV3[9:0]
/
LRCKSD3
BICKSD3
SDV3[2:0]
MSN3
CKS4[2:0]
/
BDV4[9:0]
/
SDV4[2:0]
LRCKSD4
BICKSD4
Figure 15. Definition of Clock Sync Domain
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[AK7735]
The clock source of internal dividing clock MBICKx is selected by CKSx[2:0] bits (Table 8). MBICKx is
generated by dividing the selected clock source according to the BDVx[9:0] bits setting (Table 9).
Additionally, MLRCKx is generated by dividing this MBICKx according to the SDVx[2:0] bits setting
(Table 10).
Clock Source
CKSx[2:0] bits
000
TieLow
(default)
001
PLLMCLK
010
XTI pin
011
BICK1 pin
100
BICK2 pin
101
BICK3 pin
Others
N/A
Table 8. Clock Source of Internal Dividing Clock (N/A: Not Available)
BDVx[9:0] bits
Divide by
0x000
1
0x001 – 0x1FF
BDVx+1
Table 9. MBICKx Setting
(default)
SDVx[2:0] bits
Divide by
000
64
(default)
001
48
010
32
011
128
100
256
Others
N/A
Table 10. MLRCKx Setting (N/A: Not Available)
Clock Sync Domain settings when PLLMCLK is selected as the clock source are shown in Table 11.
When PLLMCLK is selected as the clock source, frequency settings other than shown in Table 11 are
not available. Reference clocks for each setting are calculated as below.
PLLMCLK = 147.456MHz (48kHz base)/ 135.4752MHz (44.1kHz base)
MBICKx
= PLLMCLK divided by BDVx[9:0] bits setting
MLRCKx = MBICKx divided by SDVx[2:0] bits setting
ex) When PLLMCLK = 147.456MHz, BDVx[9:0] bits = 0x02F(divide by 48) and SDVx[2:0] bits =
“000”(divide by 64), MBICKx = 147.456MHz/48 = 3.072MHz, MLRCKx = 3.072MHz/64 =
48kHz.
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[AK7735]
BDVx[9:0]
bits
MBICKx
Dividing
0x23F
0x17F
0x11F
0x08F
0x047
0x17F
0x0FF
0x0BF
0x05F
0x02F
576
384
288
144
72
384
256
192
96
48
MBICKx(MHz)
48kHz
44.1kHz
Base
Base
0.256
0.2352
0.384
0.3528
0.512
0.4704
1.024
0.9408
2.048
1.8816
0.384
0.3528
0.576
0.5292
0.768
0.7056
1.536
1.4112
3.072
2.8224
SDVx[2:0]
bits
MLRCKx
Dividing
010
001
000
011
100
010
001
000
011
100
32
48
64
128
256
32
48
64
128
256
MLRCKx(kHz)
48kHz
44.1kHz
Base
Base
8
N/A
N/A
8
N/A
8
N/A
8
N/A
8
12
11.025
12
11.025
12
11.025
12
11.025
12
11.025
0x11F
288
0.512
0.4704
010
32
16
14.7
0x0BF
192
0.768
0.7056
001
48
16
14.7
0x08F
144
1.024
0.9408
000
64
16
14.7
0x047
72
2.048
1.8816
011
128
16
14.7
0x023
36
4.096
3.7632
100
256
16
14.7
0x0BF
192
0.768
0.7056
010
32
24
22.05
0x07F
128
1.152
1.0584
001
48
24
22.05
0x05F
96
1.536
1.4112
000
64
24
22.05
0x02F
48
3.072
2.8224
011
128
24
22.05
0x017
24
6.144
5.6448
100
256
24
22.05
0x08F
144
1.024
0.9408
010
32
32
29.4
0x05F
96
1.536
1.4112
001
48
32
29.4
0x047
72
2.048
1.8816
000
64
32
29.4
0x023
36
4.096
3.7632
011
128
32
29.4
0x011
18
8.192
7.5264
100
256
32
29.4
0x05F
96
1.536
1.4112
010
32
48
44.1
0x03F
64
2.304
2.1168
001
48
48
44.1
0x02F
48
3.072
2.8224
000
64
48
44.1
0x017
24
6.144
5.6448
011
128
48
44.1
0x00B
12
12.288
11.2896
100
256
48
44.1
0x02F
48
3.072
2.8224
010
32
96
88.2
0x01F
32
4.608
4.2336
001
48
96
88.2
0x017
24
6.144
5.6448
000
64
96
88.2
0x00B
12
12.288
11.2896
011
128
96
88.2
0x005
6
24.576
22.5792
100
256
96
88.2
0x017
24
6.144
5.6448
010
32
192
176.4
0x00F
16
9.216
8.4672
001
48
192
176.4
0x00B
12
12.288
11.2896
000
64
192
176.4
0x005
6
24.576
22.5792
011
128
192
176.4
Table 11. Clock Sync Domain Setting when PLLMCLK is Clock Source (N/A: Not Available)
For Clock Sync Domain, set BDVx[9:0] bits and SDVx[2:0] bits according to the input clock frequency
when the XTI or BICK pin input is selected as the clock source, as well as the PLLMCLK.
MBICKx = XTI pin or BICKx pin frequency divided by BDVx[9:0] bits setting
MLRCKx = MBICKx divided by SDVx[2:0] bits setting
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[AK7735]
3. Sampling Frequency Setting of ADC and DAC Blocks
Available sampling modes for analog block of the AK7735 are shown below. Sampling frequency mode
is set by FSMODE[4:0] bits. ADC1 can be operated by a different sampling frequency from ADC2, DAC1
and DAC2.
Mode
FSMODE[4:0] bits ADC2, DAC1, DAC2
ADC1
0
00000
8kHz
8kHz
(default)
1
00001
12kHz
12kHz
2
00010
16kHz
16kHz
3
00011
24kHz
24kHz
4
00100
32kHz
32kHz
5
00101
32kHz
16kHz
6
00110
32kHz
8kHz
7
00111
48kHz
48kHz
8
01000
48kHz
24kHz
9
01001
48kHz
16kHz
10
01010
48kHz
8kHz
11
01011
96kHz
96kHz
12
01100
96kHz
48kHz
13
01101
96kHz
32kHz
14
01110
96kHz
24kHz
15
01111
96kHz
16kHz
16
10000
96kHz
8kHz
17
10001
192kHz
192kHz
18
10010
192kHz
96kHz
19
10011
192kHz
48kHz
20
10100
192kHz
32kHz
21
10101
192kHz
16kHz
Others
N/A
N/A
N/A
Table 12. Sampling Frequency Settings of ADC and DAC Blocks (fs=48kHz base, N/A: Not Available)
Clock Sync Domain of the ADC1 (SDADC1) is selected by SDADC1[2:0] bits and Clock Sync Domain of
the ADC2, DAC1 and DAC2 (SDCODEC) is selected by SDCODEC[2:0] bits (Table 18).
The sampling frequency of LRCKSDx for SDADC1 and the sampling frequency of the ADC1 should be
the same. The sampling frequency of LRCKSDx for SDCODEC and the sampling frequency of the
ADC2, DAC1 and DAC2 should also be the same. SDADC1 and SDCODEC must be synchronized with
PLLMCLK.
Set SDADC1[2:0] bits to “000” (reference clock is fixed to “L”) when not using the ADC1. In the same
manner, SDCODEC[2:0] bits should be set to “000” when not using the ADC2, DAC1 and DAC2.
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[AK7735]
4. Master Clock Output Setting
The master clock output frequency setting of the CLKO pin is controlled by CLKOSEL[2:0] bits.
Output Frequency
Output Frequency
(fs=48kHz base)
(fs=44.1kHz base)
000
12.288MHz
11.2896MHz
001
24.576MHz
22.5792MHz
010
8.192MHz
7.5264MHz
011
6.144MHz
5.6448MHz
100
4.096MHz
3.7632MHz
101
2.048MHz
1.8816MHz
N/A
N/A
N/A
Table 13. CLKO Output Frequency Setting (N/A: Not Available)
Mode
CLKOSEL[2:0] bits
0
1
2
3
4
5
others
(default)
5. SDINx/BICKx/LRCKx pin Setting
The AK7735 has three BICK/LRCK pins and they are independent each other.
MSNx bit selects Master/Slave mode setting of the BICKx pin and the LRCKx pin (x=1~3). (Table 14)
MSNx bit (x=1~3)
BICKx pin, LRCKx pin
0
Slave Mode (Input)
1
Master Mode (Output)
Table 14. BICKx/LRCKx Pin Mode Selection
(default)
Note
* 50. Set MSNx bit to “0” when using the BICKx pin as PLL reference clock input pin.
When BICKx/LRCKx (x=1~3) pins are set to slave mode, the reference clocks of Clock Sync Domain x
are the clocks from BICKx/LRCKx pins (Table 7). When BICKx/LRCKx pins are set to master mode, the
output clocks of the BICKx/LRCKx pins can be selected from four Sync Domains by SDBCKx[2:0] bits
(x= 1~3). (Table 15)
MSNx bit SDBCKx[2:0] bits
BICKx pin/LRCKx pin
1
000
TieLow
(default)
1
001
BICKSD1, LRCKSD1
1
010
BICKSD2, LRCKSD2
1
011
BICKSD3, LRCKSD3
1
100
BICKSD4, LRCKSD4
1
Others
N/A
Table 15. Clock Sync Domain Setting of BICKx/LRCKx Pins in Master Mode (N/A: Not Available)
Note
* 51. SDBCKx[2:0] bits can be in the default setting “000” (TIeLow) when BICKx pin/LRCKx pin (x=1~3)
are in slave mode.
The AK7735 has four serial data input ports (SDINx pin). Synchronizing clock of SDINx pin can be
selected from three BICKx/LRCKx pins by EXBCKx[1:0] bits.
EXBCKx[1:0] bits
BICK/LRCK Synchronizing with SDINx Pin
00
TieLow
(default)
01
BICK1 pin, LRCK1 pin
10
BICK2 pin, LRCK2 pin
11
BICK3 pin, LRCK3 pin
Table 16. BICK/LRCK Setting Synchronizing with SDINx Pin
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[AK7735]
6. Clock Sync Domain Setting of DSP
Clock sync domain of DSP1 is selected by SDDSP1[2:0] bits. The DSP1 input port inherits the sync
domain of the input data. Clock sync domain of the output ports are set by SDDSP1O1[2:0] ~
SDDSP1O6[2:0] bits.
Clock sync domain of DSP2 is selected by SDDSP2[2:0] bits. The DSP2 input port inherits the sync
domain of the input data. Clock sync domain of the output ports are set by SDDSP2O1[2:0] ~
SDDSP2O6[2:0] bits.
DSP’s Sync Domain
DSP1
SDDSP1[2:0] bits
DSP2
SDDSP2[2:0] bits
Input Port Sync Domain
Output Port Sync Domain
Set by SDDSP1O1[2:0] bits ~
Inherit the Sync Domain of Input data
SDDSP1O6[2:0] bits
Set by SDDSP2O1[2:0] bits ~
Inherit the Sync Domain of Input data
SDDSP2O6[2:0] bits
Table 17. Sync Domain Setting of DSP
Note
* 52. The sync domains of Input/Output ports should synchronize with the sync domain of DSP.
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[AK7735]
■
Audio Data Path Setting
1. Data Bus, In/Output Port
The AK7735 has a 32-bit serial audio stereo data bus (Figure 17). Inputs and outputs of each internal
block and all input/output pins of the AK7735 are connected to this serial audio data bus. The port that
data is input to this serial audio data bus is defined as “input port” and the port that data is output from
the audio data bus is defined as “output port”. Each port selects Clock Sync Domain and inputs (outputs)
audio data that synchronized to the reference clock of the Clock Sync domain to the data bus (Figure
17).
A stereo data on each port is defined as “data source”. All data sources are connected to the serial audio
bus and a data source on any input port can be output to any output port. Data connection of the input
port and the output port with the same sampling frequency via data bus is defined as “data path”. Input
and output ports on the same data path should have the same Clock Sync Domain. If these ports have
different Clock Sync Domains, reference clocks (BICKSDx, LRCKSDx) must be synchronized and the
sampling frequency of LRCKSDx must be the same. However, phase synchronization of reference
clocks is not necessary and frequencies of BICKSDx can be different.
An SRC is necessary for data transmission between two ports that have clock sync domain with different
sampling frequencies or asynchronous reference clocks.
e.g.) Data Path Example (Figure 16)
It is an example of outputting data from the DAC1 after converting fs=8kHz input data from
the SDIN1 pin to fs=48kHz by SRC. Path 1 is defined from the SDIN1 pin to SRC1. Path2 is
defined from SRC1 to DAC1. Set the same clock sync domain for data ports of the Path1
(SDIN1 input and SRC1 output ports), and for the data ports of the Path2 (SRC1 input port
and DAC1), independently.
SDIN1pin
SDOUT1～
PATH1(fs=8kHz)
SRC1
SRCI1
SDOUT1～
SRCO1
SDIN1
5
: Input Port
SDIN1
SDIN1
SDIN1
5
: Output Port
DACI1
SDOUT1～
DAC1
5
PATH2(fs=48kHz)
Data Bus
Figure 16. Data Path Example
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[AK7735]
DIN1
SDOUT1～
DOUT1
SDIN1
DIN2
5
SDOUT1～
DOUT2
SDIN1
DIN3
5
SDOUT1～
DOUT3
SDIN1
DIN4
5
SDOUT1～
DOUT4
SDIN1
DIN5
5
SDOUT1～
DOUT5
SDIN1
DIN6
5
SDOUT1～
DOUT6
SDIN1
5
SDIN1
SDIN1pin
SDIN1
SDIN2pin
SDIN1
SDIN3pin
SDIN1
SDIN4pin
SDIN1
SDIN2
SDIN3
SDIN4
SDOUT1 pin
SDOUT1
SDOUT1～5
SDOUT2 pin
SDOUT2
SDOUT1～5
SDOUT3 pin
SDOUT3
SDOUT1～5
SDOUT4 pin
SDOUT4
SDOUT1～5
SRC1
SRC2
DIN1
SDOUT1～
DOUT1
SDIN1
DIN2
5
SDOUT1～
DOUT2
SDIN1
DIN3
5
SDOUT1～
DOUT3
SDIN1
DIN4
5
SDOUT1～
DOUT4
SDIN1
DIN5
5
SDOUT1～
DOUT5
SDIN1
DIN6
5
SDOUT1～
DOUT6
SDIN1
5
SRCI1
SDOUT1～
SRCO1
SDIN1
5
SRCI2
SDOUT1～
SRCO2
SDIN1
5
ALL0
SDIN1
SDIN1
SDOUT1～
: Input Port
5
DSP2
ADC1
SDIN1
ADC1
ADC2
SDIN1
ADC2
DAC1
DAC1
DAC2
5
SDOUT1～
DAC2
SDOUT1～
: Output Port
DSP1
Serial Data Bus (Stereo 32bit)5
Figure 17. AK7735 Audio Data Path
2. Data Bus Group Delay
When the input and output ports with the same sampling frequency are connected via data bus, group
delay of 2/fs occurs in total as audio data will have 1/fs group delay at each input and output port of the
data bus (fs is the sampling frequency of the sync domain of the input and output ports).
Therefore, this group delay will increase as the number of times that the data goes through the data path
increases.
In the example of Figure 16, 2/fs (fs=8kHz) group delay occurs when inputting the SDIN1 data to SRC
via data bus and another 2/fs (fs=48kHz) group delay occurs when inputting the SRC1 output data to
DAC1 via data bus.
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[AK7735]
3. Clock Sync Domain Setting of Input/output Port
Domain numbers are assigned to each Clock Sync Domain (Table 18). Each input/output port has
setting registers for Clock Sync Domain (Figure 20). Set a domain number to clock sync domain setting
registers for each input/output port. (Table 19, Table 20)
Domain Number Clock Sync Domain
0x0
TieLow
0x1
LRCKSD1, BICKSD1 (SD1)
0x2
LRCKSD2, BICKSD2 (SD2)
0x3
LRCKSD3, BICKSD3 (SD3)
0x4
LRCKSD4, BICKSD4 (SD4)
Table 18. Clock Sync Domain Number
If the output port sync domain setting is in auto mode, the output port inherits the sync domain of the
input data.
e.g.) Data Path Example
It is an example of outputting data from the DAC1 after converting fs=8kHz input data from
the SDIN1 pin to fs=48kHz by SRC (Figure 16). The output port of SRC1 is in auto mode.
Therefore the output port inherits the clock sync domain of SDIN1 input port.
Clock Sync Domain of the SDINx pin is automatically selected by setting EXBCKx[1:0] bits, MSN bit and
SDBCKx[2:0] bits (Table 15, Table 16).
e.g.) Clock sync domain 3 is selected for the SDIN2 pin when EXBCK2[1:0] bits = “011” and
MSN3 bit =“0” (Figure 18).
Figure 18. Clock Sync Domain Setting Example1 of SDINx Pin
e.g.) Clock sync domain 3 is selected for the SDIN1 pin when EXBCK1[1:0] bits = “001”, MSN2
bit =“1” and SDBCK2[2:0] bits = “011” (Figure 19).
Figure 19. S Clock Sync Domain Setting Example2 of SDINx Pin
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Figure 20. Clock Sync Domain Setting
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[AK7735]
4. Source Address, Source Selecting Registers
A source address is assigned to each input port source (Table 19). The output port can select any input
port source by setting a source address to the source select register.
Source
Name
Source Contents
Input Port
Clock Sync Domain
Setting Register
0x0000 0000 fixed
SDIN1 (pin) Input
TDMI1 Slot1, 2 Input
TDMI1 Slot3, 4 Input
ALL0
* 53
0x02
ALL0
SDIN1
SDIN1A
SDIN1B
SDIN1
* 54
0x03
SDIN1C
TDMI1 Slot5, 6 Input
0x04
SDIN1D
TDMI1 Slot7, 8 Input
0x05
SDIN2
SDIN2A
SDIN2 (pin) Input
TDMI2 Slot1, 2 Input
0x06
SDIN2B
TDMI2 Slot3, 4 Input
SDIN2
* 54
0x07
SDIN2C
TDMI2 Slot5, 6 Input
0x08
0x0A
SDIN2D
SDIN3
SDIN3A
SDIN3B
TDMI2 Slot7, 8 Input
SDIN3 (pin) Input
TDMI3 Slot1, 2 Input
TDMI3 Slot3, 4 Input
SDIN3
* 54
0x0B
SDIN3C
TDMI3 Slot5, 6 Input
0x0C
0x0E
SDIN3D
SDIN4
SDIN4A
SDIN4B
TDMI3 Slot7, 8 Input
SDIN4 (pin) Input
TDMI4 Slot1, 2 Input
TDMI4 Slot3, 4 Input
SDIN4
* 54
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
SDIN4C
SDIN4D
DOUT101
DOUT102
DOUT103
DOUT104
DOUT105
DOUT106
DOUT201
TDMI4 Slot5, 6 Input
TDMI4 Slot7, 8 Input
DSP1 Output 1
DSP1 Output 2
DSP1 Output 3
DSP1 Output 4
DSP1 Output 5
DSP1 Output 6
DSP2 Output 1
DOUT101
DOUT102
DOUT103
DOUT104
DOUT105
DOUT106
DOUT201
SDDSP1O1[2:0]
SDDSP1O2[2:0]
SDDSP1O3[2:0]
SDDSP1O4[2:0]
SDDSP1O5[2:0]
SDDSP1O6[2:0]
SDDSP2O1[2:0]
0x18
0x19
0x1A
DOUT202
DOUT203
DOUT204
DSP2 Output 2
DSP2 Output 3
DSP2 Output 4
DOUT202
DOUT203
DOUT204
SDDSP2O2[2:0]
SDDSP2O3[2:0]
SDDSP2O4[2:0]
0x1B
DOUT205
DSP2 Output 5
DOUT205
SDDSP2O5[2:0]
0x1C
0x1D
0x1E
0x1F
DOUT206
ADC1
ADC2
SRCO1
DSP2 Output 6
ADC1 Output
ADC2 Output
SRC1 Output
DOUT206
ADC1
ADC2
SRCO1
SDDSP2O6[2:0]
SDADC1[2:0]
SDCODEC[2:0]
SDSRCO1[2:0]
0x20
Others
SRCO2
N/A
SRC2 Output
N/A
SRCO2
N/A
SDSRCO2[2:0]
N/A
Source Address
0x00
0x01
0x09
0x0D
Table 19. Source Addresses of Input Ports (N/A: Not Available)
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Source Select
Registers
SELDO1A[5:0]
SELDO1B[5:0]
SELDO1C[5:0]
SELDO1D[5:0]
SELDO2A[5:0]
SELDO2B[5:0]
SELDO2C[5:0]
SELDO2D[5:0]
SELDO3A[5:0]
SELDO3B[5:0]
SELDO3C[5:0]
SELDO3D[5:0]
SELDO4A[5:0]
SELDO4B[5:0]
SELDO4C[5:0]
SELDO4D[5:0]
SELDA1[5:0]
SELDA2[5:0]
D1SELDI1[5:0]
D1SELDI2[5:0]
D1SELDI3[5:0]
D1SELDI4[5:0]
D1SELDI5[5:0]
D1SELDI6[5:0]
D2SELDI1[5:0]
D2SELDI2[5:0]
D2SELDI3[5:0]
D2SELDI4[5:0]
D2SELDI5[5:0]
D2SELDI6[5:0]
SELSRCI1[5:0]
SELSRCI2[5:0]
Contents
Output Port
Clock Sync Domain
Setting Register
SDOUT1(pin) Output
TDMO1 Slot1, Slot2
TDMO1 Slot3, Slot4
SDOUT1
SDDO1[2:0]
TDMO1 Slot5, Slot6
TDMO1 Slot7, Slot8
SDOUT2(pin) Output
TDMO2 Slot1, Slot2
TDMO2 Slot3, Slot4
SDOUT2
SDDO2[2:0]
TDMO2 Slot5, Slot6
TDMO2 Slot7, Slot8
SDOUT3(pin) Output
TDMO3 Slot1, Slot2
TDMO3 Slot3, Slot4
SDOUT3
SDDO3[2:0]
TDMO3 Slot5, Slot6
TDMO3 Slot7, Slot8
SDOUT4(pin) Output
TDMO4 Slot1, Slot2
TDMO4 Slot3, Slot4
SDOUT4
SDDO4[2:0]
TDMO4 Slot5, Slot6
TDMO4 Slot7, Slot8
DAC1 Input
DAC1
SDCODEC[2:0]
DAC2 Input
DAC2
DSP1 Input 1
DIN101
(Auto)
DSP1 Input 2
DIN102
(Auto)
DSP1 Input 3
DIN103
(Auto)
DSP1 Input 4
DIN104
(Auto)
DSP1 Input 5
DIN105
(Auto)
DSP1 Input 6
DIN106
(Auto)
DSP2 Input 1
DIN201
(Auto)
DSP2 Input 2
DIN202
(Auto)
DSP2 Input 3
DIN203
(Auto)
DSP2 Input 4
DIN204
(Auto)
DSP2 Input 5
DIN205
(Auto)
DSP2 Input 6
DIN206
(Auto)
SRC1 Input
SRCI1
(Auto)
SRC2 Input
SRCI2
(Auto)
Table 20. Source Select Registers of Output Ports
Notes
* 53. If the output port source is changed to ALL0 when the clock sync domain setting is “Auto”, the clock
sync domain before changing the data source will be kept. This clock sync domain should not be
stopped immediately after changing the data source otherwise the output data will not become
ALL0 correctly.
* 54. Clock Sync Domain of the SDINx pin is automatically selected by setting EXBCKx[1:0] bits, MSNx
bit and SDBCKx[2:0] bits (Table 14, Table 15, Table 16).
* 55. SDINxB~D are only valid in TDM mode. These ports are fixed to “0” if it is not in TDM mode.
* 56. Input data to the input port 1~6 of the DSP must be selected from a data based on a clock sync
domain which is synchronized with PLLMCLK.
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5. Input/Output Serial Interface Format
5-1. Data Clocks
The AK7735 has three LRCK/BICK pins that are input/output switchable to interface with external
equipment. MSNx bit controls master and slave modes of LRCKx/BICKx pins (Table 14). DCFx[2:0] bits
control each clock format of these pins independently. If LRCKx/BICKx pins are configured as slave
mode, set DCFx[2:0] bits according to the input clock. If LRCKx/BICKx pins are configured as master
mode, the output clock format is selected by DCFx[2:0] bits.
Mode
DCFx[2]
0
1
2
3
0
1
1
1
DCFx[1]
DCFx[0]
Clock Format
0
0
I2S Mode
0
1
DSP Mode
1
0
PCM Short Frame
1
1
PCM Long Frame
Table 21. AK7735 Data Clock Format
(default)
BCKPx bit controls the relationship of BICKx and LRCKx edges.
BCKPx bit
BICKx edge referenced to LRCKx start edge
0
Falling Edge
(default)
1
Rising Edge
Table 22. Relationship of BICKx and LRCKx Edges
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LRCKx
Lch
Rch
BICKx
Figure 21. I2S Mode
LRCKx
Lch
Rch
BICKx
Figure 22. DSP Mode
LRCKx
Lch + Rch
BICKx
Figure 23. PCM Short Frame / PCM Long Frame (BCKPx bit = “0”)
LRCKx
Lch + Rch
BICKx
Figure 24. PCM Short Frame / PCM Long Frame (BCKPx bit = “1”)
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5-2. Data Definitions
A serial bit stream that is sent or received by the AK7735 is a long sequence composed of “1” and “0”.
This data sequence has hierarchical levels of slot, word and bit.
Bit:
It is a smallest component in a serial data stream. The bit duration is one serial clock cycle.
Word:
It is a group of multiple bits that composes transmitting data between external devices and the
AK7735. Figure 25 shows an example of a word consists of eight bits.
Slot:
It is composed of a word and adequate additional bits for interfacing to an external device. In
Figure 25, the audio data is an 8-bit valid data and a 12-bit slot needs additional four zeroes to
satisfy an interface protocol of the external device.
If the word length is shorter than the slot length, the data alignment of the word will be the
beginning of the slot (MSB justified) or end of the slot (LSB justified). Figure 25 shows an
example of MSB justified format.
Bit
Word
Slot
Figure 25. Bit, Word and Slot Definitions
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[AK7735]
5-3. Input/ Output Interface Format
The AK7735 has four digital input ports and four digital output ports. The data format can be set
independently.
The input data format is determined by a combination of DISLx[1:0], DIEDGENx, DILSBEx and
DIDLx[1:0] bits settings (x=1~4). The output data format is determined by a combination of DOSLx[1:0],
DOEDGENx, DOLSBEx and DODLx[1:0] bits settings (x=1~4).
DISLx[1:0] bits / DOSLx[1:0] bits (x=1~4) control input/output data slot length.
DISLx[1] bit
DISLx[0] bit
Mode
Slot Length
DOSLx[1] bit DOSLx[0] bit
0
0
0
24bit
1
0
1
20bit
2
1
0
16bit
3
1
1
32bit
Table 23. Slot Length Setting of Input/Output Data
(default)
DIDLx[1:0] bits / DODLx[1:0] bits (x=1~4) control input/output audio data word length.
DIDLx[1] bit
DIDLx[0] bit
Mode
Word Length
DODLx[1] bit DODLx[0] bit
0
0
0
24bit
(default)
1
0
1
20bit
2
1
0
16bit
3
1
1
32bit
Table 24. Word Length Setting of Input/Output Audio Data
DILSBEx bit/ DOLSBEx bit (x=1~4) select the audio data format of a slot.
DILSBEx bit
Slot Data Format
DOLSBEx bit
0
MSB First
1
LSB First
Table 25. Slot Data Format Setting
(default)
DIEDGENx bit / DOEDGENx bit (x=1~4) select data transmission start timing of the data after second
channel
DIEDGENx bit
Start Timing
DOEDGENx bit
0
LRCK Edge Basis
(default)
1
Slot Length Basis
Table 26. Data Transmission Start Timing Selection of The Data After Second Channel
If the data transmitting timing is set to Slot length basis, the next channel’s data is transmitted
immediately without waiting a LRCK edge after transmitted one slot data (Figure 29~ Figure 33).
If the data transmitting timing is set to LRCK edge basis, the next channel’s data will not be transmitted
until a LRCK edge even finished transmitting one slot data (Figure 26 ~ Figure 28).
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5-3-1. Stereo Mode
AK7735 supports stereo mode. The BICKx pin should be set to arbitrary frequency more than “word
length x 2fs” when DIEDGENx bit = “0”. The BICKx pin should be set to arbitrary frequency more than
“slot length x 2fs” when DIEDGENx bit = “1”. BICK clock is supported up to 256fs (Max.24.576MHz).
The SDINx input pins of the AK7735 support stereo input mode. Two slots data input is available for
each pin. A source address is assigned to each SDINx input pin when using stereo input mode (Table
19). DISLx[1:0] bits control input data slot length of the SDINx pin. DIDLx[1:0] bits control the input data
word length of the SDINx pin. The slot data format is set by DILSBEx bit.
In stereo mode, DIEDGENx bit should be set to “0” if the data transmission timing of second channel is
LRCK edge basis. In this case, DISLx[1:0] bits setting are ignored.
The SDOUTx output pins of the AK7735 support stereo output mode. Two slots data output is available
for each pin. Each slot data can be assigned by setting SELDOxA[5:0] bits. DOSLx[1:0] bits control
output data slot length of the SDOUTx pin. DODLx[1:0] bits control the output data word length of the
SDOUTx pin. The slot data format is set by DOLSBEx bit.
In stereo mode, DOEDGENx bit must be set to “0” if the data transmission timing of second channel is
LRCK edge basis. In this case, DOSLx[1:0] bits setting are ignored.
Setting example of stereo mode is shown in Table 27.
Mode
Data Format
0
1
2
3
4
I S Compatible
PCM Short Frame
PCM Long Frame
5
Irregular I S
2
MSB Justified
LSB Justified
DCFx[2:0]
000
101
101
110
111
DILSBEx DIEDGENx
DOLSBEx DOEDGENx
0
0
0
0
1
0
0
1
0
1
2
DISLx[1:0]
DOSLx[1:0]
Slot Length
Slot Length
Slot Length
000
0
1
Table 27. Stereo Mode Setting Example (-: Do Not Care)
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DIDLx[1:0]
DODLx[1:0]
Word Length
Word Length
Word Length
Word Length
Word Length
Word Length
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[AK7735]
Mode 0: I²S Compatible Format
LRCKx
Lch
Rch
BICKx
SDINx
Lch Data (MSB First)
SDOUTx
Lch Data (MSB First)
Don’t Care
Don’t Care
Rch Data (MSB First)
Rch Data (MSB First)
Figure 26. I²S Compatible Format
Mode 1: MSB Justified Format
LRCKx
Lch
Rch
BICKx
SDINx
Lch Data (MSB First)
SDOUTx
Lch Data (MSB First)
Don’t Care
Don’t Care
Rch Data (MSB First)
Rch Data (MSB First)
Figure 27. MSB Justified Format
Mode 2: LSB Justified Format
LRCKx
Lch
Rch
BICKx
SDINx
SDOUTx
Don’t Care
Don’t Care
Lch Data (MSB First)
Lch Data (MSB First)
Rch Data (MSB First)
Rch Data (MSB First)
Figure 28. LSB Justified Format
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[AK7735]
Mode 3: PCM Short Frame Format
tBCLK
LRCKx
BICKx
SDINx
Lch Data (MSB First)
Rch Data (MSB First)
SDOUTx
Lch Data (MSB First)
Rch Data (MSB First)
Don’t Care
tBCLK x SlotLength
tBCLK x 2 x SlotLength
Figure 29. PCM Short Frame Format (BCKPx bit = “0”)
tBCLK
LRCKx
BICKx
SDINx
Lch Data (MSB First)
Rch Data (MSB First)
SDOUTx
Lch Data (MSB First)
Rch Data (MSB First)
Don’t Care
tBCLK x SlotLength
tBCLK x 2 x SlotLength
Figure 30. PCM Short Frame Format (BCKPx bit = “1”)
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[AK7735]
Mode 4: PCM Long Frame Format
tBCLK
LRCKx(Master)
LRCKx(Slave)
Don’t Care
BICKx
SDINx
Lch Data (MSB First)
Rch Data (MSB First)
SDOUTx
Lch Data (MSB First)
Rch Data (MSB First)
Don’t Care
tBCLK x SlotLength
tBCLK x 2 x SlotLength
Figure 31. PCM Long Frame Format (BCKPx bit = “0”)
tBCLK
LRCKx(Master)
LRCKx(Slave)
Don’t Care
BICKx
SDINx
Lch Data (MSB First)
Rch Data (MSB First)
SDOUTx
Lch Data (MSB First)
Rch Data (MSB First)
Don’t Care
tBCLK x SlotLength
tBCLK x 2 x SlotLength
Figure 32. PCM Long Frame Format (BCKPx bit = “1”)
Mode 5: Irregular I2S Format
LRCKx
Lch
Rch
BICKx
SDINx
Lch Data (MSB First)
Rch Data (MSB First)
SDOUTx
Lch Data (MSB First)
Rch Data (MSB First)
Don’t Care
Figure 33. Irregular I2S Format
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[AK7735]
5-3-2. TDM Mode
AK7735 supports TDM mode. BICK clock for data input/output should be set to 128fs, 192fs or 256fs
when using TDM mode. Sampling frequency up to 192kHz in 128fs mode (max. fs=128kHz in 192 mode,
max. fs=96kHz in 256 mode) is supported.
The SDINx input pins of the AK7735 support TDM mode. Eight slots data input is available at a
maximum. A source address is assigned to each 2 slot of SDINx input pins when using TDM mode.
(Table 19). DISLx[1:0] bits control input data slot length of the SDINx pin. DIDLx [1:0] bits control the
input data word length of the SDINx pin. The slot data format is set by DILSBEx bit.
In TDM mode, DIEDGENx bit must be set to “1” since the data transmission timing after second channel
is slot length basis. Slot length, word length and slot data format of each input data slot should be the
same setting.
The SDOUTx output pins of the AK7735 support TDM mode. Eight slots data output is available for each
pin at a maximum. Each slot data can be assigned independently by setting SELDOxA-D[5:0] bits in
every two slots. DOSLx[1:0] bits control output data slot length of the SDOUTx pin. DODLx[1:0] bits
control the output data word length of the SDOUTx pin. The slot data format is set by DOLSBEx bit. In
TDM mode, DOEDGENx bit must be set to “1” since the data transmission timing after second channel is
slot length basis. Slot length, word length and slot data format of each input data slot should be the same
setting.
Setting example of TDM mode is shown in Table 28.
Mode
Data Format
DCFx[2:0]
0
1
2
3
4
I2S Compatible
MSB Justified
LSB Justified
PCM Short Frame
PCM Long Frame
000
101
101
110
111
5
Irregular I2S
DILSBEx DIEDGENx DISLx[1:0]
DOLSBEx DOEDGENx DOSLx[1:0]
0
1
11 (32bit)
0
1
11 (32bit)
1
1
11 (32bit)
0
1
Slot Length
Slot Length
0
1
Slot Length
0
1
000
Table 28. TDM Mode Setting Example
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DIDLx[1:0]
DODLx[1:0]
Word Length
Word Length
Word Length
Word Length
Word Length
Word Length
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[AK7735]
Mode 0: I²S Compatible Format
256BICK
LRCKx
BICKx
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
SDINx/SDOUTx
Figure 34. TDM Mode I2S Compatible (BICK=256fs)
128BICK
LRCKx
BICKx
32 BICK
32 BICK
32 BICK
32 BICK
SLOT1
SLOT2
SLOT3
SLOT4
SDINx/SDOUTx
2
Figure 35. TDM Mode I S Compatible (BICK=128fs)
Mode 1: MSB Justified Format
256BICK
LRCKx
BICKx
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
SDINx/SDOUTx
Figure 36. TDM Mode MSB Justified Format (BICK=256fs)
128BICK
LRCKx
BICKx
32 BICK
32 BICK
32 BICK
32 BICK
SLOT1
SLOT2
SLOT3
SLOT4
SDINx/SDOUTx
Figure 37. TDM Mode MSB Justified Format (BICK=128fs)
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[AK7735]
Mode 2: LSB Justified Format
256BICK
LRCKx
BICKx
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
SDINx/SDOUTx
Figure 38. TDM Mode LSB Justified Format (BICK=256fs)
128BICK
LRCKx
BICKx
32 BICK
32 BICK
32 BICK
32 BICK
SLOT1
SLOT2
SLOT3
SLOT4
SDINx/SDOUTx
Figure 39. TDM Mode LSB Justified Format (BICK=128fs)
Mode 3: PCM Short Frame Format
256BICK
LRCKx
BICKx
Don’t Care
SDINx
SDOUTx
SLOT1
SLOT2 SLOT3
SLOT4 SLOT5
SLOT6 SLOT7 SLOT8
Figure 40. TDM Mode PCM Short Frame (BICK=256fs, BCKP bit = “0”) * 57
128BICK
LRCKx
BICKx
Don’t Care
SDINx
SDOUTx
SLOT1
SLOT2
SLOT3
SLOT4
Figure 41. TDM Mode PCM Short Frame (BICK=128fs, BCKP bit = “0”) * 57
Note
* 57. When BCKP bit = “1”, a BICK rising edge “↑” corresponds to a LRCK rising edge “↑”.
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Mode 4: PCM Long Frame Format
256BICK
LRCKx(Master)
Don’t Care
LRCKx(Slave)
BICKx
Don’t Care
SDINx
SDOUTx
SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT6
SLOT7 SLOT8
Figure 42. TDM Mode PCM Long Frame (BICK=256fs, BCKP bit = “0”) * 58
128BICK
LRCKx(Master)
Don’t Care
LRCKx(Slave)
BICKx
Don’t Care
SDINx
SDOUTx
SLOT1
SLOT2
SLOT3
SLOT4
Figure 43. TDM Mode PCM Long Frame (BICK=128fs, BCKP bit = “0”) * 58
Note
* 58. When BCKP bit = “1”, a BICK rising edge “↑” corresponds to a LRCK rising edge “↑”.
Mode 5: Irregular I2S Format
256BICK
LRCKx
BICKx
Don’t Care
SDINx
SDOUTx
SLOT1 SLOT2 SLOT3
SLOT4 SLOT5
SLOT6 SLOT7
SLOT8
Figure 44. TDM Mode Irregular I2S Format (BICK=256fs)
128BICK
LRCKx(Master)
BICKx
Don’t Care
SDINx
SDOUTx
SLOT1
SLOT2
SLOT3
SLOT4
2
Figure 45. TDM Mode Irregular I S Format (BICK=128fs)
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■ Power-up
Sequence
The AK7735 should be powered up when the PDN pin = “L”. Set the PDN pin to “H” to start the power
supply circuits for REF (reference voltage source) generator and digital circuits after all power supplies
are fed. By setting the PDN pin to “H”, control registers are initialized. Control register settings should be
made with an interval of 1ms or more after the PDN pin = “H”.
The PLL starts operation by a clock reset release (CKRESETN bit = “0” → “1”) and generates the
internal master clock after setting control registers. Therefore, necessary system clock must be input
before a clock reset release.
Interfacing with the AK7735 except control register settings should be made when PLL oscillation is
stabilized after clock reset release (take a 10ms interval or confirm “H” output of PLLLOCK signal from
the STO bit (Figure 46)). However, DSP program and coefficient data can be written even when the
system clock is stopped or during clock reset (CKRESETN bit= “0”). DSP program and coefficient data
can be written in 1ms by setting DLRDY bit “0” → “1”. DLRDY bit must be set to “0” after downloading
programs or data ( Figure 47).
112H
When using a crystal oscillator, release clock reset after crystal oscillation is stabilized. The stabilizing
time of crystal oscillation is dependent on the crystal and external circuits.
The system clock must not be stopped except during clock reset and power-down mode (PDN pin = “L”).
Figure 46. Power-up Sequence
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Figure 47. Power-up Sequence 2 (DLRDY bit Setting)
■ VREG
(Internal Circuit Drive Regulator)
The AK7735 has a regulator for driving internal digital circuits (VREG). Connect a 2.2μF (±30%)
capacitor between the AVDRV pin and the DVSS3 pin. The regulator starts operation by releasing
power-down mode, and control register settings can be made 1ms after the power-down release (PDN
pin=“H”).
The AK7735 has an overcurrent protection circuit to avoid abnormal heat of the device that is caused by
a short of the AVDRV pin to VSS and etc., and an overvoltage protection circuit to protect from exceeded
voltage when the voltage to the AVDRV pin gets too high. When these protection circuits perform,
internal circuits are powered down. The internal circuit will not return to a normal operation until being
reset by the PDN pin after removing the problems.
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[AK7735]
■ Power-down
and Reset
1. AK7735 Power-down and Reset Statuses and Power Management
Power-down and power-down release of the AK7735 is controlled by the PDN pin. After power-down is
released, the power management and reset of the AK7735 are controlled by registers such as
CKRESETN bit (Clock Reset), HRESETN bit (HUB Reset), D1RESETN and D2RESETN bits (DSP
reset), CRESETN bits (CODEC Reset) and power management bits for each block.
There are three states for the AK7735 other than normal operation: Power-down, Clock Reset and
System Reset.
1) The power-down state means the status that the PDN pin is “L”. In this state, all blocks of the
AK7735 stop the operation.
2) The clock reset state means the status that the PDN pin is “H” and CKRESETN bit is “0”. In this
state, the DSP, ADC, DAC and SRC blocks are not in operation because the PLL circuit and internal
clocks are stopped.
3) The system reset state means the status that the PDN pin is “H”, CKRESETN bit is “1”, HRESETN
bit is “0”, CRESETN bit is “0” and DxRESETN bit (x= 1, 2) is “0”. In this state, the DSP, ADC, DAC
and SRC blocks are not in operation although the PLL circuit and internal clocks are started. The
system reset is released by setting either HRESETN bit or CRESETN bit or DxRESETN bit (x=1, 2)
to “1”.
Setting
PDN
CKRESETN
DxRESETN
HRESETN CRESETN
pin
bit
bit (x=1, 2)
bit
bit
Power-down
L
x
x
x
x
Clock Reset
H
0
0
0
0
System Reset
* 59
H
1
0
0
0
System Reset Release * 60
H
1
1
1
1
Table 29. Reset State Definitions of the AK7735 (x: Don’t Care)
Notes
* 59. A stable clock should be supplied before releasing clock reset (CKRESETN bit = “1”).
* 60. The system reset is released by setting either HRESETN bit or CRESETN bit or DxRESETN bit
(x=1, 2) to “1”.
State
2. Power-down
The AK7735 can be powered down by bringing the PDN pin = “L”. Power-down status of output pins is
shown in Table 3.
3. Power-down Release
The REF generation circuit (reference voltage source) and a power supply circuit for internal digital
circuit are powered-up by bringing the PDN pin to “H” from “L” after an interval of 600ns or more when
AVDD, LVDD, TVDD and VDD33 are powered up. Control register settings should be made with an
interval of 1ms or more after setting the PDN pin = “H”.
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4. Clock Reset
When CKRESETN bit = “0” after power-down mode is released (PDN pin = “H”), the AK7735 is in clock
reset state. All blocks except the power supply circuits for REF generation and digital circuits are in
power-save mode. Even the internal PLL for master clock generation is powered down.
Control register settings should be made with an interval of 1ms (min) after releasing the power-down
mode. DSP program and coefficient data can be written in 1ms by setting DLRDY bit “0” → “1” during
clock reset. DLRDY bit must be set to “0” after downloading ( Figure 47).
112H
Necessary system clocks (Table 4, Table 5) should be input before the clock reset is released. The
internal PLL starts operation and the master clock is generated when clock reset is released
(CKRESETN bit = “1”). DSP program and coefficient data should be sent 10ms after clock reset release
or after confirming “H” output of PLLLOCK signal from the STO pin (Figure 46).
System clocks must be changed during clock reset or in power-down mode (PDN pin = “L”). The PLL
and the internal clocks are stopped by this clock reset and the clock change can be done safely. Change
register settings and system clock frequencies during the clock reset. After system clock is stabilized, the
PLL starts operation by setting CKRESETN bit to “1”.
Clock operated blocks (ADC, DAC and SRC) must be powered down before executing clock reset.
These blocks can be powered down simultaneously by setting HRESETN bit to “0” from “1”. Set
HRESETN bit to “1” from “0” with an interval of 10ms for stabilization of PLL after clock reset is released.
REFSEL Mode 1
REFSEL Mode 0
XTI
BICK1
CSN
SCLK (Simplified)
SI
C0
00
6E
00
C0
00
01
00
C0
00
00
xx
8x
C0
00
6E
0F
HRESETN
DxRESETN
CKRESETN
10ms
PLL Stop
Blocks except PLL are
PLL Stabilize
Input clock and clock mode can be changed
stopped
Command Code
Resume
Operation
& DSP Program Transition
Figure 48. Clock Mode Switching Sequence
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■ RAM
Clear
The AK7735 has a RAM clear function. After a DSP reset release, DRAM and DLRAM are cleared by
“0”. The internal PLL must have stable oscillation before a DSP reset release.
A period of 8/fs (fs: DSP operating sampling rate) is required from a DSP reset release to the RAM clear
start. The required time to clear RAM is about 112µs.
During the RAM clear period, it is possible to send a command to the DSP. (The DSP is stopped during
RAM clear sequence. The sent command is accepted automatically after this sequence is completed.)
PDN(pin)
DxRESETN bit (x=1,2)
DSP1, DSP2
RAM Clear
DSP1, DSP2
Operation Start
Period before RAM Clear Start
(8/fs)
RAM Clear Period (112us)
DSP Program Start
Figure 49. RAM Clear Sequence
Register and RAM settings of the AK7735 are not held if the PDN pin goes to “L”. The DRAM and
DLRAM are not held by a clock reset or a DSP reset.
State
Register PRAM CRAM DRAM DLRAM OFREG
Power Down
x
x
x
x
x
x
(PDN pin = “L”)
Clock Reset
Hold
Hold
Hold
x
x
Hold
(CKRESETN bit = “0”)
DSP Reset
Hold
Hold
Hold
x
x
Hold
(DxRESETN bit = “0”)
Table 30. Register and RAM Setting Status by Reset (x: Not Hold)
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■ STO
pin Output Status
The No. 23 pin has the function of the STO (status output) pin, the RDY pin and the SDOUT2 pin.
DO2SEL[1:0] bits control the function of this pin. The STO pin function is selected in the default setting.
When SDOUT2EN bit = “0” (default), the STO pin output is enabled. When SDOUT2EN bit = “1”, the
STO pin outputs “L”.
The STO pin outputs “L” when the AK7735 is powered up and the PDN pin is “L”. The STO pin outputs
“H” when the internal digital power-supply circuit (VREG) is powered up after releasing the power-down
(PDN pin = “H”).
After the power-down state is released, VREG shut down signal, PLL lock signal, WDT1 and WDT2
(watchdog timer) errors of the DSP, CRC error and SRC1~2 lock signal can be output from the STO pin
by control register settings. The AK7735 is distinguished as error state when the PDN pin = “H”,
DO2SEL[1:0] bits = “00”, SDOUT2EN bit = “0” and the STO pin = “L”.
VREG shut down status and WDT1-2 statuses, which are set by DSP instruction, are output from the
STO pin when the control register settings are in the default value.
PDN
pin
L
H
VREG
D1WDTEN bit
D2WDTEN bit
CRCE
bit
PLLLOCKE
bit
SRCLOCKE1 bit
SRCLOCKE2 bit
-
-
-
-
L
-
-
-
-
L
0
0
0
0
WDTnERR
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
1
CRCERR
PLLLOCKERR
SRCnLOCKERR
WDTnERR &
CRCERR &
PLLLOCKERR &
SRCLOCKERRn
Power
Down
Error
Normal
Operation
STO pin
Note
(default)
* 61, * 62
* 61
* 61, * 62
Table 31. STO pin Output Setting ( -: Not Care )
Notes
* 61. The STO pin outputs “L” if the one of status signal becomes “L” when setting multiple statuses to
the STO pin.
* 62. A DSP instruction setting is necessary when using WDT1 and WDT2 (watchdog timer).
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■ μP
Interface Setting and Pin Statuses
The AK7735 supports both SPI and I2C interfaces. When using SPI interface, release the power-down
state of the AK7735 while the CSN pin is “H”. When using I2C interface, the CSN pin must be pulled up
or down since it becomes a chip address pin. After a power-down release, the AK7735 is set to I2C
interface mode. SPI interface mode become enabled by sending the dummy command mentioned
below.
Input “0xDE → 0xADDA → 0x7A” to the SI/I2CFIL pin while the CSN pin is “L” after a falling edge “↓” of
the CSN pin for the dummy command. The data is in MSB first format.
CSN
SCLK
SI
don’tcare
(L/H)
0xDE (8bit)
0xADDA (16bit)
0x7A(8bit)
don’tcare
(L/H)
Statuses of the CSN, SO/SDA, SCLK/SCL and SI/I2CFIL pins are changed depending on the PDN pin.
SPI
Interface
I2C
Interface
PDN pin
L
H
CSN pin
input (“H”)
function
L
H
pull-up / pull-down
SO/SDA pin
Hi-Z
function
(pull-up / pull-down)
“Hi-Z”→ pull-up
SCLK/SCL pin SI/I2CFIL pin
input
input
function (pull-up)
function
function
function
input
input
“L”: I2C Fast Mode
“H”: I2C Fast Mode Plus
Table 32. μP Interface Setting
Note
* 63. The CSN pin and the SI/I2CFIL pin should be fixed to “L” or “H” when using I2C interface mode. The
SO/SDA pin should be pulled-up/down when using SPI interface mode.
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■ SPI
Interface
1. Configuration
The access format consists of Command code (8bits) + Address (16bits) + Data (MSB first).
Command code
Address
Data
Bit Length
8
16
Mentioned in
later section
Description
MSB bit is an R/W flag. The following 7 bits indicate access area such
as PRAM/ CRAM/Registers.
Address is fixed to 16bits.
Read/Write Data
Table 33. μP Interface Format
Write
CSN
SCLK
SI
don’tcare
(L/H)
Command Code (8bit)
Data (write)
Address (16bit)
SO
Echo Back
Hi-Z
don’tcare
(L/H)
Hi-Z
Figure 50. SPI Interface Timing (Write)
Read (Except Read Operation during Run）
CSN
SCLK
SI
don’tcare
(L/H)
Command Code (8bit)
SO
Data (Read)
Echo Back
Hi-Z
don’tcare
(L/H)
Address (16bit)
Hi-Z
Figure 51. SPI Interface Timing (Read) (Except Command 24H, 25H, 26H and 27H)
Read (during Run)
CSN
SCLK
SI
don’tcare
(L/H)
don’tcare
(L/H)
Command Code (8bit)
SO
Address (16bit)
Hi-Z
Data (Read)
Hi-Z
Figure 52. SPI Interface Timing (Read) (Command 24H, 25H, 26H and 27H)
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1-1. Write
Command
Address
Data Length
80H ~ 8FH
16bit
24bit x n
90H ~ 9FH
16bit
24bit x n
A2H
16bit
-
A3H
16bit
-
A4H
16bit
-
A5H
16bit
-
B2H
B3H
B4H
B5H
B8H
B9H
C0H
16bit
16bit
16bit
16bit
16bit
16bit
16bit
24bit x n
24bit x n
24bit x n
24bit x n
40bit x n
40bit x n
8bit x n
F2H
16bit
16bit
F4H
16bit
8bit
F5H
16bit
8bit
Description
Write preparation to CRAM of DSP1/DSP2 during RUN
(80H: write 1data, 81H: write 2data, ----, 8FH: write 16data) If
the actual amount of write operations exceeds the defined
amount, the data will be ignored.
Write preparation to OFREG of DSP1/DSP2 during RUN
(90H: write 1data, 91H: write 2data, ----, 9FH: write 16data) If
the actual amount of write operations exceeds the defined
amount, the data will be ignored.
Write execution to OFREG of DSP1 during RUN.
0 address should be written.
Write execution to OFREG of DSP2 during RUN.
0 address should be written.
Write execution to CRAM of DSP1 during RUN.
0 address should be written.
Write execution to CRAM of DSP2 during RUN.
0 address should be written.
Write operation to OFREG of DSP1 (during DSP reset)
Write operation to OFREG of DSP2 (during DSP reset)
Write operation to CRAM of DSP1 (during DSP reset)
Write operation to CRAM of DSP2 (during DSP reset)
Write operation to PRAM of DSP1 (during DSP reset)
Write operation to PRAM of DSP2 (during DSP reset)
Sequential Control Register Write
CRC Result Write
0 address should be written.
Write operation of DSP1 JX code
0 address should be written.
Write operation of DSP2 JX code
0 address should be written.
The data length is defined by the command code which specifies the area to be accessed. Writing other
than the above-mentioned command code is prohibited.
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1-2. Read
Command
24H
25H
26H
27H
32H
33H
34H
35H
38H
39H
40H
Address
0bit
0bit
0bit
0bit
16bit
16bit
16bit
16bit
16bit
16bit
16bit
Data Length
16bit + 24bit x n
16bit + 24bit x n
16bit + 24bit x n
16bit + 24bit x n
24bit x n
24bit x n
24bit x n
24bit x n
40bit x n
40bit x n
8bit x n
40H
16bit
8bit
40H
16bit
8bit
72H
16bit
16bit
76H
16bit
32bit x n
77H
16bit
32bit x n
Description
Read CRAM write preparation data of DSP1
Read OFREG write preparation data of DSP1
Read CRAM write preparation data of DSP2
Read OFREG write preparation data of DSP2
Read operation from OFREG of DSP1 (during DSP reset)
Read operation from OFREG of DSP2 (during DSP reset)
Read operation from CRAM of DSP1 (during DSP reset)
Read operation from CRAM of DSP2 (during DSP reset)
Read operation from PRAM of DSP1 (during DSP reset)
Read operation from PRAM of DSP2 (during DSP reset))
Sequential Control Register Read
Device Identification No.
(recognized as Register: Address = 0100H)
Device Revision No.
(recognized as Register: Address = 0101H)
CRC result Read
0 address should be written.
Sequential Read operation from MIR of DSP1. (max. 8)
0 address should be written. 28bits are upper-bit justified.
Lower 4 bits are for validity flags. Valid at “0000”. * 64
Sequential Read operation from MIR of DSP2. (max. 8)
0 address should be written. 28bits are upper-bit justified.
Lower 4 bits are for validity flags. Valid at “0000”. * 64
Note
* 64. Lower 4 bits for validity flags are common in eight MIR data. If the MIR data is updated by a DSP
program, all eight data flags become “0000”. If an MIR read command by a microcontroller is
executed, all eight data flags become “1111”.
When accessing RAM or control registers, data may be read from sequential address locations by
reading data continuously. Reading other than the above-mentioned command code is prohibited.
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2. Echo-Back Mode
The AK7735 has Echo-back mode that outputs the writing data sequentially from the SO pin.
2-1. Write
CSN
SI
COMMAND
ADDRESS1
COMMAND
SO
ADDRESS2
ADDRESS1
DATA1
ADDRESS2
DATA2
DATA1
don’tcare
(L/H)
COMMAND
ADDRESS1
COMMAND
Hi-Z
Figure 53. Echo-back Mode Writing (SPI)
The input data of the SI pin is echoed back on the SO pin by shifting 8-bits to the right. The last 1 byte
written data is not echoed-back. The data will not echoed-back when writing dummy command.
2-2. Read
CSN
SI
COMMAND
SO
ADDRESS1
COMMAND
don’tcare
(L/H)
ADDRESS2
DummyData
READ DATA
READ DATA
COMMAND
Hi-Z
ADDRESS1
COMMAND
Figure 54. Echo-back Mode Reading (SPI)
Data of the address1/2 fields are not echoed back in read operation. The read data on the SO pin is
output after writing to the address2 field.
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3. Command Format
3-1. DSP RAM Write and Read
3-1-1. Write Operation during DSP Reset
(1) Program RAM (PRAM) Write (during DSP reset)
Field
Write data
(1) COMMAND Code 0xB8 (DSP1) / 0xB9 (DSP2)
(2) ADDRESS1
0 0 0 0 A11 A10 A9 A8
(3) ADDRESS2
A7 A6 A5 A4 A3 A2 A1 A0
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be written continuously for each address.
(2) Coefficient RAM (CRAM) Write (during DSP reset)
Field
Write data
(1) COMMAND Code 0xB4 (DSP1) / 0xB5 (DSP2)
(2) ADDRESS1
0 0 0 A12 A11 A10 A9 A8
(3) ADDRESS2
A7 A6 A5 A4 A3 A2 A1 A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
(3) Offset REG (OFREG) Write (during system reset)
Field
Write data
(1) COMMAND Code 0xB2 (DSP1) / 0xB3 (DSP2)
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 0 D13 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
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3-1-2. Write Operation during RUN中
(1) Coefficient RAM (CRAM) Write Preparation (during RUN)
Preparation
Write data
(1) COMMAND Code 0x80~0x8F (one data at 0x80, sixteen data at 0x8F)
(2) ADDRESS1
0 0 0 A12 A11 A10 A9 A8
(3) ADDRESS2
A7 A6 A5 A4 A3 A2 A1 A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
(2) Coefficient RAM (CRAM) Write Operation (during RUN)
Execute
Write data
(1) COMMAND Code 0xA4 (DSP1) / 0xA5 (DSP2)
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
(3). Offset REG (OFREG) Write Preparation (during RUN)
Preparation
Write data
(1) COMMAND Code 0x90~0x9F (one data at 0x90, sixteen data at 0x9F)
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 0 D13 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
(4). Offset REG (OFREG) Write Operation (during RUN)
Execute
Write data
(1) COMMAND Code 0xA2 (DSP1) / 0xA3 (DSP2)
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
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3-1-3. Read Operation during DSP Reset
(1) Program RAM (PRAM) Read (during DSP reset)
Field
Write data
Readout data
(1) COMMAND Code 0x38 (DSP1) / 0x39 (DSP2)
(2) ADDRESS1
0 0 0 0 A11 A10 A9 A8
(3) ADDRESS2
A7 A6 A5 A4 A3 A2 A1 A0
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be read continuously for each address.
(2) Coefficient RAM (CRAM) Read (during DSP reset)
Field
Write data
Readout data
(1) COMMAND Code 0x34 (DSP1) / 0x35 (DSP2)
(2) ADDRESS1
0 0 0 A12 A11 A10 A9 A8
(3) ADDRESS2
A7 A6 A5 A4 A3 A2 A1 A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
Three bytes of data may be read continuously for each address.
(3) Offset REG (OFREG) Read (during DSP reset)
Field
Write data
Readout data
(1) COMMAND Code 0x32 (DSP1) / 0x33 (DSP2)
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 0 D13 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be read continuously for each address.
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3-1-4. Read Operation during RUN
(1) CRAM Write Preparation Read (during RUN)
Field
Write data
(1) COMMAND Code 0x24 (DSP1) / 0x26 (DSP2)
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
(2) OFREG Write Preparation Read (during RUN)
Field
Write data
(1) COMMAND Code 0x25 (DSP1) / 0x27 (DSP2)
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
Readout data
0 0 0 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D23~D16
D15~D8
D7~D0
Readout data
00000000
0 0 A5 A4 A3 A2 A1 A0
00000000
0 0 D13 D12 D11 D10 D9 D8
D7~D0
(3) MIR Register Read (during RUN)
Field
Write data
Readout data
(1) COMMAND Code 0x76 (DSP1) / 0x77 (DSP2)
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
(4) DATA1
D27~D20
(5) DATA2
D19~D12
(6) DATA3
D11~D4
(7) DATA4
D3 D2 D1 D0 (flag3) (flag2) (flag1) (flag0)
MIR register sequential read for DSP1/DSP2.
Max 8 data (32 bytes) may be read continuously.
The data is 28-bit MSB justified. Lower 4 bits are validity flags; the data is
valid only when all flags are zero.
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3-2. Register Write and Read
3-2-1. Register Write
(1) Control Register Write
Field
Write data
(1) COMMAND Code 0xC0
(2) ADDRESS1
A15~A8
(3) ADDRESS2
A7~A0
(4) DATA
D7~D0
One byte of data may be written continuously for each address.
(2) External Conditional Jump Code (JX register) Write
Field
Write data
(1) COMMAND Code 0xF4 (DSP1) / 0xF5 (DSP2)
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
(4) DATA
D7~D0
(3) CRC Code Write
Field
(1) COMMAND Code
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
Write data
0xF2
00000000
00000000
D15~D8
D7~D0
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3-2-2. Register Read
(1) Control Register Read
Field
Write data
Readout data
(1) COMMAND Code 0x40
(2) ADDRESS1
A15~A8
(3) ADDRESS2
A7~A0
(4) DATA
D7~D0
One byte of data may be written continuously for each address.
(2) CRC Code Read
Field
(1) COMMAND Code
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
Write data
0x72
00000000
00000000
Readout data
D15~D8
D7~D0
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4. RAM and Register Write/Read Timing
4-1. RAM Write Timing during DSP Reset
Write to Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during DSP reset in
the order of command code (8 bits), address (16 bits) and data. When writing the data to consecutive
address locations, continue to input data only. Address is incremented by 1 automatically.
DxRESETN bit
(x=1,2)
CSN
SCLK
don’t care
(L/H)
SI
Command
Address
DATA
DATA
DATA
DATA
DATA
don’t care
(L/H)
RDY = “H”
Figure 55. Writing to RAM at Consecutive Address Locations (SPI)
DxRESETN bit
(x=1,2)
CSN
SCLK
SI
don’tcare
(L/H)
Command
Address DATA
don’tcare
(L/H)
Command
Address DATA
don’tcare
(L/H)
RDY = “H”
Figure 56. Writing to RAM at Random Address Locations (SPI)
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4-2. RAM Write Timing during RUN
These operations described below are to rewrite the Coefficient RAM (CRAM) and Offset REG (OFREG)
during RUN. Data writing is executed in two steps; write preparation and write execution. The written
data can be confirmed by reading the write preparation data.
(1) Write Preparation
After inputting the assigned command code (8 bits) to select the number of data from 1 to 16, input the
starting address of write (16 bits) and the number of data assigned by command code in this order.
(2) Write Preparation Data Confirmation
After write preparation, prepared data for writing can be confirmed. Address and Data are read in this
order by write preparation data confirmation command “24H/26H” (CRAM) or “25H/27H” (OFREG). The
data will be “0x000001” when reading more than write preparation data. Execute write preparation again
when the address and data are disturbed by external noise.
(3) Write Execution
Upon completion of the above operation, execute a RAM write during RUN by inputting the
corresponding command code and address (16 bits, all “0”) in this order.
Note
* 65. Execute Write Preparation and Write Preparation Data Confirmation before Write Execution. A
Write Preparation Data Confirmation sequence can be skipped, but a malfunction occurs when
executing Write Execution to RAM without a Write Preparation sequence. Access operation by a
microcontroller is prohibited until RDY changes to “H”.
Write modification of the RAM content is executed whenever the RAM address for modification is
accessed. For example, when 5 data are written, from RAM address “10”, it is executed as shown below.
RAM execution address
7
8
9
10
↓
○
11
↓
○
13
16
11
12
↓
○
Write execution position
wait
Note
* 66. Address “13” is not executed until rewriting address “12”.
13
↓
○
14
↓
○
15
DxRESETN bit= “1”
(x= 1, 2)
CSN
(Ex.) When # of DATA is 4
CRAM Command Code 0x83
OFREG Command Code 0x93
SCLK
SI
don’tcare
(L/H)
RDY = “H”
Command Address DATA0
Code
DATA1
DATAn-1 DATAn
CRAM
0x80(# of DATA: 1)~0x8F(# of DATA: 16)
OFREG
0x90(# of DATA: 1)~0x9F(# of DATA: 16)
don’tcare
(L/H)
Figure 57. CRAM/OFREG Write Preparation (SPI)
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DxRESETN bit= “1”
(x=1,2)
CSN
SCLK
don’t care
(L/H)
SI
Command
don’t care
(L/H)
CRAM: 24H/26H, OFREG: 25H/27H
SO
Address
Hi-Z
DATA
DATA
DATA
DATA
DATA
Hi-Z
RDY= “H”
Figure 58. CRAM/OFREG Write Preparation Data Read (SPI)
DxRESETN bit= “1”
(x=1,2)
CSN
SCLK
SI
don’tcare
(L/H)
Command
00000000
00000000
max 400ns
CRAM: A4H/A5H, OFREG: A2H/A3H
RDY
RDYLG * 67
Figure 59. CRAM/OFREG Write (SPI)
Notes
* 67. The RDY pin rises to “H” in two LRCK cycles at maximum if the DSP program is designed to access
the modification address in every sampling cycle. The RDY signal keeps “L” level even if a write
command is completed internally while CSN is “L” level.
* 68. Writing to a CRAM or OFREG address that is not used in the DSP program is prohibited during
RUN. If it is executed, the RDY pin keeps “L” output until the PDN pin becomes “L”. In the case of
I2C interface mode, communication will not be made correctly after that.
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4-3. External Conditional Jump
External Conditional Jump Code Writing
(1) COMMAND
0xF4 (DSP1) / 0xF5 (DSP2)
(2) Address0
00000000
(3) Address1
00000000
(4) DATA
D7~D0
An External Conditional Jump code can be input during both DSP Reset and RUN. Input data is set to
the designated register on the rising edge of LRCK assigned to the DSP. The RDY pin changes to “L”
when the command code is transferred, and it changes to “H” when write operations are completed.
This Jump code is reset to 0 by setting the PDN pin to “L”, but it is not reset by DSP reset or Clock reset.
A DSP instruction setting is necessary when using external conditional jump code.
SCLK
SI
don’tcare
(L/H)
F4H / F5H
00H
00H
D7…D0
don’tcare
(L/H)
CSN
RDY
Figure 60. External Conditional Jump Timing (SPI)
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■ I2C
Interface
Access to the AK7735 registers and RAM can be controlled by an I²C bus. The AK7735 supports
fast-mode I2C-bus (max: 400kHz) and fast-mode plus (max: 1MHz).
SI/I2CFIL pin
Bus Mode
L
Fast Mode
H
Fast Mode Plus
2
Table 34. I C Bus Mode Setting
Note
* 69. The CSN pin and the SI/I2CFIL pin must be fixed to “L” or “H” when using I2C interface. The
AK7735 does not support Hs mode (max: 3.4MHz).
1. Data Transfer
In order to access any IC devices on the I2C bus, input a start condition first, followed by one byte of
Slave address which includes the Device Address. IC devices on the BUS compare this Device address
with their own addresses and the IC device which has an identical address with the Device address
generates an acknowledgement. An IC device with the identical address then executes either a read or a
write operation. After the command execution, input a Stop condition.
1-1. Data Change
Change the data on the SDA line while the SCL line is “L”. The SDA line condition must be stable and
fixed while the clock is “H”. Change the Data line condition between “H” and “L” only when the clock
signal on the SCL line is “L”. Change the SDA line condition while the SCL line is “H” only when the start
condition or stop condition is input.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 61. Data Change I2C)
1-2. Start Condition and Stop Condition
A start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All
instructions are initiated by a Start condition. A stop condition is generated by the transition of “L” to “H”
on the SDA line while the SCL line is “H”. All instructions end by a Stop condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 62. Start Condition and Stop Condition (I2C)
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1-3. Repeated Start Condition
When a Start condition is received again instead of a Stop condition, the bus changes to a Repeated
Start condition. A Repeated Start condition is functionally the same as a Start condition.
SCL
SDA
START CONDITION
Repeated Start CONDITION
Figure 63. Repeated Start Condition (I2C)
1-4. Acknowledge
The IC device that sends data releases the SDA line (“H”) after sending one byte of data. The IC device
that receives data then sets the SDA line to “L” at the next clock. This operation is called
“acknowledgement”, and it enables verification that the data transfer has been properly executed.
The AK7735 generates an acknowledgement upon receipt of a Start condition and a Slave address. For
a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. For a
read instruction, succeeded by generation of an acknowledgement, the AK7735 releases the SDA line
after outputting data at the designated address, and it monitors the SDA line condition. When the Master
side generates an acknowledgement without sending a Stop condition, the AK7735 outputs data at the
next address location. When no acknowledgement is generated, the AK7735 ends data output (not
acknowledged).
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
START
CONDITION
Figure 64. Generation of Acknowledgement (I2C)
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1-5. The First Byte
The First Byte, which includes the Slave-address, is input after the Start condition is set, and a target IC
device that will be accessed on the bus is selected by the Slave-address.
When the Slave-address is inputted, an external device that has the identical device address generates
an acknowledgement and instructions are then executed. The 8th bit of the First Byte (lowest bit) is
allocated as the R/W Bit. When the R/W Bit is “1”, the read instruction is executed, and when it is “0”, the
write instruction is executed.
The Slave-address of the AK7735 is set by the CSN pin.
CSN pin = “H”
0
0
1
1
0
0
0
R/W
CSN pin = “L”
0
0
1
1
1
0
0
R/W
Figure 65. First Byte Configuration (I2C)
Note
* 70. In this document, there is a case that describes a “Write Slave-address assignment” when both
address bits match and a Slave-address at R/W Bit = “0” is received. There is a case that
describes “Read Slave-address assignment” when both address bits matches and a
Slave-address at R/W Bit = “1” is received.
1-6. The Second and Succeeding Bytes
The data format of the second and succeeding bytes of the AK7735 Transfer / Receive Serial data
(command code, address and data in microcontroller interface format) on the I2C BUS are all configured
with a multiple of 8-bits. When transferring or receiving those data on the I2C BUS, they are divided into
an 8-bit data stream segment and they are transferred / received with the MSB side data first with an
acknowledgement in-between.
Example)
When transferring / receiving A1B2C3 (hex) 24-bit serial data in microprocessor interface format:
2
(1) I C format
(1) Microcomputer format
A1
B2
C3
A1
B2
A
24BIT
8BIT
C3
A
8BIT
8BIT
A …Acknowledge
Figure 66. Division of Data (I2C)
Note
* 71. In this document, there is a case that describes a write instruction command code which is received
at the second byte as “Write Command”. There is a case that describes a read instruction
command code which is received at the second byte as “Read Command”.
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2. Write Sequence
In the AK7735, when a “Write-Slave-address assignment” is received at the first byte, the write
command at the second byte, the address at the third and fourth bytes, and data at the fifth and
succeeding bytes are received. The number of write data bytes is fixed by the received command code.
S
T
A
R
T
S
T
O
P
R/W=”0”
Slave
SDA S Address
Command
Code
A
C
K
Address(1)
Address(0)
A
C
K
A
C
K
Data(0)
A
C
K
A
C
K
P
Data(n)
Data(1)
A
C
K
A
C
K
A
C
K
Figure 67. Write Sequence (I2C)
3. Read Sequence
In the AK7735, when a “write- slave-address assignment” is received at the first byte, the read command
at the second byte and the address at the third and fourth bytes are received. When the fourth byte is
received and an acknowledgement is transferred, the read command waits for the next restart condition.
When a “read slave-address assignment” is received at the first byte, data is transferred at the second
and succeeding bytes. The number of readable data bytes is fixed by the received read command.
After reading the last byte, assure that a “not acknowledged” signal is received. If this “not
acknowledged” signal is not received, the AK7735 continues to send data regardless whether data is
present or not, and since it did not release the BUS, the stop condition cannot be properly received.
S
T
A
R
T
R
E
S
T
A
R
T
R/W=”0”
Slave
SDA S Address
Command
Code
A
C
K
Address(0)
A
C
K
Slave
S Address
Address(1)
A
C
K
A
C
K
S
T
O
P
R/W=”1”
Data(0)
A
C
K
MA
AC
SK
T
E
R
P
Data(n)
Data(1)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
MN
A A
S C
T K
E
R
Figure 68. Read Sequence (I2C)
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4. Not Acknowledge
The AK7735 cannot receive instructions while the RDY pin (Data Write Ready pin) is at a low level. The
maximum transition time of the RDY pin from low level to high level is 2 × LRCK. It is possible to confirm
in a faster cycle than 2 x LRCK that the RDY pin becomes high by checking the AK7735 internal
condition, which is made by verifying the acknowledgement.
4-1. Generation of “Not Acknowledge”
The AK7735 does not accept command codes until the RDY pin becomes high, when a command is
received to set the RDY pin to a low level. In order to confirm the RDY pin condition, a “Write
Slave-Address assignment” should be sent after the Start condition. If the RDY pin is then at a low level,
“Acknowledgement” is not generated at the succeeding clock (generation of “Not Acknowledged”).
After sending “Not Acknowledged”, the BUS is released and all receiving data are ignored until the next
start condition (behaves as if it received Slave address of other device).
4-2. When Read Slave-address assignment is received without receiving Read command code
Data read in the AK7735 can be made only in the previously documented Read sequence. Data cannot
be read out without receiving a read command code. In the AK7735, a “Not Acknowledged” is generated
when a “Read Slave-address Assignment” without proper receipt of read command is received.
5. Limitation in use of I2C Interface
The AK7735 does not operate in Hs Mode (max: 3.4MHz). The AK7735 supports Fast mode (max:
400kHz) and Fast plus mode (max: 1MHz).
Note
* 72. Do not turn off the power of the AK7735 whenever the power supplies of other devices of the same
system are turned on. Pull-up resistors of SDA and SCL pins should be connected to TVDD or less
voltage. (The diodes against TVDD exist in the SDA and SCL pins.)
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■ Simple
Write Error Check
The AK7735 have a cyclic redundancy check (CRC) function for a simple checking of writing data for
RAM and registers.
1. Checked Data
1-1. SPI Interface
SI data during CSN = “L” is checked.
• Serial Data D(x): SI data which is input during a period from a falling edge to a rising edge of CSN
• Generator Polynomial G(x)=x16+x12+x5+1 (Divisor=0x1021, Default=0, MSB-first, Not Inverted)
• The remainder of D(x) divided by G(x) is R(x).
1-2. I2C Interface
Command code, address and data from the second byte are checked. (Acknowledge is not included.
Therefore, the checked result will be the same as the SPI interface if the same command code, address
and data are written.) The first byte which includes a slave address is not checked. It can be checked by
Acknowledge.
• Serial Data D(x): Command Code, Address and Data (Slave Address is not included)
• Generator Polynomial G(x)=x16+x12+x5+1 (Divisor=0x1021, Default=0, MSB-first, Not Inverted)
• The remainder of D(x) divided by G(x) is R(x).
2. Simple Write Error Check Sequence
There are two ways to check write error.
2-1. CRC Result
(1) Write serial data D(x) to be checked.
(2) Read out a CRC result (remainder R(x)) by the command code 72H.
(3) Check the result by a microprocessor.
(4) When checking other serial data, repeat the sequence from (1) to (3).
Note
* 73. The internal CRC result is not updated by command code 72H.
2-2. STO pin State
(1) Set control register CRCE bit to “1”.
(2) Write serial data D(x) to be checked.
(3) Write the R(x) value to registers by the command code F2H.
(4) If the remainder of D(x) divided by G(x) is equal to R(x), the STO pin outputs “H”. If not, it outputs “L”.
(5) When checking other serial data, repeat the sequence from (2) to (4).
Note
* 74. The STO pin keeps outputting “L” until a correct value of R(x) is written in sequence (3).
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■ DSP
Block
1. Settings of DSP Memory
The AK7735 integrates two DSPs (DSP1 and DSP2) which have the same architecture. The DSP1 and
the DSP2 share program RAM (PRAM), coefficient RAM (CRAM) data RAM (DRAM) and delay RAM
(DLRAM). Assigned memory area for each DSP is set by register settings. Both DSPs must be in reset
state when setting memory assignment.
PRAMDIV bit controls PRAM assignment for DSP1 and DSP2. CRAMDIV[1:0] bits control CRAM
assignment, DRAMDIV bit controls DRAM assignment and DLRAMDIV[1:0] bits control DLRAM
assignment.
Mode
0
1
PRAMDIV bit
DSP1
DSP2
0
2048 word
2048 word
1
4096 word
Reset
Table 35. PRAM Assignment for DSP1 and DSP2
(default)
Note
* 75. The DSP2 must be reset when setting to Mode 1 (PRAMDIV bit = “1”).
Mode CRAMDIV[1:0] bits
DSP1
DSP2
0
00
4096 word
2048 word
(default)
1
01
2048 word
4096 word
2
10
6144 word
Reset
3
11
N/A
N/A
Table 36. CRAM Assignment for DSP1 and DSP2 (N/A: Not Available)
Note
* 76. The DSP2 must be reset when setting to Mode 2 (CRAMDIV[1:0] bits = “10”).
Mode
0
1
DRAMDIV bit
DSP1
DSP2
0
2048 word
2048 word
1
4096 word
Reset
Table 37. DRAM Assignment for DSP1 and DSP2
(default)
Note
* 77. The DSP2 must be reset when setting to Mode 1 (DRAMDIV bit = “1”).
Mode
0
1
2
3
DLRAMDIV[1:0] bits
DSP1
DSP2
00
12288 word
Not Connected
01
8192 word
4096 word
10
4096 word
8192 word
11
Not Connected
12288 word
Table 38. DLRAM Assignment for DSP1 and DSP2
(default)
Note
* 78. The DSP1 and DSP2 can be operated without connecting to DLRAM. However, program access to
DLRAM is not permitted.
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BANK size and BANK addressing mode of DRAM, that is assigned, can be set independently for the
DSP1 and the DSP2.
DRAM BANK sizes for DSP1 and DSP2 are controlled by D1DRMBK[1:0] bits and D2DRMBK[1:0] bits,
respectively.
D1DRMBK[1:0] bits
Mode
BANK 1 Size
BANK 0 Size
D2DRMBK[1:0] bits
0
00
1024
Rest of Area
(default)
1
01
2048
Rest of Area
2
10
3072
Rest of Area
3
11
N/A
N/A
Table 39. DRAM BANK Size Setting for DSP1 and DSP2 (N/A: Not Available)
DRAM BANK addressing modes for DSP1 and DSP2 are controlled by D1DRMA[1:0] bits and
D2DRMA[1:0] bits, respectively.
D1DRMA[1:0] bits
Mode
BANK 1 (DP1)
BANK 0 (DP0)
D2DRMA[1:0] bits
0
00
Ring
Ring
(default)
1
01
Ring
Linear
2
10
Linear
Ring
3
11
Linear
Linear
Table 40. DRAM BANK Addressing Mode Setting for DSP1 and DSP2
BANK size and BANK addressing mode of DLRAM, that is assigned, can be set independently for the
DSP1 and DSP2.
DLRAM BANK sizes for DSP1 and DSP2 are controlled by D1DLRMBK[2:0] bits and D2DLRMBK[2:0]
bits, respectively.
D1DLRMBK [2:0] bits
Mode
BANK 1 Size
BANK 0 Size
D2DLRMBK [2:0] bits
0
000
0
Rest of Area
(default)
1
001
2048 word
Rest of Area
2
010
4096 word
Rest of Area
3
011
6144 word
Rest of Area
4
100
8192 word
Rest of Area
5
101
10240 word
Rest of Area
6
110
12288 word
0
7
111
N/A
N/A
Table 41. DLRAM BANK Size Setting for DSP1 and DSP2 (N/A: Not Available)
DLRAM BANK addressing modes for DSP1 and DSP2 are controlled by D1DLRMA bit and D2DLRMA
bit, respectively.
D1DLRMA bit
Mode
BANK 1
BANK 0
D2DLRMA bit
0
0
Ring
Ring
(default)
1
1
Linear
Ring
Table 42. DLRAM BANK Addressing Mode Setting for DSP1 and DSP2
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Sampling mode of DLRAM BANK 0 for the DSP1 and DSP2 are controlled by D1SS[1:0] bits and
D2SS[1:0] bits, respectively.
D1SS[1:0] bits
Mode
Sampling Mode of DLRAM BANK 0
D2SS[1:0] bits
0
00
Update Address in Every Sampling
(default)
1
01
Update Address in Every 2 Samplings
2
10
Update Address in Every 4 Samplings
3
11
Update Address in Every 8 Samplings
Table 43. DLRAM BANK0 Sampling Mode setting of DSP1/DSP2
The DSP1 and DSP2 are able to generate a trigonometric COS table for trigonometric processing. Input
1/4 cycle data of the COS table to CRAM and the DSP generates rest of 3/4 cycle data automatically.
COS table length for CRAM input is variable according to the cycle resolution setting. The cycle
resolution of DSP1 and DSP2 is controlled by D1WAVP[2:0] bits and D2WAVP[2:0] bits, respectively.
D1WAVP[2:0] bits
Mode
Cycle Resolution
COS Table Length
D2WAVP[2:0] bits
0
000
128 points
33 word
(default)
1
001
256 points
65 word
2
010
512 points
129 word
3
011
1024 points
257 word
4
100
2048 points
513 word
5
101
4096 points
1025 word
6
110
N/A
N/A
7
111
N/A
N/A
Table 44. Cycle Resolution Setting of Trigonometric Table for DSP1/DSP2 (N/A: Not Available)
2. Soft SRC Function
DOUT1 port of DSP1 has a built-in FIFO to realize synchronous SRC program for sampling rate
conversion. The output data of DOUT1 port of DSP1 can be up sampled by the FIFO.
A DSP filtering process is necessary when using the soft SRC function. The soft SRC is capable of
integral multiple conversion of a sampling rate between two synchronized clock sync domains,
supporting 6 times up sampling at maximum.
Up Sampling
(6 word FIFO x2)
DIN1
DIN2
DOUT2
DIN3
DIN4
DOUT1
DSP1
DIN5
DOUT3
DOUT4
DOUT5
DIN6
DOUT6
Figure 69. DSP1 Soft SRC Function
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■
Analog Input Block
1. Microphone Input Gain
The AK7735 has gain amplifiers for microphone input. The gain of L and R channels can be
independently selected by MGNL[3:0] and MGNR[3:0] bits (Table 45). The input impedance is typ. 20k
when ADC1VL/R bits is “0” and it is typ.25 k when ADC1VL/R bits are “1”. This gain amplifier executes
zero crossing detection when changing the gain by setting MICLZCE bit = “1” / MICRZCE bit = “1”. Zero
crossing detection is executed independently for L and R channels. Zero crossing timeout period is
16ms (@fs=48kHz base). When MICLZCE bit = “0”/ MICRZCE bit = “0”, the volume is changed
immediately by register settings.
When writing to MGNL/R[3:0] bits continuously, take an interval of zero crossing timeout period or more.
If the MGNL/R[3:0] bits are changed before zero crossing, the volume of Lch and Rch may differ. When
the volume level that is same as the present volume is set, the zero crossing counter is not reset and
time outs according to the previous writing timing. Therefore, in this case, writing to MGNL/R [3:0] bits
continuously is possible with a shorter interval of the zero crossing timeout period.
1-1. Microphone Gain
Mode
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MGNL[3] MGNL[2] MGNL[1]
MGNL[0]
Input Gain
MGNR[3] MGNR[2] MGNR[1] MGNR[0]
0
0
0
0
0dB
(default)
0
0
0
1
2dB
0
0
1
0
4dB
0
0
1
1
6dB
0
1
0
0
8dB
0
1
0
1
10dB
0
1
1
0
12dB
0
1
1
1
14dB
1
0
0
0
16dB
1
0
0
1
18dB
1
0
1
0
21dB
1
0
1
1
24dB
1
1
0
0
27dB
1
1
0
1
30dB
1
1
1
0
33dB
1
1
1
1
36dB
Table 45. Microphone Input Gain
1-2. Zero Crossing Timeout
The microphone gain is changed independently on the timing of zero crossing detection or zero crossing
timeout.
48kHz base 44.1kHz base
16ms
17.4ms
Zero Crossing Timeout Period
Table 46. Zero Crossing Timeout Period
016014707-E-00
2016/12
- 94 -
[AK7735]
1-3. Start-up Time of MIC Input Pin
The AK7735 starts to charge a DC cut capacitor when the PDN pin is set to “H” from “L”. Since the input
impedance is 25kΩ, the time constant will be 25ms if the DC cut capacitor is 1µF. A wait time of about
100ms should be taken before power up the ADC to charge the DC cut capacitor sufficiently. A click
noise may occur just after the ADC is powered up if this wait time is not enough.
2. Microphone Input Selector
The AK7735 has microphone input selectors. Each microphone amplifier input is selectable between
single-ended input and differential input by AD1LSEL bit or AD1RSEL bit.
AK7735
AIN1L / INP1 pin
ADC Lch
INN1 pin
MIC-Amp Lch
AD1LSEL bit
AIN1R / INP2 pin
ADC Rch
INN2 pin
AD1RSEL bit
MIC-Amp Rch
Figure 70. Microphone Input Selector
AD1LSEL bit
0
1
ADC Lch
AD1RSEL bit
INP1/INN1
(default)
0
AIN1L
1
Table 47. Microphone Input Selector
ADC Rch
INP2/INN2
AIN1R
(default)
Note
* 79. When using differential input mode, it is prohibited to input signal to only one side like pseudo
differential input.
016014707-E-00
2016/12
- 95 -
[AK7735]
3. Microphone Bias Output
The AK7735 has a line of microphone bias output. The power supply of microphone is supplied from the
MPWR pin by setting PMMB bit = “1”. The output voltage is 2.5V (AVDD=3.3V) and the load resistance is
min. 2kΩ.
PMMB bit
MPWR pin
0
Hi-Z
(default)
1
Output
Table 48. Microphone Bias Output
AK7735
AK7735
PMMB bit
PMMB bit
MPWR pin
MPWR pin
4.7k
4.7k
4.7k
Microphone
4.7k
Microphone
INP1
AIN1L
INN1
100nF
4.7k
Microphone
MIC-Amp Lch
100nF
MIC-Amp Lch
Microphone
INP2
AIN1R
INN2
100nF
4.7k
100nF
MIC-Amp Rch
MIC-Amp Rch
Figure 71. MIC Block Circuit (Differential Input)
016014707-E-00
Figure 72. MIC Block Circuit (Single-end Input)
2016/12
- 96 -
[AK7735]
■
ADC Block
1. ADC Block High Pass Filter
The AK7735 has a digital high pass filter (HPF) for DC offset cancelling of each ADC. The cut-off
frequency of the HPF is about 0.9Hz (fs=48kHz), depending on operation frequency.
2. ADC Digital Volume
The AK7735 has independent digital volume controls for Lch and Rch (256 levels, 0.5dB steps) of each
ADC.
ADC1
ADC1
ADC2
ADC2
Attenuation
VOLAD1L[7:0] VOLAD1R[7:0] VOLAD2L[7:0] VOLAD2R[7:0]
Level
00h
00h
00h
00h
+24.0dB
01h
01h
01h
01h
+23.5dB
02h
02h
02h
02h
+23.0dB
:
:
:
:
:
2Fh
2Fh
2Fh
2Fh
+0.5dB
30h
30h
30h
30h
0.0dB
(default)
31h
31h
31h
31h
-0.5dB
:
:
:
:
:
FDh
FDh
FDh
FDh
-102.5dB
FEh
FEh
FEh
FEh
-103.0dB
FFh
FFh
FFh
FFh
Mute (-∞)
Table 49. ADC Digital Volume Control Setting
The transition time between set values is selected by ATSPAD bit.
Mode
ATSPAD bit
Transition Time
0
0
4/fs
(default)
1
1
16/fs
Table 50. ADC Volume Level Transition Time
The transition between set values is soft transition. It takes 1020/fs (21.3ms@fs=48kHz) from 00h to
FFh(MUTE) in Mode 0. If the PDN pin goes to “L”, the volume of each ADC channel is initialized to 30h.
ATSPAD bit
0
1
00h ⇔ FFh Transition Time
LRCK Cycle
fs=48kHz
fs=44.1kHz
fs=8kHz
1020/fs
21.3ms
23.1ms
127.5ms
1020/fs x4
85.0ms
92.5ms
510.0ms
Table 51. ADC Volume Transition Time from 00h to FFh
016014707-E-00
(default)
2016/12
- 97 -
[AK7735]
code
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
dB
24.0
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
code
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
dB
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
-5.5
-.6.0
-6.5
-7.0
-7.5
code
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
dB
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-13.5
-14.0
-14.5
-15.0
-15.5
-16.0
-16.5
-17.0
-17.5
-18.0
-18.5
-19.0
-19.5
-20.0
-20.5
-21.0
-21.5
-22.0
-22.5
-23.0
-23.5
code
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
dB
-24.0
-24.5
-25.0
-25.5
-26.0
-26.5
-27.0
-27.5
-28.0
-28.5
-29.0
-29.5
-30.0
-30.5
-31.0
-31.5
-32.0
-32.5
-33.0
-33.5
-34.0
-34.5
-35.0
-35.5
-36.0
-36.5
-37.0
-37.5
-38.0
-38.5
-39.0
-39.5
code
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
dB
-40.0
-40.5
-41.0
-41.5
-42.0
-42.5
-43.0
-43.5
-44.0
-44.5
-45.0
-45.5
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
-51.0
-51.5
-52.0
-52.5
-53.0
-53.5
-54.0
-54.5
-55.0
-55.5
code
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
dB
-56.0
-56.5
-57.0
-57.5
-58.0
-58.5
-59.0
-59.5
-60.0
-60.5
-61.0
-61.5
-62.0
-62.5
-63.0
-63.5
-64.0
-64.5
-65.0
-65.5
-66.0
-66.5
-67.0
-67.5
-68.0
-68.5
-69.0
-69.5
-70.0
-70.5
-71.0
-71.5
code
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
dB
-72.0
-72.5
-73.0
-73.5
-74.0
-74.5
-75.0
-75.5
-76.0
-76.5
-77.0
-77.5
-78.0
-78.5
-79.0
-79.5
-80.0
-80.5
-81.0
-81.5
-82.0
-82.5
-83.0
-83.5
-84.0
-84.5
-85.0
-85.5
-86.0
-86.5
-87.0
-87.5
code
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
dB
-88.0
-88.5
-89.0
-89.5
-90.0
-90.5
-91.0
-91.5
-92.0
-92.5
-93.0
-93.5
-94.0
-94.5
-95.0
-95.5
-96.0
-96.5
-97.0
-97.5
-98.0
-98.5
-99.0
-99.5
-100.0
-100.5
-101.0
-101.5
-102.0
-102.5
-103.0
Mute
Table 52. ADC Digital Volume Settings
016014707-E-00
2016/12
- 98 -
[AK7735]
3. ADC Soft Mute
The ADC block has a digital soft mute circuit. The soft mute operation is performed at digital domain. The
output signal is attenuated to -∞ in “ATT setting level x ATT transition time” from the current ADC digital
volume setting level by setting AD1MUTE bit or AD2MUTE bit to “1”. When the AD1MUTE bit or
AD2MUTE bit returns to “0”, the mute is cancelled and the output attenuation level gradually changes to
ATT setting level in “ATT setting level x ATT transition time”. If the soft mute is cancelled before
attenuating to -∞ after starting the operation, the attenuation is discontinued and the volume level returns
to original volume setting level by the same cycle. The soft mute is effective for changing the signal
source without stopping the signal transmission.
The attenuation level transition takes 828/fs from 0dB to -∞ and from -∞ to 0dB. Soft mute function is
available when each ADC is in operation. The attenuation value is initialized by setting the PDN pin = “L”.
AD1MUTE, AD2MUTE,
Group Delay (GD)
GD
0dB
Attenuation Level
828/fs
-∞dB
828/fs
Output Image
Figure 73. ADC Soft Mute
4. ADC2 Input Selector
ADC2 of the AK7735 has an input selector for 1 stereo differential input and 2 stereo single-ended
inputs. These inputs are selected by AD2SEL[1:0] bits. In the case that these registers are changed
during operation, mute output signal to reduce switching noise as needed.
Mode
0
1
2
3
AD2SEL[1:0] bits
Selected Pin
00
AIN2LP, AIN2LN, AIN2RP, AIN2RN
01
AIN3L, AIN3R
10
AIN4L, AIN4R
11
N/A
Table 53. ADC2 Input Select (N/A: Not Available)
(default)
Note
* 80. When using differential input mode, it is prohibited to input signal to only one side like pseudo
differential input.
016014707-E-00
2016/12
- 99 -
[AK7735]
4-1. Input Selector Switching Sequence
The input selector should be changed after enabling soft mute function to avoid the switching noise of
the input selector.
ADC2 Input selector switching sequence:
1) Enable Soft Mute Function before Changing Channel
2) Change Channel
3) Disable Soft Mute Function
AD2MUTE bit
(2)
DATT Level
(1)
(1)
Attenuation
(3)
-∞
Channel
IN3L/IN3R
IN4L/IN4R
Figure 74. ADC2 Input Channel Switching Sequence Example
The period of (1) varies according to the setting value of the DATT level. Transition time of attenuation
level from 0dB to - is shown below.
(1) Period (Max)
ATSPAD bit
LRCK Cycle
fs=48kHz
fs=44.1kHz fs=8kHz
0
828/fs
17.25ms
18.78ms
103.5ms (default)
1
828/fs x 4
69ms
75.10ms
414ms
The input channel should be changed during the period (2). An interval around 200ms is needed before
releasing the soft mute after changing the channel (period (3)).
5. ADC Digital Filter Select
The AK7735 has four kinds of digital filters in ADC block. ADSD and ADSL bits select a digital filter.
ADC1 and ADC2 have a common setting for digital filter.
Mode
0
1
2
3
ADSD bit
0
0
1
1
ADSL bit
Digital Filter
0
Sharp Roll-Off Filter
1
Slow Roll-Off Filter
0
Short Delay Sharp Roll-Off Filter
1
Short Delay Slow Roll-Off Filter
Table 54. ADC Digital Filter Select
016014707-E-00
(default)
2016/12
- 100 -
[AK7735]
6. ADC Input Volume Selection
Single-ended input amplitude (differential input amplitude) of ADC1 L/Rch and ADC2 L/Rch can be
switched between 2.3Vpp (±2.3Vpp) and 2.83Vpp (±2.83Vpp) by ADC1VL/R bit and ADC2VL/R bit,
respectively.
Mode
0
1
Input Full Scale Voltage
ADC1VL bit / ADC1VR bit
ADC2VL bit / ADC2VR bit
Single-end Input
Differential Input
0
2.3Vpp
±2.3Vpp
1
2.83Vpp
±2.83Vpp
Table 55. ADC Input Full Scale Voltage Selection
016014707-E-00
(default)
2016/12
- 101 -
[AK7735]
■
DAC Block
1. DAC Digital Volume
The AK7735 has channel-independent digital volume controls in DAC block. (256 levels, 0.5 steps)
DAC1 Lch
DAC1 Rch
DAC2 Lch
DAC2 Rch
VOLDA1L[7:0] VOLDA1R[7:0] VOLDA2L[7:0] VOLDA2R[7:0]
00h
00h
00h
00h
01h
01h
01h
01h
02h
02h
02h
02h
:
:
:
:
17h
17h
17h
17h
18h
18h
18h
18h
19h
19h
19h
19h
:
:
:
:
FDh
FDh
FDh
FDh
FEh
FEh
FEh
FEh
FFh
FFh
FFh
FFh
Table 56. DAC Digital Volume Setting
Attenuation
Level
+12.0dB
+11.5dB
+11.0dB
:
+0.5dB
0.0dB
-0.5dB
:
-114.5dB
-115.0dB
Mute (-∞)
(default)
Transition time between set values can be selected by ATSPDA bit.
MODE
ATSPDA
Transition Time
0
0
4/fs
(default)
1
1
16/fs
Table 57. DAC Volume Transition Time Setting
The transition between set values is soft transition. It takes 1020/fs (21.3ms@fs=48kHz) from 00h to FFh
(MUTE) in Mode 0. If the PDN pin is set to “L”, the VOLDA1L[7:0], VOLDA1R[7:0], VOLDA2L[7:0] and
VOLDA2R[7:0] bits are initialized to 18h.
ATSPDA bit
0
1
00h ↔ FFh Transition Time
LRCK Cycle
fs=48kHz fs=44.1kHz fs=8kHz
1020/fs
21.3ms
23.1ms
127.5ms
1020/fs x4
85.0ms
92.5ms
510.0ms
Table 58. DAC Volume Transition Time (00h ↔ FFh)
016014707-E-00
(default)
2016/12
- 102 -
[AK7735]
code
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
dB
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
code
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
dB
-4.0
-4.5
-5.0
-5.5
-.6.0
-6.5
-7.0
-7.5
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-13.5
-14.0
-14.5
-15.0
-15.5
-16.0
-16.5
-17.0
-17.5
-18.0
-18.5
-19.0
-19.5
code
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
dB
-20.0
-20.5
-21.0
-21.5
-22.0
-22.5
-23.0
-23.5
-24.0
-24.5
-25.0
-25.5
-26.0
-26.5
-27.0
-27.5
-28.0
-28.5
-29.0
-29.5
-30.0
-30.5
-31.0
-31.5
-32.0
-32.5
-33.0
-33.5
-34.0
-34.5
-35.0
-35.5
code
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
dB
-36.0
-36.5
-37.0
-37.5
-38.0
-38.5
-39.0
-39.5
-40.0
-40.5
-41.0
-41.5
-42.0
-42.5
-43.0
-43.5
-44.0
-44.5
-45.0
-45.5
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
-51.0
-51.5
code
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
dB
-52.0
-52.5
-53.0
-53.5
-54.0
-54.5
-55.0
-55.5
-56.0
-56.5
-57.0
-57.5
-58.0
-58.5
-59.0
-59.5
-60.0
-60.5
-61.0
-61.5
-62.0
-62.5
-63.0
-63.5
-64.0
-64.5
-65.0
-65.5
-66.0
-66.5
-67.0
-67.5
code
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
dB
-68.0
-68.5
-69.0
-69.5
-70.0
-70.5
-71.0
-71.5
-72.0
-72.5
-73.0
-73.5
-74.0
-74.5
-75.0
-75.5
-76.0
-76.5
-77.0
-77.5
-78.0
-78.5
-79.0
-79.5
-80.0
-80.5
-81.0
-81.5
-82.0
-82.5
-83.0
-83.5
code
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
DB
-84.0
-84.5
-85.0
-85.5
-86.0
-86.5
-87.0
-87.5
-88.0
-88.5
-89.0
-89.5
-90.0
-90.5
-91.0
-91.5
-92.0
-92.5
-93.0
-93.5
-94.0
-94.5
-95.0
-95.5
-96.0
-96.5
-97.0
-97.5
-98.0
-98.5
-99.0
-99.5
code
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
dB
-100.0
-100.5
-101.0
-101.5
-102.0
-102.5
-103.0
-103.5
-104.0
-104.5
-105.0
-105.5
-106.0
-106.5
-107.0
-107.5
-108.0
-108.5
-109.0
-109.5
-110.0
-110.5
-111.0
-111.5
-112.0
-112.5
-113.0
-113.5
-114.0
-114.5
-115.0
Mute
Table 59. DAC Digital Volume Level Setting
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2. DAC Soft Mute
The DAC block has a digital soft mute circuit. The soft mute operation is performed at digital domain.
The output signal is attenuated to -∞ in “ATT setting level x ATT transition time” from the current DAC
digital volume setting level by setting DA1MUTE bit or DA2MUTE bit to “1”. When the DA1MUTE bit or
DA2MUTE bit returns to “0”, the mute is cancelled and the output attenuation level gradually changes to
ATT setting level in “ATT setting level x ATT transition time”. If the soft mute is cancelled before
attenuating to -∞ after starting the operation, the attenuation is discontinued and the volume level returns
to original volume setting level by the same cycle. The soft mute is effective for changing the signal
source without stopping the signal transmission.
The attenuation level transition takes 924/fs from 0dB to -∞ and from -∞ to 0dB. Soft mute function is
available when each DAC is in operation. The attenuation value is initialized by setting the PDN pin = “L”.
The DAC1 (DAC2) is reset by setting PMDA1 bit (PMDA2 bit) to “0”. A click noise may occur when reset
the DAC block and releasing the reset. The output signal should be muted externally if the click noise
adversely affects the system performance.
DA1MUTE or DA2MUTE bit
924/fs
924/fs
0dB
Attenuation Level
-∞dB
GD
Group Delay (GD)
Output Image
Soft Mute Operation
Figure 75. DAC Soft Mute Operation
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[AK7735]
Analog ouptut pins will output VCOM voltage by setting HRESETN bit = “1” → “0” while PMDAx bit is “1”.
Use this mode when changing system clock during DAC operation to prevent a click noise caused by
resuming DAC operation after changing the system clock (Figure 76, CASE1).
Analog outputs goes to Hi-z state by setting HRESETN bi = “1” → “0” while PMDAx bit is “0”. Therefore a
click noise may occur when resuming DAC operation after changing the system clock (Figure 76,
CASE2). The output signal should be muted externally if the click noise adversely affects the system
performance.
PMDAx bit
HRESETN bit
Analog Output
0
0
Hi-Z Output
0
1
Hi-Z Output
1
0
VCOM Voltage Output
1
1
Normal Operation
Table 60. Analog Output Status during HUB Reset
HRESETN bit
CASE 1
PMDAx bit = “1”
VCOM Output
Analog Output
Operation Start
CASE 2
Click Noise
PMDAx bit
Hi-Z Output
Analog Output
Operation Start
Figure 76. Analog Output Status during HUB Reset
3. DAC Digital Filter Select
The AK7735 has four kinds of digital filters in DAC block. DASD and DASL bits select a digital filter.
DAC1 and DAC2 have a common digital filter setting.
Mode
0
1
2
3
DASD bit
0
0
1
1
DASL bit
Digital Filter
0
Sharp Roll-Off Filter
1
Slow Roll-Off Filter
0
Short Delay Sharp Roll-Off Filter
1
Short Delay Slow Roll-Off Filter
Table 61. DAC Digital Filter Select
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4. DAC De-emphasis Filter Control
The AK7735 has a digital de-emphasis filter (tc=50/15µs) that corresponds to three sampling
frequencies (32kHz, 44.1kHz and 48kHz) by IIR filter. The de-emphasis filter frequency is selected by
DEMx[1:0] bits (x=1, 2) (Table 62).
The de-emphasis filer only corresponds to the frequencies shown in Table 62. DEMx[1:0] bits must be
set to the default setting “01” when the AK7735 is operated with other sampling frequencies.
DEMx[1] bit
DEMx[0] bit
Mode
0
0
44.1kHz
0
1
OFF
(default)
1
0
48kHz
1
1
32kHz
Table 62. DAC De-emphasis Filter Control
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[AK7735]
■ SRC
Block
1. Sampling Rate
The AK7735 includes two stereo digital sampling rate converters (SRC). The input sampling rate (FSI)
and the output sampling rate (FSO) are supported from 8kHz to 192kHz. Available sampling rate ratio is
FSO/FSI = 0.167~6.0.
1-1. Up Sampling (1.00 FSO/FSI 6.00)
Supported sampling rates are shown below. (Passband and Stopband are proportional to FSI when the
FSO/FSI ratios are same.)
FSO
192kHz
48kHz
48kHz
48kHz
48kHz
48kHz
48kHz
48kHz
192kHz
44.1kHz
44.1kHz
44.1kHz
44.1kHz
44.1kHz
44.1kHz
16kHz
16kHz
8kHz
FSI
FSO/FSI Passband
48kHz
4.00
22.00kHz
48kHz
1.00
22.00kHz
44.1kHz
1.09
20.21kHz
32kHz
1.50
14.67kHz
24kHz
2.00
11.00kHz
16kHz
3.00
7.33kHz
12kHz
4.00
5.50kHz
8kHz
6.00
3.67kHz
44.1kHz
4.35
20.21kHz
44.1kHz
1.00
20.21kHz
32kHz
1.38
14.67kHz
24kHz
1.84
11.00kHz
16kHz
2.76
7.33kHz
12kHz
3.68
5.50kHz
8kHz
5.51
3.67kHz
16kHz
1.00
7.33kHz
8kHz
2.00
3.67kHz
8kHz
1.00
3.67kHz
Table 63. Up Sampling Example
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Stopband
26.00kHz
26.00kHz
23.89kHz
17.33kHz
13.00kHz
8.67kHz
6.50kHz
4.33kHz
23.89kHz
23.89kHz
17.33kHz
13.00kHz
8.67kHz
6.50kHz
4.33kHz
8.67kHz
4.33kHz
4.33kHz
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[AK7735]
1-2. Down Sampling (0.167 FSO/FSI < 1.00)
Three kinds of filter mode can be selected by SRCFAUD bit and SRCFEC bit when down sampling.
Supported sampling rates are shown below. (Passband and Stopband are proportional to FSI when the
FSO/FSI ratios are same.)
1) Audio Mode (SRCFAUD bit = “1”, SRCFEC bit = “0”)
FSO
FSI
FSO/FSI
Passband Stopband
44.1kHz
48kHz
0.919
20.00kHz 24.10kHz
48kHz
88.2kHz
0.544
19.25kHz 26.23kHz
48kHz
96kHz
0.5
20.90kHz 27.00kHz
44.1kHz 88.2kHz
0.5
19.20kHz 24.81kHz
44.1kHz
96kHz
0.459
18.70kHz 25.00kHz
16kHz
44.1kHz
0.363
5.79kHz
7.95kHz
48kHz
192kHz
0.25
25.19kHz 34.60kHz
44.1kHz
192kHz
0.229
25.19kHz 34.60kHz
8kHz
48kHz
0.167
3.16kHz
4.66kHz
8kHz
44.1kHz
0.181
2.90kHz
4.28kHz
Table 64. Down Sampling Example (Audio Mode)
2) Voice Mode (SRCFAUD bit = “0”, SRCFEC bit = “0”)
FSO
FSI
FSO/FSI
Passband Stopband
24kHz
32kHz
0.75
10.94kHz 11.95kHz
16kHz
24kHz
0.667
7.22kHz
7.97kHz
16kHz
32kHz
0.5
7.14kHz
7.97kHz
8kHz
16kHz
0.5
3.57kHz
3.98kHz
16kHz
48kHz
0.333
6.80kHz
7.97kHz
8kHz
32kHz
0.25
3.26kHz
3.99kHz
Table 65. Down Sampling Example (Voice Mode)
3) Echo Canceller Mode (SRCFEC bit = “1”)
In echo canceller mode, the input signal should be attenuated sufficiently for more than FSO/2
frequency.
FSO
FSI
FSO/FSI
Passband Stopband
32kHz
44.1kHz
0.726
20.21kHz 23.89kHz
32kHz
48kHz
0.667
22.00kHz 26.00kHz
24kHz
44.1kHz
0.544
20.21kHz 23.89kHz
24kHz
48kHz
0.5
22.00kHz 26.00kHz
16kHz
44.1kHz
0.363
20.21kHz 23.89kHz
16kHz
48kHz
0.333
22.00kHz 26.00kHz
Table 66. Down Sampling Example (Echo Canceller Mode)
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2. SRC Input/Output
Input sources of SRC1~2 are selected by SELSRCI1[5:0] and SELSRCI2[5:0] bits (Table 19, Table 20).
The input clock sync domains are inherited from the input data. The output clock sync domains are set
by SDSRCO1[2:0] and SDSRCO2[2:0] bits (Table 19, Table 20). Then the output data is sent to the data
bus.
3. SRC Soft Mute
The SRC1 and SRC2 have soft mute function independently.
3-1. Manual Mode
When SMUTEx bit (x=1, 2) is set to “1”, the SRC output data are attenuated to in 1024 FSO cycles.
When the SMUTEx bit is set to “0”, the mute is cancelled and the output attenuation level gradually
changes to 0dB in 1024 FSO cycles. If the soft mute is cancelled before mute state, the attenuation is
discontinued and the attenuation level returns to 0dB by the same cycles. The soft mute is effective for
changing the signal source without stopping the signal.
SMUTEx bit
0dB
Attenuation Level
at SRCOx
-dB
(3)
(1)
(2)
Figure 77. Soft Mute Manual Mode
(1) SMUTEx bit (x=1, 2) = “0”→“1”: The output data is attenuated to during 1024 FSO cycles.
(2) SMUTEx bit (x=1, 2) =“1”→“0”: The output attenuation level gradually changes to 0dB from in
1024 FSO cycles.
(3) If the soft mute is cancelled within 1024 FSO cycles, the attenuation is discontinued and the
attenuation level returns to 0dB by the same number of clock cycles.
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3-2. Semi-Auto Mode
Semi-automatic soft mute mode is set by SAUTOx bit (x=1, 2) = “1”. In this mode, soft mute is released
within 21.25ms after continuing the mute when PMSRCx bit (x=1, 2) is set to “1”. If SMUTEx bit is “1”
when PMSRCx bit is released (“0” → “1”), the soft mute is not cancelled.
“0”
PMSRCx bit
“0”
Don’t Care
SMUTEx bit
(1)
0dB
Attenuation
－∞dB
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