[AK7755]
AK7755
DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp
1. General Description
The AK7755 is a highly integrated digital signal processor, including a mono ADC, a stereo audio CODEC,
a MIC pre-amplifier, a line-out amplifier and digital audio I/F. The audio DSP has 2560step at fs = 48kHz
parallel processing power. As the AK7755 is a RAM based DSP, it is programmable for user requirements
such as high performance hands free function and acoustic effects. The AK7755 is available in a space
saving small 36-pin QFN package.
2. Features
DSP
- Word length: 24-bit (Data RAM 24-bit floating point)
- Instruction cycle: 8.1ns (2560fs at fs=48kHz)
- Multiplier 24 x 24 → 48-bit (double precision available)
- Divider 20 / 20 → 20-bit (with floating point normalization function)
- ALU: 52-bit arithmetic operation (with overflow margin 4-bit)
- Program RAM: 4096 × 36-bit
- Coefficient RAM: 2048 × 24-bit
- Data RAM: 2048 × 24-bit (24-bit floating point)
- Offset Register: 32 × 13-bit
- Delay RAM: 8192 × 24-bit
- Accelerator Coefficient RAM: 2048 × 20-bit
- Accelerator Data RAM: 2048 × 16-bit
- JX pins (Interrupt)
- Master/Slave Operation
- Master Clock: 2560fs
(Internally Generated by PLL from 32, 48, 64, 128, 256 and 384fs clock)
Two Digital Interfaces (I/F1, I/F2)
- Digital Signal Input Port (4ch): MSB justified 24-bit, LSB justified 24/20/16-bit, I2S
- Digital Signal Output Port (6ch): MSB justified 24-bit, LSB justified 24/20/16-bit, I2S
- Short / Long Frame
- 24-bit linear, 8-bit A-law, 8-bit μ-law
- TDM 256fs (8ch) MSB justified and I2S formats
Stereo 24-bit ADC:
- Sampling Frequency: fs=8kHz ~ 96kHz
- ADC Characteristics S/(N+D): 91dB, DR, S/N: 102dB
- Two-Channel Analog Input Selector (Differential, Single-ended Input)
- Channel Independent Mic Analog Gain Amplifier
(0~18dB (2dB Step), 18~36dB (3dB Step))
- Analog DRC (Dynamic Range Control)
- Channel Independent Digital Volume (24~-103dB, 0.5dB Step Mute)
- Digital HPF for DC Offset Cancelling
Mono 24-bit ADC
- Sampling Frequency: 8kHz ~ 96kHz
- ADC Characteristics S/(N+D): 90dB; DR, S/N: 100dB
- Line Amplifier: 21dB ~ -21dB, 3dB Step
- Digital Volume (24dB ~ -103dB, 0.5dB step, Mute)
- Digital HPF for DC Offset Cancelling
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[AK7755]
Stereo 24-bit DAC
- Sampling Frequency: fs=8kHz ~ 96kHz
- Digital Volume (12dB ~ -115dB, 0.5step, Mute)
- Digital De-emphasis Filter (tc=50/15us, fs=32kHz, 44.1kHz, 48kHz)
Line Output
- Single-ended Output
- S/(N+D): 91dB, DR, S/N: 106dB
- Stereo Analog Volume (+0dB ~ -28dB, 2.0dB step, Mute)
Analog Mixer
Digital Mixer
4ch Digital Microphone Interface
I2C Bootloader
- EEPROM Mat Selectable
μP Interface: SPI, I2C-bus (400kHz Fast Mode)
Power supply
Analog (AVDD): 3.0V ~ 3.6V (typ. 3.3V)
Digital1 (DVDD): 1.14V ~ 1.3V (typ. 1.2V)
(External Power Supply or Internal Regulator is selectable)
I/F (TVDD): 1.7V ~ 3.6V (typ. 3.3V)
Operating Temperature Range: -40C ~ 85C
Package: 36-pin QFN (0.5mm pitch)
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3. Table of Contents
1. General Description ................................................................................................................................................1
2. Features ...................................................................................................................................................................1
3. Table of Contents ....................................................................................................................................................3
4. Block Diagram and Functions ................................................................................................................................4
■ Block Diagram................................................................................................................................................. 4
■ DSP Block Diagram ........................................................................................................................................ 5
5. Pin Configurations and Functions ..........................................................................................................................6
■ Ordering Guide ................................................................................................................................................ 6
■ Pin Layout ....................................................................................................................................................... 6
■ Pin Functions ................................................................................................................................................... 9
■ Handling of Unused Pin ................................................................................................................................ 10
6. Absolute Maximum Ratings ................................................................................................................................. 11
7. Recommended Operating Conditions ................................................................................................................... 11
8. Electrical Characteristics ......................................................................................................................................12
■ Analog Characteristics................................................................................................................................... 12
■ DC Characteristics ......................................................................................................................................... 17
■ Power Consumptions ..................................................................................................................................... 17
■ Digital Filter Characteritics ........................................................................................................................... 18
■ Switching Characteristics .............................................................................................................................. 19
9. Functional Description..........................................................................................................................................26
■ System Clock ................................................................................................................................................. 26
■ Control Register Settings ............................................................................................................................... 30
■ Power-up Sequence ....................................................................................................................................... 53
■ LDO (Internal Circuit Drive Regulator) ........................................................................................................ 56
■ Power-down Sequence .................................................................................................................................. 56
■ Power-down and Reset .................................................................................................................................. 57
■ RAM Clear .................................................................................................................................................... 60
■ Serial Data Interface ...................................................................................................................................... 60
■ μP Interface Setting and Pin Status ............................................................................................................... 67
■ SPI Interface (I2CSEL pin = “L”) ................................................................................................................. 67
■ I2C Bus Interface (I2CSEL pin= “H”) ........................................................................................................... 80
■ Analog Input Block ....................................................................................................................................... 85
■ ADC Block .................................................................................................................................................... 88
■ DAC Blocks .................................................................................................................................................. 91
■ Analog Output Block..................................................................................................................................... 93
■ Simple Write Error Check ............................................................................................................................. 95
■ EEPROM Interface ........................................................................................................................................ 96
■ Digital Microphone Interface ...................................................................................................................... 100
■ Digital Mixer ............................................................................................................................................... 101
10. Recommended External Circuits ......................................................................................................................102
■ Connection Diagram.................................................................................................................................... 102
■ Peripheral Circuit......................................................................................................................................... 106
11. Package .............................................................................................................................................................108
■ Outline Dimensions ..................................................................................................................................... 108
■ Package & Lead frame material .................................................................................................................. 108
■ Marking ....................................................................................................................................................... 109
12. Revision History ............................................................................................................................................... 110
IMPORTANT NOTICE ....................................................................................................................................... 112
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4. Block Diagram and Functions
■ Block Diagram
Figure 1. Block Diagram
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■ DSP Block Diagram
CP0, CP1
Pointer
DP0, DP1
Coefficient RAM
Data RAM
2048w x 24-Bit(20.4f)
2048w×24-Bit
OFREG
32w x 13-Bit
DLP0, DLP1
Delay RAM
8192w x 24-Bit(20.4f)
CBUS(24-Bit)
DBUS(28-Bit)
MPX24
Micon I/F
MPX24
X
Serial I/F
Control
PRAM
DEC
Y
4096w×36-Bit
Multiply
24 ×24 → 48-Bit
PC
Stack : 5level(max)
28-Bit
48-Bit
TMP 12×24-Bit
PTMP(LIFO) 6×24-Bit
MUL
DBUS
2×16/20/24-Bit
DIN4
2×16/20/24-Bit
DIN3
2×16/20/24-Bit
DIN2
2×16/20/24-Bit
DIN1
ALU
2×16/20/24-Bit
DOUT4
52-Bit
2×16/20/24-Bit
DOUT3
2×16/20/24-Bit
DOUT2
2×16/20/24-Bit
DOUT1
SHIFT
52-Bit
48-Bit
A
B
Overflow Margin: 4-Bit
52-Bit
DR0 3
Accelerator
52-Bit
Coefficient RAM
(ACCRAM)
2048w x 20-Bit
Over Flow Data
Generator
Division 2020→20
Data RAM
(ACDRAM)
2048w x 16-Bit
Peak Detector
Figure 2. DSP Block Diagram
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5. Pin Configurations and Functions
■ Ordering Guide
-40 +85C
36-pin QFN (0.5mm pitch)
Evaluation Board for AK7755
AK7755EN/VN
AKD7755
OUT3
OUT2
DVSS
DVDD/AVDRV
LDOE
PDN
AVDD
CSN/CAD/MATSEL
SI/EXTEEP
27
26
25
24
23
22
21
20
19
■ Pin Layout
OUT1
28
18
SCLK/SCL
AVDD
29
17
SO/SDA
AVSS
30
16
SDOUT1/EEST
IN4/INN2/DMCLK2
31
15
SDOUT2/JX3/MAT0
IN3/INP2/DMDAT2
32
14
SDOUT3/JX2/MAT1
IN2/INN1/DMCLK1
33
13
DVSS
IN1/INP1/DMDAT1
34
12
TVDD
LIN
35
11
XTI
AVDD
36
10
XTO
36pin QFN
1
2
3
4
5
6
7
8
9
VCOM
AVSS
I2CSEL
SDIN2/JX1
SDIN1/JX0
STO/RDY
LRCK
BICK
CLKO
(TOP VIEW)
PIN
Input
Output
I/O
Power
Figure 3. Pin Layout
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PDN
AVDD
CSN
SI
21
20
19
LDOE
23
22
DVSS
DVDD/AVDRV
24
OUT2
26
25
OUT3
27
I2CSEL pin = “L”
OUT1
28
18
SCLK
AVDD
29
17
SO
AVSS
30
16
SDOUT1/EEST
IN4/INN2/DMCLK2
31
15
SDOUT2/JX3
IN3/INP2/DMDAT2
32
14
SDOUT3/JX2
IN2/INN1/DMCLK1
33
13
DVSS
IN1/INP1/DMDAT1
34
12
TVDD
LIN
35
11
XTI
AVDD
36
10
XTO
36pin QFN
5
6
7
8
9
STO/RDY
LRCK
BICK
CLKO
4
SDIN2/JX1
SDIN1/JX0
2
3
AVSS
I2CSEL=“L”
1
VCOM
(TOP VIEW)
PIN
Input
Output
I/O
Power
OUT3
OUT2
DVSS
DVDD/AVDRV
LDOE
PDN
AVDD
CAD
EXTEEP=“L”
27
26
25
24
23
22
21
20
19
I2CSEL pin = “H”, EXTEEP pin = “L”
OUT1
28
18
SCL
AVDD
29
17
SDA
AVSS
30
16
SDOUT1/EEST
IN4/INN2/DMCLK2
31
15
SDOUT2/JX3
IN3/INP2/DMDAT2
32
14
SDOUT3/JX2
IN2/INN1/DMCLK1
33
13
DVSS
IN1/INP1/DMDAT1
34
12
TVDD
LIN
35
11
XTI
AVDD
36
10
XTO
36pin QFN
1
2
3
4
5
6
7
8
9
VCOM
AVSS
I2CSEL=“H”
SDIN2/JX1
SDIN1/JX0
STO/RDY
LRCK
BICK
CLKO
(TOP VIEW)
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PIN
Input
Output
I/O
Power
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[AK7755]
OUT3
OUT2
DVSS
DVDD/AVDRV
LDOE
PDN
AVDD
MATSEL=“L”
EXTEEP=“H”
27
26
25
24
23
22
21
20
19
I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “L”
OUT1
28
18
SCL
AVDD
29
17
SDA
AVSS
30
16
SDOUT1/EEST
IN4/INN2/DMCLK2
31
15
SDOUT2/JX3
IN3/INP2/DMDAT2
32
14
SDOUT3/JX2
IN2/INN1/DMCLK1
33
13
DVSS
IN1/INP1/DMDAT1
34
12
TVDD
LIN
35
11
XTI
AVDD
36
10
XTO
36pin QFN
1
2
3
4
5
6
7
8
9
VCOM
AVSS
I2CSEL=“H”
SDIN2/JX1
SDIN1/JX0
STO/RDY
LRCK
BICK
CLKO
(TOP VIEW)
PIN
Input
Output
I/O
Power
OUT3
OUT2
DVSS
DVDD/AVDRV
LDOE
PDN
AVDD
MATSEL=“H”
EXTEEP=“H”
27
26
25
24
23
22
21
20
19
I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “H”
OUT1
28
18
SCL
AVDD
29
17
SDA
AVSS
30
16
SDOUT1/EEST
IN4/INN2/DMCLK2
31
15
MAT0
IN3/INP2/DMDAT2
32
14
MAT1
IN2/INN1/DMCLK1
33
13
DVSS
IN1/INP1/DMDAT1
34
12
TVDD
LIN
35
11
XTI
AVDD
36
10
XTO
36pin QFN
1
2
3
4
5
6
7
8
9
VCOM
AVSS
I2CSEL=“H”
SDIN2/JX1
SDIN1/JX0
STO/RDY
LRCK
BICK
CLKO
(TOP VIEW)
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PIN
Input
Output
I/O
Power
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[AK7755]
■ Pin Functions
No. Pin Name
1
VCOM
2
AVSS
3
I2CSEL
4
5
6
7
8
9
SDIN2
JX1
SDIN1
JX0
STO
RDY
LRCK
BICK
CLKO
10 XTO
11 XTI
12 TVDD
13 DVSS
SDOUT3
JX2
14
MAT1
15
SDOUT2
JX3
MAT0
SDOUT1
EEST
SO
17
SDA
16
SCLK
18
SCL
19
SI
EXTEEP
I/O Function
Common Voltage Output Pin of Analog Block
O
▪ Connect a 2.2μF capacitor between AVSS.
▪ Do not connect to an external circuit.
- Analog Ground Pin 0V
I2C-BUS Select Pin
▪ I2CSEL pin = “L”: SPI Interface
I
▪ I2CSEL pin = “H”: I2C-bus Interface
The I2CSEL pin must be fixed to “L” (DVSS) or “H” (TVDD).
I Serial Data Input2 Pin
I External Conditional Jump1 Pin (JX1E bit = “1”)
I Serial Data Input1 Pin
I External Conditional Jump0 Pin (JX0E bit = “1”)
O Status Output Pin
O RDY Pin
I/O LR Channel Select Pin (Internal pull-down)
I/O Serial Bit Clock Output Pin (Internal pull-down)
O Clock Output Pin
Crystal oscillator output pin
O
▪ When a crystal oscillator is used, connect it between XTI and XTO.
▪ When a crystal oscillator is not used, leave this pin as open.
Crystal oscillator input pin
▪ When a crystal oscillator is used, connect it between XTI and XTO.
I
▪ When a crystal oscillator is not used, connect this pin to the external clock
or leave open.
- Digital IO Power Supply Pin: 1.7~3.6V (typ. 3.3V)
I Ground Pin 0V
O Serial Data Output3 Pin
I External Conditional Jump2 Pin (JX2E bit = “1”)
I2CSEL pin = EXTEEP pin = MATSEL pin = “H”
I
EEPROM Download Mat Select Address1
O Serial Data Output2 Pin
I External Conditional Jump3 Pin (JX3E bit = “1”)
I2CSEL pin = EXTEEP pin = MATSEL pin = “H”
I
EEPROM Download Mat Select Address0
O Serial Data Output1 Pin
O EEPROM Interface Status
O SO Pin (I2CSEL pin = “L”)
I/O I2CBUS Interface (I2CSEL pin = “H”)
Serial Data Clock Pin for SPI Interface (I2CSEL pin = “L”)
I
▪ Set this pin to “H” when there is no clock input.
I2CBUS Interface Pin (I2CSEL pin = “H”)
I/O
EEPROM Download This becomes an output pin when EXTEEP pin = “H”.
Serial Data Input Pin for SPI Interface (I2CSEL pin = “L”)
I
▪ Set this pin to “L” when not used.
I EEPROM Download Control Pin (I2CSEL pin = “H”)
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ChipSelectN Pin for SPI Interface (I2CSEL pin = “L”)
I
CSN
▪ Set this pin to “H” when the AK7755 is in power-down mode or when the
microprocessor I/F is not used.
20
I I2CBUS Address Pin (I2CSEL pin = “H”)
CAD
I EEPROM Mat Select Pin (I2CSEL pin = EXTEEP pin = “H”)
MATSEL
21 AVDD
- Analog Power Supply Pin: (typ. 3.3V)
Power-down N Pin
22 PDN
I
▪ The AK7755 can be powered-down by this pin.
▪ Set this pin to “L” upon power-up the AK7755.
LDO Select Pin
LDOE pin = “L”: 24 pin External 1.2V Power Supply
23 LDOE
I
LDOE pin = “H”: 24 pin LDO Output (LDO Drive)
The LDOE pin must be fixed to “L(DVSS)” or “H(TVDD)”.
I Power Supply Pin for Digital Core: (typ. 1.2V)
DVDD
LDO Output (LDOE pin = “H”)
24
O
AVDRV
Connect a 1uF capacitor between this pin and DVSS. This pin must not be
connected to an external circuit.
25 DVSS
- Ground Pin 0V
26 OUT2
O Line Output 2 Pin
27 OUT3
O Line Output 3 Pin
28 OUT1
O Line Output 1 Pin
29 AVDD
- Analog Power Supply Pin: 3.3V (typ)
30 AVSS
- Analog Ground Pin 0V
I ADC Input Pin (AINE bit = “1”)
IN4/INN2
31
DMCLK2
O Digital MIC Clock Output 2 Pin (DMIC2 bit = “1”)
I ADC Input Pin (AINE bit = “1”)
IN3/INP2
32
DMDAT2
I Digital MIC Clock Input 2 Pin (DMIC2 bit = “1”)
I ADC Input Pin (AINE bit = “1”)
IN2/INN1
33
DMCLK1
O Digital MIC Clock Output 1 Pin (DMIC1 bit = “1”)
I ADC Input Pin (AINE bit = “1”)
IN1/INP1
34
DMDAT1
I Digital MIC Clock Input 1 Pin (DMIC1 bit = “1”)
35 LIN
I Mono ADC Input Pin
36 AVDD
- Analog Power Supply Pin: 3.3V (typ)
Note 1. All digital input pins must not be allowed to float. If analog input pins are not used, leave them open.
The I2CSEL pin, LDOE pin and CAD/MATSEL pin should be fixed to “L” (DVSS) or “H”
(TVDD).
■ Handling of Unused Pin
The unused I/O pins must be processed appropriately as below.
Classification Pin Name
LIN, IN1/INP1/DMDAT1, IN2/INN1/DMCLK1,
Analog
IN3/INP2/DMDAT2, IN4/INN2/DMCLK2, OUT1, OUT2,
OUT3
STO/RDY, CLKO, XTI, XTO, SDOUT3/ JX2/MAT1,
SDOUT2/JX3/MAT0, SDOUT1/EEST, SO/SDA, LRCK,
BICK
Digital
I2CSEL, SDIN2/JX1, SDIN1/JX0,
SCLK/SCL, SI/EXTEEP, CSN/CAD/MATSEL, LDOE
014006643-E-01
Setting
These pins must be open.
These pins must be open.
These pins must be
connected to DVSS.
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[AK7755]
6. Absolute Maximum Ratings
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
min
max
Power Supplies
Analog
AVDD
-0.3
4.3
Digital1(I/F)
TVDD
-0.3
4.3
Digital2(Core)
ΔTVDD
-0.3
1.6
DVSS-AVSS
(Note 2)
ΔGND
-0.3
0.3
Input Current, Any Pin Except Supplies
IIN
−
±10
Analog Input Voltage (Note 3)
VINA
-0.3
(AVDD+0.3)≤4.3
Digital Input Voltage (Note 4)
VIND
-0.3
(TVDD+0.3)≤4.3
Ambient Temperature
Ta
-40
85
Storage Temperature
Tstg
-65
150
Note 2. All voltages with respect to ground. AVSS and DVSS must be the same voltage.
Note 3. The maximum analog input voltage is smaller value between (AVDD+0.3)V and 4.3V.
Note 4. The maximum digital input voltage is smaller value between (DVDD+0.3)V and 4.3V.
Unit
V
V
V
V
mA
V
V
C
C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
min
typ
max
Unit
Power Supplies
Analog
AVDD
3.0
3.3
3.6
V
Digital1(I/F)
TVDD
1.7
3.3
3.6
V
Digital2(Core)
DVDD
1.14
1.2
1.3
V
Note 5. AVDD and TVDD must be powered up first before DVDD when DVDD is supplied externally
(LDOE pin = “L”). In this case, the power-up sequence between AVDD and TVDD is not critical.
When using the internal regulator (LDOE pin = “H”), the power-up sequence between AVDD and
TVDD is not critical. But all power supplies must be ON before starting operation of the AK7755 by
PDN pin = “H”.
Note 6. Do not turn off the power supply of the AK7755 with the power supply of the surrounding device
turned on. Pull-up of SDA and SCL pins must not exceed TVDD.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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8. Electrical Characteristics
■ Analog Characteristics
1. MIC Amplifier Gain
(Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V)
Parameter
min
Input Impedance
14
MGNL[3:0]bits=0h, MGNR[3:0]bits=0h
MGNL[3:0]bits=1h, MGNR[3:0]bits=1h
MGNL[3:0]bits=2h, MGNR[3:0]bits=2h
MGNL[3:0]bits=3h, MGNR[3:0]bits=3h
MGNL[3:0]bits=4h, MGNR[3:0]bits=4h
MGNL[3:0]bits=5h, MGNR[3:0]bits=5h
MGNL[3:0]bits=6h, MGNR[3:0]bits=6h
MIC
MGNL[3:0]bits=7h, MGNR[3:0]bits=7h
AMP
Gain
MGNL[3:0]bits=8h, MGNR[3:0]bits=8h
MGNL[3:0]bits=9h, MGNR[3:0]bits=9h
MGNL[3:0]bits=Ah, MGNR[3:0]bits=Ah
MGNL[3:0]bits=Bh, MGNR[3:0]bits=Bh
MGNL[3:0]bits=Ch, MGNR[3:0]bits=Ch
MGNL[3:0]bits=Dh, MGNR[3:0]bits=Dh
MGNL[3:0]bits=Eh, MGNR[3:0]bits=Eh
MGNL[3:0]bits=Fh, MGNR[3:0]bits=Fh
typ
20
0
2
4
6
8
10
12
14
16
18
21
24
27
30
33
36
max
Unit
kΩ
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
2. Line-in Amplifier Gain
(Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V)
Parameter
min
typ
max
Unit
Input Impedance
14
20
kΩ
LIGN[3:0]bits=0h
0
dB
LIGN[3:0]bits=1h
-3
dB
LIGN[3:0]bits=2h
-6
dB
LIGN[3:0]bits=3h
-9
dB
LIGN[3:0]bits=4h
-12
dB
LIGN[3:0]bits=5h
-15
dB
LIGN[3:0]bits=6h
-18
dB
Line-in
LIGN[3:0]bits=7h
-21
dB
Gain
AMP
(Note 7) LIGN[3:0]bits=8h
N/A
dB
LIGN[3:0]bits=9h
+3
dB
LIGN[3:0]bits=Ah
+6
dB
LIGN[3:0]bits=Bh
+9
dB
LIGN[3:0]bits=Ch
+12
dB
LIGN[3:0]bits=Dh
+15
dB
LIGN[3:0]bits=Eh
+18
dB
LIGN[3:0]bits=Fh
+21
dB
Note 7. If the output signal of line-in amplifier is input to the analog mixer, +18dB gain is added to the signal
at the mixer.
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3. MIC Amp + ADC
Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V;
Signal Frequency 1kHz; Sampling Rate fs=48kHz; Measurement Frequency =20Hz to 20kHz
Sampling Rate fs=96kHz; Measurement Frequency =20Hz to 40kHz
CKM mode0(CKM[2:0]= “000”); BITFS[1:0]= “00” (64fs); DSM bit = “0”; Differential Input Mode
Parameter
min
typ
max
Unit
Resolution
24
Bit
Dynamic Characteristics (Differential Input mode)
Fs=48kHz (Note 12)
80
91
S/(N+D)
Fs=48kHz (Note 13)
88
(-1dBFS)
dB
Fs=96kHz (Note 12)
89
(Note 14)
Fs=96kHz (Note 13)
85
Fs=48kHz (A-weighted) (Note 12)
94
102
Dynamic
Fs=48kHz (A-weighted) (Note 13)
93
Range
dB
Fs=96kHz (Note 12)
95
(Note 8)
Fs=96kHz (Note 13)
89
Fs=48kHz (A-weighted) (Note 12)
94
102
MIC Amp
Fs=48kHz (A-weighted) (Note 13)
93
+ ADC
S/N
dB
Fs=96kHz (Note 12)
95
Fs=96kHz (Note 13)
89
Inter-Channel Isolation (Note 9)
90
105
dB
DC accuracy (Differential Input)
Channel Gain Mismatch
0.0
0.3
dB
Analog Input
(Note 12)
±2.00
±2.20
±2.40
Input Voltage
Vp-p
(Differential Input) (Note 10)
(Note 13)
±0.277
(Note 12)
2.00
2.20
2.40
Input Voltage
Vp-p
(Single-ended Input) (Note 11)
(Note 13)
0.277
Note 8. S/(N+D) when -60dB FS signal is applied.
Note 9. Indicates inter-channel isolation between Lch and Rch when –1dBFS signal is input.
Note 10. INP1/INN1 and INP2/INN2 pins.
Note 11. IN1, IN2, IN3 and IN4 pins.
Note 12. MGNL/R[3:0] bits = 0h (0dB)
Note 13. MGNL/R[3:0] bits = 9h (18dB)
Note 14. When setting DSM bit = “1”, S/(N+D) performance of the ADC degrades if an ADC and a DAC
are simultaneously operated by the sampling frequency with fs = 8k, 12k, or 24kHz. However, this
deterioration does not occur if ADC and DAC are not operated simultaneously. When DSM bit is
set to “0” (default), S/(N+D) performance of the ADC is not deterioraded even if the ADC and
DAC are operated simultaneously.
014006643-E-01
2018/08
- 13 -
[AK7755]
4. Line-in Amp + ADC
Ta=25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V;
Signal Frequency 1kHz; Sampling Rate fs=48kHz; Measurement Frequency =20Hz to 20kHz
Sampling Rate fs=96kHz; Measurement Frequency =20Hz to 40kHz
CKM mode0(CKM[2:0]= “000”); BITFS[1:0]= “00” (64fs);
Parameter
Resolution
Dynamic Characteristics
Fs=48kHz (Note 17)
Fs=48kHz (Note 18)
S/(N+D)
(-1dBFS) Fs=96kHz (Note 17)
Fs=96kHz (Note 18)
Fs=48kHz (A-weighted) (Note 17)
Dynamic
Fs=48kHz (A-weighted) (Note 18)
Line-in Amp Range
Fs=96kHz (Note 17)
(Note 15)
+ ADC
Fs=96kHz (Note 18)
Fs=48kHz (A-weighted) (Note 17)
Fs=48kHz (A-weighted) (Note 18)
S/N
Fs=96kHz (Note 17)
Fs=96kHz (Note 18)
Analog Input
(Note 17)
Input Voltage (Note 16)
(Note 18)
Note 15. S/(N+D) when -60dB FS signal is applied.
Note 16. The Lin pin.
Note 17. LIGN[3:0] bits = 0h (0dB)
Note 18. LIGN[3:0] bits = Eh (+18 dB)
014006643-E-01
min
typ
77
90
86
88
85
100
90
95
86
100
90
95
86
92
92
2.00
2.20
0.277
max
24
Unit
Bit
dB
dB
dB
2.40
Vp-p
2018/08
- 14 -
[AK7755]
5. Line-out AMP Gain
Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V
Parameter
LOVOL1[3:0]bits=0h, LOVOL2[3:0]bits=0h,
LOVOL3[3:0]bits=0h
LOVOL1[3:0]bits=1h, LOVOL2[3:0]bits=1h,
LOVOL3[3:0]bits=1h
LOVOL1[3:0]bits=2h, LOVOL2[3:0]bits=2h,
LOVOL3[3:0]bits=2h
LOVOL1[3:0]bits=3h, LOVOL2[3:0]bits=3h,
LOVOL3[3:0]bits=3h
LOVOL1[3:0]bits=4h, LOVOL2[3:0]bits=4h,
LOVOL3[3:0]bits=4h
LOVOL1[3:0]bits=5h, LOVOL2[3:0]bits=5h,
LOVOL3[3:0]bits=5h
LOVOL1[3:0]bits=6h, LOVOL2[3:0]bits=6h,
LOVOL3[3:0]bits=6h
LOVOL1[3:0]bits=7h, LOVOL2[3:0]bits=7h,
LOVOL3[3:0]bits=7h
Line-out
Gain
AMP
LOVOL1[3:0]bits=8h, LOVOL2[3:0]bits=8h,
LOVOL3[3:0]bits=8h
LOVOL1[3:0]bits=9h, LOVOL2[3:0]bits=9h,
LOVOL3[3:0]bits=9h
LOVOL1[3:0]bits=Ah, LOVOL2[3:0]bits=Ah,
LOVOL3[3:0]bits=Ah
LOVOL1[3:0]bits=Bh, LOVOL2[3:0]bits=Bh,
LOVOL3[3:0]bits=Bh
LOVOL1[3:0]bits=Ch, LOVOL2[3:0]bits=Ch,
LOVOL3[3:0]bits=Ch
LOVOL1[3:0]bits=Dh, LOVOL2[3:0]bits=Dh,
LOVOL3[3:0]bits=Dh
LOVOL1[3:0]bits=Eh, LOVOL2[3:0]bits=Eh,
LOVOL3[3:0]bits=Eh
LOVOL1[3:0]bits=Fh, LOVOL2[3:0]bits=Fh,
LOVOL3[3:0]bits=Fh
014006643-E-01
min
typ
max
Unit
mute
dB
-28
dB
-26
dB
-24
dB
-22
dB
-20
dB
-18
dB
-16
dB
-14
dB
-12
dB
-10
dB
-8
dB
-6
dB
-4
dB
-2
dB
0
dB
2018/08
- 15 -
[AK7755]
6. DAC+Line-out Amp
Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V;
Signal Frequency 1kHz; Sampling Rate fs=48kHz; Measurement Frequency =20Hz to 20kHz
Sampling Rate fs=96kHz; Measurement Frequency =20Hz to 40kHz
CKM mode0(CKM[2:0]=000); BITFS[1:0] bits = “00”; LOVOL1/2/3[3:0] bits = Fh(0dB);
Parameter
min
typ
max
Resolution
24
Dynamic Characteristics 1 (OUT1, OUT2, OUT3)
fs=48kHz
80
91
S/(N+D) (0 dBFS)
fs=96kHz
89
fs=48kHz (A-weighted)
100
106
Dynamic Range (Note 19)
fs=96kHz
101
fs=48kHz (A-weighted)
100
106
S/N
fs=96kHz
101
DAC
Inter-Channel Isolation (f=1kHz) (Note 20)
90
110
DC accuracy
Channel Gain Mismatch
0.0
0.5
Analog Output
Output Voltage
(Note 21)
2.28
2.51
2.74
Load Resistance
10
Load Capacitance
30
Note 19. S/(N+D) when -60dB FS signal is applied.
Note 20. Indicates inter-channel isolation between Lch and Rch of DAC when –1dBFS signal is input.
Note 21. Full-scale output voltage. The output voltage is proportional to AVDD (AVDD x 0.76).
014006643-E-01
Unit
Bit
dB
dB
dB
dB
dB
Vp-p
kΩ
pF
2018/08
- 16 -
[AK7755]
■ DC Characteristics
(Ta= -40 to 85C, AVDD=3.3V, DVDD=1.2V, TVDD=1.7 to 3.6V, AVSS=DVSS=0V)
Parameter
Symbol
min
typ
max
High Level Input Voltage
VIH
80%TVDD
Low Level Input Voltage
VIL
20%TVDD
SCL, SDA High Level Input Voltage
VIH
70%TVDD
SCL, SDA Low Level Input Voltage
VIL
30%TVDD
DMDAT1, DMDAT2 High Level Input Voltage
VIH2 65%AVDD
(DMIC1, DMIC2 bit = “1”)
DMDAT1, DMDAT2 Low Level Input Voltage
VIL2
35%AVDD
(DMIC1, DMIC2 bit = “1”)
TVDD-0.3
VOH
High Level Output Voltage Iout= -100A (Note 22)
0.3
VOL
Low Level Output Voltage Iout=100A (Note 23)
TVDD≥2.0V
VOL
0.4
SDA Low Level Output Voltage
Iout=3mA
TVDD