AK9232NK

[AK9232NK/33NK/34NK Application Note] AK9232NK/33NK/34NK Application notes This document shows circuit and layout diagrams of the AK9232/33/34 as the reference design. ■ Circuit Diagram It shows compositions of power supply decoupling capacitors and analog input filters. Peripheral Parts/Pattern Details R1,R2,C1,C2,C3 : Low-pass Filter of the AIN0 R3,R4,C4,C5,C6 : Low-pass Filter of the AIN1 C7,C8 : Decoupling Capacitor for HVDD C9,C10 : Decoupling Capacitor for DRVDD C11,C12 : Decoupling Capacitor for VREFP-VREFN C13,C14 : Decoupling Capacitor for VDD0 C15,C16 : Decoupling Capacitor for VDD1 Figure 1 Circuit Diagram Rev 1.0 2019/10 - 1 - [AK9232NK/33NK/34NK Application Note] ■ Layout Four layered printing board is used. The second layer is for the ground and the third layer is for power supply. HVDD and DRVDD are separated on the power supply layer. All areas except parts and wirings are GND in the first and the fourth layers. All used chip parts here are located as 1005 (1.0mm x 0.5mm) size layout. GND Figure 2 First Layer Layout Figure 3 Second Layer Layout DRVDD HVDD Figure 4 Third Layer Layout Figure 5 Fourth Layer Layout (Reverse Side) Rev 1.0 2019/10 - 2 - [AK9232NK/33NK/34NK Application Note] Digital wiring reduction method for the AK9232/33/34 is shown in this document. Each model has a CONVSTN, CSN, SDATI, SDATO, SDO0, SDO1, and CALC pins. Wirings can be reduced according to the application and the environment. Maximum four digital wirings can be eliminated. CALC (4) SDO1 (3) SDO0 SDATO (2) SCLK CSN CONSTN SDATI (1) Figure 6. Circuit Diagram Figure 7. Layout Rev 1.0 2019/10 - 3 - [AK9232NK/33NK/34NK Application Note] (1) Short of CONVSTN/CSN Pins The CONVSTN pin and the CSN pin can be shorted and used as a common pin. Data sampled on a falling edge of the CONVSTN/CSN pin will be output from the SDOx pin on the next falling edge of the CONVSTN/CSN pin. The SCLK pin must be set to “H” when setting the CSN pin to “L”. Figure 8. Data Output Timing (CONVSTN, CSN Common) Rev 1.0 2019/10 - 4 - [AK9232NK/33NK/34NK Application Note] (2) Short of SDATO/SDATI Pins (SDATI/O) Register writing and reading via 3-wire serial interface (CSN, SCLK and SDATI/SDATO pins) are enabled by shorting the SDATO pin and the SDATI pin. In this case, the pin of a connected device to the AK923X should be I/O pin. The SCLK pin must be set to “H” when setting the CSN pin to “L”. Figure 9. Serial I/F Timing (SDATI, SDATO Common) Rev 1.0 2019/10 - 5 - [AK9232NK/33NK/34NK Application Note] (3) Wiring Reduction of SDO0 or SDO1 By setting CONT bit = “1” (serial output mode) by register access, the A/D conversion result of the CH1 is output from the SDO0 pin after outputting the A/D conversion result of the CH0 (the A/D conversion result of the CH0 is output from the SDO1pin after outputting the A/D conversion result of the CH1). In this case, clock should be input continuously for 39 cycles to the SCLK pin while the CSN pin is “L”. “L” signal is output from SDOX pins when the 40th or more clock cycles are input. The SCLK pin must be set to “H” when setting the CSN pin to “L”. * The maximum conversion rate is 0.93MSPS in serial output mode. Figure 10. Data Output Timing in Serial Output Mode Rev 1.0 2019/10 - 6 - [AK9232NK/33NK/34NK Application Note] (4) Wiring Reduction of the CALC Pin Monitoring by the CALC pin is not necessary in following two cases. 1. In case of receiving data on a falling edge “↓” of CSN after tDD (max) from a falling edge “↓” of CONVSTN. * 10. Guaranteed by design. This value is not tested in mass production. Figure 11. Conversion Timing 2. In case of “(1)”, shorting the CONVSTN/CSN pins Rev 1.0 2019/10 - 7 - [AK9232NK/33NK/34NK Application Note] Disclaimer Please note that this document is written for reference only and it does not guarantee any information written in this document. Asahi Kasei Microdevices Corporations assumes no responsibility for any damages or losses resulting from the use of this document. Inquiry For any inquiries about this application note, please contact us from the link below. Rev 1.0 2019/10 - 8 -