[AK4499]
AK4499
Premium Switched Resistor 4ch DAC
1. General Description
The AK4499 is a 32-bit 4ch Switched Resistor DAC which adopts newly developed technology,
achieving the industry’s leading level low distortion and low noise characteristics. It corresponds to a
768kHz PCM input and an DSD512 input at maximum, suitable for playback of high resolution audio
sources that are becoming widespread in Network Audio and USB-DACs Audio systems. In addition, it
is capable of supporting a wide range of signals and achieving low out-of-band noise. The AK4499 has
six types of 32-bit digital filters, realizing simple and flexible sound reproduction in wide range of
applications.
2.
Features
• 4-ch Switched Resistor DAC
• THD+N: -124 dB
• Dynamic Range, S/N: 140 dB (Mono), 137 dB (Stereo), 134 dB (4ch)
• 128x Over Sampling
• Sampling Rate: 8 kHz to 768 kHz
• 32-bit 8x Digital Filter
Short Delay Sharp Roll-off, GD = 6.0/fs
Short Delay Slow Roll-off, GD = 5.0/fs
Sharp Roll-off
Slow Roll-off
Super Slow Roll-off
Low Dispersion Short Delay Filter
• DSD64, DSD128, DSD256, DSD512 Input Support
Filter1 (fc = 37 kHz, DSD64 mode)
Filter2 (fc = 65 kHz, DSD64 mode)
• Digital De-emphasis for 32, 44.1 and 48kHz sampling
• Soft Mute
• Digital Attenuator (0 dB to -127 dB, 0.5 dB step + mute)
• Mono Mode
• External Digital Filter Interface (EXDF Mode)
• PCM/DSD, EXDF/DSD Mode Automatic Mode Switching Function
• Audio I/F Format
- MSB Justified
- LSB Justified
- I2S
- DSD
- TDM
• Daisy Chain
• Master Clock
- fs = 8 kHz to 32 kHz
: 256fs, 384fs, 512fs, 768fs, 1152fs
- fs = 32 kHz to 54 kHz
: 256fs, 384fs, 512fs, 768fs
- fs = 54 kHz to 108 kHz
: 256fs, 384fs
- fs = 108 kHz to 216 kHz : 128fs, 192fs
- fs = 384 kHz
: 32fs, 48fs, 64fs, 96fs
- fs = 768 kHz
:16fs, 32fs, 48fs, 64fs
• Register Control Mode with 3-wire Serial or I2C interface
019001308-E-00
2019/02
-1-
[AK4499]
• Pin Control Mode
• Power Supply:
Internal LDO (LDOE pin = “H”); TVDD = 3.0 3.6 V, AVDD = 4.75 5.25 V,
VDDL1/R1/L2/R2 = 4.75 5.25 V
External Supply (LDOE pin = “L”); TVDD = 1.7 3.6 V, DVDD = 1.7 to 1.98 V,
AVDD = 4.75 5.25 V, VDDL1/R1/L2/R2 = 4.75 5.25 V
• Operational Temperature: -40 to 85 C
• Digital Input Level: CMOS
• Package: 128-pin HTQFP
019001308-E-00
2019/02
-2-
[AK4499]
3. Table of Contents
1.
General Description ........................................................................................................................ 1
2.
Features .......................................................................................................................................... 1
3.
Table of Contents ............................................................................................................................ 3
4.
Block Diagram and Functions ......................................................................................................... 4
4.1. Block Diagram ................................................................................................................................. 4
4.2. Functions ......................................................................................................................................... 5
5.
Pin Configurations and Functions ................................................................................................... 6
5.1. Pin Configurations ........................................................................................................................... 6
5.2. Functions ......................................................................................................................................... 7
5.3. Handling of Unused Pin ..................................................................................................................11
6.
Absolute Maximum Ratings .......................................................................................................... 13
7.
Recommended Operating Conditions .......................................................................................... 14
8.
Electical Characteristics ................................................................................................................ 15
8.1. Analog Characteristics................................................................................................................... 15
8.2. DAC Digital Filter Characteristics (PCM Mode) ............................................................................ 19
8.3. DAC Digital-Filter Characteristics (DSD Mode)............................................................................. 29
8.4. DC Characteristics ......................................................................................................................... 30
8.5. Switching Characteristics .............................................................................................................. 31
8.6. Timing Diagram.............................................................................................................................. 36
9.
Functional Descriptions ................................................................................................................ 41
9.1. Control Mode ................................................................................................................................. 41
9.2. D/A Conversion Mode.................................................................................................................... 42
9.3. System Clock ................................................................................................................................. 45
9.4. Audio Interface Format .................................................................................................................. 51
9.5. Digital Filter .................................................................................................................................... 64
9.6. De-emphasis Filter (PCM Mode) ................................................................................................... 65
9.7. Digital Attenuator ........................................................................................................................... 66
9.8. Gain Adjustment Function ............................................................................................................. 67
9.9. Zero Detection, DSD Full-scale Detection .................................................................................... 68
9.10. LR Channel Output Signal Select, Phase Inversion Function .................................................... 73
9.11. PCM/DSD, EXDF/DSD Automatic Mode Switching Function ..................................................... 74
9.12. LDO.............................................................................................................................................. 83
9.13. Power Up/Down Sequence ......................................................................................................... 84
9.14. Power Down, Standby and Reset Function ................................................................................ 89
9.15. Synchronize Function (PCM Mode, EXDF Mode) ...................................................................... 93
9.16. Register Control Interface............................................................................................................ 95
9.17. Register Map ............................................................................................................................... 99
9.18. Register Definitions ................................................................................................................... 100
10.
Recommended External Circuits ................................................................................................ 106
10.1. External Connection Example ................................................................................................... 106
10.2. Grounding and Power Supply Decoupling ................................................................................ 108
10.3. Reference Voltage ..................................................................................................................... 108
10.4. Analog Output ............................................................................................................................ 108
11.
Package .......................................................................................................................................114
11.1.
Outline Dimensions (HTQFP14 x 14-128, Unit: mm) ...........................................................114
11.2.
Material & Terminal Finish .....................................................................................................115
11.3.
Marking..................................................................................................................................115
12.
Ordering Guide ............................................................................................................................116
13.
Revision Histroy ...........................................................................................................................116
IMPORTANT NOTICE ...........................................................................................................................117
019001308-E-00
2019/02
-3-
[AK4499]
4.
Block Diagram and Functions
4.1. Block Diagram
TVDD DVDD DVSS
LDOE
PDN
BICK/BCK/DCLK
SDATA1/DINL1/DSDL1
LRCK/DINR1/DSDR1
SDATA2/DINL2/DSDL2
L
TDMO
DINR2/DSDR2
AVDD
AVSS
LDO
PCM
Data
Interface
External
DF
Interface
De-emphasis
&
Interpolator
SR
DACL1
Modulator
DATT
Soft Mute
SSLOW/WCK
TDM0/DCLK
DEM0/DSDL1
DSDR1
TDM1/DSDL2
DCHAIN/DSDR22
SR
DACR1
Normal path
DSDD bit “0”
PCM/DSD
EXDF/DSD
Automatic
Mode
Switching
Volume Bypass
DSDD bit “1”
DSD
Data
Interface/
DSD
Filter
De-emphasis
8x
&
Interpolator
Interpolator
SR
DACL2
Modulator
DATT
Soft Mute
SR
DACR2
Normal path
DSDD bit “0”
Volume Bypass
DSDD bit “1”
Clock
Divider
Control
Register
SMUTE/CSN
SD/ CCLK/SCL
SLOW/CDTI/SDA
VREFHL1
VREFLL1
1
VSSL1
VDDL1
VCOML1
EXTCL1N
IOUTL1N
OPINL1N
OPINL1P
IOUTL1P
EXTCL1P
EXTCR1P
IOUTR1P
OPINR1P
OPINR1N
IOUTR1N
EXTCR1P
VCOMR1
VDDR1
VSSR1
VREFLR1
VREFHR1
VREFHL2
VREFLL2
21
VSSL2
VDDL2
VCOML2
EXTCL2N
IOUTL2N
OPINL2N
OPINL2P
IOUTL2P
EXTCL2P
EXTCR2P
IOUTR2P
OPINR2P
OPINR2N
IOUTR2N
EXTCR2P
VCOMR2
VDDR2
VSSR2
VREFLR2
VREFHR2
MCLK Stop
Detection
IREF
INVR/ ACKS/ TEST MCLK VTSEL
CAD1
I2C
PSN DIF0/ DIF1/ DIF2/
DZFL DZFR CAD0
EXTR
Figure 1. AK4499 Block Diagram
019001308-E-00
2019/02
-4-
[AK4499]
4.2. Functions
Block
PCM Data Interface
External DF Interface
DSD Data Interface
DSD Filter
Function
Execute serial/parallel conversion of SDATA1/2 input data by synchronizing
with LRCK and BICK, and generate TDM output data.
Receive external digital filter outputs. Execute serial/parallel conversion of
DINL1/2 and DINR1/2 input data by synchronizing with BICK.
1-bit data that is input from DSDL1/2 and DSDR1/2 pins is received by
synchronizing with DCLK.
FIR filter that reduces high frequency noise of DSD input data
DATT, Soft Mute
De-emphasis &
Interpolator
ΔΣ Modulator
Apply DATT and Soft Mute process to input data.
A digital filter that applies De-emphasis process to input data and executes
over sampling.
Output multi-bit data to SR DAC. This block consists of a third-order digital
delta-sigma modulator.
SR DAC
Convert multi bit output of ΔΣ Modulator into analog signal. This block consists
of a switched resistor DAC.
Control Register
Keep register settings for each mode. Control registers are accessed in 3-wire
(CSN, CCLK, CDTI) or I2C-Bus (SCL, SDA) control mode.
Clock Divider
Divide Master Clock
In PCM mode, master clock is divided automatically by fs rate auto detection
function. In DSD mode, the master clock frequency is set by DCKS bit.
MCLK Stop Detection Detects when the master clock input is absent.
IREF
Generate reference current from the reference voltage generated internally,
using an external resistor.
LDO
Generate power for internal digital circuit (1.8V typ.).
019001308-E-00
2019/02
-5-
[AK4499]
5.
Pin Configurations and Functions
VSSR2
VSSR2
VSSR2
VDDR2
VDDR2
VCOMR2
VDDR2
EXTCR2N
IOUTR2N
IOUTR2N
OPINR2N
IOUTR2P
OPINR2P
IOUTR2P
EXTCR2P
NC
EXTCL2P
NC
IOUTL2P
IOUTL2P
OPINL2N
OPINL2P
IOUTL2N
EXTCL2N
IOUTL2N
VDDL2
VCOML2
VDDL2
VDDL2
VSSL2
VSSL2
VSSL2
5.1. Pin Configurations
VREFLL2
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
97
VREFLR2
VREFLL2
98
63
VREFLR2
VREFLL2
62
VREFLR2
VREFLL2
99
100
VREFHL2
101
61
VREFLR2
60
VREFHR2
VREFHL2
102
59
VREFHR2
VREFHL2
103
58
VREFHR2
VREFHL2
104
57
VREFHR2
EXTR
105
56
TEST
AVSS
106
55
INVR/I2C
AVDD
107
MCLK
AK4499
108
DVDD
109
DVSS
110
TVDD
111
LDOE
112
PDN
113
54
DCHAIN/DSDR2
53
TDM1/DSDL2
52
TDM0/DCLK
51
DSDR1
50
DEM0/DSDL1
49
TDMO
48
SSLOW/WCK
SMUTE/CSN
114
47
DINR2/DSDR2
SD/CCLK/SCL
115
46
SDATA2/DINL2/DSDL2
SLOW/CDTI/SDA
116
45
LRCK/DINR1/DSDR1
DIF0/DZFL
117
44
SDATA1/DINL1/DSDL1
DIF1/DZFR
118
43
BICK/BCK/DCLK
DIF2/CAD0
119
42
ACKS/CAD1
VTSEL
120
41
PSN
VREFHL1
121
40
VREFHR1
VREFHL1
122
39
VREFHR1
VREFHL1
123
38
VREFHR1
VREFHL1
124
VREFLL1
125
VREFLL1
128pin HTQFP
(Top View)
37
VREFHR1
36
VREFLR1
126
35
VREFLR1
VREFLL1
127
34
VREFLR1
VREFLL1
128
33
30 31 32
VREFLR1
VSSR1
VSSR1
Input
VSSR1
VDDR1
VDDR1
VDDR1
26 27 28 29
VCOMR1
25
EXTCR1N
IOUTR1N
OPINR1N
IOUTR1N
OPINR1P
IOUTR1P
IOUTR1P
NC
EXTCR1P
NC
EXTCL1P
IOUTL1P
IOUTL1P
OPINL1P
IOUTL1N
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
OPINL1N
9
IOUTL1N
8
EXTCL1N
7
VCOML1
6
VDDL1
5
VDDL1
4
VDDL1
3
VSSL1
2
VSSL1
VSSL1
1
Back TAB: Note1
Output
I/O
Power
Note 1: The exposed pad on the bottom surface of the package should be connected to AVSS.
019001308-E-00
2019/02
-6-
[AK4499]
5.2. Functions
No.
Pin Name
I/O
Function
1-3
4-6
VSSL1
VDDL1
-
7
VCOML1
I
8
EXTCL1N
O
External Capacitor connection pin. This pin should be
connected to 1 µF to VSSL1.
9,10
IOUTL1N
O
Current Output pin (L1ch Negative Signal).
11
OPINL1N
O
Common Voltage Input pin (L1ch Negative Signal).
12
OPINL1P
O
Common Voltage Input pin (L1ch Positive Signal).
13,14
IOUTL1P
O
Current Output pin (L1ch Positive Signal).
15
EXTCL1P
O
External Capacitor connection pin. This pin should be
connected to 1 µF to VSSL1.
16,17
NC
-
No internal bonding. Connect to AVSS.
18
EXTCR1P
O
External Capacitor connection pin. This pin should be
connected to 1 µF to VSSR1.
19,20
IOUTR1P
O
Current Output pin (R1ch positive signal).
21
OPINR1P
O
Common Voltage input pin (R1ch positive signal).
22
OPINR1N
O
Common Voltage input pin (R1ch negative signal).
23,24
IOUTR1N
O
Current Output pin (R1ch negative signal).
25
EXTCR1N
O
External Capacitor connection pin. This pin should be
connected to 1 µF to VSSR1.
26
VCOMR1
I
27-29
30-32
33-36
37-40
VDDR1
VSSR1
VREFLR1
VREFHR1
I
I
41
PSN
I
L1ch Analog Ground pin.
L1ch Analog Power Supply pin.
L1ch VCOM pin. VCOML1 is connected to the midpoint
of resistors between VREFHL1 and VREFLL1.
R1ch VCOM pin. VCOMR1 is connected to the midpoint
of resistors between VREFHR1 and VREFLR1.
R1ch Analog Power Supply pin.
R1ch Analog Ground pin.
R1ch Low Level Reference Voltage Input pin.
R1ch High Level Reference Voltage Input pin.
Control Mode Select pin (Internal pull-up pin)
“L”: Register Control mode
“H”: Pin Control mode
019001308-E-00
Power Down
State
Hi-Z
Pull-down to
VSSL1
(250 kΩ, typ)
Connected to
OPINL1N
(64 Ω, typ)
Connected to
IOUTL1N
(64 Ω, typ)
Connected to
IOUTL1P
(64 Ω, typ)
Connected to
OPINL1P
(64 Ω, typ)
Pull-down to
VSSL1
(250 kΩ, typ)
Pull-down to
VSSR1
(250 kΩ, typ)
Connected to
OPINR1P
(64 Ω, typ)
Connected to
IOUTR1P
(64 Ω, typ)
Connected to
IOUTR1N
(64 Ω, typ)
Connected to
OPINR1N
(64 Ω, typ)
Pull-down to
VSSR1
(250 kΩ, typ)
Hi-Z
Hi-Z
Hi-Z
Pull-Up to
TVDD
(100 kΩ, typ)
2019/02
-7-
[AK4499]
No.
Pin Name
I/O
ACKS
I
CAD1
BICK
BCK
DCLK
SDATA1
DINL1
I
I
I
I
I
I
DSDL1
I
LRCK
DINR1
I
I
DSDR1
I
SDATA2
DINL2
I
I
DSDL2
I
DINR2
I
DSDR2
I
48
SSLOW
WCK
I
I
49
TDMO
O
DEM0
I
DSDL1
I
DSDR1
I
TDM0
DCLK
TDM1
I
I
42
43
44
45
46
47
50
51
52
53
54
55
56
DSDL2
I
DCHAIN
I
DSDR2
I
INVR
I
I2C
I
TEST
I
Power Down
State
Function
Clock Setting Mode Select pin in Pin Control mode
“L”: Fixed Speed mode
“H”: Auto Setting mode
Chip Address 1 pin in Register Control mode
Audio Serial Data Clock pin in PCM mode
Audio Serial Data Clock pin in EXDF mode
DSD Clock Pin in DSD mode (@DSDPATH bit = ”1”)
Audio Serial Data Input pin in PCM mode
Audio Serial Data Input pin in EXDF mode
Audio Serial Data Input pin in DSD mode
(@DSDPATH bit = ”1”)
Input Channel Clock pin in PCM mode
Audio Serial Data Input pin in EXDF mode
Audio Serial Data Input pin in DSD mode
(@DSDPATH bit = ”1”)
Audio Serial Data Input pin in PCM mode
Audio Serial Data Input pin in EXDF mode
Audio Serial Data Input pin in DSD mode
(@DSDPATH bit = ”1”)
Audio Serial Data Input pin in EXDF mode
Audio Serial Data Input pin in DSD mode
(@DSDPATH bit = ”1”)
Digital Filter Select pin in Pin Control mode
Word Clock input pin in EXDF mode
Audio Serial Data Output pin in Daisy Chain mode
(Internal pull-down pin)
De-emphasis Enable pin in Pin Control mode
Audio Serial Data Input pin in DSD mode
(@DSDPATH bit = ”0”)
Audio Serial Data Input pin in DSD mode
(@DSDPATH bit = ”0”)
TDM Mode select 0 pin in Pin control mode.
DSD Clock pin in DSD mode (@DSDPATH bit =”0”)
TDM Mode select 1 pin in Pin control mode.
Audio Serial Data Input pin in DSD mode
(@DSDPATH bit = ”0”)
Daisy Chain Mode Select pin in Pin Control mode.
Audio Serial Data Input Pin in DSD mode
(@DSDPATH bit = ”0”)
R1/2ch Signal Invert pin in Pin Control mode
Serial Control Interface Select pin in Register Control
mode.
“L”: 3-wire serial control interface.
“H”: I2C Bus serial control interface.
Connect to DVSS (Internal pull-down pin)
019001308-E-00
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pull-down to
DVSS
(100 kΩ, typ)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Pull-down to
DVSS
(100 kΩ, typ)
2019/02
-8-
[AK4499]
No.
Pin Name
I/O
Function
57-60
61-64
65-67
68-70
VREFHR2
VREFLR2
VSSR2
VDDR2
I
I
-
71
VCOMR2
I
72
EXTCR2N
O
External Capacitor Connection pin. This pin should be
connected to 1 µF to VSSR2.
73,74
IOUTR2N
O
Current Output pin (R2ch negative signal).
75
OPINR2N
O
Common Voltage Input pin (R2ch negative signal).
76
OPINR2P
O
Common Voltage Input pin (R2ch positive signal).
77,78
IOUTR2P
O
Current Output pin (R2ch positive signal).
79
EXTCR2P
O
External Capacitor connection pin. This pin should be
connected to 1 µF to VSSR2.
80,81
NC
-
No internal bonding. Connect to AVSS.
82
EXTCL2P
O
External Capacitor connection pin. This pin should be
connected to 1 µF to VSSL2.
83,84
IOUTL2P
O
Current Output pin (L2ch positive signal).
85
OPINL2P
O
Common Voltage Input pin (L2ch positive signal).
86
OPINL2N
O
Common Voltage Input pin (L2ch negative signal).
87,88
IOUTL2N
O
Current Output pin (L2ch negative signal).
89
EXTCL2N
O
External Capacitor connection pin. This pin should be
connected to 1 µF to VSSL2.
90
VCOML2
I
91-93
94-96
97-100
101-104
VDDL2
VSSL2
VREFLL2
VREFHL2
I
I
105
EXTR
I
106
107
AVSS
AVDD
-
R2ch High Level Reference Voltage Input pin.
R2ch Low Level Reference Voltage Input pin.
R2ch Analog Ground pin.
R2ch Analog Power Supply pin.
R2ch VCOM pin. VCOMR2 is connected to the midpoint
of resistors between VREFHR2 and VREFLR2.
L2ch VCOM pin. VCOML2 is connected to the midpoint
of resistors between VREFHL2 and VREFLL2.
L2ch Analog Power Supply pin.
L2ch Analog Ground pin.
L2ch Low Level Reference Voltage Input pin.
L2ch High Level Reference Voltage Input pin.
External Resistor connection pin. This pin should be
connected to 33 kΩ (±1 %) to AVSS.
Analog Ground pin
Clock Interface Power Supply Pin, 4.75 to 5.25 V
019001308-E-00
Power Down
State
Hi-Z
Hi-Z
Hi-Z
Pull-down to
VSSR2
(250 kΩ, typ)
Connected to
OPINR2N
(64 Ω, typ)
Connected to
IOUTR2N
(64 Ω, typ)
Connected to
IOUTR2P
(64 Ω, typ)
Connected to
OPINR2P
(64 Ω, typ)
Pull-down to
VSSR2
(250 kΩ, typ)
Pull-down to
VSSL2
(250 kΩ, typ)
Connected to
OPINL2P
(64 Ω, typ)
Connected to
IOUTL2P
(64 Ω, typ)
Connected to
IOUTL2N
(64 Ω, typ)
Connected to
OPINL2N
(64 Ω, typ)
Pull-down to
VSSL2
(250 kΩ, typ)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
2019/02
-9-
[AK4499]
No.
Pin Name
I/O
108
MCLK
I
Power Down
State
Hi-Z
Function
Master Clock Input pin
(LDOE pin = “H”) LDO Output pin. This pin should be
O connected to DVSS with 1.0 µF. This pin is
DVSS
prohibited to connect to other devices.
109
DVDD
(LDOE pin = “L”) 1.7 V to 1.98V Digital Power
Supply pin
110
DVSS
Digital Ground pin
111
TVDD
Digital Power Supply pin, 3.0 V to 3.6 V
Internal LDO Enable pin.
112
LDOE
I
Hi-Z
“L”: Disable, “H”: Enable
Power-Up, Power-Down pin
When at “L”, the AK4499 is in Power-Down mode.
Hi-Z
113
PDN
I
The AK4499 must always be in Power-Down mode
(PDN = “L”)
upon supply power on.
When this pin is changed to “H”, Soft Mute cycle is
SMUTE
I
initiated.
When returning to “L”, Soft Mute releases.
114
Hi-Z
Chip Select pin in 3-wire serial Register Control
CSN
I
mode
SD
I
Digital Filter Select pin in Pin Control mode
Control Data Clock pin in 3-wire serial Register
CCLK
I
115
Control mode
Hi-Z
Control Data Clock Input pin in I2C Bus Register
SCL
I
Control mode
SLOW
I
Digital Filter Select pin in Pin Control mode
Control Data Input pin in 3-wire serial Register
CDTI
I
116
Control mode
Hi-Z
2
Control Data Input pin in I C Bus Register Control
SDA
I/O
mode
DIF0
I
Digital Input Format 0 pin in Pin Control mode
Pull-down to
117
DVSS
Lch Zero Input Detect pin in Register Control mode
DZFL
O
(100 kΩ, typ)
(Internal pull-down pin)
DIF1
I
Digital Input Format 1 pin in Pin Control mode
Pull-down to
118
DVSS
Rch Zero Input Detect pin in Register Control mode
DZFR
O
(100 kΩ, typ)
(Internal pull-down pin)
DIF2
I
Digital Input Format 2 pin in Pin Control mode
119
Hi-Z
CAD0
I
Chip Address 0 pin in Register Control mode
MCLK VIH/L Level Select pin.
120
VTSEL
I
VTSEL = “L”; VIH = 1.36 V, VIL = 0.34 V
Hi-Z
VTSEL = “H”; VIH = 2.2 V, VIL = 0.8 V
121-124 VREFHL1
I
L1ch High Level Reference Voltage Input pin.
Hi-Z
125-128 VREFLL1
I
L1ch Low Level Reference Voltage Input pin.
Hi-Z
The TAB on the bottom surface of the package
TAB
should be connected to AVSS.
Note 2. All input pins except internal pull-up/down pins must not be left floating.
Note 3. The AK4499 must be powered down by the PDN pin when changing Pin Control/Register
Control modes by the PSN pin.
Note 4. PCM mode, DSD mode, and EXDF mode are selectable in Register Control mode.
019001308-E-00
2019/02
- 10 -
[AK4499]
5.3. Handling of Unused Pin
Unused I/O pins must be connected appropriately.
5.3.1. Pin Control Mode (PCM mode only)
Classification Pin Name
IOUTL1P, IOUTL1N, OPINL1P, OPINL1N
IOUTR1P, IOUTR1N, OPINR1P, OPINR1N
Analog
IOUTL2P, IOUTL2N, OPINL2P, OPINL2N
IOUTR2P, IOUTR2N, OPINR2P, OPINR2N
Digital
Setting
Open
Connect to DVSS or
Open
TEST
5.3.2. Register Control Mode
5.3.2.1. PCM Mode
Classification Pin Name
IOUTL1P, IOUTL1N, OPINL1P, OPINL1N
IOUTR1P, IOUTR1N, OPINR1P, OPINR1N
Analog
IOUTL2P, IOUTL2N, OPINL2P, OPINL2N
IOUTR2P, IOUTR2N, OPINR2P, OPINR2N
WCK, DEM0, DINR2, DSDR1/SDTO4, TDM0,
TDM1, DCHAIN
Digital
TEST
TDMO, DZFL, DZFR
Setting
Open
Connect to DVSS
Connect to DVSS or
Open
Open
5.3.2.2. DSD Mode
5.3.2.2.1. DSDPATH bit = “0”
Classification Pin Name
IOUTL1P, IOUTL1N, OPINL1P, OPINL1N
IOUTR1P, IOUTR1N, OPINR1P, OPINR1N
Analog
IOUTL2P, IOUTL2N, OPINL2P, OPINL2N
IOUTR2P, IOUTR2N, OPINR2P, OPINR2N
WCK, BICK, SDATA1, LRCK, SDATA2, DINR2
Digital
TEST
TDMO, DZFL, DZFR
5.3.2.2.2. DSDPATH bit = “1”
Classification Pin Name
IOUTL1P, IOUTL1N, OPINL1P, OPINL1N
IOUTR1P, IOUTR1N, OPINR1P, OPINR1N
Analog
IOUTL2P, IOUTL2N, OPINL2P, OPINL2N
IOUTR2P, IOUTR2N, OPINR2P, OPINR2N
WCK, DEM0, DSDR1/TSTO4, TDM0, TDM1,
DCHAIN
Digital
TEST
TDMO, DZFL, DZFR
019001308-E-00
Setting
Open
Connect to DVSS
Connect to DVSS or
Open
Open
Setting
Open
Connect to DVSS
Connect to DVSS or
Open
Open
2019/02
- 11 -
[AK4499]
5.3.2.3. EXDF Mode
Classification Pin Name
IOUTL1P, IOUTL1N, OPINL1P, OPINL1N
IOUTR1P, IOUTR1N, OPINR1P, OPINR1N
Analog
IOUTL2P, IOUTL2N, OPINL2P, OPINL2N
IOUTR2P, IOUTR2N, OPINR2P, OPINR2N
DEM0, DSDR1/TSTO4, TDM0, TDM1, DCHAIN
Digital
TEST
TDMO, DZFL, DZFR
5.3.2.4. In case I2C-Bus control mode
Classification Pin Name
Digital
CSN
5.3.3. Pull-up, Pull-down Pin List
Classification
pull-up pin (typ = 100 kΩ)
pull-down pin (typ = 100 kΩ)
Setting
Open
Connect to DVSS
Connect to DVSS or
Open
Open
Setting
Connect to DVSS
Pin Name
PSN
TDMO, DZFL, DZFR, TEST
019001308-E-00
Internal Termination
TVDD
DVSS
2019/02
- 12 -
[AK4499]
6. Absolute Maximum Ratings
(AVSS = DVSS = VSSL1/R1/L2/R2 = 0 V; Note 5)
Parameter
Symbol
Min.
Max.
Unit
Digital I/O
V
VDD
-0.3
4.0
Digital Core
V
DVDD
-0.3
2.5
Clock Interface
V
AVDD
-0.3
6.0
Power
VDD
Analog
V
-0.3
6.0
L1/R1/L2/R2
Supplies
Each VSS Difference (Note 6)
V
GND
0
0.3
|VDDL1/R1－AVDD| (Note 7)
V
VD
0
0.3
|VDDL2/R2－AVDD| (Note 7)
V
VD
0
0.3
VREFHL1
V
-0.3
VDDL1+0.3 or 6.0
VREFHR1
V
-0.3
VDDR1+0.3 or 6.0
High VREF
VREFHL2
V
-0.3
VDDL2+0.3 or 6.0
VREFHR2
V
-0.3
VDDR2+0.3 or 6.0
VREFLL1
V
-0.3
VDDL1+0.3 or 6.0
Reference
VREFLR1
V
-0.3
VDDR1+0.3 or 6.0
Voltage
Low VREF
VREFLL2
V
-0.3
VDDL2+0.3
or
6.0
(Note 8)
VREFLR2
V
-0.3
VDDR2+0.3 or 6.0
VCOML1
V
-0.3
VDDL1+0.3 or 6.0
VCOMR1
V
-0.3
VDDR1+0.3 or 6.0
Common Voltage
VCOML2
V
-0.3
VDDL2+0.3 or 6.0
VCOMR2
V
-0.3
VDDR2+0.3 or 6.0
Input Current, Any Pin Except Supplies and
IIN
10
mA
VREF
Analog
IOUTL1P/L1N/R1P/R1N,
VDDL1/R1+0.3 or
-0.3
VOUTA
V
Output
OPINL1P/L1N/R1P/R1N
6.0
Voltage
IOUTL2P/L2N/R2P/R2N,
VDDL2/R2+0.3 or
(Note 9)
-0.3
VOUTA
V
OPINL2P/L2N/R2P/R2N
6.0
Digital Input Voltage
VIND
-0.3
TVDD+0.3
V
Ambient Temperature (Power applied)
Ta
-40
85
C
Storage Temperature
Tstg
-65
150
C
Note 5. All voltages are with respect to ground.
Note 6. AVSS, DVSS, VSSL1, VSSR1, VSSL2, and VSSR2 must be connected to the same analog
ground plane. The exposed pad on the bottom surface of the package must be connected to
AVSS.
Note 7. VDDL1, VDDR1, VDDL2, VDDR2, and AVDD must be referenced to the same voltage level.
Note 8. Maximum input voltage of VREFHL1/R1/L2/R2 pins is lower value between (VDDL1/R1/L2/R2
+0.3) V and 6.0 V.
Note 9. Maximum value of the Analog Output Voltage must not exceed 6.0V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
019001308-E-00
2019/02
- 13 -
[AK4499]
7. Recommended Operating Conditions
(AVSS = DVSS = VSSL1/R1/L2/R2 = 0 V; Note 5)
Parameter
Symbol
Min.
Typ.
Max.
Unit
(LDOE pin = “L”;
Note 10)
Digital I/O
TVDD
DVDD
1.8/3.3
3.6
V
Digital Core
DVDD
1.7
1.8
1.98
V
Clock Interface
AVDD
4.75
5.0
5.25
V
VDD
Power
Analog
4.75
5.0
5.25
V
L1/R1/L2/R2
Supplies
(LDOE pin = “H”;
Note 11)
Digital I/O
TVDD
3.0
3.3
3.6
V
Clock Interface
AVDD
4.75
5.0
5.25
V
VDD
Analog
4.75
5.0
5.25
V
L1/R1/L2/R2
VDDL1
VREFHL1
VDDL1-0.5
V
VREFHR1
VDDR1-0.5
VDDR1
V
High VREF
VREFHL2
VDDL2-0.5
VDDL2
V
VREFHR2
VDDR2-0.5
VDDR2
V
VREFLL1
VSSL1
V
Referenc
VREFLR1
VSSR1
V
e Voltage Low VREF
VREFLL2
VSSL2
V
(Note 12)
VREFLR2
VSSR2
V
VCOML1
(VREFHL1+VREFLL1)/2
V
VCOMR1
(VREFHR1+VREFLR1)/2
V
Common Voltage
VCOML2
(VREFHL2+VREFLL2)/2
V
VCOMR2
(VREFHR2+VREFLR2)/2
V
Note 10. When the LDOE pin = “L”, TVDD must be supplied before DVDD is powered up or at the same
time. The power up sequence between other power supplies is not critical.
Note 11. When the LDOE pin = “H”, the internal LDO supplies 1.8 V (typ) from the DVDD pin. The
power up sequence between AVDD and TVDD is not critical.
Note 12. Reference voltage of VREFHL1/R1/L2/R2 must be input after VDDL1/R1/L2/R2 is powered up
or at the same time. Assuming that VREF Voltage divides into Common Voltage.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
019001308-E-00
2019/02
- 14 -
[AK4499]
8.
Electical Characteristics
8.1. Analog Characteristics
8.1.1. PCM Mode
(Ta = 25C; LDOE pin = “L”, TVDD = 3.3 V, DVDD = 1.8 V, AVDD = 5.0 V, AVSS = DVSS = 0 V;
VDDL1/R1/L2/R2 = VREFHL1/R1/L2/R2 = 5.0 V, VSSL1/R1/L2/R2 = VREFLL1/R1/L2/R2 = 0 V;
VCOML1/R1/L2/R2 = (VREFHL1/R1/L2/R2 + VREFLL1/R1/L2/R2)/2; 32-bit Input data; BICK = 64fs;
Signal Frequency = 1 kHz; fs = 44.1 kHz; Measurement bandwidth = 20 Hz to 20 kHz; External Circuit:
(Figure 82); GC[1:0] bits = “00”; unless otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Resolution
32
bit
Dynamic Characteristics
fs = 44.1 kHz
BW = 20 kHz 0dBFS
-124
-110
dB
THD fs = 96 kHz
BW = 40 kHz 0dBFS
-124
dB
fs = 192 kHz
BW = 80 kHz 0dBFS
-124
dB
0dBFS
-124
dB
fs = 44.1 kHz
BW = 20 kHz
-71
dB
60dBFS
0dBFS
-121
dB
fs = 96 kHz
BW = 40 kHz
-67
dB
60dBFS
THD+N
0dBFS
-118
dB
fs = 192 kHz
BW = 80 kHz
-62
dB
60dBFS
fs = 384 kHz
BW = 80 kHz 0dBFS
-118
dB
fs = 768 kHz
BW = 80 kHz 0dBFS
-118
dB
134
dB
Dynamic Range (60 dBFS with A-weighting)
4-ch mode
129
134
Stereo mode
137
dB
S/N (A-weighted)
Mono mode
140
dB
(Note 13)
Interchannel Isolation (1 kHz)
110
120
dB
DC Accuracy
Interchannel Gain Mismatch)
0.15
0.3
dB
Gain Drift
100
ppm/C
Differential Output Current (IOUTP-IOUTN)
(Note 14)
61.8
72.8
83.8
mApp
Center Current
(Note 15)
0
mA
Load Capacitance (Analog Output Pins)
(Note 16)
5
pF
Note 13. External circuits shown in Figure 83 are used in Mono mode.
Note 14. When the input signal is 0dBFS, the output current can be calculated by the following formula:
IOUTL1 (Typ. @ 0dBFS) = (IOUTL1P) – (IOUTL1N) = 72.8 mApp (VREFHL1 VREFLL1)/5.
IOUTR1 (Typ. @ 0dBFS) = (IOUTR1P) – (IOUTR1N) =72.8 mApp (VREFHR1 VREFLR1)/5.
IOUTL2 (Typ. @ 0dBFS) = (IOUTL2P) – (IOUTL2N) = 72.8 mApp (VREFHL2 VREFLL2)/5.
IOUTR2 (Typ. @ 0dBFS) = (IOUTR2P) – (IOUTR2N) =72.8 mApp (VREFHR2 VREFLR2)/5.
Note 15. Center current is the current that flows each IOUT pin during common output.
(When positive input of operational amplifier in I-V Conversion = VCOML1/R1/L2/R2 =
(VREFHL1/R1/L2/R2 + VREFLL1/R1/L2/R2)/2V)
Note 16. The load capacitance value of analog output pins (IOUTL1P/L1N/R1P/R1N pins,
OPINL1P/L1N/R1P/R1N pins, IOUTL2P/L2N/R2P/R2N pins, OPINL2P/L2N/R2P/R2N pins) is
with respect to ground.
Note 17. Absolute resistance error of subsequent stage circuits recommended to be 0.1% in order to
meet specifications.
019001308-E-00
2019/02
- 15 -
[AK4499]
(Ta = -40 to 85 C; LDOE pin = “L”, TVDD = 1.7 to 3.6 V, DVDD = 1.7 to 1.98 V, AVDD = 4.75 to 5.25
V, VDDL1/R1/L2/R2 = 4.75 to 5.25 V, VREFHL1/R1/L2/R2 = 4.75 to 5.25 V, DVSS = AVSS =
VSSL1/R1/L2/R2 = VREFLL1/R1/L2/R2 = 0 V; VCOML1/R1/L2/R2 = (VREFHL1/R1/L2/R2 +
VREFLL1/R1/L2/R2)/2; 32-bit Input data; BICK = 64fs; Signal Frequency = 1 kHz; fs = 44.1 kHz;
External Circuit: Figure 82; GC[1:0] bits = ”00”; unless otherwise specified.)
Power Supplies
Parameter
Min.
Typ.
Max.
Unit
Power Supply Current
Normal operation (PDN pin = “H”)
VDDL1/L2/R1/R2 total
32
48
mA
(Note 18)
(44)
(66)
mA
VREFHL1/L2/R1/R2 total
92
116
mA
AVDD
4.4
6.6
mA
TVDD
fs = 44.1 kHz
12
18
mA
LDOE pin = “H”
fs = 96 kHz
20
30
mA
fs = 192 kHz
33
50
mA
LDOE pin = “L”
1
1.5
mA
DVDD
fs = 44.1 kHz
12
18
mA
LDOE pin = “L”
fs = 96 kHz
20
30
mA
fs = 192 kHz
33
50
mA
Total power dissipation (LDOE pin
= “L”)
fs = 44.1 kHz
667
mW
(VDDL1/L2/R1/R2+VREFHL1/L2/R
1/R2+AVDD+TVDD+ DVDD)
Power down (PDN pin = “L”)
(Note 18)
(VDDL1/L2/R1/R2+VREFHL1/L2/R1/R2+AVDD+TVD
10
250
A
D+ DVDD)
Note 18. In power down mode, the PSN pin = TVDD and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held to DVSS.
Note 19. The DVDD pin becomes an output pin when the LDOE pin = “H”.
Note 20. The values in () at VDDL1/L2/R1/R2 total power supply current indicate consumption current
when there is zero input data.
019001308-E-00
2019/02
- 16 -
[AK4499]
8.1.2. DSD Mode
(Ta = 25 C; LDOE pin = “L”, TVDD = 3.3 V, DVDD = 1.8 V, AVDD = 5.0 V, AVSS = DVSS = 0 V;
VDDL1/R1/L2/R2 = VREFHL1/R1/L2/R2 = 5.0 V, VSSL1/R1/L2/R2 = VREFLL1/R1/L2/R2 = 0 V;
VCOML1/R1/L2/R2 = (VREFHL1/R1/L2/R2 + VREFLL1/R1/L2/R2)/2; Signal Frequency = 1 kHz;
Measurement bandwidth = 20 Hz to 20 kHz; External Circuit: Figure 82; GC[1:0] bits = ”00”); unless
otherwise specified.)
Dynamic Characteristics
Parameter
Min.
Typ.
Max.
Unit
0 dB
DSD data stream: DSD64
-124
dB
(Note 21)
0 dB
DSD data stream: DSD128
-124
dB
(Note 21)
THD
0 dB
DSD data stream: DSD256
-124
dB
(Note 21)
0 dB
DSD data stream: DSD512
-106
dB
(Note 21)
S/N (ADigital “0”
DSD data stream: DSD64
134
dB
weighted,
(Note 22)
Normal path)
Digital “0”
DSD data stream: DSD128
134
dB
(Note 22)
Digital “0”
DSD data stream: DSD256
134
dB
(Note 22)
Digital “0”
DSD data stream: DSD512
131
dB
(Note 22)
Note 21. The output level is assumed as 0dB when a 1kHz 25% to 75% duty sine wave is input. Click
noise may occur if the input signal exceeds 0dB.
Note 22. Digital “0” is a “01101001” digital zero code pattern.
019001308-E-00
2019/02
- 17 -
[AK4499]
DSD Data Stream: Power Supplies in 22.5792MHz Operation
(Ta = -40 to 85 C; LDOE pin = “L”, TVDD = 1.7 to 3.6 V, DVDD = 1.7 to 1.98 V, AVDD = 4.75 to 5.25 V,
VDDL1/R1/L2/R2 = 4.755.25 V, VREFHL1/R1/L2/R2 = 4.75 to 5.25 V, DVSS = AVSS =
VSSL1/R1/L2/R2 = VREFLL1/R1/L2/R2 = 0 V; VCOML1/R1/L2/R2 = (VREFHL1/R1/L2/R2 +
VREFLL1/R1/L2/R2)/2; Signal Frequency = 1 kHz; Measurement bandwidth = 20Hz to 20kHz; External
Circuit: Figure 82; 36.4mApp circuit output mode (GC[1:0] bits = ”00”); unless otherwise specified.)
Power Supplies
Parameter
Min.
Typ.
Max.
Unit
Power Supply Current
Normal operation (PDN pin = “H”)
52
78
mA
VDDL1/L2/R1/R2 total
(76)
(114)
mA
VREFHL1/L2/R1/R2 total
92
116
mA
AVDD
4.4
6.6
mA
TVDD
LDOE pin = “H”
20
30
mA
LDOE pin = “L”
DVDD
LDOE pin = “L”
Total power dissipation (LDOE pin = “L”)
(VDDL1/L2/R1/R2+VREFHL1/L2/R1/R2+AVDD+TV
DD+ DVDD)
019001308-E-00
1
1.5
mA
-
20
30
mA
-
798
-
mW
2019/02
- 18 -
[AK4499]
8.2. DAC Digital Filter Characteristics (PCM Mode)
8.2.1. Sharp Roll-Off Filter Characteristics
・fs = 44.1 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Normal Speed mode; DEM = OFF; SD bit or SD pin = “0”, SLOW bit or SLOW
pin = “0”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
20.0
kHz
Frequency Response
(Note 23)
6.0 dB
22.05
kHz
Pass band
(Note 24)
PB
0
20.0
kHz
Stop band
(Note 24)
SB
24.1
kHz
Pass band Ripple
(Note 25)
PR
0.005
dB
Stop band Attenuation
(Note 23)
SA
100
dB
Group Delay
(Note 26)
GD
29.2
1/fs
・fs = 96 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Double Speed mode; DEM = OFF; SD bit or SD pin = “0”, SLOW bit or SLOW
pin = “0”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
43.5
kHz
Frequency Response
(Note 23)
6.0 dB
48.0
kHz
Pass band
(Note 24)
PB
0
43.5
kHz
Stop band
(Note 24)
SB
52.5
kHz
Pass band Ripple
(Note 25)
PR
0.005
dB
Stop band Attenuation
(Note 23)
SA
100
dB
Group Delay
(Note 26)
GD
29.2
1/fs
・fs = 192 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Quad Speed mode; DEM = OFF; SD bit or SD pin = “0”, SLOW bit or SLOW pin
= “0”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
87
kHz
Frequency Response
(Note 23)
6.0 dB
96.0
kHz
Pass band
(Note 24)
PB
0
87
kHz
Stop band
(Note 24)
SB
104.9
kHz
Pass band Ripple
(Note 25)
PR
0.005
dB
Stop band Attenuation
(Note 23)
SA
100
dB
Group Delay
(Note 26)
GD
29.2
1/fs
Note 23. Frequency response refers to the output level of 1 kHz. Stopband attenuation band ranges
from SB to fs.
Note 24. The passband and stopband frequencies scale with fs.
For example, PB = 0.4535 fs (@0.01 dB), SB = 0.546 fs.
Note 25. This value is the gain amplitude in pass band width.
Note 26. The calculating delay time which occurred by digital filtering. This value is from setting the
16/20/24/32 bit data of both channels to the output of analog signal.
019001308-E-00
2019/02
- 19 -
[AK4499]
Figure 2. Sharp Roll-Off Filter Frequency Response
Figure 3. Sharp Roll-Off Filter Pass Band Ripple
019001308-E-00
2019/02
- 20 -
[AK4499]
8.2.2. Slow Roll-Off Filter Characteristics
・fs = 44.1 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Normal Speed mode; DEM = OFF; SD bit or SD pin = “0”, SLOW bit or SLOW
pin = “1”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
8.0
kHz
Frequency Response
(Note 23)
6.0 dB
21.0
kHz
Pass band
(Note 27)
PB
0
8.0
kHz
Stop band
(Note 27)
SB
39.2
kHz
Pass band Ripple
(Note 25)
PR
0.007
dB
Stop band Attenuation
(Note 23)
SA
92
dB
Group Delay
(Note 26)
GD
6.5
1/fs
・fs = 96 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Double Speed mode; DEM = OFF; SD bit or SD pin = “0”, SLOW bit or SLOW
pin = “1”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
17.6
kHz
Frequency Response
(Note 23)
6.0 dB
45.6
kHz
Pass band
(Note 27)
PB
0
17.6
kHz
Stop band
(Note 27)
SB
85.4
kHz
Pass band Ripple
(Note 25)
PR
0.007
dB
Stop band Attenuation
(Note 23)
SA
100
dB
Group Delay
(Note 26)
GD
6.5
1/fs
・fs = 192 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Quad Speed mode; DEM = OFF; SD bit or SD pin = “0”, SLOW bit or SLOW pin
= “1”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
35.2
kHz
Frequency Response
(Note 23)
6.0 dB
91.2
kHz
Pass band
(Note 27)
PB
0
35.2
kHz
Stop band
(Note 27)
SB
170.7
kHz
Pass band Ripple
(Note 25)
PR
0.007
dB
Stop band Attenuation
(Note 23)
SA
100
dB
Group Delay
(Note 26)
GD
6.5
1/fs
Note 27. The passband and stopband frequencies scale with fs.
For example, PB = 0.1836 fs (@0.01 dB), SB = 0.8889 fs.
019001308-E-00
2019/02
- 21 -
[AK4499]
Figure 4. Slow Roll-Off Filter Frequency Response
Figure 5. Slow Roll-Off Filter Pass Band Ripple
019001308-E-00
2019/02
- 22 -
[AK4499]
8.2.3. Short Delay Sharp Roll-Off Filter Characteristics
・fs = 44.1 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Normal Speed mode; DEM = OFF; SD bit or SD pin = “1”, SLOW bit or SLOW
pin = “0”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
20.0
kHz
Frequency Response
(Note 23)
6.0 dB
22.05
kHz
Pass band
(Note 28)
PB
0
20.0
kHz
Stop band
(Note 28)
SB
24.1
kHz
Pass band Ripple
(Note 25)
PR
0.005
dB
Stop band Attenuation
(Note 23)
SA
100
dB
Group Delay
(Note 26)
GD
6.0
1/fs
・fs = 96 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Double Speed mode; DEM = OFF; SD bit or SD pin = “1”, SLOW bit or SLOW
pin = “0”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
43.5
kHz
Frequency Response
(Note 23)
6.0 dB
48.0
kHz
Pass band
(Note 28)
PB
0
43.5
kHz
Stop band
(Note 28)
SB
52.5
kHz
Pass band Ripple
(Note 25)
PR
0.005
dB
Stop band Attenuation
(Note 23)
SA
100
dB
Group Delay
(Note 26)
GD
6.0
1/fs
・fs = 192 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Quad Speed mode; DEM = OFF; SD bit or SD pin = “1”, SLOW bit or SLOW pin
= “0”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
87.0
kHz
Frequency Response
(Note 23)
6.0 dB
96.0
kHz
Pass band
(Note 28)
PB
0
87.0
kHz
Stop band
(Note 28)
SB
104.9
kHz
Pass band Ripple
(Note 25)
PR
0.005
dB
Stop band Attenuation
(Note 23)
SA
100
dB
Group Delay
(Note 26)
GD
6.0
1/fs
Note 28. The passband and stopband frequencies scale with fs.
For example, PB = 0.4535 fs (@0.01 dB), SB = 0.546 fs.
019001308-E-00
2019/02
- 23 -
[AK4499]
Figure 6. Short Delay Sharp Roll-Off Filter Frequency Response
Figure 7. Short Delay Sharp Roll-Off Filter Pass Band Ripple
019001308-E-00
2019/02
- 24 -
[AK4499]
8.2.4. Short Delay Slow Roll-Off Filter Characteristics
・fs = 44.1 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Normal Speed mode; DEM = OFF; SD bit or SD pin = “1”, SLOW bit or SLOW
pin = “1”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
8.0
kHz
Frequency Response
(Note 23)
6.0 dB
21.0
kHz
Pass band
(Note 29)
PB
0
8.0
kHz
Stop band
(Note 29)
SB
39.2
kHz
Pass band Ripple
(Note 25)
PR
0.007
dB
Stop band Attenuation
(Note 23)
SA
92
dB
Group Delay
(Note 26)
GD
5.0
1/fs
・fs = 96 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Double Speed mode; DEM = OFF; SD bit or SD pin = “1”, SLOW bit or SLOW
pin = “1”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
17.6
kHz
Frequency Response
(Note 23)
6.0 dB
45.6
kHz
Pass band
(Note 29)
PB
0
17.6
kHz
Stop band
(Note 29)
SB
85.4
kHz
Pass band Ripple
(Note 25)
PR
0.007
dB
Stop band Attenuation
(Note 23)
SA
100
dB
Group Delay
(Note 26)
GD
5.0
1/fs
・fs = 192 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Quad Speed mode; DEM = OFF; SD bit or SD pin = “1”, SLOW bit or SLOW pin
= “1”, SSLOW bit or SSLOW pin = “0”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.01 dB
0
35.2
kHz
Frequency Response
(Note 23)
6.0 dB
91.2
kHz
Pass band
(Note 29)
PB
0
35.2
kHz
Stop band
(Note 29)
SB
170.7
kHz
Pass band Ripple
(Note 25)
PR
0.007
dB
Stop band Attenuation
(Note 23)
SA
100
dB
Group Delay
(Note 26)
GD
5.0
1/fs
Note 29. The passband and stopband frequencies scale with fs.
For example, PB = 0.1836 fs (@0.01dB), SB = 0.8866 fs.
019001308-E-00
2019/02
- 25 -
[AK4499]
Figure 8. Short Delay Slow Roll-Off Filter Frequency Response
Figure 9. Short Delay Slow Roll-Off Filter Passband Ripple
019001308-E-00
2019/02
- 26 -
[AK4499]
8.2.5. Low-dispersion Short Delay Filter Characteristics
・fs = 44.1 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Normal Speed mode; DEM = OFF; SD bit or SD pin = “1”, SLOW bit or SLOW
pin = “0”, SSLOW bit or SSLOW pin = “1”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.05 dB
0
18.4
kHz
Frequency Response
(Note 23)
6.0 dB
22.05
kHz
Pass band
(Note 30)
PB
0
18.4
kHz
Stop band
(Note 30)
SB
25.7
kHz
Pass band Ripple
(Note 25)
PR
0.05
dB
Stop band Attenuation
(Note 23)
SA
80
dB
Group Delay
(Note 26)
GD
10.0
1/fs
Group Delay Distortion
ΔGD
±0.035
1/fs
・fs = 96 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Double Speed mode; DEM = OFF; SD bit or SD pin = “1”, SLOW bit or SLOW
pin = “0”, SSLOW bit or SSLOW pin = “1”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.05 dB
0
40.1
kHz
Frequency Response
(Note 23)
6.0 dB
48.0
kHz
Pass band
(Note 30)
PB
0
40.1
kHz
Stop band
(Note 30)
SB
55.9
kHz
Pass band Ripple
(Note 25)
PR
0.05
dB
Stop band Attenuation
(Note 23)
SA
80
dB
Group Delay
(Note 26)
GD
10.0
1/fs
Group Delay Distortion
ΔGD
±0.035
1/fs
・fs = 192 kHz
(Ta = -40 to 85C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; Quad Speed mode; DEM = OFF; SD bit or SD pin = “1”, SLOW bit or SLOW pin
= “0”, SSLOW bit or SSLOW pin = “1”)
Parameter
Symbol
Unit
Min.
Typ.
Max.
Digital Filter
0.05 dB
0
80.2
kHz
Frequency Response
(Note 23)
6.0 dB
96.0
kHz
Pass band
(Note 30)
PB
0
80.2
kHz
Stop band
(Note 30)
SB
111.8
kHz
Pass band Ripple
(Note 25)
PR
0.05
dB
Stop band Attenuation
(Note 23)
SA
80
dB
Group Delay
(Note 26)
GD
10.0
1/fs
Group Delay Distortion
ΔGD
±0.035
1/fs
Note 30. The passband and stopband frequencies scale with fs.
For example, PB = 0.418 fs (@0.05 dB), SB = 0.582 fs.
019001308-E-00
2019/02
- 27 -
[AK4499]
Figure 10. Low Dispersion Short Delay Filter Frequency Response
Figure 11. Low Dispersion Short Delay Filter Passband Ripple
019001308-E-00
2019/02
- 28 -
[AK4499]
8.3. DAC Digital-Filter Characteristics (DSD Mode)
(Ta = -40 to 85 C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; fs = 44.1 kHz; DSDSEL[1:0] bits = “00”)
(1) DSD64
Parameter
Digital Filter Response
DSDF=”0”
Cut off frequency; 37kHz
DSDF=”1”
Cut off frequency; 65kHz
(Note 31)
20 kHz
50 kHz
100 kHz
20 kHz
100 kHz
150 kHz
(2) DSD128 (128fs frequency tracks from 64fs.)
Parameter
Digital Filter Response
(Note 31)
DSDF=”0”
40 kHz
Cut off frequency; 74kHz
100 kHz
200 kHz
DSDF=”1”
40 kHz
Cut off frequency; 131kHz
200 kHz
300 kHz
(3) DSD256
Parameter
Digital Filter Response
DSD filter
Cut off frequency; 238kHz
(Note 31)
80 kHz
200 kHz
400 kHz
Min.
Typ.
Max.
Unit
-
-0.8
-5.8
-21.1
-0.3
-7.6
-21.4
-
dB
dB
dB
dB
dB
dB
Min.
Typ.
Max.
Unit
-
-0.8
-5.8
-21.1
-0.3
-7.6
-21.4
-
dB
dB
dB
dB
dB
dB
Min.
Typ.
Max.
Unit
-
-0.3
-2.1
-9.3
-
dB
dB
dB
(4) DSD512 (512fs frequency tracks from 256fs)
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response
(Note 31)
DSD filter
160 kHz
-0.3
dB
Cut off frequency; 476kHz
400 kHz
-2.1
dB
800 kHz
-9.3
dB
Note 31. The output level is assumed as 0dB when a 1kHz 25% to 75% duty sine wave is input. Click
noise may occur if the input signal exceeds 0dB.
019001308-E-00
2019/02
- 29 -
[AK4499]
8.4. DC Characteristics
(Ta = -40 to 85 C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V; unless otherwise specified.)
Parameter
Symbol
Min.
Typ.
Max.
Unit
MCLK pin (VTSEL pin = “L”)
High-Level Input Voltage
VIH
1.36
V
Low-Level Input Voltage
VIL
0.34
V
MCLK pin (VTSEL pin = “H”)
High-Level Input Voltage
VIH
2.2
V
Low-Level Input Voltage
VIL
0.8
V
1.7 V TVDD < 3.0 V (except MCLK pin)
VIH
80%TVDD
V
High-Level Input Voltage
VIL
20%TVDD
V
Low-Level Input Voltage
3.0 V TVDD 3.6 V (except MCLK pin)
VIH
70%TVDD
V
High-Level Input Voltage
VIL
30%TVDD
V
Low-Level Input Voltage
High-Level Output Voltage
(TDMO, DZFL, DZFR pins: Iout = -100 µA)
VOH
V
TVDD0.3
Low-Level Output Voltage
(except SDA pin: Iout = 100 µA)
VOL
0.3
V
(SDA pin, 2.0 V < TVDD 3.6 V: Iout = 3 mA)
VOL
0.4
V
VOL
20%TVDD
V
(SDA pin, 1.7 V TVDD 2.0 V: Iout = 3 mA)
Input Leakage Current
(Note 32)
Iin
10
A
Note 32. The TEST, TDMO, DIF0, and DIF1 pin have internal pull-down and the PSN pin has internal
pull-up resistors. The resistance is 100 kΩ (typ). Therefore, the TEST, TDMO, DIF0, DIF1, and
PSN pins are not included in this specification.
019001308-E-00
2019/02
- 30 -
[AK4499]
8.5. Switching Characteristics
(Ta = -40 to 85 C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V, CL = 20 pF, AFSD bit = “0”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing
(Note 33)
Frequency
fCLK
2.048
MHz
49.152
Duty Cycle
dCLK
40
60
%
Pulse Width
tCLKH
9.155
ns
tCLKL
9.155
ns
LRCK Clock Timing
Normal Mode (TDM[1:0] bits/pins = 00)
Normal Speed mode
fsn
8
54
kHz
Double Speed mode
fsd
54
108
kHz
Quad Speed mode
fsq
108
216
kHz
Oct Speed mode
fso
216
388
kHz
Hex Speed mode
fsh
388
776
kHz
Duty Cycle
Duty
45
55
%
TDM128 Mode (TDM[1:0] bits/pins = 01)
Normal Speed mode
fsn
8
54
kHz
Double Speed mode
fsd
54
108
kHz
Quad Speed mode
fsq
108
216
kHz
High time
tLRH
1/128fs
ns
Low time
tLRL
1/128fs
ns
TDM256 Mode (TDM[1:0] bits/pins = 10)
Normal Speed mode High time
fsn
8
54
kHz
Double Speed mode
fsd
54
108
kHz
High time
tLRH
1/256fs
ns
Low time
tLRL
1/256fs
ns
TDM512 Mode (TDM[1:0] bits/pins = 11)
Normal Speed mode
fsn
8
54
kHz
High time
tLRH
1/512fs
ns
Low time
tLRL
1/512fs
ns
Note 33. The MCLK frequency should be changed while the AK4499 is in reset state by setting the PDN
pin = “L” or RSTN bit = “0”.
019001308-E-00
2019/02
- 31 -
[AK4499]
(Ta = -40 to 85 C; VDDL1/R1/L2/R2 = 4.75 to 5.25 V, AVDD = 4.75 to 5.25 V, TVDD = 1.7 to 3.6 V,
DVDD = 1.7 to 1.98 V, CL = 20 pF, AFSD bit = “1”)
Parameter (fs auto detect mode, Note 34) Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing
Frequency
fCLK
7.68
MHz
49.152
Duty Cycle
dCLK
40
60
%
Pulse Width
tCLKH
9.155
ns
tCLKL
9.155
ns
LRCK Clock Timing
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed mode
fsn
30
54
kHz
Double Speed mode
fsd
87
108
kHz
Quad Speed mode
fsq
174
216
kHz
Oct Speed mode
fso
348
388
kHz
Hex Speed mode
fsh
696
776
kHz
Duty Cycle
Duty
45
55
%
TDM128 Mode (TDM[1:0] bits = “01”)
Normal Speed mode
fsn
30
54
kHz
Double Speed mode
fsd
87
108
kHz
Quad Speed mode
fsq
174
216
kHz
High time
tLRH
1/128fs
ns
Low time
tLRL
1/128fs
ns
TDM256 Mode (TDM[1:0] bits = “10”)
Normal Speed mode High time
fsn
30
54
kHz
Double Speed mode
fsd
87
108
kHz
High time
tLRH
1/256fs
ns
Low time
tLRL
1/256fs
ns
TDM512 Mode (TDM[1:0] bits = “11”)
Normal Speed mode
fsn
30
54
kHz
High time
tLRH
1/512fs
ns
Low time
tLRL
1/512fs
ns
Note 34. In fs Auto Detection mode (AFSD bit = “1”), normal operation is not guaranteed if a clock of a
frequency other than the above is input to the MCLK pin and the LRCK pin.
019001308-E-00
2019/02
- 32 -
[AK4499]
Parameter
Symbol
Min.
Typ.
Max.
Unit
PCM Audio Interface Timing
Normal Mode (TDM[1:0] bits/pins = “00”)
BICK Period
Normal Speed mode
tBCK
1/256fsn
ns
tBCK
Double Speed mode
1/128fsd
ns
Quad Speed mode
tBCK
1/64fsq
ns
tBCK
ns
Oct Speed mode
1/64fso
Hex Speed mode
tBCK
1/64fsh
ns
ns
BICK Pulse Width Low
tBCKL
9
BICK Pulse Width High
tBCKH
9
ns
ns
tBLR
5
BICK “” to LRCK Edge
(Note 35)
ns
tLRB
5
LRCK Edge to BICK “”
(Note 35)
ns
SDATA1/2 Hold Time
tSDH
5
SDATA1/2 Setup Time
tSDS
5
ns
TDM128 Mode (TDM[1:0] bits/pins = “01”)
BICK Period
tBCK
1/128fsn
ns
Normal Speed mode
Double Speed mode
tBCK
1/128fsd
ns
tBCK
1/128fsq
ns
Quad Speed mode
14
ns
BICK Pulse Width Low
tBCKL
BICK Pulse Width High
tBCKH
14
ns
14
ns
tBLR
BICK “” to LRCK Edge
(Note 35)
14
ns
tLRB
LRCK Edge to BICK “”
(Note 35)
5
ns
SDATA1/2 Hold Time
tSDH
5
ns
SDATA1/2 Setup Time
tSDS
TDM256 Mode (TDM[1:0] bits/pins =
“10”)
BICK Period
Normal Speed mode
tBCK
1/256fsn
ns
Double Speed mode
tBCK
1/256fsd
ns
BICK Pulse Width Low
tBCKL
14
ns
BICK Pulse Width High
tBCKH
14
ns
tBLR
14
ns
BICK “” to LRCK Edge
(Note 35)
tLRB
14
ns
LRCK Edge to BICK “”
(Note 35)
tBSS
5
ns
TDMO Setup time BICK “”
tBSH
5
ns
TDMO Hold time BICK “”
tSDH
5
ns
SDATA1/2 Hold Time
tSDS
5
ns
SDATA1/2 Setup Time
TDM512 Mode (TDM[1:0] bits/pins = “11”)
BICK Period
Normal Speed mode
tBCK
1/512fsn
ns
BICK Pulse Width Low
tBCKL
14
ns
BICK Pulse Width High
tBCKH
14
ns
tBLR
14
ns
BICK “” to LRCK Edge
(Note 35)
tLRB
14
ns
LRCK Edge to BICK “”
(Note 35)
tBSS
5
ns
TDMO Setup time BICK “”
tBSH
5
ns
TDMO Hold time BICK “”
SDATA Hold Time
tSDH
5
ns
SDATA Setup Time
5
ns
tSDS
Note 35. It is defined so that LRCK edges do not occur at the same timing of a rising edge of BICK.
019001308-E-00
2019/02
- 33 -
[AK4499]
Parameter
PCM Audio Interface Timing
External Digital Filter Mode
BCK Period
BCK Pulse Width Low
BCK Pulse Width High
BCK “” to WCK Edge
WCK Period
WCK Edge to BCK “”
WCK Pulse Width Low
WCK Pulse Width High
DINL/R Hold Time
DINL/R Setup Time
BCK Period
Symbol
Min.
Typ.
Max.
Unit
tB
tBL
tBH
tBW
tWCK
tWB
tWCKL
tWCKH
tDH
tDS
tB
27
10
10
5
1.3
5
54
54
5
5
27
-
-
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
Parameter
Symbol
Min.
Typ.
Max.
Unit
DSD Audio Interface Timing
Sampling Frequency
fs
30
44.1
48
kHz
(DSD64 Mode, DSDSEL[1:0] bits= “00”)
DCLK Period
tDCK
1/64fs
ns
DCLK Pulse Width Low
tDCKL
144
ns
DCLK Pulse Width High
tDCKH
144
ns
DCLK Edge to DSDL/R
(Note 36)
tDDD
20
ns
20
(DSD128 Mode, DSDSEL[1:0] bits = “01”)
DCLK Period
tDCK
1/128fs
ns
DCLK Pulse Width Low
tDCKL
72
ns
DCLK Pulse Width High
tDCKH
72
ns
DCLK Edge to DSDL/R
(Note 36)
tDDD
10
ns
10
(DSD256 Mode, DSDSEL[1:0] bits = “10”)
DCLK Period
tDCK
1/256fs
ns
DCLK Pulse Width Low
tDCKL
36
ns
DCLK Pulse Width High
tDCKH
36
ns
DCLK Edge to DSDL/R
(Note 36)
tDDD
5
ns
5
(DSD512 Mode, DSDSEL[1:0] bits = “11”)
DCLK Period
tDCK
1/512fs
ns
DCLK Pulse Width Low
tDCKL
18
ns
DCLK Pulse Width High
tDCKH
18
ns
DSDL/R Setup Time
tDDS
5
ns
DSDL/R Hold Time
tDDH
5
ns
Note 36. DSD data transmitting device must meet this time. “tDDD” is defined from DCLK “↓” until
DSDL/R edge when DCKB bit = “0” (default), “tDDD” is defined from DCLK “↑” until DSDL/R
edge when DCKB bit = “1”. If the audio data format is in phase modulation mode, “tDDD” is
defined from DCLK edge “↓” or “↑” until DSDL/R edge regardless of DCKB bit setting.
019001308-E-00
2019/02
- 34 -
[AK4499]
Parameter
Symbol
Min. Typ.
Control Interface Timing (3-wire Serial Control Mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
tCSS
50
CSN “” to CCLK “”
tCSH
50
CCLK “” to CSN “”
Control Interface Timing (I2C-Bus Control Mode):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
(Note 37)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Capacitive load on bus
Cb
Power-down & Reset Timing
PDN Accept Pulse Width
tAPD
600
PDN Reject Pulse Width
tRPD
Note 37. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 38. I2C -bus is a trademark of NXP B.V.
019001308-E-00
Max.
Unit
-
ns
ns
ns
ns
ns
ns
ns
ns
400
0.3
0.3
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
30
ns
ns
2019/02
- 35 -
[AK4499]
8.6. Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK = tCLKH x fCLK x 100,
tCLKL x fCLK x 100
1/fs
VIH
VIL
LRCK
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
tWCK
VIH
WCK
VIL
tWCKH
tWCKL
tB
VIH
BCK
VIL
tBH
tBL
Figure 12. Clock Timing
019001308-E-00
2019/02
- 36 -
[AK4499]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSH
tBSS
TDMO
50%TVDD
tSDS
tSDH
VIH
SDATA1/2
VIL
Figure 13. Audio Interface Timing (PCM Mode)
VIH
WCK
VIL
tBW
tWB
VIH
BCK
VIL
tDS
tDH
VIH
DINL1/2
DINR1/2
VIL
Figure 14. Audio Interface Timing (External Digital Filter I/F Mode)
019001308-E-00
2019/02
- 37 -
[AK4499]
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL1/2
DSDR1/2
VIL
tDDD
VIH
DSDL1/2
DSDR1/2
VIL
DSD Audio Interface Timing (DSD64/128/256 Mode)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDS
tDDH
VIH
DSDL1/2
DSDR1/2
VIL
DSD Audio Interface Timing (DSD512 Mode)
Figure 15. Audio Interface Timing (DSD Mode, DCKB bit = “0”)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL1/2
DSDR1/2
VIL
tDDD
tDDD
VIH
DSDL1/2
DSDR1/2
VIL
Figure 16. Audio Interface Timing (DSD Mode, Phase Modulation Format, DCKB bit = “0”)
019001308-E-00
2019/02
- 38 -
[AK4499]
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
A4
VIH
VIL
Figure 17. WRITE Command Input Timing (3-wire Serial Control Mode)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
Figure 18. WRITE Data Input Timing (3-wire Serial Control Mode)
019001308-E-00
2019/02
- 39 -
[AK4499]
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 19. I2C Bus Control Mode Timing
tAPD
tRPD
VIH
PDN
VIL
Figure 20. Power Down & Reset Timing
019001308-E-00
2019/02
- 40 -
[AK4499]
9.
Functional Descriptions
9.1. Control Mode
Each function of the AK4499 is controlled by pins (Pin Control mode) or registers (Register Control
mode) (Table 1). Select the control mode by setting the PSN pin. The AK4499 must be powered down
by the PDN pin when changing the PSN pin setting. There is a possibility of malfunction if the device is
not powered down when changing the control mode since the previous setting is not reinitialized.
Register settings are invalid in Pin Control mode, and pin settings are invalid in Register Control mode.
Table 2 shows available functions of each control mode.
Table 1. Pin/Register Control Mode Select
PSN pin
Control Mode
L
Register Control mode
H
Pin Control mode
Table 2. Function List @Pin/Register Control Mode
(Y: Available, N/A: Not available)
Pin Control
Register Control
Function
Mode
Mode
DSD Mode Select
N/A
Y
EXDF Mode Select
N/A
Y
System Clock Setting Select
Y
Y
Audio Format Select
Y
Y
TDM Mode
Y
Y
Daisy Chain
Y
Y
Digital Filter Select
Y
Y
De-emphasis Filter Select
Y
Y
Digital Attenuator
N/A
Y
Zero Detection
N/A
Y
Mono Mode
N/A
Y
Output signal select
N/A
Y
(Mono, Channel select)
Output signal polarity select
Y
Y
(Invert)
DSD Full Scale Detect
N/A
Y
Soft Mute
Y
Y
Register Reset
N/A
Y
Clock Synchronization Function
N/A
Y
disable (default: enable)
Automatic Mode Switching
N/A
Y
(PCM/DSD, EXDF/DSD)
Register Control
N/A
Y
Gain Control
N/A
Y
019001308-E-00
2019/02
- 41 -
[AK4499]
9.2. D/A Conversion Mode
The AK4499 is able to convert either PCM or DSD data to an analog signal. D/A conversion mode is in
common for DAC1 and DAC2. In PCM mode, clocks and PCM data can be input from the BICK, LRCK
and SDTI1/2 pins. In DSD mode, clocks and DSD data can be input from the DCLK, DSDL1/2 and
DSDR1/2 pins.
The AK4499 supports external Digital Filter I/F (EXDF) in PCM data input mode. In EXDF mode, clocks
and PCM data can be input from the MCLK, BCK, WCK, DINL1/2 and DINR1/2 pins. Table 3 shows
available functions in PCM/DSD/EXDF mode.
The AK4499 only supports PCM mode in pin control mode.
Table 3. Function List of PCM/EXDF/DSD Mode @Register Control Mode
(Y: Available, N/A: Not available)
Function
Default State
Addr
Bit
PCM EXDF
Automatic Mode Switching
Disable
15H
ADPE
Y
Y
(PCM/DSD, EXDF/DSD)
System clock setting
512fs
02H
DCKS
N/A
N/A
@DSD mode
System clock setting
16fs (fs = 44.1
00H
ECS
N/A
Y
@EXDF mode
kHz)
Digital Filter select
N/A
N/A
39 kHz filter
09H
DSDF
@DSD mode
Short Delay
SD
01H,
Digital Filter select
N/A
Sharp Roll-off
SLOW
Y
@PCM mode
02H, 05H
filter
SSLOW
01H
DEM1[1:0]
N/A
De-emphasis Response
OFF
Y
0AH
DEM2[1:0]
N/A
N/A
Path select @ DSD mode
Normal Path
06H
DSDD
Audio Data Interface Format
N/A
32-bit MSB
00H
DIF[2:0]
Y
@ PCM mode
Audio Data Interface Format
32-bit LSB
00H
DIF[2:0]
N/A
Y
@ EXDF mode
TDM Interface Format
Normal Mode
0AH
TDM[1:0]
Y
N/A
Daisy Chain
Disable
0BH
DCHAIN
Y
N/A
03-04H
ATTL1/2[7:0]
Attenuation Level
0 dB
Y
Y
0C-0DH
ATTR1/2[7:0]
Data Zero Detect Enable
Disable
01H
DZFE
Y
Y
Inverting Enable of DZF
“H” active
02H
DZFB
Y
Y
02H,
Mono/Stereo mode select
Stereo
MONO1/2
Y
Y
0BH
INVL1/2
Data Invert mode select
OFF
05H
Y
Y
INVR1/2
The data selection of L
L/R channel
02H-05H
SELLR1/2
Y
Y
channel and R channel
DSD Mute Function @ FullDisable
06H
DDM
N/A
N/A
scale Detected
Normal
Soft Mute Enable
01H
SMUTE
Y
Y
Operation
RSTN
Reset
00H
RSTN
Y
Y
Clock Synchronization
Enable
07H
SYNCE
Y
Y
Function
019001308-E-00
DSD
Y
Y
N/A
Y
N/A
N/A
Y
N/A
N/A
N/A
N/A
Y
Y
Y
Y
Y
Y
Y
Y
Y
N/A
2019/02
- 42 -
[AK4499]
9.2.1. D/A Conversion Mode Setting and Pin Assignment
Switching PCM/DSD/EXDF mode is executed by setting DP bit and EXDF bit. In DSD mode, the input
clock and the data input pin can be changed by DSDPATH bit. Register settings and pin assignment for
each mode are shown below.
・PCM Mode
The AK4499 enters PCM mode by setting DP bit = “0” and EXDF bit = ”0”. Clock and data are input to
the #43, #44, #45 and #46 pins in PCM mode (Table 4).
・DSD Mode
The AK4499 enters DSD mode by setting DP bit = “1”. In this case, EXDF bit setting will not be reflected
on the circuit operation. In DSD mode, clock and data are input to the #50, #51, #52, #53 and #54 pins
if DSDPATH bit = “0”, and are input to the #43, #44, #45, #46 and #47 pins if DSDPATH bit = “1” (Table
4).
・EXDF Mode
The AK4499 enters EXDF mode by setting DP bit = “0” and EXDF bit = “1”. Clock and data are input to
the #43, #44, #45, #46 and #47 pins in EXDF mode (Table 4).
Table 4. PCM/DSD/EXDF Mode Control and Pin Assign (×: Do Not Care)
Pin Assign
#47
#48
pin
pin
#50
pin
#51
pin
#52
pin
#53
pin
#54
pin
SDATA2
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
DINR1
DINL2
DINR2
WCK
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
DSD
L1
DSD
R1
DCLK
DSD
L2
DSD
R2
DSDL1
DSDR1
DSDL2
DSDR2
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
DP
bit
EXDF
bit
DSD
PATH
bit
D/A
Conv.
Mode
#43
pin
#44
pin
#45
pin
#46
pin
0
0
×
PCM
BICK
SDATA1
LRCK
0
1
×
EXDF
BCK
DINL1
Not
Used
DCLK
0
1
×
DSD
1
The AK4499 must be in reset state by setting RSTN bit = “0” when switching the data input mode
(PCM/DSD/EXDF) by DP bit and EXDF bit or when changing DSD signal input path by DSDPATH bit.
RSTN bit should not be changed for 4/fs after switching these modes. It takes 2 to 3/fs for mode
transition.
Switching to DSD mode, manual and automatic settings are selectable. The AK4499 is in manual
setting mode when ADPE bit = “0” and it is in automatic setting mode when ADPE bit = “1”. In automatic
setting mode, the AK4499 monitors input signals to select PCM or DSD mode if EXDF bit = “0”, and it
monitors input signals to select EXDF or DSD mode if EXDF bit = “1”. DP bit setting is ignored in this
mode (ADPE bit = “1”). Refer to “9.11. PCM/DSD, EXDF/DSD Automatic Mode Switching Function” for
details.
019001308-E-00
2019/02
- 43 -
[AK4499]
9.2.2. D/A Conversion Mode Switching Timing (Manual Setting)
Figure 21, Figure 22 and Figure 23 show switching timing of PCM, DSD and EXDF modes in manual
mode (ADPE bit = “0”). To prevent noise caused by excessive input, DSD signal should be input 4/fs
after setting RSTN bit = “0” until the device is completely reset internally when the conversion mode is
changed to DSD mode from PCM/EXDF mode. DSD signal should be stopped 4/fs after setting RSTN
bit = “0” until the device is completely reset internally when the conversion mode is changed to
PCM/EXDF from DSD mode.
RSTN bit
4/fs
D/A Mode
PCM or EXDF Mode
DSD Mode
0
D/A Data
PCM or EXDF Data
DSD Data
“L”
Figure 21. D/A Mode Switching Timing (from PCM/EXDF Mode to DSD Mode)
RSTN bit
3/fs
D/A Mode
DSD Mode
PCM or EXDF Mode
4/fs
D/A Data
DSD Data
PCM Data
“L”
Figure 22. D/A Mode Switching Timing (from DSD Mode to PCM/EXDF Mode)
Figure 23 shows switching timing of PCM and EXDF modes. Set EXDF bit 4/fs after setting RSTN bit =
“0” until the device is completely reset internally when changing the conversion mode.
RSTN bit
4/fs
D/A Mode
D/A Data
PCM or EXDF Mode
PCM or EXDF Data
3/fs
PCM or EXDF Mode
“L”
PCM or EXDF Data
Figure 23. D/A Mode Switching Timing (from PCM Mode to EXDF Mode)
019001308-E-00
2019/02
- 44 -
[AK4499]
9.3. System Clock
9.3.1. PCM Mode
The external clocks, which are required to operate the AK4499, are MCLK, BICK and LRCK. MCLK,
BICK and LRCK should be synchronized but the phase of MCLK is not critical. MCLK is used to operate
the digital filter, the delta sigma modulator and SR DAC.
For the internal sampling speed mode and MCLK-to-LRCK divider setting, there are two system clock
setting modes in pin control mode and there are three setting modes in register control mode (Table 5,
Table 6).
Table 5. System Clock Setting Mode @Pin Control Mode
ACKS pin
Mode
0
Fixed Speed mode
(default)
1
Auto Setting mode
Table 6. System Clock Setting Mode @Register Control Mode (×: Do not care)
AFSD bit
ACKS bit
Mode
0
0
Manual Setting mode
(default)
0
1
Auto Setting mode
1
×
fs Auto Detect mode
The AK4499 is automatically placed in standby state when MCLK is stopped for more than 1 μs during
normal operation, and the analog output becomes Hi-z state (Table 47).
When MCLK is input again, the AK4499 exits this power down state and starts operation again. In this
case, register settings are not initialized. The AK4499 is in power down state and the analog output is
floating state (Hi-z) until MCLK, BICK and LRCK are supplied.
9.3.1.1. Fixed Speed Mode (Pin Control Mode)
The AK4499 will be in fixed speed mode by setting ACKS pin = “L” in pin control mode. In this mode,
the sampling speed is fixed to normal speed mode. The MCLK frequency corresponding to each
sampling speed should be provided externally (Table 7).
Table 7. System Clock Example (Fixed Speed Mode) (N/A: Not available)
LRCK
fs
32.0 kHz
44.1 kHz
48.0 kHz
128fs
N/A
N/A
N/A
192fs
N/A
N/A
N/A
256fs
8.1920
11.2896
12.2880
MCLK (MHz)
384fs
512fs
12.2880 16.3840
16.9344 22.5792
18.4320 24.5760
019001308-E-00
768fs
24.5760
33.8688
36.8640
1024fs
32.7680
N/A
N/A
1152fs
36.8640
N/A
N/A
BICK
64fs
2.0480 MHz
2.8224 MHz
3.0720 MHz
Sampling
Speed
Normal
2019/02
- 45 -
[AK4499]
9.3.1.2. Manual Setting Mode (Register Control Mode Only)
The AK4499 will be in manual setting mode by setting AFSD bit = “0” and ACKS bit = “0” in register
control mode. In manual setting mode, sampling speed is set by DFS[2:0] bits (Table 8). The MCLK
frequency corresponding to each sampling speed should be provided externally (Table 9, Table 10). The
AK4499 is in manual setting mode when power down is released (PDN pin = “L” → “H”). After changing
the sampling speed by DFS[2:0] bits, reset the AK4499 once by setting RSTN bit. This function is only
supported in register control mode.
Table 8. Sampling Speed (Manual Setting Mode)
DFS[2:0] bits
Sampling Speed
Sampling Rate (fs)
000
Normal Speed mode
7.2 kHz 54 kHz
001
Double Speed mode
54 kHz 108 kHz
010
Quad Speed mode
108 kHz 216 kHz
011
Quad Speed mode
108 kHz 216 kHz
100
Oct Speed mode
216 kHz 388 kHz
101
Hex Speed mode
388 kHz 776 kHz
110
Oct Speed mode
216 kHz 388 kHz
111
Hex Speed mode
388 kHz 776 kHz
(default)
Table 9. System Clock Example (Manual Setting Mode) (N/A: Not available)
LRCK
MCLK(MHz)
Sampling
Speed
fs
16fs
32fs
48fs
64fs
96fs
128fs
32.0 kHz
N/A
N/A
N/A
N/A
N/A
N/A
44.1 kHz
N/A
N/A
N/A
N/A
N/A
N/A
Normal
48.0 kHz
N/A
N/A
N/A
N/A
N/A
N/A
88.2 kHz
N/A
N/A
N/A
N/A
N/A
N/A
Double
96.0 kHz
N/A
N/A
N/A
N/A
N/A
N/A
176.4 kHz
N/A
N/A
N/A
N/A
N/A
22.5792
Quad
192.0 kHz
N/A
N/A
N/A
N/A
N/A
24.5760
352.8 kHz
N/A
11.2896 16.9344 22.5792 33.8688
N/A
Oct
384 kHz
N/A
12.2880 18.4320 24.5760 36.8640
N/A
705.6 kHz 11.2896 22.5792 33.8688 45.1584
N/A
N/A
Hex
768 kHz
12.2880 24.5760 36.8640 49.1520
N/A
N/A
LRCK
fs
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz
192.0 kHz
352.8 kHz
384 kHz
705.6 kHz
768 kHz
Table 10. System Clock Example (Manual Setting Mode) (N/A: Not available)
MCLK(MHz)
192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
N/A
8.1920 12.2880 16.3840 24.5760 32.7680 36.8640
N/A
11.2896 16.9344 22.5792 33.8688
N/A
N/A
N/A
12.2880 18.4320 24.5760 36.8640
N/A
N/A
N/A
22.5792 33.8688 45.1584
N/A
N/A
N/A
N/A
24.5760 36.8640 49.1520
N/A
N/A
N/A
33.8688 45.1584
N/A
N/A
N/A
N/A
N/A
36.8640 49.1520
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
019001308-E-00
Sampling
Speed
Normal
Double
Quad
Oct
Hex
2019/02
- 46 -
[AK4499]
9.3.1.3. Auto Setting Mode
The AK4499 will be in auto setting mode by setting ACKS pin = “H” in pin control mode, or AFSD bit =
“0” and ACKS bit = “1” in register control mode. In auto setting mode, the MCLK and LRCK frequency
ratio is detected to automatically set the sampling speed mode (Table 11). Therefore, sampling speed
setting is not necessary. The frequencies of MCLK corresponding to each sampling speed mode should
be input externally (Table 12, Table 13).
Table 11. Sampling Speed (Auto Setting Mode)
MCLK
Sampling Speed
Normal (fs 32
1024fs/1152fs
kHz)
512fs/256fs (*) 768fs/384fs (*)
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
16fs/32fs
48fs
Hex
LRCK
fs
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz
192.0 kHz
352.8 kHz
384.0 kHz
705.6 kHz
768.0 kHz
Table 12. System Clock Example (Auto Setting Mode) (N/A: Not available)
MCLK (MHz)
32fs
48fs
64fs
96fs
128fs
192fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
N/A
LRCK
fs
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz
192.0 kHz
352.8 kHz
384.0 kHz
705.6 kHz
768.0 kHz
Table 13. System Clock Example (Auto Setting Mode) (N/A: Not available)
MCLK (MHz)
256fs
384fs
512fs
768fs
1024fs
1152fs
8.1920(*) 12.2880(*) 16.3840
24.5760
32.7680
36.8640
11.2896(*) 16.9344(*) 22.5792
33.8688
N/A
N/A
12.2880(*) 18.4320(*) 24.5760
36.8640
N/A
N/A
22.5792
33.8688
N/A
N/A
N/A
N/A
24.5760
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Sampling
Speed
Normal
Double
Quad
Oct
Hex
Sampling
Speed
Normal
Double
Quad
Oct
Hex
(*) When MCLK = 256fs/384fs, auto setting mode supports sampling rates of 8kHz to 96kHz. However,
the oversampling ratio is adjusted from 128 to 64 resulting in ~3dB SNR loss and increased out-ofband noise for sampling rates under 54 kHz.
019001308-E-00
2019/02
- 47 -
[AK4499]
9.3.1.4. fs Auto Detect Mode (Register Control Mode Only)
The AK4499 will be in fs auto setting mode by setting AFSD bit = “1” in register control mode. In fs auto
setting mode, the MCLK and LRCK frequency ratio is detected to set the sampling speed mode
automatically. Therefore, sampling speed setting is not necessary. The frequencies of MCLK
corresponding to each sampling speed mode should be input externally (Table 14, Table 15).
It takes 8/fs to 9/fs for mode transition after setting AFSD bit = “1”.
LRCK
fs
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz
192.0 kHz
352.8 kHz
384 kHz
705.6 kHz
768 kHz
LRCK
fs
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz
192.0 kHz
352.8 kHz
384 kHz
705.6 kHz
768 kHz
Table 14. System Clock Example (N/A: Not available)
MCLK (MHz)
16fs
32fs
48fs
64fs
96fs
128fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
22.5792
N/A
N/A
N/A
N/A
N/A
24.5760
N/A
11.2896 16.9344 22.5792 33.8688
N/A
N/A
12.2880 18.4320 24.5760 36.8640
N/A
11.2896 22.5792 33.8688 45.1584
N/A
N/A
12.2880 24.5760 36.8640 49.1520
N/A
N/A
Sampling
Speed
Normal
Double
Quad
Table 15. System Clock Example (N/A: Not available)
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
N/A
8.1920 12.2880 16.3840 24.5760 32.7680 36.8640
N/A
11.2896 16.9344 22.5792 33.8688
N/A
N/A
N/A
12.2880 18.4320 24.5760 36.8640
N/A
N/A
N/A
22.5792 33.8688 45.1584
N/A
N/A
N/A
N/A
24.5760 36.8640 49.1520
N/A
N/A
N/A
33.8688 45.1584
N/A
N/A
N/A
N/A
N/A
36.8640 49.1520
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
Hex
Sampling
Speed
Normal
Double
Quad
Oct
Hex
In fs auto detect mode, auto detection result of the sampling speed can be read out by ADFS[2:0] bits
(Table 16).
Table 16. Relationship between ADFS[2:0] bits and Sampling Speed
ADFS[2:0] bits Read Result
Mode
000
Normal Speed mode
001
Double Speed mode
010
Quad Speed mode
011
Quad Speed mode
100
Oct Speed mode
101
Hex Speed mode
110
Oct Speed mode
111
Hex Speed mode
019001308-E-00
2019/02
- 48 -
[AK4499]
9.3.2. DSD Mode (Register Control Mode Only)
The external clocks that are required in DSD mode are MCLK and DCLK. MCLK should be
synchronized with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit (Table
17). The AK4499 is automatically placed in standby state when MCLK is stopped during normal
operation (PDN pin = “H”), and the analog output becomes Hi-z state. When the reset is released (PDN
bit = “0” → “1”), the AK4499 is in power-down state until MCLK and DCLK are input.
Table 17. System Clock (DSD Mode, fs = 32 kHz, 44.1 kHz, 48 kHz)
DCKS bit MCLK Frequency
DCLK Frequency
0
512fs
64fs/128fs/256fs/512fs (default)
1
768fs
64fs/128fs/256fs/512fs
The AK4499 supports DSD data stream rates of DSD64, DSD128, DSD256 and DSD512 modes. The
data sampling speed is selected by DSDSEL[1:0] bits (Table 18).
Table 18.
DSD data
stream select
DSDSEL[1:0]
bits
00
01
10
11
DSD data stream
DSD Mode
DCLK
Frequency
fs = 32 kHz
fs = 44.1 kHz
fs = 48 kHz
DSD64
DSD128
DSD256
DSD512
64fs
128fs
256fs
512fs
2.048 MHz
4.096 MHz
8.192 MHz
16.284 MHz
2.8224 MHz
5.6448 MHz
11.2896 MHz
22.5792 MHz
3.072MHz
6.144MHz
12.288MHz
24.576MHz
(default)
The AK4499 has a Volume bypass function for play backing DSD signal. Two modes are selectable by
DSDD bit (Table 19). When setting DSDD bit = “1”, the output volume control and zero detect functions
are not available.
Table 19. DSD Play Back Path Selection
DSDD
Mode
0
Normal Path
(default)
1
Volume Bypass
019001308-E-00
2019/02
- 49 -
[AK4499]
9.3.3. External Digital Filter Mode (EXDF Mode, Register Control Mode Only)
The external clocks that are required in EXDF mode are MCLK, BCK and WCK. The BCK and MCLK
clocks must be the same frequency and continuous, not burst mode. BCK and MCLK frequencies for
each sampling speed are shown in Table 20. Set ECS bit according to Table 20.
The AK4499 is automatically placed in standby state when an MCLK edge is not detected during
normal operation, and the analog output becomes Hi-Z state. When the reset is released (RSTN bit =
“0” → “1”), the AK4499 is in standby state until MCLK, BCK and WCK are input.
Table 20. System Clock Example (EXDF Mode) N/A: Not available
MCLK&BCK (MHz)
Sampling
ECS bit
Speed[kHz]
32fs
48fs
64fs
96fs
352.8 kHz
1
11.2896
16.9344
22.5792
33.8688
384 kHz
1
12.288
18.432
24.576
36.864
705.6 kHz
0
22.5792
33.8688
N/A
N/A
N/A
N/A
768 kHz
0
24.576
36.864
019001308-E-00
2019/02
- 50 -
[AK4499]
9.4. Audio Interface Format
9.4.1. PCM Mode
9.4.1.1. Input Data Format
Four data modes, such as Normal Mode, TDM128, TDM256, and TDM512 Modes, are available.
Mode settings are available by the pins (TDM0/1 pins and DIF0/1/2 pins) and registers (TDM[1:0] bits
and DIF[2:0] bits). The AK4499 must be reset by setting RSTN bit when the format setting is changed
during operation.
Normal Mode (TDM[1:0] bits = “00” or TDM1 pin = “L”, TDM0 pin = “L”)
4-ch Data is shifted in via the SDATA1/2 pins using BICK and LRCK inputs. Eight data formats are
supported and selected by the DIF0/1/2 pins or DIF[2:0] bits as shown in Table 21. In all formats the
serial data is MSB first, 2's compliment format and is read on the rising edge of BICK. Mode 2 can be
used for 16-bit and 20-bit, Mode 6 can be used for 16-bit, 20-bit and 24-bit MSB justified formats by
zeroing the unused LSBs.
TDM128 Mode (TDM[1:0] bits = “01” or TDM1 pin = “L”, TDM0 pin = “H”)
In Register Control mode up to 8-ch Data is shifted in via the SDATA1/2 pins using BICK and LRCK
inputs. In Pin Control mode up to 4-ch data is supported via the SDATA1 pin. BICK is fixed to 128fs.
Six data formats are supported and selected by the DIF[2:0] bits or DIF0/1/2 pins as shown in Table 21.
In all formats the serial data is MSB first, 2's compliment format and is read on the rising edge of BICK.
Refer to Data Slot Selection Function or Daisy Chain mode for options to route data to DAC outputs.
TDM256 Mode (TDM[1:0] bits = “10” or TDM1 pin = “H”, TDM0 pin = “L”)
In Register Control mode up to 16-ch Data is shifted in via the SDATA1/2 pins using BICK and LRCK
inputs. In Pin Control mode up to 8-ch data is supported via the SDATA1 pin. .BICK is fixed to 256fs.
Six data formats are supported and selected by the DIF[2:0] bits or DIF0/1/2 pins as shown in Table 21.
In all formats the serial data is MSB first, 2's compliment format and is read on the rising edge of BICK.
Refer to Data Slot Selection Function or Daisy Chain mode for options to route data to DAC outputs.
TDM512 Mode (TDM[1:0] bit = “11” or TDM1 pin = “H”, TDM0 pin = “H”)
Up to 16-ch Data is shifted in via the SDATA1 pin using BICK and LRCK inputs. Input data to the
SDATA2 pin is ignored. BICK is fixed to 512fs. Six data formats are supported and selected by the
DIF[2:0] bits or DIF0/1/2 pins as shown in Table 21. In all formats the serial data is MSB first, 2's
compliment format and is read on the rising edge of BICK. Refer to Data Slot Selection Function or
Daisy Chain mode for options to route data to DAC outputs.
019001308-E-00
2019/02
- 51 -
[AK4499]
Table 21. Audio Interface Format (N/A: Not available)
TDM[1:0] DIF[2:0]
Mode
SDATA1/2 Format
LRCK BICK
Figure
bits/pins
bits/pins
0
000
16-bit LSB justified
H/L
32fs Figure 24
1
001
20-bit LSB justified
H/L
40fs Figure 25
2
010
24-bit MSB justified
H/L
48fs Figure 26
16-bit I2S compatible
L/H
32fs
011
Figure 27
Normal 3
2
24-bit I S compatible
L/H
00
48fs
(Note 39)
4
100
24-bit LSB justified
H/L
48fs Figure 25
5
101
32-bit LSB justified
H/L
64fs Figure 28
6
110
32-bit MSB justified
H/L
64fs Figure 29 (default)
7
111
32-bit I2S compatible
L/H
64fs Figure 30
000
N/A
N/A
N/A
N/A
001
N/A
N/A
N/A
N/A
8
010
24-bit MSB justified
H/L
128fs Figure 31
9
011
24-bit I2S compatible
L/H
128fs Figure 32
TDM128
01
10
100
24-bit LSB justified
H/L
128fs Figure 33
11
101
32-bit LSB justified
H/L
128fs Figure 31
12
110
32-bit MSB justified
H/L
128fs Figure 31
13
111
32-bit I2S compatible
L/H
128fs Figure 32
000
N/A
N/A
N/A
N/A
001
N/A
N/A
N/A
N/A
14
010
24-bit MSB justified
H/L
256fs Figure 34
15
011
24-bit I2S compatible
L/H
256fs Figure 35
TDM256
10
16
100
24-bit LSB justified
H/L
256fs Figure 36
17
101
32-bit LSB justified
H/L
256fs Figure 34
18
110
32-bit MSB justified
H/L
256fs Figure 34
19
111
32-bit I2S compatible
L/H
256fs Figure 35
000
N/A
N/A
N/A
N/A
001
N/A
N/A
N/A
N/A
20
010
24-bit MSB justified
H/L
512fs Figure 37
2
21
011
24-bit I S compatible
L/H
512fs Figure 38
TDM512
11
22
100
24-bit LSB justified
H/L
512fs Figure 39
23
101
32-bit LSB justified
H/L
512fs Figure 37
24
110
32-bit MSB justified
H/L
512fs Figure 37
2
25
111
32-bit I S compatible
L/H
512fs Figure 38
Note 39. The cycle numbers of BICK for each channel must be the same as the bit length setting or
more. L channel data can be input when LRCK = “H” and R channel data can be input when
LRCK = “L” if the LRCK indication is “H/L”. L channel data can be input when LRCK = “L” and
R channel data can be input when LRCK = “H” if the LRCK indication is “L/H”.
Note 40. In Pin Control mode, replace “0” to “L” and “1” to “H” for setting.
019001308-E-00
2019/02
- 52 -
[AK4499]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDATA1/2
Mode 0
15
14
6
5
1
0
14
4
15
3
16
2
1
0
17
31
15
0
14
6
5
4
14
1
15
3
16
2
1
17
0
31
15
0
14
1
BICK
(64fs)
SDATA1/2
Mode 0
Don’t care
15
14
0
Don’t care
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 24. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
0
1
0
1
BICK
(64fs)
SDATA1/2
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDATA1/2
Mode 4
Don’t care
23
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 25. Mode 1, 4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDATA1/2
23
22
1
0
Don’t care
23
22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 26. Mode 2 Timing
019001308-E-00
2019/02
- 53 -
[AK4499]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDATA1/2
23
0
1
22
Don’t care
23
22
1
0
23
Don’t care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 27. Mode 3 Timing
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK (128fs)
SDATA1/2
31
0
1
2
12
13
14
23
1
24
0
31
31
0
1
2
12
13
14
23
1
24
0
31
0
1
BICK (64fs)
SDATA1/2
31 30
20 19 18
8
9
0
1
31 30
20
19 18
Lch Data
8
9
0
1
31
Rch Data
31: MSB, 0:LSB
Figure 28. Mode 5 Timing
LRCK
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
BICK (128fs)
SDATA1/2
31 30
0
1
12 11 10
2
12
13
0
14
31 30
23
24
31
0
1
12
2
11 10
12
13
0
14
31
23
24
31
0
1
BICK (64fs)
SDATA1/2
31 30
20 19 18
9
8
1
0
31 30
Lch Data
20
19 18
9
8
1
0
31
Rch Data
31: MSB, 0:LSB
Figure 29. Mode 6 Timing
019001308-E-00
2019/02
- 54 -
[AK4499]
LRCK
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
24
25
31
0
1
BICK (128fs)
SDATA1/2
31
0
1
13 12 11
2
12
13
0
14
31
24
25
31
0
1
13
2
12 11
12
0
13
14
0
1
BICK (64fs)
SDATA1/2
0
31
21 20 19
8
9
1
2
0
31
21
20 19
Lch Data
9
8
1
2
0
Rch Data
31: MSB, 0:LSB
Figure 30. Mode 7 Timing
128 BICK
LRCK
BICK(128fs)
SDATA1/2
Mode8
23 22
SDATA1/2
Mode11,12
31 30
0
23 22
0
23 22
0
0 31 30
0 31 30
23 22
0
0 31 30
23 22
0 31 30
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
Figure 31. Mode 8/11/12 Timing
128 BICK
LRCK
BICK(128fs)
SDATA1/2
Mode9
23 22
SDATA1/2
Mode13
31 30
0
0
23 22
0 31 30
0
23 22
0
23 22
0 31 30
0 31 30
23
0 31 30
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
Figure 32. Mode 9/13 Timing
019001308-E-00
2019/02
- 55 -
[AK4499]
128 BICK
LRCK
BICK(128fs)
SDATA1/2
23 22
23 22
0
23 22
0
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 33. Mode 10 Timing
256 BICK
LRCK
BICK (256fs)
SDATA1/2
Mode14
SDATA1/2
Mode17,18
23 22
0
23 22
31 30
0
23 22
0 31 30
0
0 31 30
23 22
23 22
0
0 31 30
31 30
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 34. Mode 14/17/18 Timing
256 BICK
LRCK
BICK (256fs)
SDATA1/2
Mode15
SDATA1/2
Mode19
23
0
23
31 30
0
23
0 31 30
0
23
0 31 30
23
0
0 31 30
31
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 35. Mode 15/19 Timing
256 BICK
LRCK
BICK(256fs)
SDATA1/2
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
0
23
32 BICK
32 BICK
32 BICK
32 BICK
Figure 36. Mode 16 Timing
019001308-E-00
2019/02
- 56 -
[AK4499]
512BICK
LRCK
BICK(512fs)
SDATA1
Mode20
SDATA1
Mode23,24
23 22
0
23 22
0
23 22
0
23 22
2
31 22
0 31 22
0 31 22
R1
L1
23
0
2
0 31 22
L2
31
0
R2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 37. Mode 20/23/24 Timing
512BICK
LRCK
BICK(512fs)
SDATA1
Mode21
SDATA1
Mode25
23 22
0
23 22
0
23 22
0
31 22
0 31 22
0 31 22
L1
23 22
0
23
2
2
R1
0 31 22
L2
31
0
R2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 38. Mode 21/25 Timing
512BICK
LRCK
BICK(512fs)
SDATA1
Mode22
23 22
L1
0
23 22
2
R1
0
23 22
2
L2
0
23 22
0
23
2
R2
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 39. Mode 22 Timing
019001308-E-00
2019/02
- 57 -
[AK4499]
9.4.1.2. Data Slot Selection Function (Register Control Mode)
Data slot of 1cycle LRCK for each audio data format is defined as Figure 40, Figure 41, Figure 42 and
Figure 43. DAC output data can be selected by SDS[2:0] bits (Register Control mode only), as shown in
Table 22.
LRCK
SDATA1
L1
R1
SDATA2
L2
R2
Figure 40. Data Slot in Normal Mode
128 BICK
LRCK
SDATA1
L1
R1
L2
R2
SDATA2
L3
R3
L4
R4
Figure 41. Data Slot in TDM128 Mode
256 BICK
LRCK
SDATA1
L1
R1
L2
R2
L3
R3
L4
R4
SDATA2
L5
R5
L6
R6
L7
R7
L8
R8
Figure 42. Data Slot in TDM256 Mode
512 BICK
LRCK
SDATA1
L1
R1
L2
R2
L3
R3
L4
R4
L5
R5
L6
R6
L7
R7
L8
R8
Figure 43. Data Slot in TDM512 Mode
019001308-E-00
2019/02
- 58 -
[AK4499]
Table 22. Data Select (×: Do not care)
DAC1
DAC2
TDM[1:0] bits SDS[2:0] bits
Lch Rch Lch Rch
00
×××
L1
R1
L2
R2
01
10
11
×00
L1
R1
L2
R2
×01
L2
R2
L3
R3
×10
L3
R3
L4
R4
×11
L4
R4
L1
R1
000
001
010
011
100
101
110
111
L1
L2
L3
L4
L5
L6
L7
L8
R1
R2
R3
R4
R5
R6
R7
R8
L2
L3
L4
L5
L6
L7
L8
L1
R2
R3
R4
R5
R6
R7
R8
R1
000
001
010
011
L1
L2
L3
L4
R1
R2
R3
R4
L2
L3
L4
L5
R2
R3
R4
R5
100
101
110
111
L5
L6
L7
L8
R5
R6
R7
R8
L6
L7
L8
L1
R6
R7
R8
R1
019001308-E-00
2019/02
- 59 -
[AK4499]
9.4.1.3. Daisy Chain
In TDM512/256 mode, multiple AK4499s can be connected by Daisy Chain. Daisy Chain mode can be
configured from DCHAIN bit or DCHAIN pin (Table 23). SDS[2:0] bits setting will be ignored in Daisy
Chain mode.
Table 23 Daisy Chain Control
DCHAIN bit
DCHAIN pin
0
1
Daisy Chain Mode
TDMO pin
Disable
Enable
L
Data output
(default)
9.4.1.3.1. TDM512 Mode
Figure 44 shows an example of TDM512 mode Daisy Chain structure (TDM[1:0] bits= “11” ). 16ch data
is input to the second AK4499’s SDATA1 pin from a DSP. Connect the second AK4499’s TDMO pin to
the first AK4499’s SDATA1 pin.
Figure 45 shows a data I/O example of TDM512 mode. SDATA1 (L/7/8, R7/8) data is the input for the
DAC of the second AK4499, and the second AK4499 outputs the data from TDMO by shifting 4ch. The
first AK4499 accepts SDATA1 (L5/6, R5/6) data as input data of DAC. DIF[2:0] bits setting or DIF0/1/2
pins setting of both first AK4499 and the second AK4499 must be the same.
4ch Analog Output
L5/6, R5/6
TDMO
SDATA1
4ch Analog Output
L7/8, R7/8
L1/2/3/4/5/6,
R1/2/3/4/5/6
TDMO
SDATA1
L1/2/3/4/5/6/7/8,
R1/2/3/4/5/6/7/8
Second
AK4499
First
AK4499
DSP
Figure 44. Daisy Chain (TDM512 Mode)
512 BICK
LRCK
SDATA1
L1
R1
L2
R2
L3
R3
L4
R4
L5
R5
L6
R6
(DSP)
TDMO
(Second)
L7
R7
L8
R8
Second AK4499
L1
R1
L2
R2
L3
R3
L4
R4
L5
R5
L6
R6
First AK4499
Figure 45. Daisy Chain (TDM512 Mode)
019001308-E-00
2019/02
- 60 -
[AK4499]
9.4.1.3.2. TDM256 Mode
Figure 46 shows an example of TDM256 mode Daisy Chain structure (TDM[1:0] bits = “10”). 8ch data is
input to the second AK4499’s SDATA1 pin from a DSP. Connect the second AK4499’s TDMO pin to the
first AK4499’s SDATA1 pin.
Figure 47 shows a data I/O example of TDM256 mode. SDATA1 (L3/4, R3/4) data is the input for the
DAC of the second AK4499, and the second AK4499 outputs the data from TDMO by shifting 4ch. The
first AK4499 accepts SDATA1 (L1/2, R1/2) data as input data of DAC. DIF[2:0] bits setting or DIF0/1/2
pins setting of both first AK4499 and the second AK4499 must be the same.
4ch Analog Output
L1/2, R1/2
TDMO
4ch Analog Output
L3/4, R3/4
L1/2,
R1/2
SDATA1
TDMO
SDATA1
L1/2/3/4,
R1/2/3/4
Second
AK4499
First
AK4499
DSP
Figure 46. Daisy Chain (TDM256 Mode)
256 BICK
LRCK
SDATA1
L1
R1
L2
R2
L3
R3
(DSP)
L4
R4
Second AK4499
L1
TDMO
(Second)
R1
L2
R2
First AK4499
Figure 47. Daisy Chain (TDM256 Mode)
019001308-E-00
2019/02
- 61 -
[AK4499]
9.4.2. DSD Mode (Register Control Mode Only)
4ch Data is shifted in via the DSDL1/2 and DSDR1/2 pins using DCLK inputs (Figure 48). DSD data is
supported by both Normal mode and Phase Modulation mode (Figure 49). The AK4499 does not
support phase modulation when DCLK is 512fs (DSDSEL[1:0] bits = “11”).
Polarity of DCLK is possible to invert by DCKB bit. Input data is clocked in on a rising edge of DCLK
when DCKB bit = “0” and it is clocked in on a falling edge of DCLK when DCKB bit = “1”.
In case of DSD mode, the setting of DIF[2:0] bits is ignored.
DCLK (DSD64/128/256/512)
DCKB bit = ”0”
DCLK (DSD64/128/256/512)
DCKB bit = ”1”
DSDL1/2, DSDR1/2
D0
D1
D2
D3
Figure 48. DSD Mode Timing
DCLK (DSD64/128/256)
DCKB bit=”0”
DCLK (DSD64/128/256)
DCKB bit=”1”
DSDL1/2, DSDR1/2
D1
D2
D0
D1
D2
Phase Modulation
Figure 49. DSD Mode Timing (Phase Modulation Format)
019001308-E-00
D3
2019/02
- 62 -
[AK4499]
9.4.3. External Digital Filter Mode (EXDF Mode; Register Control Mode Only)
The audio data is input by BCK and WCK from the DINL1/2 and DINR1/2 pins. Three formats are
available (Table 24) by DIF[2:0] bits setting. The data is latched on the rising edge of BCK. The BCK
and MCLK clocks must not burst.
Table 24. Audio Interface Format (EXDF Mode) (N/A: Not available)
Mode
DIF[2:0] bits
Input Format
0
000
16-bit LSB justified
001
N/A
0
010
16-bit LSB justified
011
N/A
1
100
24-bit LSB justified
2
101
32-bit LSB justified
1
110
24-bit LSB justified
(default)
2
111
32-bit LSB justified
1/fs (fs = 384 kHz, 768 kHz)
WCK
0
1
8
9
10
11
16
17
26
27
28
29
30
31
0
1
BCK
DINL1/2
DINR1/2
31
0
30
1
24 23
5
22
6
21
7
20
8
17
16
47
15
48
14
6
5
65
49
4
3
92
2
93
1
94
0
95
0
1
BCK
DINL1/2
DINR1/2
Don’t care
0
1
Don’t care
13
14
15
Don’t care
16
23
24
25
31
2
3
44
45
1
46
0 Don’t care
47
0
1
BCK
DINL1/2
DINR1/2
Don’t care
Don’t care
31
3
2
1
0
Don’t care
Figure 50. EXDF Mode Timing (32-bit LSB justified)
019001308-E-00
2019/02
- 63 -
[AK4499]
9.5. Digital Filter
Six types of digital filter in PCM mode and two types of digital filter in DSD mode are available in the
AK4499 for sound color selection of music playback.
9.5.1. PCM Mode
In PCM mode, the digital filter can be selected by the SD, SLOW and SSLOW pins if the AK4499 is in
Pin Control mode, and it can be selected by the SD, SLOW and SSLOW bits in Register Control mode
(Table 25).
SSLOW
0
0
0
0
1
1
1
1
Table 25. Digital Filter Setting (N/A: not available)
SD
SLOW
Mode
0
0
Sharp Roll-off filter
0
1
Slow Roll-off filter
1
0
Short Delay Sharp Roll-off filter
1
1
Short Delay Slow Roll-off filter
0
0
Super Slow Roll-off filter
0
1
Super Slow Roll-off filter
1
0
Low Dispersion Short Delay filter
1
1
N/A
(default)
9.5.2. DSD Mode
In DSD64/128 mode, the cutoff frequency of digital filter can be switched by the DSDF bit. Table 26
shows the cutoff frequency @fs = 44.1 kHz.
Table 26. DSD Filter Select (×: Do Not Care)
Internal DSD Filter
DSD rate
DSDF bit
Cut Off Frequency
@fs = 44.1 kHz
0
DSD64@DSDF bit = ”0”
37 kHz
1
DSD64@DSDF bit = ”1”
65 kHz
0
DSD128@DSDF bit = ”0”
74 kHz
1
DSD128@DSDF bit = ”1”
131 kHz
×
DSD256
238 kHz
×
DSD512
476 kHz
However, GC[1:0] bits must not be set to “00” when DSDD bit = “0” and DSDF bit = “1” in DSD64/128
mode, or when DSDD bit = “0” in DSD256/512 mode. Otherwise a pop noise may occur.
019001308-E-00
2019/02
- 64 -
[AK4499]
9.6. De-emphasis Filter (PCM Mode)
The AK4499 has a de-emphasis function by IIR filter (50/15 s). This function is only valid in PCM
Normal Speed mode.
In Register Control mode, a digital de-emphasis filter is available for 32kHz*, 44.1kHz or 48kHz*
sampling rates (tc = 50/15µs) and is enabled or disabled by DEM1/2[1:0] bits independently for DAC1
and DAC2 (Table 27). DEM1/2[1:0] bits setting value is held even if the data mode is switched among
PCM, DSD and EXDF modes.
Table 27. De-emphasis Control in Register Control Mode
DEM1/2[1:0] bits
Mode
00
44.1 kHz
01
OFF
(default)
10
48 kHz
11
32 kHz
In Pin Control mode, a digital de-emphasis filter is available for 44.1kHz sampling rates (tc = 50/15µs)
and is enabled or disabled by DEM pin (Table 28).
Table 28. De-emphasis Control in Pin Control Mode
DEM pin
Mode
L
44.1 kHz
H
OFF
019001308-E-00
2019/02
- 65 -
[AK4499]
9.7. Digital Attenuator
The AK4499 includes a channel independent digital attenuator for output volumes (ATT) with 256 levels
at 0.5dB step including MUTE (Table 29). When changing output levels, it is executed in soft transition,
thus no switching noise occurs during these transitions. It can attenuate the input data from 0dB to 127dB and MUTE when assuming the output signal level is 0dB when ATTL1/2 [7:0] bits and
ATTR1/2[7:0] bits = “FFH”.
The digital attenuator is disabled in volume bypass mode (DSDD bit = “1”) at DSD mode. Digital
attenuation is fixed to 0 dB in pin control mode.
Table 29. Attenuation Level of Digital Attenuator
ATTL1/R1/L2/R2[7:0] bits
ATT Code
Attenuation Level
FFH
FEH
FDH
:
:
02H
01H
00H
255
254
253
:
:
2
1
0
0dB
-0.5dB
-1.0dB
:
:
-126.5dB
-127.0dB
MUTE (-∞)
(default)
The transition time of when changing digital output volume is defined as (Transition time of 1 code shift)
x (previous ATT level – changed ATT level). The transition time of 1 code shift is set by ATS[1:0] bits
(Table 30). Register setting values will be kept even switching the PCM and DSD modes.
Table 30. Transition Time between Set Values of ATT[7:0] bits
Transition Time of 1 Code Shift
ATS[1:0]
bits
PCM Mode
EXDF Mode
DSD Mode
00
4080/fs
4080 WCK Cycle
4080/(2fs)
(default)
01
2040/fs
2040 WCK Cycle
2040/(2fs)
10
510/fs
510 WCK Cycle
510/(2fs)
11
255/fs
255 WCK Cycle
255/(2fs)
It takes 4080/fs (92.5 ms @fs = 44.1 kHz) from “FFH” (0dB) to “00H” (MUTE) when ATS[1:0] bits “00” in
PCM mode. ATTL1/2[7:0] bits and ATTR1/2[7:0] bits are initialized to “FFH” (0dB) by setting the PDN
pin = “L”.
If the digital volume attenuation level is changed during reset period, the output volume will become a
setting value after releasing the reset. It will change to a setting value immediately if the volume is
changed within 10/fs after releasing reset.
019001308-E-00
2019/02
- 66 -
[AK4499]
9.8. Gain Adjustment Function
The AK4499 has the gain adjustment function. The analog output amplitude can be adjusted by GC[1:0]
bits. In Pin Control mode, the gain mode is fixed to 72.8 mApp output mode.
Table 31. Current Output Level between Set Values of GC[1:0] bits
Current Output Level
GC[1:0] bits
DSD:
DSD:
PCM/EXDF
Normal Path
Volume bypass
00
72.8 mApp
72.8 mApp
45.5 mApp
(default)
01
72.8 mApp
45.5 mApp
45.5 mApp
10
45.5 mApp
45.5 mApp
45.5 mApp
11
45.5 mApp
45.5 mApp
45.5 mApp
019001308-E-00
2019/02
- 67 -
[AK4499]
9.9. Zero Detection, DSD Full-scale Detection
The AK4499 has a zero detection function and a DSD full-scale detection function. These detection
flags can be output from the DZFL/R pin. DDMOE bit selects the output detection flag of the DZFL/R
pin (Table 32). The output polarity of the DZFL/R pin can be inverted by DZFB bit (Table 33).
DDMOE bit
Table 32. Output Select for DZFL/R Pins
DZFL/R Pin Output
0
Zero Detection Flag
1
DSD Full-scale Detection Flag
(default)
Table 33. Output Polarity Select for DZFL/R Pins
DZFB bit
DZFL/R Pin Output
0
“H” when detect flag
1
“L” when detect flag
(default)
9.9.1. Zero Detection
The AK4499 has a channel-independent zero detection function. As shown in Figure 51, DATT soft
mute block outputs are the monitor nodes of zero detection. Zero detection flag is generated when the
monitor node of each channel is continuously “0” for a detection time shown in Table 34.
Zero detection flag is generated immediately when the AK4499 is set to reset state (RSTN bit = “0”).
Zero detection flag will be cleared in 4/fs–5/fs by releasing the reset (RSTN bit = “1”). The zero
detection function is disabled if Volume Bypass is selected in DSD mode (Table 19).
PCM
EXDF
DSD
Table 34. Zero Detection Time
Sampling Speed
Detection Time
Any Sampling Speed
8192 / fs
Any Sampling Speed
8192 WCK cycle
DSD64/128/256
8192 / fs
DSD512
16384 / fs
019001308-E-00
2019/02
- 68 -
[AK4499]
BICK/BCK/DCLK
SDATA/DINL/DSDL
LRCK/DINR1/DSDR1
PCM
Data
Interface
De-emphasis
&
Interpolator
External
DF
Interface
SSLOW/WCK
TDM0/DCLK
Modulator
DATT
Soft Mute
PCM/DSD
EXDF/DSD
Automatic
Mode
Switching
SR
DAC
Monitor Node
SR
DAC
Normal path
DSDD bit “0”
DSD Data
Interface/
DSD Filter
Volume Bypass
DSDD bit “1”
Figure 51. Zero Detection Monitor Node
Zero detection flag can be output from the DZFL/R pins by setting DZFE bit = “1” when DDMOE bit =
“0”. The output flag of the DZFL/R pins can be selected by DZFM bit and DZFSEL bit (Table 35).
Table 35. Output Signal Setting of DZFL/R Pins (DDMOE bit = “0”) (×: Do Not Care)
DZFE
DZFM DZFSEL
DZFL pin
DZFR pin
bit
bit
bit
0
×
×
0
1
0
“L”
L1ch Zero Detection Flag
L2ch Zero Detection Flag
AND Signal of
Lch and Rch Zero
Detection Flags
1
1
×
“L”
R1ch Zero Detection Flag
R2ch Zero Detection Flag
AND Signal of
Lch and Rch Zero
Detection Flags
(default)
9.9.2. DSD Full-Scale Detection Function
The AK4499 has independent full-scale detection function for each channel in DSD mode. Mute
function of analog output signal becomes enabled after detecting full-scale signal by setting DDM bit =
“1”. DDM bit setting should be made while PW bit = “0” or RSTN bit = “0”.
Figure 52 shows a block diagram of DSD signal playback. Input data of each channel pin (DSDL1/2 or
DSDR1/2) is received via the DSD_IF block and full-scale detection is executed at the DSD full-scale
detection block. Full-scale detection is valid only the AK4499 is in power-on state.
DDM
DSDL1/L2
or DSDR1/R2
DSDF
"0"
DSD_IF
Register
(DDMT+8)
DSD
filter
"1"
"0"
DATT
Soft Mute
"1"
Delta
Sigma
Analog Output
"0"
SR
"1"
Zero Data
DML1
DSD
DML2
Full Scale DMR1
Detect DMR2
DDMT
DSDD
DDM
Mute
Figure 52. DSD Block Diagram
019001308-E-00
2019/02
- 69 -
[AK4499]
If the input data of any channel is continuously “H” or “L” for the time set by DDMT bit, the AK4499 is in
full-scale detection state (Table 37) and corresponding DML1/2 or DMR1/2 bit becomes “1”
independently. DML1/2 and DMR1/2 bits can be readout by register reading.
Full-scale detection signal can also be output from the DZFL/R pin by setting DDMOE bit = “1”. The
output flag of the DZFL/R pin can be selected by DZFE, DZFM and DZFSEL bits (Table 36).
Table 36. Output Signal Setting of DZFL/R Pins (DDMOE bit = “1”) (×: Do Not Care)
DZFE
DZFM DZFSEL
DZFL pin
DZFR pin
bit
bit
bit
×
0
0
1
0
1
×
1
1
×
L1ch Full-scale Detection Flag
L2ch Full-scale Detection Flag
“L”
AND Signal of L1/R1/L2/R2ch
Zero Detection Flag
019001308-E-00
R1ch Full-scale Detection Flag
R2ch Full-scale Detection Flag
OR Signal of L1/R1/L2/R2ch
Full-scale Detection Flag
2019/02
- 70 -
[AK4499]
The AK4499 mutes the analog output when full-scale data is input to either L or R channel if DDM bit =
“1”. The output data of DSD_IF block is delayed by Register block for “Setting Time of DDMT bit + 8
DCLK cycles” to avoid clicking noise until the analog output is muted completely when DDM bit = “1”.
Therefore, the analog output delay becomes larger according to this delay time (Table 37). DDM bit
setting should be made while PW1 bit = PW2 bit = “0” or RSTN bit = “0”.
Full-scale detection state is released when the input data of the full-scale input channel is toggled. The
operation after full-scale detection is released is according to DSDD bit setting that selects DSD
playback path (Table 38).
When DSDD bit = “0” (Normal Path), the transition time until the output data returns to normal after
releasing full-scale detection state is according to the setting of ATS[1:0] bits (Table 30).
If DSDD bit = “1” (Volume Bypass), the output data returns to normal immediately when the full-scale
detection state is released.
The full-scale detection function is assuming full-scale input that occurs when switching the data mode
between PCM and DSD modes. Therefore, click noise will not occur when the input signal becomes fullscale from zero data and vice versa but there is a possibility that click noise occurs when the input
signal becomes full-scale from the state there is an input signal and vice versa.
Table 37. DSD Full-scale Detection Time Setting
DDMT bit
Detection Time
Register Delay
0
256 DCLK cycle
264 DCLK cycle
1
128 DCLK cycle
136 DCLK cycle
(default)
Table 38. Relationship between Output Signal Transition Time and DSDD Bit (DDM bit = “1”)
DSDD bit
Mode
Mute Transition time
Mute Release time
0
Normal Path
Rapidly
As ATS[1:0] bits
(default)
1
Volume Bypass
Rapidly
019001308-E-00
2019/02
- 71 -
[AK4499]
DSDL/R pin
DSD Full Scale Data
DSD Data
DSD Full Scale Data
RSTN bit
Internal
RSTN signal
3~4/fs
(1)
Analog output
(DSDD bit = “0”)
Analog output
(DSDD bit = “1”)
(2)
(2)
Notes:
(1) Internal reset is released after 3-4/fs by setting RSTN bit = “1”.
(2) Excessive signals will be output from the analog output if full-scale signal is input after releasing
internal reset. This behavior does not depend on DSDD bit setting.
Figure 53. Analog Output Waveform with DSD Full-scale Input (DDM bit = “0”)
DSDL/R pin
DSD Full Scale Data
DSD Data
DSD Full Scale Data
RSTN bit
Internal
RSTN signal
3~4/fs
(1)
(2)
(2)
Full scale Detect flag
(DML or DMR)
(5)
Analog output
(DSDD bit=”0”)
(3)
(4)
Analog output
(DSDD bit=”1”)
Notes:
(1) Internal reset is released after 3–4/fs by setting RSTN bit = “1”.
(2) The internal detection flag becomes “1” if the input data is full-scale for a period set by DDMT bit
after releasing internal reset.
(3) Analog output is forced to zero output when full-scale signal is detected. No clicking noise occurs
during a period from digital data input until full-scale detection since the analog output data delays
for Register delay time (Table 37) if DDM bit is set to “1”.
(4) Full-scale detection state is cleared when normal signal is input when the AK4499 is in full-scale
detection state. Analog signal output starts after the Register delay time (Table 37) by clearing the
full-scale detection state.
(5) Analog output transition time is different according to DSDD bit setting. When DSDD bit = “0”,
analog output transition time is set by ATS[1:0] bits (Table 30). When DSDD bit = “1”, analog
output recovers immediately.
Figure 54. Analog Output Waveform with DSD Full-scale Input (DDM bit = “1”)
019001308-E-00
2019/02
- 72 -
[AK4499]
9.10. LR Channel Output Signal Select, Phase Inversion Function
In Register Control mode, input and output combination of the AK4499 can be changed by MONO1/2
bits and SELLR1/2 bits. In addition, the output signal phase can be inverted by INVL1/2 bits and
INVR1/2 bits (Table 39). These functions are available on all audio formats. In Pin Control mode, Rch
output signal phase of DAC1/2 can be inverted by the INVR pin (Table 40).
Table 39. Output Select for DAC1/2 (Register Control Mode)
MONO1 bit SELLR1 bit INVL1 bit INVR1 bit
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MONO2 bit SELLR2 bit INVL2 bit INVR2 bit
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
1
0
1
1
1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
1
1
L1
R1
L1ch in
L1ch in Invert
L1ch in
L1ch in Invert
R1ch in
R1ch in Invert
R1ch in
R1ch in Invert
L1ch in
L1ch in Invert
L1ch in
L1ch in Invert
R1ch in
R1ch in Invert
R1ch in
R1ch in Invert
R1ch in
R1ch in
R1ch in Invert
R1ch in Invert
L1ch in
L1ch in
L1ch in Invert
L1ch in Invert
L1ch in
L1ch in
L1ch in Invert
L1ch in Invert
R1ch in
R1ch in
R1ch in Invert
R1ch in Invert
L2
L2ch in
L2ch in Invert
L2ch in
L2ch in Invert
R2ch in
R2ch in Invert
R2ch in
R2ch in Invert
L2ch in
L2ch in Invert
L2ch in
L2ch in Invert
R2ch in
R2ch in Invert
R2ch in
R2ch in Invert
R2
R2ch in
R2ch in
R2ch in Invert
R2ch in Invert
L2ch in
L2ch in
L2ch in Invert
L2ch in Invert
L2ch in
L2ch in
L2ch in Invert
L2ch in Invert
R2ch in
R2ch in
R2ch in Invert
R2ch in Invert
Table 40. Output Select (Pin Control Mode)
INVR pin
L1
R1
L2
R2
L
H
L1ch in
L1ch in
R1ch in
R1ch in Invert
L2ch in
L2ch in
R2ch in
R2ch in Invert
019001308-E-00
2019/02
- 73 -
[AK4499]
9.11. PCM/DSD, EXDF/DSD Automatic Mode Switching Function
The AK4499 has automatic mode switching function that determines D/A conversion mode from the
input clock and data. This function is available by setting ADPE bit = “1” when the PDN pin = “H” in
register control mode. DP bit is for manual setting. It will be ignored when ADPE bit is “1”.
The automatic mode switching function is valid between PCM mode and DSD mode or EXDF mode
and DSD mode. PCM/DSD automatic switching mode is enabled by setting ADPE bit = “1” when EXDF
bit = “0”, EXDF/DSD automatic switching mode is enabled by setting ADPE bit = “1” when EXDF bit =
“1”. EXDF bit setting should be made before changing ADPE bit = “0” → “1”. Note that automatic mode
switching function is not available between PCM mode and EXDF mode.
The result of automatic mode detection can be readout by ADP bit. When ADPE bit = “1”, ADP bit
outputs “0” if the detection result is PCM or EXDF mode and outputs “1” if it is DSD mode. This readout
function of ADP bit is invalid and “0” data is readout when ADPE bit = “0”.
To prevent clicking noises on mode switching, the mute function of DSD full-scale detection should be
enabled by setting DDM bit = “1” when using this automatic mode switching function. DDM bit must be
set while PW bit or RSTN bit = “0”. By setting DDM bit = “1”, group delay will be 18/fs longer in
PCM/EXDF mode and 136 to 264 DCLK cycle longer according to full-scale detection time setting by
DDMT bit in DSD mode (Table 37). This function does not support DSD phase modulation format and
edge inversion function of DSD receiving data (DCKB bit = “1”).
The automatic mode switching function supports both DSD data paths set by DSDPATH bit. The
AK4499 determines mode from the clock input of the DCLK pin (#52) when DSDPATH bit = “0”, and it
determines mode from clock and data inputs of the BICK/BCK/DCLK pin (#43), LRCK/DSDR1 pin (#45)
and WCK pin (#48).
9.11.1. Automatic Mode Switching when DSDPATH bit = “0”
When DSDPATH bit = “0”, the AK4499 detects PCM (or EXDF) mode or DSD mode by counting a clock
input to the DCLK pin (#52). MCLK should be input during mode detection.
Mode detection condition is different according to DSDSEL[1:0] bits setting. The AK4499 detects DSD
mode if the number of clock pulse in 1/fs is in a range shown in Table 41 and PCM (or EXDF) mode is
detected if not.
Table 41. Mode Detection Condition when DSDPATH = ”0”
DSD mode
DSDSEL[1:0] bits
Number of DCLK Pulse in 1/fs
Detection Result
DSD64
DSD128
DSD256
DSD512
00
01
10
11
53 < pulse number < 77
106 < pulse number < 154
212 < pulse number < 308
424 < pulse number < 616
DSD Mode
When the mode is changed from PCM (or EXDF) to DSD, zero data should be input to both L and R
channels in DSD mode after inputting zero data to both channels in PCM (or EXDF) mode. When the
mode is changed from DSD mode to PCM (or EXDF), zero pattern data should be input to both L and R
channels in DSD mode before inputting zero data to both channels in PCM (or EXDF) mode. In this
case, 1024/fs of zero data input period is necessary. Refer to Figure 55 for operation sequence.
019001308-E-00
2019/02
- 74 -
[AK4499]
PDN pin
(1)
ADPE bit
RSTN bit
(2)
MCLK pin
BICK pin
or BCK pin
LRCK pin
or WCK pin
SDATA1/2 pins or
DINL1/L2/R1/R2 pins
“L” PCM or EXDF data “L”
“L” PCM or EXDF data
DCLK pin
DSDL1/R1 pins
DSDL2/R2 pins
DSD zero
DSD data
DSD zero
(4)
(4)
ADP bit
(Result of Mode Detection)
(5)
IOUT pins
(current output)
(5)
(6)
(6)
(5)
Hi-z
Notes:
(1) Automatic mode switching between PCM (or EXDF) and DSD modes is enabled by setting ADPE
bit = “1”.
(2) When DSDPATH bit = “0”, MCLK input is necessary for mode detection.
(3) In PCM mode, analog output delay time becomes longer for about 18/fs comparing with when
setting ADPE bit = “0”.
(4) The AK4499 transitions to DSD mode if the number of DCLK input clock pulse in 1/fs satisfies the
condition. The condition of DSD mode detection is set by DSDSEL[1:0] bits (Table 41).
(5) In DSD mode, analog output delay time becomes longer comparing with when setting ADPE bit =
“0”. In this case, delay time depends on DDMT bit setting.
(6) The AK4499 transitions to PCM (or EXDF) mode if the number of DCLK input clock pulse does not
satisfies the condition.
Figure 55. Mode Switching Sequence when DSDPATH bit = “0”
019001308-E-00
2019/02
- 75 -
[AK4499]
9.11.2. Automatic Mode Switching when DSDPATH bit = “1”
When the DSDPATH bit = “1”, the AK4499 detects PCM (or EXDF) mode or DSD mode from a clock
and data inputs of the BICK/BCK/DCLK pin (#43), LRCK/DSDR1 pin (#45) and WCK pin (#48).
9.11.2.1. Mode Detection Start Condition
If one of the five conditions shown below is satisfied, the AK4499 executes mode detection. The
AK4499 keeps previous mode instead of executing mode detection if any condition is not satisfied.
These start conditions of mode detection are common regardless of EXDF bit setting.
1. Input data of all channels are zero for a period set by ADPT[1:0] bits (Table 42).
2. Output data of all channels are zero for a period set by ADPT[1:0] bits (Table 42) because of the
attenuation setting or SMUTE bit setting.
3. Input data of all channels are full-scale for a period set by DDMT bit in DSD mode (Table 37).
4. PW1 bit = PW2 bit = “0”
5. RSTN bit = “0”
Table 42. Time Until Mode Detection after Input Data Becomes Zero
ADPT[1:0] bits
Wait Time
00
8192/fs+18/fs
(default)
01
4096/fs+18/fs
10
2048/fs+18/fs
11
1024/fs+18/fs
9.11.2.2. Mode Detection
9.11.2.2.1. PCM/DSD Mode Automatic Switching (EXDF bit = “0”)
The AK4499 detects mode from the input signal to the LRCK/DSDR1 pin (#45). Input one of “01101001
01101001”, “01010101 01010101”, or “00110011 00110011” zero code pattern continuously to the
LRCK/DSDR1 pin when changing to DSD mode from PCM mode (Table 43).
Input a clock that toggles in N times 16BICK cycle or a clock that is continuously “L” or “H” for 32BICK
cycles or more to the LRCK/DSDL1 pin (#3) (Table 43). Refer to Figure 56 and Figure 57 for operation
sequence.
The AK4499 keeps previous mode instead of executing mode switching if any condition is not satisfied.
Table 43. Input Signal when Switching PCM/DSD Mode
#45 LRCK/DSDR1 Pin Input Signal
One of zero code pattern below is input twice consecutively
“01101001 01101001”
or “01010101 01010101”
or “00110011 00110011”
Clock toggles in N times 16BICK cycles (N ≥ 1)
or Clock that keeps “L” or “H” for 32BICK cycles
Detection Result
DSD Mode
PCM Mode
The AK4499 executes data mode detection even if there is no MCLK input while PW bit = “0” or RSTN
bit = “0”. However, the analog output becomes Hi-Z and the AK4499 enters standby state when MCLK
is stopped. The AK4499 resumes operation according to a data mode that is detected when MCLK is
input again. The data mode will be maintained if the input clock to the BICK/BCK/DCLK pin (#43) is
stopped.
The AK4499 executes internal reset for 3–4/fs automatically when switching the data mode and
resumes operation.
019001308-E-00
2019/02
- 76 -
[AK4499]
PDN pin
ADPE bit
RSTN bit
MCLK pin
(7)
BICK/DCLK pin
LRCK/DSDR1 pin
SDATA1/DSDL1 pin
SDATA2/DSDL2 pin
DSD mode Detect
Operation Enable
PCM data
“L”
(3)
(1)
“L”
DSD zero
DSD data
DSD zero
DSD data
(3)
(2)
(2)
ADP bit
(Result of Auto DSD mode setting)
Internal RSTN signal
IOUT pins
(current output)
(5)
3~4/fs
(4)
(4)
(6)
Hi-z
Notes:
(1) Automatic mode switching between PCM and DSD modes is enabled by setting ADPE bit = “1”
after setting PDN pin “L” → “H”. If RSTN bit is in default value “0”, mode detection operation will
start.
(2) Mode detection is performed by monitoring input signal code pattern of the LRCK/DSDR1 pin. It is
executed for 34 cycles of the BICK/DCLK pin input clock and then ADP bit is changed on a rising
edge of input signal of the LRCK/DSDR1 pin. Mode detection is executed even when there is no
MCLK input. The AK4499 starts data mode detection when input data of both channels are zero for
a period set by ADPT[1:0] bits.
(3) The AK4499 finishes data mode detection when a data that is not zero is input.
(4) In PCM mode, analog output delay time becomes 18/fs longer comparing with when setting ADPE
bit = “0”.
(5) When data mode is changed, the AK4499 executes internal reset for 3–4/fs automatically.
(6) In DSD mode, analog output delay time becomes longer comparing with when setting ADPE bit =
“0”. In this case, delay time depends on DDMT bit setting.
(7) A clock input to the BICK/DCLK pin is necessary for data mode detection. The data mode will be
maintained if the input clock to the BICK/DCLK pin is stopped.
Figure 56. Changing to DSD Mode after Power-up in PCM Mode (DSDPATH bit = ”1”, EXDF bit = “0”)
019001308-E-00
2019/02
- 77 -
[AK4499]
PDN pin
ADPE bit
RSTN bit
MCLK pin
(9)
BICK/DCLK pin
(2)
LRCK/DSDR1 pin “L”
SDATA1/DSDL1 pin
SDATA2/DSDL2 pin“L”
DSD mode Detect (1)
DSD zero
DSD data
DSD zero
DSD zero
DSD data
DSD zero
(4)
“L”
PCM data
“L”
(4)
Operation Enable
(3)
(3)
ADP bit
(Result of Auto DSD mode setting)
Internal RSTN signal
IOUT pins
(current output)
(7)
3～4/fs
(5)
(5)
Hi-z
(8)
(6)
Notes:
(1) Automatic mode switching between PCM and DSD modes is enabled by setting ADPE bit = “1”
after setting the PDN pin “L” → “H”. If RSTN bit is in default value “0”, mode detection operation will
start.
(2) Upon power up the AK4499, the AK4499 operates in PCM mode if DCLK is input and DSDL1 is not
input.
(3) Mode detection is performed by monitoring input signal code pattern of the LRCK/DSDR1 pin. It is
executed for 34 cycles of the BICK/DCLK pin input clock and then ADP bit is changed on a rising
edge of input signal of the LRCK/DSDR1 pin. ADP bit outputs “0” in PCM mode and “1” in DSD
mode. Mode detection is executed even when there is no MCLK input.
(4) The AK4499 finishes data mode detection when a data that is not zero is input. Then the AK4499
restarts the mode detection when input data of all channels are continuously zero for the period set
by ADPT[1:0] bits.
(5) In DSD mode, analog output delay time becomes longer comparing with when setting ADPE bit =
“0”. In this case, delay time depends on DDMT bit setting.
(6) If DSD data input is stopped in DSD mode, the AK4499 stays in DSD mode and continues
operation. In this case, full-scale data is input to the AK4499. Excessive signal output can be
avoided by setting DDM bit = “1” enabling automatic mute function works when detecting DSD fullscale input.
(7) When data mode is changed, the AK4499 executes internal reset for 3–4/fs automatically.
(8) In PCM mode, analog output delay time becomes 18/fs longer comparing with when setting ADPE
bit = “0”.
(9) A clock input to the BICK/DSLK pin is necessary for data mode detection. The data mode will be
maintained if the input clock to the BICK/DCLK pin is stopped.
Figure 57. Changing to PCM Mode after Power-up in DSD Mode (DSDPATH bit = ”1”, EXDF bit = “0”)
019001308-E-00
2019/02
- 78 -
[AK4499]
9.11.2.2.2. EXDF/DSD Automatic Mode Switching (EXDF bit = “1”)
The AK4499 detects mode from the input clocks to the WCK pin (#48) and the BCK/DCLK pin (#43).
DSD mode is detected if the number of rising edge of the BCK/DCLK input clock exceeds 256 times in
one cycle WCK input clock counting from a rising edge. EXDF mode is detected if the number of rising
edge of the BCK/DCLK input clock does not reach 256 times in one cycle WCK input clock twice
continuously (Table 44). Refer to Figure 58 and Figure 59 for the operation sequence.
The AK4499 keeps previous mode instead of executing mode switching if any condition is not satisfied.
Table 44. Mode Detection Conditions when Switching EXDF/DSD Mode
BCK/DCLK Pulse in One WCK Cycle
Detection Result
Once “256 < BCK/DCLK pulse number”
DSD Mode
Twice Continuously “BCK/DCLK pulse number ≤ 256”
EXDF Mode
The AK4499 executes data mode detection even if there is no MCLK input while PW bit = “0” or RSTN
bit = “0”. However, the analog output becomes Hi-Z and the AK4499 enters standby state when MCLK
is stopped. The AK4499 resumes operation according to a data mode that is detected when MCLK is
input again. The data mode will be maintained if the input clock to the BICK/BCK/DCLK pin (#43) is
stopped.
The AK4499 executes internal reset for 3–4/fs automatically when switching the data mode and
resumes operation.
019001308-E-00
2019/02
- 79 -
[AK4499]
PDN pin
EXDF bit
(1)
ADPE bit
RSTN bit
MCLK pin
(8)
BCK/DCLK pin
WCK pin
“L”
DINR1/DSDR1
pin
Mode Detect
Operation Enable
“L”
(9) “L”
EXDF data
(2)
(4)
“L”
DSD zero
DSD data
(4)
(3)
(3)
ADP bit
(Result of Mode Detection)
Internal RSTN bit
IOUT pins
(current output)
3~4/fs
(6)
(5)
(5)
(7)
Hi-z
Notes:
(1) EXDF bit must be set before setting ADPE bit.
(2) Automatic mode switching between EXDF and DSD modes is enabled by setting ADPE bit = “1”
after setting PDN pin “L” → “H”. If RSTN bit is in default value “0”, mode detection operation will
start.
(3) Mode detection is performed by monitoring input clock of the WCK pin and the BCK/DCLK pin. It
takes 256DCLK cycles for mode switching from EXDF to DSD mode, and takes 2WCK cycles for
mode switching from DSD to EXDF mode. Mode detection is executed even when there is no
MCLK input.
(4) The AK4499 finishes data mode detection when a data that is not zero is input. The AK4499
restarts data mode detection when input data of both channels are zero for a period set by
ADPT[1:0] bits.
(5) In EXDF mode, analog output delay time becomes 18/fs longer comparing with when setting
ADPE bit = “0”.
(6) When DSD mode is changed, the AK4499 executes internal reset for 3 to 4/fs automatically.
(7) In DSD mode, analog output delay time becomes longer comparing with when setting ADPE bit =
“0”. In this case, delay time depends on DDMT bit setting.
(8) A clock input to the BICK/DCLK pin is necessary for data mode detection. The data mode will be
maintained if the input clock to the BICK/DCLK pin is stopped.
(9) WCK input should be “L” when using DSD mode since DSD mode detection is performed by
monitoring presence or absence of the WCK input clock when EXDF bit = “1”.
Figure 58. Changing to DSD Mode after Power-up In EXDF Mode (DSDPATH bit = ”1”, EXDF bit = “1”)
019001308-E-00
2019/02
- 80 -
[AK4499]
PDN pin
EXDF bit
(1)
ADPE bit
RSTN bit
MCLK pin
(9)
BCK/DCLK pin
“L”
WCK pin
DSD zero
DINR1/DSDR1 pin
“L”
Mode Detect
Operation Enable
(2)
DSD data
(4)
DSD zero
EXDF data
“L”
(4)
(3)
(3)
ADP bit
(Result of Mode Detection)
Internal RSTN bit
IOUT pins
(current output)
3~4/fs
(7)
(5)
(5)
(8)
Hi-z
(6)
Notes:
(1) EXDF bit must be set before setting ADPE bit.
(2) Automatic mode switching between EXDF and DSD modes is enabled by setting ADPE bit = “1”
after setting PDN pin “L” → “H”. If RSTN bit is in default value “0”, mode detection operation will
start.
(3) Mode detection is performed by monitoring input clock of the WCK pin and the BCK/DCLK pin. It
takes 256DCLK cycles for mode switching from EXDF to DSD mode, and takes 2WCK cycles for
mode switching from DSD to EXDF mode. Mode detection is executed even when there is no
MCLK input.
(4) The AK4499 finishes data mode detection when a data that is not zero is input. The AK4499
restarts data mode detection when input data of both channels are zero for a period set by
ADPT[1:0] bits.
(5) In DSD mode, analog output delay time becomes longer comparing with when setting ADPE bit =
“0”. In this case, delay time depends on DDMT bit setting.
(6) If DSDR input is stopped in DSD mode, the AK4499 stays in DSD mode and continues operation.
In this case, full-scale data is input to the AK4499. Excessive signal output can be avoided by
setting DDM bit = “1” enabling automatic mute function works when detecting DSD full-scale input.
(7) When data mode is changed, the AK4499 executes internal reset for 3 to 4/fs automatically.
(8) In EXDF mode, analog output delay time becomes 18/fs longer comparing with when setting ADPE
bit = “0”.
(9) A clock input to the BICK/DCLK pin is necessary for data mode detection. The data mode will be
maintained if the input clock to the BICK/DCLK pin is stopped.
Figure 59. Changing to EXDF Mode after Power-up In DSD Mode (DSDPATH bit = ”1”, EXDF bit = “1”)
019001308-E-00
2019/02
- 81 -
[AK4499]
Soft Mute Function
The AK4499 has soft mute function. The soft mute operation is performed at digital domain. When
setting the SMUTE pin to “H” or SMUTE bit to “1”, the output signal is attenuated by during
ATT_DATA ATT transition time from the current ATT level.
When setting back the SMUTE pin to “L” or SMUTE bit to “0”, the mute is cancelled and the output
attenuation gradually changes to the ATT level during ATT_DATA ATT transition time (Refer to Table
30 for ATT). If the soft mute is cancelled before attenuating after starting the operation, the
attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for
changing the signal source without stopping the signal transmission.
Soft mute function is not available when bypassing the volume (DSDD bit = “1”) in DSD mode.
SMUTE pin or
SMUTE bit
(1)
(1)
ATT_Level
(3)
Attenuation
-
GD
GD
DACOUT L/R
DZFL/R pins
(Register control
mode only)
(2)
8192/fs
Notes:
(1) ATT_DATA ATT transition time. For example, this time is 4080LRCK cycles at ATS[1:0] bits =
“00”, ATT_DATA = “FFH” in PCM Normal Speed mode.
(2) When the input data for each channel is continuously zeros for 8192 LRCK cycles (16384 cycles in
DSD512 mode), the DZFL/R pin for each channel goes to “H”. The DZFL/R pin immediately returns
to “L” if the input data is not zero.
(3) If the soft mute is cancelled before attenuating after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle.
Figure 60. Soft Mute Function
019001308-E-00
2019/02
- 82 -
[AK4499]
9.12. LDO
When TVDD = 3.0 to 3.6V, the power for digital core circuit (DVDD) is supplied by the internal LDO by
setting the LDOE pin to “H”. Table 45 shows the DVDD pin statuses with the PDN and LDOE pins
setting. The internal LDO is powered up by setting the PDN pin from “L” to “H” (power-down release)
and it starts supplying 1.8V DVDD. Connect a 1µF capacitor to the DVDD pin when using the LDO. It
takes 2ms (max.) to power-up the internal LDO.
PDN
pin
×
Table 45. LDO Select Mode (×: Do Not Care)
TVDD
DVDD
LDOE pin
L
1.7 to 3.6 V
H
3.0 to 3.6 V
LDO OFF: Supply 1.7 to 1.98V to the DVDD pin externally
L
500 Ω Pull-down
H
LDO ON: LDO outputs 1.8V.
(Do not connect DVDD with other device loads)
The AK4499 has error detect function, as shown in Table 46 for LDO operation (LDOE pin = “H”). The
internal LDO will be powered down and stop supplying the power to the digital core when an error is
detected. In this case, the analog signal output and the PDA pin becomes Hi-z state (In I2C mode, ACK
is not output). The AK4499 must be reset by setting the PDN pin = “L” → “H” to recover from the error
detection status.
Table 46. Error Detection
Error Detection Conditions
No
Error Correction
1
LDO Overvoltage
Detection
The AK4499 detects an error when the output voltage of the LDO
pin exceeds overvoltage threshold.
Threshold: 2.35 V(typ)
min: 2.2 V / max: 2.5 V
2
LDO Overcurrent
Detection
The AK4499 detects an error when the current flows PMOS from
LDO output exceeds overcurrent threshold.
Threshold: 105 mA(typ)
min: 80 mA / max: 130 mA
019001308-E-00
2019/02
- 83 -
[AK4499]
9.13. Power Up/Down Sequence
The AK4499 is powered down when the PDN pin is “L”. In power down state, all circuits stop operation
and initialized, and the analog output becomes floating (Hi-z) state. The PDN pin must held “L” for more
than 600 ns for a certain reset after all power supplies are on. There is a possibility of malfunctions with
the “L” pulse less than 600 ns. Power down is released by setting the PDN pin to “H” from “L”. In this
time Bias generating circuit and LDO (if LDOE pin = “H”) are powered up and the analog output
becomes floating (Hi-z) state until all clocks are input.
9.13.1. Pin Control Mode (PSN pin = “H”)
All circuits will be powered up by inputting MCLK, LRCK and BICK clocks after the PDN pin = “H”.
Figure 61 shows system timing example of power down/up when using the internal LDO (LDOE pin =
“H”).
Power
(TVDD)
Power
(AVDD, VDDL1/2,
VDDR1/2)
(1)
(6)
Reference Voltage
(VREFHL1/L2/R1/R2)
PDN pin
(2)
DVDD pin
Internal PDN signal
(3)
Internal State
Normal Operation
Reset
“0”data
SDATA1/2 pins
“0”data
GD
IOUT pins
(current output)
(7)
Clock In
(8)
Hi-Z
Reset
GD
(4)
(4)
Hi-Z
(7)
(8)
MCLK, LRCK, BICK
External
Mute
(5)
Mute ON
Mute ON
Notes:
(1) VREFHL1/L2/R1/R2 reference voltages should be input after AVDD is powered up or at the same
time. Power up sequence between AVDD, TVDD and VDDL1/L2/R1/R2 are not critical.
(2) The PDN pin must be “L” when start supplying AVDD, TVDD and VDDL1/L2/R1/R2. It must be held
“L” for more than 600 ns after AVDD, TVDD and VDDL1/L2/R1/R2 are powered up.
(3) The DVDD pin output voltage (generated by Internal LDO) is powered up by setting the PDN pin =
“H” if the LDOE pin = “H”. The internal PDN signal will rise in 2 ms (max.) after the PDN pin = “H”
and the internal circuit will start operation.
(4) Click noise occurs on an edge of PDN signal. This noise is output even if “0” data is input.
(5) Mute the analog output externally if click noise (4) adversely affect system performance.
(6) VREFHL1/L2/R1/R2 reference voltages should be stopped before AVDD is powered down or at the
same time. Power down sequence between AVDD, TVDD and VDDL1/L2/R1/R2 are not critical.
(7) Analog outputs are floating (Hi-Z) in power down state.
(8) Do not input clocks (MCLK, BICK and LRCK) until after TVDD is turned on.
Figure 61. Power-down/up Sequence Example (Pin Control Mode, LDOE pin = “H”)
019001308-E-00
2019/02
- 84 -
[AK4499]
The timing example when not using the internal LDO (LDOE pin = “L”) is shown in Figure 62.
Power
(TVDD)
(1)
(6)
Power
(DVDD)
(2)
Power
(AVDD, VDDL1/2,
VDDR1/2)
(1)
(6)
Reference Voltage
(VREFHL1/L2/R1/R2)
PDN pin
Internal PDN signal
(3)
Internal State
Normal Operation
Reset
“0”data
SDATA1/2 pins
“0”data
GD
IOUT pins
(current output)
(7)
Clock In
(8)
Hi-Z
Reset
GD
(4)
(4)
Hi-Z
(7)
(8)
MCLK, LRCK, BICK
External
Mute
(5)
Mute ON
Mute ON
Notes:
(1) TVDD must be powered up before DVDD is powered up or at the same time. Power up sequence
between other power supplies are not critical. VREFH L1/L2/R1/R2 reference voltages should be
input after AVDD is powered up or at the same time.
(2) The PDN pin must be “L” when start supplying AVDD, TVDD, DVDD and VDDL1/L2/R1/R2. It must
be held “L” for more than 600 ns after AVDD, TVDD, DVDD and VDDL1/L2/R1/R2 are powered up.
(3) When the LDOE pin = “L”, the internal PDN signal is on in 1 μs (max.) after the PDN pin is set to
“H”, and the internal circuit will start operation.
(4) Click noise occurs on an edge of PDN signal. This noise is output even if “0” data is input.
(5) Mute the analog output externally if click noise (4) adversely affect system performance.
(6) TVDD must be powered down after or at the same time of DVDD. Power down sequence between
other power supplies are not critical. VREFH L1/L2/R1/R2 reference voltages should be stopped
before AVDD is powered down or at the same time.
(7) Analog outputs are floating (Hi-Z) in power down state.
(8) Do not input clocks (MCLK, BICK and LRCK) until after TVDD is turned on.
Figure 62. Power-down/up Sequence Example (Pin Control Mode, LDOE pin = “L”)
019001308-E-00
2019/02
- 85 -
[AK4499]
9.13.2. Register Control Mode (PSN pin = “L”)
Figure 63 shows system timing example of power down/up when using the internal LDO (LDOE pin =
“H”). Register access becomes available and internal LDO is powered up after setting the PDN pin =
“H”. The analog circuit starts operation by supplying necessary clocks (MCLK, LRCK and BICK for PCM
mode, MCLK, DCLK and EXDF for DSD mode, MCLK, BCK and WCK for EXDF mode), and the clock
divider will start operation after about 3/fs. In this time, the analog output pins output zero signals. Then
the AK4499 transitions to normal operation by setting RSTN bit = “1”.
Power
(TVDD)
Power
(AVDD, VDDL1/2,
VDDR1/2)
(1)
Reference Voltage
(7)
(VREFHL1/L2/R1/R2)
PDN pin
(2)
DVDD pin
Internal PDN signal
(3)
RSTN bit
(6)
Internal State
(Digital Core)
(6)
Normal Operation
Reset
SDATA pin
or DSDL/R pin
“0”data
“0”data
GD
IOUT pins
(current output)
Clock In
(9)
Hi-Z
(4)
Reset
GD
(4)
Hi-Z
(10)
(9)
(10)
MCLK, LRCK, BICK
DZFL/R pins
External
Mute
(8)
(8)
(5)
Mute ON
Mute ON
Notes:
(1) VREFHL1/L2/R1/R2 reference voltages should be input after AVDD is powered up or at the same
time. Power up sequence between AVDD, TVDD and VDDL1/L2/R1/R2 are not critical.
(2) The PDN pin must be “L” when start supplying AVDD, TVDD and VDDL1/L2/R1/R2. It must be held
“L” for more than 600 ns after AVDD, TVDD and VDDL1/L2/R1/R2 are powered up.
(3) The DVDD pin output voltage (generated by Internal LDO) is powered up by setting the PDN pin =
“H” if the LDOE pin = “H”. The internal PDN signal will rise in 2 ms (max.) after the PDN pin = “H”
and control register access becomes available.
(4) Click noise occurs on an edge of PDN signal. This noise is output even if “0” data is input.
(5) Mute the analog output externally if click noise (4) adversely affect system performance.
(6) It takes 3 to 4/fs until a reset instruction is valid when writing “0” to RSTN bit and it takes 3 to 4/fs
when releasing the reset.
(7) VREFHL1/L2/R1/R2 reference voltages should be stopped before AVDD is powered down or at the
same time. Power down sequence between AVDD, TVDD and VDDL1/L2/R1/R2 are not critical.
(8) The DZF pin outputs “L” in power down state.
(9) Analog outputs are floating (Hi-Z) in power down state.
(10) Do not input clocks (MCLK, BICK and LRCK) until after TVDD is turned on.
Figure 63. Power-down/up Sequence Example (Register Control Mode, LDOE pin = “H”)
019001308-E-00
2019/02
- 86 -
[AK4499]
The timing example of power up/down when not using LDO (LODE pin = “L”) is shown in Figure 64.
Power
(TVDD)
(1)
(7)
Power
(DVDD)
(2)
Power
(AVDD,VDDL1/2,
VDDR1/R2)
(1)
(7)
Reference Voltage
(VREFHL1/L2/R1/R2)
PDN pin
Internal PDN Signal
(3)
RSTN bit
(6)
Internal State
(Digital Core)
(6)
Normal Operation
Reset
SDATA pin
or DSDL/R pin
“0”data
“0”data
GD
IOUT pins
(current output)
Clock In
MCLK, LRCK, BICK
DZF pin
External
Mute
(9)
Hi-Z
(4)
Reset
GD
(4)
Hi-Z
(10)
(9)
(10)
(8)
(8)
(5)
Mute ON
Mute ON
Notes:
(1) TVDD must be powered up before DVDD is powered up or at the same time. Power up sequence
between other power supplies are not critical. VREFH L1/L2/R1/R2 reference voltages should be
input after AVDD is powered up or at the same time.
(2) The PDN pin must be “L” when start supplying AVDD, TVDD, DVDD and VDDL1/L2/R1/R2. It must
be held “L” for more than 600 ns after AVDD, TVDD, DVDD and VDDL1/L2/R1/R2 are powered up.
(3) When the LDOE pin = “L”, the internal PDN signal is on in 1 μs (max.) after the PDN pin is set to
“H”, and the internal circuit will start operation.
(4) Click noise occurs on an edge of PDN signal. This noise is output even if “0” data is input.
(5) Mute the analog output externally if click noise (4) adversely affect system performance.
(6) It takes 3 to 4/fs until a reset instruction is valid when writing “0” to RSTN bit and it takes 3 to 4/fs
when releasing the reset.
(7) TVDD must be powered down after or at the same time of DVDD. Power down sequence between
other power supplies are not critical. VREFH L1/L2/R1/R2 reference voltages should be stopped
before AVDD is powered down or at the same time.
(8) The DZFL/R pins output “L” in power down state.
(9) Analog outputs are floating (Hi-Z) in power down state.
(10) Do not input clocks (MCLK, BICK and LRCK) until after TVDD is turned on.
Figure 64. Power-down/up Sequence Example (Register Control Mode, LDOE pin = “L”)
019001308-E-00
2019/02
- 87 -
[AK4499]
9.13.3. Power Up Sequence of External Operational Amplifier for I-V Conversion
The output current of the AK4499 is converted voltage by external I-V conversion circuit. An operational
amplifier used in this I-V conversion circuit must be powered up or stopped when the AK4499 is
powered up. By doing this, a feedback path of the operational amplifier is maintained and DC offset
(click noise) occurring at power-up of the operational amplifier can be suppressed.
AK4499 Power
0V
(1)
(4)
External OPAMP Power (+)
0V
(2)
External OPAMP Power (-)
External OPAMP Output
(VOUTP-VOUTN)
(3)
0V
Hi-Z (~VSS)
Hi-Z (~VSS)
Normal Operation
(1)
(2)
(3)
(4)
Power up the AK4499. Refer to “9.13.1. Power Up/Down Sequence” for power-up sequence.
Power up an external operational amplifier after power up the AK4499.
When power down the system, the external amplifier must be powered down before the AK4499.
Power down the AK4499 after the external amplifier. Refer to “9.13.1.Power Up/Down Sequence”
for power-down sequence of the AK4499.
Figure 65. Power Up Sequence of External Operational Amplifier for I-V Conversion
There is a possibility of IC destruction due to breakdown of the withstanding voltage of the analog
output pins (IOUTLP/LN/RP/RN) if the power supply of the external operational amplifier is turned on
before power up the AK4499. Therefore, connect a Zener diode (VRWM = 6 to 7 V) between each
VDDL1/R1/L2/R2 and VSSL1/R1/L2/R2 if the power up/down sequence shown in Figure 65 cannot be
followed.
If the power supply of the external amplifier is turned on before power up the AK4499, there is a
possibility that click noise occurs due to DC difference. Connect an external mute circuit to the analog
signal line to prevent this click noise. Refer to “10.4.4. External Mute Circuit” for the external mute
circuit.
019001308-E-00
2019/02
- 88 -
[AK4499]
9.14. Power Down, Standby and Reset Function
Power Down, Standby and Reset functions of the AK4499 are controlled by PDN pin, PW bit, MCLK,
and RSTN bit (Table 47).
Table 47. Power Down, Standby, and Reset Function (×: Do Not Care)
State
PDN
pin
MCLK
Input
PW1/2
bits
RSTN
bit
DIGITAL
Block
ANALOG
Block
LDO /
Register
Analog Output
Power Down
L
×
×
×
OFF
OFF
OFF
Hi-Z
H
No
×
×
OFF
OFF
ON
Hi-Z
H
Yes
0
×
OFF
OFF
ON
Hi-Z
Reset
H
Yes
1
0
OFF
ON
ON
Zero output
Normal
Operation
H
Yes
1
1
ON
ON
ON
Signal output
Standby
PW1 bit
PW2 bit
0
0
1
0
0
1
1
1
Table 48. Standby and Reset Function (detail)
Analog Output
RSTN bit
DAC1
DAC2
0
Hi-Z
Hi-Z
1
Hi-Z
Hi-Z
0
Zero output
Hi-Z
1
Signal output
Hi-Z
0
Hi-Z
Zero output
1
Hi-Z
Signal output
0
Zero output
Zero output
1
Signal output
Signal output
019001308-E-00
2019/02
- 89 -
[AK4499]
9.14.1. Standby Sequence by MCLK
The AK4499 detects a clock stop and all circuits except MCLK stop detection circuit, control register,
IREF circuit and LDO (only when the LDOE pin = “H”) stop operation if MCLK is not input for 1 μs (min.)
during operation (PDN pin = “H”). In this case, the analog output goes floating state (Hi-Z). The AK4499
returns to normal operation if PW bit and RSTN bit are “1” and there are BCLK and LRCK inputs after
starting to supply MCLK again. The zero detection function is disabled when MCLK is stopped. Figure
66 shows standby sequence example by MCLK.
PDN pin
(4)
MCLK pin
MCLK Stop
(1)
Internal
State
Normal Operation
(1)
Standby
SDATA pin
or DSDL/R pins
Normal Operation
(3)
GD
(2)
IOUT pins
(current output)
Hi-Z
Notes:
(1) The AK4499 detects MCLK stop and becomes standby state when MCLK edge is not detected for
1 μs (min.) during operation.
(2) The analog output goes to floating state (Hi-Z) in standby state.
(3) Click noise can be reduced by inputting “0” data when stopping and resuming MCLK supply.
(4) Resume MCLK input to release the standby state. In this case, power-up sequence by the PDN pin
is not necessary.
Figure 66. Standby Sequence Example by MCLK Stop
019001308-E-00
2019/02
- 90 -
[AK4499]
9.14.2. Standby Sequence by PW bits
All circuits except control register, IREF circuit and LDO (only when the LDOE pin = “H”) stop operation
by setting PW1/2 bits to “0”. In this case, control register access is available. The analog output goes to
floating state (Hi-Z). Figure 67 shows power ON/OFF sequence by PW1/2 bits.
PW1/2 bits
RSTN bit
(1)
Internal
State
(6)
Standby
Normal Operation
SDATA pin
or DSDL/R pins
Normal Operation
“0” data
GD
IOUT pins
(current output)
GD
(3)
Hi-Z
(2)
DZFL/R pins
External
MUTE
(2)
(5)
(4)
Notes:
(1) The corresponding channels become standby state immediately when writing “0” to PW1/2 bits.
(2) Click noise occurs on an edge of PW1/2 bits (“ ”). This noise is output even if “0” data is input.
(3) The analog output is floating (Hi-Z) state when PW1/2 bits = “0”.
(4) Mute the analog output externally if click noise (2) or Hi-z output (3) adversely affect system
performance.
(5) The zero detection function is enable when the AK4499 is in standby state (PW1/2 bits = “0”). This
figure shows the seuqnece when DZFE bit = “1” and DDMOE bit = “0”.
(6) It takes 2 to 3/fs until standby state is released when writing “1” to PW1/2 bits.
Figure 67. Standby Sequence by PW1/2 bit (Register Control Mode)
019001308-E-00
2019/02
- 91 -
[AK4499]
9.14.3. Reset by RSTN bit
Digital circuits except control registers, MCLK stop detection circuit, and clock divider are reset by
setting RSTN bit to “0”. In this case, control register settings are held, the analog output becomes zero
signal output and the DZFL/DZFR pin outputs “H”. Figure 68 shows reset sequence by RSTN bit.
RSTN bit
3~4/fs (1)
3~4/fs (1)
Internal
RSTN signal
Internal
State
Normal Operation
Normal Operation
Digital Block Reset
SDATA pin
or DSDL/R pins
“0” data
GD
GD
IOUT pins
(current output)
(2)
(3)
(2)
1/fs
DZFL/R pins
(5)
External
MUTE
(4)
Notes:
(1) It takes 3 to 4/fs until a reset instruction is valid when changing RSTN bit to “0” and it takes 3 to 4/fs
when releasing the reset.
(2) Click noise occurs on an edge of internal RSTN signal. This noise is output even if “0” data is input.
(3) Mute the analog output externally if click noise (2) adversely affect system performance.
(4) The analog output is zero signal when RSTN bit = “0”.
(5) This figure shows the seuqnece when DZFE bit = “1” and DDMOE bit = “0”. The DZF pin goes “H”
on a falling edge of RSTN bit and goes “L” 1/fs after a rising edge of internal RSTN bit.
Figure 68 . Reset Timing Example (Register Control Mode)
019001308-E-00
2019/02
- 92 -
[AK4499]
9.15. Synchronize Function (PCM Mode, EXDF Mode)
The AK4499 has a synchronize function. With this synchronize function, group delays between each
device can be kept within 3/256 fs when using multiple AK4499’s.
In PCM or EXDF mode, clock synchronize function becomes valid when input data of all channels are
“0” for 8192 times continuously, when all channels data become “0” and kept for 8192 times
continuously by attenuation, or when RSTN bit = “0”. In PCM mode, the internal counter is synchronized
with a rising edge of LRCK (falling edge of LRCK when the data format is I2S compatible). In EXDF
mode, the internal counter is synchronized with a rising edge of WCK. In this case, the analog output
becomes zero signal. This function is disabled by setting SYNCE bit = “0” in Register Control mode.
Figure 69 shows a synchronizing sequence when the input data is “0” for 8192 times continuously.
Figure 70 shows a synchronizing sequence by RSTN bit.
“0” data
SDATA1/2 pins
SMUTE bit
or SMUTE pin
(5)
(5)
ATT_Level
Attenuation
GD
GD
(3)
Analog output
SYNC Operation
Enable
(1)
8192/fs
8192/fs
(2)
(2)
Internal Counter
Reset
Internal Data
“0” force enable
GD
(6)
8~10/fs (4)
Notes:
(1) When all channels data are “0” for 8192 times continuously, the synchronize function is enabled.
(2) To ensure the synchronization, zero data input should be kept for 500 μs at least after the
synchronize function is enabled.
(3) Input data of ΔΣ Modulator is fixed to “0” forcibly for 8 to 9/fs when internal counter is reset.
(4) Click noise may occur when the internal counter is reset. This noise is output even if “0” data is
input. Mute the analog output externally if this click noise affects the system performance.
(5) Refer to “9.7. Digital Attenuator” for ATT transition time.
(6) When the internal clock and external input clock are in synchronization, the internal counter will not
be reset even if the synchronize function is valid.
Figure 69. Synchronization Sequence by Continuous “0” Data Input for 8192 Times
019001308-E-00
2019/02
- 93 -
[AK4499]
If RSTN bit is set to “0”, digital circuit is reset in 3 to 4/fs and the synchronization function becomes
valid.
RSTN bit
>500us (6)
3~4/fs (4)
2~3/fs (4)
Internal
RSTN bit
Internal
State
Normal Operation
Normal Operation
Digital Block Power-down
D/A In
(Digital)
force”0” (2)
(3)
D/A Out
(Analog)
GD
GD (3)
(5)
(5)
2/fs(1)
Both DZFL/R pin
SYNC Operation (1)
Internal Counter
Reset
Internal
Data
8~9/fs (2)
Notes:
(1) Since the analog output corresponding to digital input has group delay (GD), it is recommended to
have a no-input period longer than the group delay before writing “0” to RSTN bit.
(2) The synchronization function becomes valid on a falling edge of RSTN bit. It takes about 2/fs to
become invalid after the internal RSTN is changed when changing RSTN bit to “1”.
(3) It takes 3 to 4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes 3 to
4/fs when changing RSTN bit to “1”. The synchronization function becomes valid immediately when
writing “0” to RSTN bit. Therefore, there is a case that the internal counter is reset before internal
RSTN signal of the LSI is changed.
(4) Input data of ΔΣ Modulator is fixed to “0” forcibly for 2 to 3/fs when the internal counter is reset.
(5) Click noise occurs on rising and falling edges of the internal RSTN signal and when the internal
counter is reset. This noise is output even if “0” data is input. Mute the analog output externally if
this click noise affects the system performance.
(6) To ensure the synchronization, reset state should be kept for 500 μs at least after the synchronize
function is enabled.
Figure 70. Synchronization Sequence by RSTN bit (Register Control Mode)
019001308-E-00
2019/02
- 94 -
[AK4499]
9.16. Register Control Interface
9.16.1. 3-wire Serial Control Mode (I2C pin = “L”)
Internal registers may be written to through 3-wire µP interface pins: CSN, CCLK and CDTI. The data
on this interface consists of Chip address (2 bits, C1/0), Read/Write (1 bit; fixed to “1”, write only),
Register address (MSB first, 5 bits) and Control data (MSB first, 8 bits). The data is output on a falling
edge of CCLK and the data is received on a rising edge of CCLK. The writing of data is valid when CSN
“”. The clock speed of CCLK is 5 MHz (max).
Setting the PDN pin to “L” resets the registers to their default values. In Register Control mode, the
digital block except control registers and clock divider is reset by setting RSTN bit to “0”. In this case,
the register values are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1-0:
R/W:
A4-0:
D7-0:
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Chip Address (C1 bit = CAD1 pin, C0 bit = CAD0 pin)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 71. Control I/F Timing
* The AK4499 does not support read commands in 3-wire serial control mode.
* When the PDN pin = “L”, writing into control registers is prohibited.
* The control data cannot be written when the CCLK rising edge is 15 times or less, or 17 times or more
during CSN is “L”.
019001308-E-00
2019/02
- 95 -
[AK4499]
9.16.2. I2C Bus Control Mode (I2C pin = “H”)
The AK4499 supports the fast-mode I2C-bus (max:400 kHz, Ver1.0).
9.16.2.1. WRITE Operation
Figure 72 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 78). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave
address are fixed as “00100”. The next bits are CAD1 and CAD0 (device address bits). This bit
identifies the specific device on the bus. The hard-wired input pin (CAD1 pin, CAD0 pin) sets these
device address bits (Figure 73). If the slave address matches that of the AK4499, the AK4499
generates an acknowledge and the operation is executed. The master must generate the acknowledgerelated clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 79). A
R/W bit value of “1” indicates that the read operation is to be executed, and “0” indicates that the write
operation is to be executed.
The second byte consists of the control register address of the AK4499 and the format is MSB first. The
most significant three bits are fixed as “000” (Figure 74). The data after the second byte contains control
data. The format is MSB first, 8bits (Figure 75). The AK4499 generates an acknowledge after each byte
is rece
ived. Data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH
transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 78).
The AK4499 can perform more than one byte write operation per sequence. After receipt of the third
byte the AK4499 generates an acknowledge and awaits the next data. The master can transmit more
than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving
each data packet the internal address counter is incremented by one, and the next data is automatically
taken into the next address. If the address exceeds “15H” prior to generating a stop condition, the
address counter will “roll over” to “00H” and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state
of the data line can only be changed when the clock signal on the SCL line is LOW (Figure 80) except
for the START and STOP conditions.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
A
C
K
Data(n+1)
Data(n+x)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 72. Data Transfer Sequence in I2C Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(CAD1 and CAD0 are set by pin)
Figure 73. The First Byte
0
0
0
A4
A3
A2
A1
A0
D1
D0
Figure 74. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 75. Byte Structure after The Second Byte
019001308-E-00
2019/02
- 96 -
[AK4499]
9.16.2.2. READ Operation
Set the R/W bit = “1” for the READ operation of the AK4499. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds “15H” prior to generating stop condition, the address counter will “roll over” to “00H” and the
data of “00H” will be read out.
The AK4499 supports two basic read operations: Current Address Read and Random Address Read.
9.16.2.2.1. Current Address Read
The AK4499 has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave
address with R/W bit “1”, the AK4499 generates an acknowledge, transmits 1-byte of data to the
address set by the internal address counter and increments the internal address counter by 1. If the
master does not generate an acknowledge but generates a stop condition instead, the AK4499 ceases
the transmission.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+2)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 76. Current Address Read
9.16.2.2.2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to
issuing the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation.
The master issues a start request, a slave address (R/W bit = “0”) and then the register address to
read. After the register address is acknowledged, the master immediately reissues the start request and
the slave address with the R/W bit “1”. The AK4499 then generates an acknowledge, 1 byte of data and
increments the internal address counter by 1. If the master does not generate an acknowledge but
generates a stop condition instead, the AK4499 ceases the transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 77. Random Address Read
019001308-E-00
2019/02
- 97 -
[AK4499]
SDA
SCL
S
P
start condition
stop condition
Figure 78. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 79. Acknowledge (I2C Bus)
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 80. Bit Transfer (I2C Bus)
019001308-E-00
2019/02
- 98 -
[AK4499]
9.17. Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
Register
Name
Control 1
Control 2
Control 3
L1ch ATT
R1ch ATT
Control 4
DSD1
Control 5
Reserved
DSD2
Control 6
Control 7
L2ch ATT
R2ch ATT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control 8
D7
D6
D5
D4
D3
D2
D1
D0
Default
ACKS
DZFE
DP
ATTL1[7]
ATTR1[7]
INVL1
DDM
DZFSEL
0
DML2
TDM[1]
ATS[1]
ATTL2[7]
ATTR2[7]
0
0
0
0
0
0
0
ADPE
EXDF
DZFM
ADP
ATTL1[6]
ATTR1[6]
INVR1
DML1
0
0
DMR2
TDM[0]
ATS[0]
ATTL2[6]
ATTR2[6]
0
0
0
0
0
0
0
ADPT[1]
ECS
SD
DCKS
ATTL1[5]
ATTR1[5]
INVL2
DMR1
0
0
0
SDS[1]
MONO2
ATTL2[5]
ATTR2[5]
0
0
0
0
0
0
0
ADPT[0]
AFSD
DFS[1]
DCKB
ATTL1[4]
ATTR1[4]
INVR2
DDMOE
0
0
0
SDS[2]
SDS[0]
ATTL2[4]
ATTR2[4]
0
0
0
0
0
0
0
0
DIF[2]
DFS[0]
MONO1
ATTL1[3]
ATTR1[3]
SELLR2
0
0
0
0
PW2
0
ATTL2[3]
ATTR2[3]
0
0
0
0
0
0
0
0
DIF[1]
DEM1[1]
DZFB
ATTL1[2]
ATTR1[2]
0
DDMT
GC[1]
0
DSDPATH
PW1
0
ATTL2[2]
ATTR2[2]
0
0
0
0
0
0
0
ADFS[2]
DIF[0]
DEM1[0]
SELLR1
ATTL1[1]
ATTR1[1]
DFS[2]
DSDD
GC[0]
0
DSDF
DEM2[1]
DCHAIN
ATTL2[1]
ATTR2[1]
0
0
0
0
0
0
0
ADFS[1]
RSTN
SMUTE
SLOW
ATTL1[0]
ATTR1[0]
SSLOW
0CH
22H
00H
FFH
FFH
00H
00H
01H
00H
00H
0DH
00H
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
DSDSEL[0]
SYNCE
0
DSDSEL[1]
DEM2[0]
0
ATTL2[0]
ATTR2[0]
0
0
0
0
0
0
0
ADFS[0]
Notes:
(1) In 3-wire serial control mode, the AK4499 does not support read commands.
(2) The AK4499 supports read command in I2C-bus control mode.
(3) If the address exceeds “15H”, the address counter will “roll over” to “00H” and the next write/read
address will be “00H” by automatic increment function in I2C-Bus mode.
(4) Bits indicated as 0 in each address must contain a “0” value. Malfunctions may occur if writing “1”
value to these bits.
(5) Writing after 16H is forbidden. Malfunctions may also occur by this action.
(6) When the PDN pin goes to “L”, the registers are initialized to their default values.
(7) When RSTN bit is set to “0”, the digital block except control registers and clock divider is reset, and
the registers are not initialized to their default values.
(8) When the PSN pin status is changed, the AK4499 should be reset by the PDN pin.
(9) The AK4499 is register compatible with the AK4490, AK4493, AK4495 and the AK4497.
019001308-E-00
2019/02
- 99 -
[AK4499]
9.18. Register Definitions
Addr
00H
Register Name
Control 1
R/W
Default
D7
ACKS
R/W
0
D6
EXDF
R/W
0
D5
ECS
R/W
0
D4
AFSD
R/W
0
D3
DIF[2]
R/W
1
D2
DIF[1]
R/W
1
D1
DIF[0]
R/W
0
D0
RSTN
R/W
0
RSTN:
Internal Timing Reset
0: Reset. All registers are not initialized. (default)
1: Normal Operation
DIF[2:0]:
Audio Data Interface modes (Table 21)
Initial value is “110” (Mode 6: 32bit MSB justified)
AFSD:
Sampling Frequency Auto Detect Mode Enable (PCM/EXDF modes only, Table 14, Table
15).
0: Disable: Manual or Auto Setting mode (default)
1: Enable: Auto Detect mode
ECS:
EXDF mode clock setting (Table 20)
0: WCK = 705.6 kHz or 768 kHz mode (default)
1: WCK = 352.8 kHz or 384 kHz mode
EXDF:
External Digital Filter I/F Mode (Register Control mode only)
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
ACKS:
Master Clock Frequency Auto Setting Mode Enable (PCM/EXDF modes only). (Table 6,
Table 12, Table 13)
0: Disable: Manual Setting mode (default)
1: Enable: Auto Setting mode
Addr
01H
Register Name
Control 2
R/W
Default
SMUTE:
D7
DZFE
R/W
0
D6
DZFM
R/W
0
D5
SD
R/W
1
D4
D3
D2
D1
DFS[1] DFS[0] DEM1[1] DEM1[0]
R/W
R/W
R/W
R/W
0
0
0
1
D0
SMUTE
R/W
0
Soft Mute Enable
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM1[1:0]: DAC1 De-emphasis Filter Control (Table 27)
Initial value is “01” (OFF).
DFS[2:0]:
Sampling Speed Control (Table 8)
Initial value is “000” (Normal Speed mode). A click noise occurs when changing DFS[2:0]
bits setting.
SD:
Short Delay Filter Enable (Table 25)
0: Traditional filter
1: Short Delay filter (default)
019001308-E-00
2019/02
- 100 -
[AK4499]
DZFM:
Output select for DZFL/R pins (Table 35, Table 36)
DZFE:
Output select for DZFL/R pins (Table 35, Table 36)
Addr
Register Name
D7
D6
D5
D4
02H
Control 3
DP
ADP
DCKS DCKB
R/W
R/W
R
R/W
R/W
Default
0
0
0
0
D3
MONO1
R/W
0
D2
DZFB
R/W
0
D1
D0
SELLR1 SLOW
R/W
R/W
0
0
SLOW:
Slow Roll-off Filter Enable (Table 25)
0: Sharp Roll-off filter (default)
1: Slow Roll-off filter
SELLR1:
DAC1 data selection of L channel and R channel (Table 39)
DZFB:
Inverting Enable of DZF (Table 33)
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
MONO1:
DAC1 Mono/Stereo mode select (Table 39)
0: Stereo mode (default)
1: Mono mode
DCKB:
Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS:
Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
ADP:
Read Back register for internal operation mode. This bit is valid when ADRE bit = “1”.
It is invalid when ADPE bit = “0” and readouts “0” when read.
0: PCM mode/EXDF mode
1: DSD Mode
DP:
DSD/PCM Mode Select
0: PCM mode (default)
1: DSD mode
When DP bit is changed, the AK4499 should be reset by RSTN bit.
019001308-E-00
2019/02
- 101 -
[AK4499]
Addr
03H
04H
Register Name
L1ch ATT
R1ch ATT
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
ATTL1[7] ATTL1[6] ATTL1[5] ATTL1[4] ATTL1[3] ATTL1[2] ATTL1[1] ATTL1[0]
ATTR1[7] ATTR1[6] ATTR1[5] ATTR1[4] ATTR1[3] ATTR1[2] ATTR1[1] ATTR1[0]
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
ATTL1[7:0]: DAC1 L channel Attenuation Level setting (Table 29)
ATTR1[7:0]: DAC1 R channel Attenuation Level setting (Table 29)
Addr
05H
Register Name
Control 4
R/W
Default
D7
INVL1
R/W
0
D6
INVR1
R/W
0
D5
INVL2
R/W
0
D4
D3
INVR2 SELLR2
R/W
R/W
0
0
D2
0
R/W
0
D1
D0
DFS[2] SSLOW
R/W
R/W
0
0
SSLOW:
Super Slow Roll-off (Digital Filter bypass mode) or Low Dispersion Filter Enable (Table 25)
0: Disable (default)
1: Enable
DFS[2]:
Sampling Speed Control (Table 8)
Initial value is “000” (Normal Speed mode). A click noise occurs when changing DFS[2:0]
bits setting.
SELLR2:
DAC2 data selection of L channel and R channel (Table 39)
INVR2:
DAC2 IOUTR Output Phase Inverting (Table 39)
0: Disable (default)
1: Enable
INVL2:
DAC2 IOUTL Output Phase Inverting (Table 39)
0: Disable (default)
1: Enable
INVR1:
DAC1 IOUTR Output Phase Inverting (Table 39)
0: Disable (default)
1: Enable
INVL1:
DAC1 IOUTL Output Phase Inverting (Table 39)
0: Disable (default)
1: Enable
019001308-E-00
2019/02
- 102 -
[AK4499]
Addr
06H
Register Name
DSD1
R/W
Default
D7
DDM
R/W
0
D6
DML1
R
0
D5
D4
DMR1 DDMOE
R
R/W
0
0
D3
0
R/W
0
D2
DDMT
R/W
0
D1
D0
DSDD DSDSEL[0]
R/W
R/W
0
0
DSDSEL[1:0]:DSD sampling speed control (Table 18)
DSDD:
DSD Playback Path Control
0: Normal Path (default)
1: Volume Bypass
DDMT:
DSD Signal Full-scale Detection Time Setting (Table 37)
DDMOE:
Zero Detection/DSD Signal Full-scale Detection Flag Selection (Table 32)
DMR1/L1: This register outputs detection flag when a full-scale is detected at the DSDR1 pin /DSDL1
pin.
DDM:
Addr
07H
DSD data mute
The AK4499 has an internal mute function that mutes the output when DSD input data
becomes all “1” or all “0” for 2048 samples (1/fs) continuously. DDM bit controls this
function.
0: Disable (default)
1: Enable
Register Name
Control 5
R/W
Default
D7
DZFSEL
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
SYNCE:
SYNC Mode Enable
0: SYNC mode Disable
1: SYNC mode Enable (default)
GC[1:0]:
Gain Control (Table 31)
DZFSEL:
Output select for DZFL/R pins (Table 35, Table 36)
Addr
08H
08H:
Register Name
Reserved
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
D2
GC[1]
R/W
0
D1
GC[0]
R/W
0
D0
SYNCE
R/W
1
D3
0
R/W
0
D2
0
R/W
0
D1
0
R/W
0
D0
0
R/W
0
All Reserved
019001308-E-00
2019/02
- 103 -
[AK4499]
Addr
09H
Register Name
DSD2
R/W
Default
D7
DML2
R
0
D6
DMR2
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
DSDPATH
R/W
0
D1
DSDF
R/W
0
D0
DSDSEL[1]
R/W
0
DSDSEL[1:0]: DSD sampling speed control (Table 18)
DSDF:
Cut-off frequency of DSD Filter control (Table 26)
DSDPATH: DSD data input pin select (Table 4)
DMR2/L2: This register outputs detection flag when a full-scale signal is detected at the DSDR2 pin/
DSDL2 pin.
Addr
0AH
Register Name
Control 6
R/W
Default
D7
D6
TDM[1] TDM[0]
R/W
R/W
0
0
D5
SDS[1]
R/W
0
D4
SDS[2]
R/W
0
D3
PW2
R/W
1
D2
PW1
R/W
1
D1
D0
DEM2[1] DEM2[0]
R/W
R/W
0
1
DEM2[1:0]: DAC2 De-emphasis Filter Control (Table 27)
Initial value is “01” (OFF).
PW1:
DAC1 Power Control (Table 47)
PW2:
DAC2 Power Control (Table 47)
SDS[2:0]:
Output Data Slot Selection of Each Channel (Table 22)
TDM[1:0]: TDM Mode Select
00: Normal (default)
01: TDM128
10: TDM256
11: TDM512
Addr
0BH
Register Name
Control 7
R/W
Default
D7
ATS[1]
R/W
0
D6
D5
D4
ATS[0] MONO2 SDS[0]
R/W
R/W
R/W
0
0
0
D3
0
R/W
0
DCHAIN:
Daisy Chain Mode Enable
0: Daisy Chain mode Disable (default)
1: Daisy Chain mode Enable
SDS[2:0]:
Output Data Slot Selection of Each Channel (Table 22)
MONO2:
DAC2 Mono/Stereo mode select (Table 39)
0: Stereo mode (default)
1: Mono mode
ATS[1:0]:
Transition Time Between Set Values of ATT[7:0] bits (Table 30)
Initial value is “00”.
019001308-E-00
D2
0
R/W
0
D1
DCHAIN
R/W
0
D0
0
R/W
0
2019/02
- 104 -
[AK4499]
Addr
0CH
0DH
Register Name
L2ch ATT
R2ch ATT
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
ATTL2[7] ATTL2[6] ATTL2[5] ATTL2[4] ATTL2[3] ATTL2[2] ATTL2[1] ATTL2[0]
ATTR2[7] ATTR2[6] ATTR2[5] ATTR2[4] ATTR2[3] ATTR2[2] ATTR2[1] ATTR2[0]
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
ATTL2[7:0]: DAC2 L channel Attenuation Level setting (Table 29)
ATTR2[7:0]: DAC2 R channel Attenuation Level setting (Table 29)
Addr
0EH
0FH
10H
11H
0EH:
0FH:
10H:
11H:
Addr
12H
13H
14H
12H:
13H:
14H:
Register Name
Reserved
Reserved
Reserved
Reserved
R/W
Default
D7
0
0
0
0
R/W
0
D6
0
0
0
0
R/W
0
D5
0
0
0
0
R/W
0
D4
0
0
0
0
R/W
0
D3
0
0
0
0
R/W
0
D2
0
0
0
0
R/W
0
D1
0
0
0
0
R/W
0
D0
0
0
0
0
R/W
0
D7
0
0
0
R
0
D6
0
0
0
R
0
D5
0
0
0
R
0
D4
0
0
0
R
0
D3
0
0
0
R
0
D2
0
0
0
R
0
D1
0
0
0
R
0
D0
0
0
0
R
0
Reserved
Reserved
Reserved
Reserved
Register Name
Reserved
Reserved
Reserved
R/W
Default
Reserved
Reserved
Reserved
Addr Register Name
15H
Control 8
R/W
Default
D7
ADPE
R/W
0
D6
D5
ADPT[1] ADPT[0]
R/W
R/W
0
0
D4
0
R/W
0
D3
0
R/W
0
D2
ADFS[2]
R
0
D1
D0
ADFS[1] ADFS[0]
R
R
0
0
ADFS[2:0]: fs Auto Detect Mode Detection Result (Table 16)
ADPT[1:0]: Time until PCM/DSD mode detection when input data becomes zero (PCM/EXDF⇔DSD
modes) (Table 42)
ADPE:
Automatic Mode Switching Function Enable Bit for PCM/EXDF and DSD Modes
0: Disable (default)
1: Enable
019001308-E-00
2019/02
- 105 -
[AK4499]
10. Recommended External Circuits
10.1. External Connection Example
Digital I/O 3.3V Digital core 1.8V
Analog 5.0V
ZD
ZD
+ 2200u
10u 1u
10u
+
+
+
51
1
2k
10u
2k
VR
EF
HR
10u
+
0.1u
1u +
8
83
82 +
1u
+15V
-15V
81
80
1u
79 +
78
77
76
75
74
73
1u
+15V
-15V
70
69
68
VREFHR2
0.1u
+10u
2k
67
66
65
+
10u
2k
VR
VREFLR2
EF
HR
64
57
58
59
60
61
62
63
SSLOW/WCK
TDMO
DEM0/DSDL1
DSDR1
TDM0/DCLK
TDM1/DSDL2
DCHAIN/DSDR2
INVR/I2C
TESTE
VREFHR2
VREFHR2
VREFHR2
VREFHR2
VREFLR2
VREFLR2
VREFLR2
VREFLR2
0.1u
47
48
49
50
51
52
53
54
55
56
45
46
41
42
43
44
32 VSSR1
40
29 VDDR1
30 VSSR1
31 VSSR1
VREFLR1
VREFHR1
VREFHR1
VREFHR1
VREFHR1
PSN
ACKS/CAD1
BICK/BCK/DCLK
SDATA1/DINL1/DSDL1
LRCK/DINR1/DSDR1
SDATA2/DINL2/DSDL2
DINR2/DSDR2
0.1u
36
37
38
39
10u
2k
VR
EF
HR
+
84
0.1u
2200u +
+ 2200u
ZD
ZD
+
Electrolytic Capacitor
Micro-
DSP
Controller
Ceramic Capacitor
Resistor
Figure 81. Typical Connection Diagram
(AVDD = VDDL1/R1/L2/R2 = 5.0 V, TVDD = 3.3 V, LDOE pin = “L”, Register Control Mode)
Notes:
(1) Chip Address = “00”.
(2) Power lines of AVDD, TVDD, VDDL1/R1 and VDDL2/R2 should be distributed separately, from the
point with low impedance of regulators or other parts.
(3) AVSS, DVSS, VSSL1/R1 and VSSL2/R2 must be connected to the same analog ground plane.
(Analog ground should have low impedance as a solid pattern. THD+N characteristics will degrade
if there are impedances between each VSS.)
(4) When using LDO, the digital core circuit power supply (DVDD) is supplied from the built-in LDO.
DVDD should not be used for any external circuit loads.
(5) Connect VCOML1/R1/L2/R2 and positive input pin of I-V conversion op-amp from the midpoint
each four Voff circuits that connects VREFHL1/L2/R1/R2 and VREFLL1/L2/R1/R2 via the external
voltage divider resistors. Four Voff circuits do not connect any other pins except
VCOML1/R1/L2/R2 and positive input pins.
(6) It is recommended to input MCLK via a 51Ω damping resistor. Without the resistor, there is a
possibility that THD+N characteristic degrades because of high-frequency noise of MCLK.
(7) All digital input pins except pull-down/pull-up pins should not be allowed to float.
019001308-E-00
2019/02
- 106 -
R2ch Out
10u+
2k
85
L2ch Out
28 VDDR1
72 +
71
87
R2ch
Mute
26 VCOMR1
27 VDDR1
EXTCR2N
VCOMR2
VDDR2
VDDR2
VDDR2
VSSR2
VSSR2
VSSR2
2k
VR
VREFLL2
EF
HR
R2ch
Mute 2
24 IOUTR1N
25 EXTCR1N
10u
1u
R2ch LPF
Circuit
1u +
89 +
88
R2N
I-V
Circuit
R1N
I-V
Circuit
21 OPINR1P
22 OPINR1N
23 IOUTR1N
90
R2P
I-V
Circuit
R1P
I-V
Circuit
R1ch LPF
Circuit
R1ch
Mute 2
R1ch
Mute
R1ch Out
18 EXTCR1P
19 IOUTR1P
20 IOUTR1P
+
10u
+
92
91
L2ch
Mute
17
AK4499
86
94
0.1u
93
L2ch
Mute 2
13
14
1u +
15
16
OPINL2N
OPINL2P
IOUTL2P
IOUTL2P
EXTCL2P
NC
NC
EXTCR2P
IOUTR2P
IOUTR2P
OPINR2P
OPINR2N
IOUTR2N
IOUTR2N
2k
95
L2P
I-V
Circuit
L1P
I-V
Circuit
12
96
L2ch LPF
Circuit
10
11
VREFHR1
VREFHR1
5
6
7
9
1u +
+15V
-15V
4
VREFHL2
VSSL2
VSSL2
VSSL2
VDDL2
VDDL2
VDDL2
VCOML2
EXTCL2N
IOUTL2N
IOUTL2N
L2N
I-V
Circuit
L1N
I-V
Circuit
L1ch LPF
Circuit
L1ch
Mute 2
L1ch
Mute
L1ch Out
+15V
-15V
3
VSSL1
VSSL1
VSSL1
VDDL1
VDDL1
VDDL1
VCOML1
EXTCL1N
IOUTL1N
IOUTL1N
OPINL1N
OPINL1P
IOUTL1P
IOUTL1P
EXTCL1P
NC
NC
33 VREFLR1
34 VREFLR1
35 VREFLR1
VREFHL1
2
+
0.1u
VREFLL1 128
VREFLL1 127
VREFLL1 126
VREFLL1 125
VREFHL1 124
VREFHL1 123
VREFHL1 122
VREFHL1 121
VTSEL 120
DIF2/CAD0 119
DIF1/DZFR 118
DIF0/DZF 117
SLOW/CDTI/SDA
116
L
SD/CCLK/SCL 115
SMUTE/CSN 114
PDN 113
LDOE 112
TVDD 111
DVSS 110
DVDD 109
MCLK 108
AVDD 107
AVSS 106
EXTR 105
0.1u
2200u
0.1u
VREFHL2 104
VREFHL2 103
VREFHL2 102
VREFHL2 101
VREFLL2 100
VREFLL2 99
VREFLL2 98
VREFLL2 97
0.1u
VREFHL1
+
33k
[AK4499]
(8) A 1 µF capacitor must be connected to the EXTCL1P/L1N, EXTCR1P/R1N, EXTCL2P/L2N, and
EXTCR2P/R2N pins independently, even when only using one of DAC1 or DAC2.
(9) There is a possibility of IC destruction due to breakdown of the withstanding voltage of the analog
output pins (IOUTLP/LN/RP/RN). Connect a Zener diode (VRWM = 6 to 7 V) between each
VDDL1/R1/L2/R2 and VSSL1/R1/L2/R2 if the power up/down sequence shown in Figure 65 cannot
be followed.
(10) To avoid click noise, connect an external mute circuit if the power up/down sequence shown in
Figure 65 cannot be followed. Refer to “10.4.4. External Mute Circuit” for details.
019001308-E-00
2019/02
- 107 -
[AK4499]
10.2. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, TVDD,
DVDD and VDDL1/R1/L2/R2. AVDD and VDDL1/R1/L2/R2 are supplied from analog supply in system,
and TVDD and DVDD are supplied from digital supply in system. Power lines of VDDL1/R1/L2/R2
should be distributed separately, from the point with low impedance of regulators or other parts.
When not using LDO (LDOE pin = “L”), TVDD must be powered up before DVDD is powered up or at
the same time. AVSS, DVSS, VSSL1/R1 and VSSL2/R2 must be connected to the same analog ground
plane. Decoupling capacitors for high frequency should be placed as near as possible to the AK4499.
10.3. Reference Voltage
The differential voltage between the VREFHL1/R1/L2/R2 pin and the VREFLL1/R1/L2/R2 pin set the
full-scale of the analog output range. The VREFHL1/R1/L2/R2 pin is normally connected to 5.0V
reference voltage, and the VREFLL1/R1/L2/R2 pin is normally connected to the 0V reference voltage.
Connect a 0.1µF ceramic capacitor and 2200 µF electrolytic capacitor between the VREFHL1/R1/L2/R2
pin and the VREFL L1/R1/L2/R2 pin.
The VREFHL1/R1/L2/R2 and VREFL L1/R1/L2/R2 pins should avoid noises from other power supplies.
Connect the VREFHL1/R1/L2/R2 to the analog 5.0V via a 1Ω resistor, and the VREFL pin to the analog
ground via a 1Ω resistor when it is difficult to obtain expected analog characteristics because of noises
from other power supplies (A low pass filter of fc=36Hz will be composed with the 2200 µF capacitor
and the 1Ω resistor. It removes signal frequency noise from other power supply lines). However, the
direct voltage at the VREFHL1/R1/L2/R2 and VREFL L1/R1/L2/R2 pins drops ±23 mV since a current of
±23 mA flows at VREFH/L via 1 Ω resistor.
The ceramic capacitors should be connected as near as possible to the pins. All digital signals,
especially clocks, should be kept away from the VREFHL1/R1/L2/R2 and VREFLL1/R1/L2/R2 pins in
order to avoid unwanted coupling into the AK4499.
10.4. Analog Output
10.4.1. I-V Conversion Circuit Example
The analog outputs are full differential outputs. The full-scale output is 36.4 mApp Typ. The output
current is converted to voltage by the I-V conversion circuit. Common voltage of the output signals is
2.5V but signal common of the I-V converted voltage can be adjusted with positive input of op-amp for
I-V conversion, four Voff circuits, and VCOML1/R1/L2/R2, that is (VREFHL1/L2/R1/R2 +
VREFLL1/L2/R1/R2)/2, since the output impedance is 110 Ω (typ.). For example, input Voff = 1.9V to
obtain 0V signal common voltage at Rfb = 360Ω.
The output range of I-V conversion is 4.6 Vrms centered around signal common voltage, and 9.2 Vrms
after differential summing. IOUTL1P/R1P/L2P/R2P current and IOUTL1N/R1N/L2N/R2N current cannot
be summed. The differential outputs are summed externally after I-V conversion.
019001308-E-00
2019/02
- 108 -
[AK4499]
AK4499
VCOML1
I-V Conversion Circuit
Voff
+15V
360
IOUTL1N
180p
OPINL1N
-15V
+
Voff
2.5V
10u
0.1u
+
*
OPA1612
+
LPF Circuit
VOUTL1P 500 100
10u
Analog
Out
1.2n
0.1u
1n
+
OPA1612
OPINL1P
Voff
2.5V
+
10u
VOUTL1N 500 100
2.5V
2k
+
10u
Voff
0.1u
VREFLL1
360
VCOMR1
VREFHL1
2k
0.1u
IOUTL1P
Voff Circuit
1.2n
0.1u
+
*
180p
10u
Voff
Figure 82. L1ch External I-V Conversion Circuit Example (same for R1ch, L2ch and R2ch)
Notes:
(1) Input voltage range of the operational amplifier for I-V conversion circuit is from 0.5 V (typ.) to 2.5 V
(typ.). The signal common voltage (VOUTL1P and VOUTL1N) does not have to be 0V.
(2) Resistors used in the I-V conversion circuit are recommended to be within 0.1% of absolute error in
order to meet specifications.
Table 49. Frequency Response of Differential Output Circuit
Gain (1 kHz, typ)
0.0 dB
20 kHz
-0.18 dB
Frequency
Response
40 kHz
-0.69 dB
(ref: 1 kHz, typ)
80 kHz
-2.28 dB
019001308-E-00
2019/02
- 109 -
[AK4499]
In mono mode, connect I-V conversion voltage output terminals with resistors and take differential
output from the midpoint (Voff) of the connection as shown in Figure 83.
I-V Conv. Circuits
AK4499
+15
360
-15
IOUTL1N
+
180p
OPINL1N
Voff L1
+
*
OPA1612
10u
0.1u
+
OPINL1P
Voff L1
180p
+
*
+
1n
10u
1.2n
0.1u
+
100
1.2n
10u
0.1u
OPA1612
510
10u
510
100
510
100
0.1u
IOUTL1P
360
360
IOUTR1P
+
180p
OPINR1P
Voff R1
+
*
OPA1612
10u
0.1u
+
OPA1612
OPINR1N
Voff R1
180p
+
*
+
1.2n
10u
0.1u
1n
10u
0.1u
+
10u
100
1.2n
510
100
100
100
100
0.1u
IOUTR1N
VOUTP
360
360
IOUTL2N
100
OPINL2N
Voff L2
100
+
180p
+
*
OPA1612
0.1u
+
10u
510
OPINL2P
Voff L2
180p
+
*
+
1n
10u
10u
1.2
n
1.2
n
0.1u
+
VOUTN
100
100
10u
0.1u
OPA1612
100
510
100
0.1u
IOUTL2P
360
360
IOUTR2P
+
180p
OPINR2P
Voff R2
+
*
OPA1612
10u
0.1u
+
OPA1612
OPINR2N
Voff R2
180p
+
*
1n
10u
10u
510
100
0.1u
IOUTR2N
Voff Cirsuits, these are four
circuits.
VREFHx
1.2n
0.1u
+
100
1.2n
10u
0.1u
+
510
2.5V
2k
+
2k
10u
Voff x
0.1u
VREFLx
360
x = L1/R1/L2/R2
Figure 83. External I-V Conversion Circuit Example (Mono mode)
019001308-E-00
2019/02
- 110 -
[AK4499]
10.4.2. External Analog Low Pass Filter Example
Differential voltage signal after I-V conversion is summed by differential summing circuit (low pass
filter). Figure 84 shows an example of differential summing circuit and Table 50 shows the frequency
response.
AK4499
I-V Conv.Circuit
Differential Summing Circuit
+15V
-15V
IOUTLN
600
1200
OPINLN
VOUTLN
68n
15
OPINLP
+
3.3n
OPA1611
15
3.3n
7
2
3
+
* 4
10u
0.1u
+
VOUTL
10u
0.1u
VOUTLP
1200 68n
Analog
Out
600
IOUTLP
Voff Circuit
Figure 84. External 2nd Order LPF Circuit Example for PCM mode (fc = 112 kHz (typ), Q = 0.692 (typ))
Table 50. Frequency Response of External LPF Circuit Example
Gain (1 kHz, typ)
-6.02 dB
20 kHz
-6.04 dB
Frequency
Response
40 kHz
-6.14 dB
(ref:1 kHz, typ)
80 kHz
-7.19 dB
019001308-E-00
2019/02
- 111 -
[AK4499]
In DSD mode, signal pass out-of-band noise included in DSD data will be reduced by an internal digital
filter of the AK4499 and an external analog low-pass filter (differential summing circuit). The cutoff
frequency of the external analog low-pass filter can be changed by setting C1, C2, and C3 capacitance
in Figure 85 according to the values shown in Table 51.
AK4499
Differential Summing Circuit
I-V Conv. Circuit
+15V
-15V
IOUTLN
VOUTLN
1200
1200
1200
OPINLN
C1
C2
30
OPINLP
+
C3
OPA1611
30
C3
7
2
3
+
* 4
10u
0.1u
+
VOUTL
10u
0.1u
VOUTLP
1200 C1
1200 C2
Analog
Out
1200
IOUTLP
Voff Circuit
Figure 85. External 3rd Order LPF Circuit Example for DSD mode
Table 51. C1//2/3 Setting Value to Synchronize DSD Filter and fc of External 3rd LPF
Internal DSD Filter
C1, C2, C3 Setting Value [nF]
DSD Rate
Cut Off Frequency
@fs = 44.1 kHz
C1
C2
C3
DSD64@DSDF bit = ”0”
37 kHz
7.5
160
3.0
DSD64@DSDF bit = “1”
65 kHz
4.7
91
1.8
DSD128@DSDF bit = “0”
74 kHz
3.9
82
1.5
DSD128@DSDF bit =”1”
131 kHz
2.2
47
0.91
DSD256
238 kHz
1.2
27
0.47
DSD512
476 kHz
0.62
13
0.24
019001308-E-00
2019/02
- 112 -
[AK4499]
10.4.3. Feedback Loop of External Operational Amplifier
Figure 86 shows the internal status of the AK4499 when the analog output is Hi-Z (PDN = L, PW1/2 = L,
or audio clocks stopped) and when the analog output is idle (reset state). Feedback loop of the external
amplifier is always maintained while the power supply of the AK4499 is on.
AK4499
I-V Conv. Circuit
AK4499
IOUTL1N
I-V Conv. Circuit
IOUTL1N
2.5V
OPINL1N
Voff
+
*
Voff
+
*
OPINL1N
OPINL1P
Voff
+
*
Voff
+
*
OPINL1P
IOUTL1P
2.5V
Hi-Z
IOUTL1P
Idle
Figure 86. Internal Status of the AK4499 when Outputting Hi-Z or Idle
10.4.4. External Mute Circuit
Click noise may occur due to DC offset if the power up/down sequence shown in Figure 65 cannot be
followed and external operational amplifier is powered up before the AK4499. Connect external mute
circuits shown in Figure 87 to analog signal lines to prevent a click noise. The external mute circuit
should be connected to the signal after I-V conversion (Figure 81). Base current will be input to the
transistor RN2202 when the power (5.0V typ.) is not supplied to the VDDL1/R1/L2/R2 pins. In this case,
emitter current flows to the 2SC3327 via 3.8kΩ resistance as base current and the analog signal line is
short to the signal ground. Note that there is a possibility that THD+N performance degrades about 3dB
by connecting an external mute circuit.
+15V
+15V
10k
10k
3.8k
VDDL
3.8k
VDDR
RN2202
3.8k
RN2202
3.8k
2SC3327
220
2SC3327
220
VOUTL
VOUTL
VOUTR
VOUTR
Figure 87. External Mute Circuit Example
019001308-E-00
2019/02
- 113 -
[AK4499]
11. Package
11.1. Outline Dimensions (HTQFP14 x 14-128, Unit: mm)
019001308-E-00
2019/02
- 114 -
[AK4499]
11.2. Material & Terminal Finish
Package molding compound:
Lead frame material:
Pin surface treatment:
Epoxy, Halogen (bromine and chlorine) free
EFTEC64
Solder (Pb free) plate
11.3. Marking
AKM
AK4499EQ
XXXXXXX
128
1
1) Pin #1 indication
2) Date Code: XXXXXXX (7 digits)
3) Marking Code: AK4499EQ
4) AKM Logo
019001308-E-00
2019/02
- 115 -
[AK4499]
12. Ordering Guide
AK4499EQ
AKD4499
40 to +85C
128-pin HTQFP (0.4 mm pitch)
Evaluation Board for AK4499
13. Revision Histroy
Date (Y/M/D)
19/02/27
Revision
00
Reason
First Edition
Page
019001308-E-00
Contents
2019/02
- 116 -
[AK4499]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third party
with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the
aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other
transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations
in which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or
related technology or any information contained in this document, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws
and regulations. The Products and related technology may not be used for or incorporated into
any products or systems whose manufacture, use, or sale is prohibited under any applicable
domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws
and regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as
a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without
prior written consent of AKM.
019001308-E-00
2019/02
- 117 -
工商网监
湘ICP备2023018690号
