AME9003AEJHZ

AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller n General Description The AME9003 is AME’ s next generation direct drive CCFL controller. Like its cousins, the AME9001 and AME9002, the AME9003 controller provides a cost efficient means to drive single or multiple cold cathode fluorescent lamps (CCFL), driving 3 external MOSFETs that, in turn, drive a wirewound transformer that is coupled to the CCFL. The AME9003, like the AME9002 includes extra circuitry that allows for a special one second start up period wherein the voltage across the CCFL is held at a higher than normal voltage to allow older tubes (or cold tubes) a period in which they can ” warm up” . During this one second startup period the driving frequency is adjusted off of resonance so that the tube voltage can be controlled. As soon as the CCFL ” strikes ” the special start up period ends and the circuit operates in its normal mode. However the AME9003 uses an extra capacitor to accurately set the start up interval. In addition to that the AME9003 features a soft start AND soft finish on each dimming cycle edge in order to minimize any audible vibrations during the dimming function. The AME9003 also includes features such as, dimming control polarity selection, undervoltage lockout and fault detection. It is designed to work with input voltages from 7V up to 24V. When disabled the circuit goes into a zero current mode. n Pin Configuration 24 23 22 21 20 19 18 17 16 15 14 13 AME9003 1 2 3 4 5 6 7 8 9 10 11 12 AME9003 1. VREF 2. CE 3. SSC 4. RDELTA 5. SSC1ST 6. RT2 7. VSS 8. OVPH 9. OVPL 10.FCOMP 11.CSDET 12.BATTFB 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. OUTC OUTAPB OUTA VBATT BRPOL VDD CT1 FB COMP BRIGHT SSV PNP Evaluation Board Available !! n System Block Diagram Controller External Components CCFL Array n Features l Small 24 pin QSOP package l 24 pin PDIP/SOIC also available l Drives multiple tubes l Special 1 second start up mode l Automatically checks for common fault conditions l 7.0V < Vbatt < 24V l Low component count l Low Idd < 3.5mA l 3.3V. Over voltage protection input (LOW). During the initial start up period if OVPL < 2.5 volts then FCOMP is allowed to ramp up (decreasing the oscillator frequency allowing the circuit to get closer to resonance). If, during the initial start up period, OVPL > 2.5 volts then FCOMP is held at its original value (not allowed to increase so the oscillator frequency stays constant). This action is designed to hold the voltage across the CCFL constant while the CCFL "warms up". Frequency control point. Initially this pin is at VSS which yields a maximum switching frequency. Depending on the voltage at OVPL and OVPH the pin FCOMP will normally ramp upwards lowering the switching frequency towards the circuit's resonant frequency. 2 CE 3 SSC 4 RDELTA 5 SSC1ST 6 7 RT2 VSS 8 OVPH 9 OVPL 10 FCOMP 2 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller n Pin Description Pin # Pin Name Pin Description Current sense detect. Connect this pin to the CCFL current sense resistor divider. During the initial startup period this pin senses that the CCFL has struck when V(CSDET) > 1.25 volts. If, after the initial start up period, this pin is below 1.25V for 8 consecutive clock cycles after SSC > 3V then the circuit will shutdown. UVLO feedback pin. If this pin is above 1.5V then the OUTA pin is allowed to switch, if below 1.25V then OUTA is disabled. Drives one of the external NFETs, opposite phase of OUTAPB. Drives one of the external NFETs, opposite phase of OUTC. Drives the high side PFET. Battery input. This is the positive supply for the OUTA driver. Brightness polarity control. When this pin is low the CCFL brightness increases as the voltage at the BRIGHT pin increases. When this pin is high the CCFL brightness decreases as the voltage at the BRIGHT pin increases. Regulated 5V supply input. Sets the dimming cycle frequency. Usually about 100Hz. Negative input of the voltage control loop error amplifier. Output of the voltage control loop error amplifier. Brightness control input. A DC voltage on this controls the duty cycle of the dimming cycle. This pin is compared to a 3V ramp at the CT1 pin. Analog brightness control may be accomplished by small modifications to the external circuitry. Soft start ramp for the voltage control loop. (20uA source current.) The voltage at SSV clamps the voltage at COMP to be no greater than SSV thereby limiting the increase of the switching duty cycle. Drives the base of an external PNP transistor used for the 5V LDO. 11 CSDET 12 13 14 15 16 BATTFB OUTC OUTAPB OUTA VBATT 17 BRPOL 18 19 20 21 VDD CT1 FB COMP 22 BRIGHT 23 SSV 24 PNP 3 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller n Ordering Information AME9003 x x x x x Special Feature Number of Pins Package Type Operating Temperature Range Pin Configuration Pin Configuration Operating Temperature Range Package Type Number of Pins Special Feature A: 1 . 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. VREF CE SSC RDELTA FAULTB RT2 VSS OVPH OVPL FCOMP CSDET BATTFB OUTC OUTAPB OUTA VBATT BRPOL VDD CT1 FB COMP BRIGHT SSV PNP E: -40OC to 85OC J: SOIC (300 mil) P: Plastic DIP T: QSOP H: 24 Z: Lead free 4 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller n Ordering Information (contd.) Part Number AME9003AETH Marking* AME9003AETH xxxxxxxx yyww AME9003AETH xxxxxxxx yyww AME9003AEPH xxxxxxxx yyww AME9003AEPH xxxxxxxx yyww AME9003AEJH xxxxxxxx yyww AME9003AEJH xxxxxxxx yyww Output Voltage N/A Package QSOP-24 Operating Temp. Range - 40oC to + 85oC AME9003AETHZ N/A QSOP-24 - 40oC to + 85oC AME9003AEPH N/A PDIP-24 - 40oC to + 85oC AME9003AEPHZ N/A PDIP-24 - 40oC to + 85oC AME9003AEJH N/A SOIC-24 - 40oC to + 85oC AME9003AEJHZ N/A SOIC-24 - 40oC to + 85oC Note: yyww represents the date code * A line on top of the first letter represents lead free plating such as AME9003 Please consult AME sales office or authorized Rep./Distributor for the availability of output voltage and package type . 5 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller n Absolute Maximum Ratings Parameter Battery Voltage (VBATT) Enable ESD Classification Maximum 25 5.5 B Unit V V Caution: Stress above the listed absolute maximum rating may cause permanent damage to the device n Recommended Operating Conditions Parameter Battery Voltage (VBATT) Ambient Temperature Range Junction Temperature Rating 7 - 24 - 40 to + 85 - 40 to + 125 Unit V o C C o n Thermal Information Parameter Thermal Resistance (QSOP - 24) Maximum Junction Temperature Maximum Lead Temperature (10 Sec) Maximum 325 150 300 Unit o C/W o C C o 6 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller n Electrical Specifications TA= 25OC unless otherwise noted, VBATT = 15V, CT1 = 0.047uF, RT2 = 56K Parameter 5V supply (VSUPPLY) Output voltage Line regulation Load regulation Temperature drift 3.4V reference (VREF) Initial voltage Line regulation Temperature drift Brightness oscillator (CT1, BRIGHT) Full Scale Brightness Threshold Zero Scale Brightness Threshold Frequency Accuracy Frequency Range Line regulation Temperature drift Comparator offset Vco oscillator (RT2, RDELTA) Initial frequency Line regulation Temperature drift VCO pullin range Error amplifiers (FB, COMP) Offset voltage, WRT Vref Input bias current Input offset current Open loop gain Unity gain frequency Output high voltage (comp) Output low voltage COMP 100% Duty COMP 0% Duty VOS IB IOS AOL FT VOH VOL VCOMP VCOMP ISOURCE = 50uA ISINK = 500uA 3 0 3.32 0.4 50 1 1 70 1 mV nA nA dB Mhz V V V V FVCO(OUTA) LINE VCO TCVCO PULLVCO Note 2 7< Vbatt < 24V -10C < Ta < 70C 47 -0.8 +-1.5 RT2/(RDELTA X 5) 52 0.8 kHz % % % VCT1,HIGH VCT1, LOW FCT1 FCT1 LINECT1 TCCT1 VOSCT1 Note 1 7< Vbatt < 24V -10C < Ta < 70C 2.9 0 70 10 -1 =+-3 10 3.1 100 130 1000 1 V mV Hz Hz % % mV VREF VREFLINE VREFTC Vbatt = 15V, Iref = 0 7< Vbatt < 24V -10C 2.5V and OVPH < 3.3V then the charging current is zero and the voltage at FCOMP remains the same. c) If OVPH > 3.3V then FCOMP is discharged to approximately 1V, SSV is also driven to VSS. AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller Figure 10. Ignition Flow Chart START Start 1 second timer F=Fmax Set SSV = 0V Yes No V(OVPH)> 3.3V No V(OVPL) > 2.5V Yes Timer End? Yes Yes V(OVPL) > 2.5V No Shutdown No Yes V(CSDET) < 1.25V Timer End? Yes V(CSDET) < 1.25V (after normal blanking and for 8 clk cycles) Yes No No No No F > Fmin? F > Fmin? No Yes F(new)=F(old) - delta Yes F(new)=F(old) - delta Start Up Side ------- | ------ Steady State Operation Side 17 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller Figure 11. Start Up and Steady State Waveform 3V BRIGHT * CT1 ** 1.25V CSDET 5V BLANKING INTERV AL BLANKING INTERVAL VBATTOK VDDOK } VALID OVPH>3.3V 2.5V (OVPL senses the CCFL voltage through a resistor or capacitor divider) then FCOMP stops increasing and the frequency remains constant. The frequency will remain constant until: OVPL < 2.5V OR.... OVPH > 3.3V (see below) OR...... The one second time period runs out and the circuit shuts down. If the voltage across the tube increases enough so that OVPH > 3.3V (as sensed through a resistor or capacitor divider) then FCOMP is pulled low (~1V), the switching frequency is increased, SSV is pulled low and the switching duty cycle goes to zero. It will remain in this state until: OVPH < 3.3V OR.... The one second time period runs out and the circuit shuts down. Ideally, during one of these states, the CCFL will strike, current will flow in the CCFL and the circuit will move from the start up mode into the steady state mode. Once an arc has struck, as sensed by CSDET > 1.25 volts, then the circuit will drive the CCFL at 100% brightness 19 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller The SSC pin is pulled to VSS everytime the lamp is turned off, whether for a dimming cycle, user shutdown or fault occurrence. It ramps up slowly depending on the size of capacitor C3 connected to the SSC pin (in steady state mode SSC1ST is high impedance so capacitor C31 has no effect). The period of time when the b) and c) fault checks are disabled is called the b lanking? time. The blanking time occurs from the time SSC is pulled to VSS until it reaches 3V. See Figure 9 for some idealized waveforms illustrating the behavior just described. Control Algorithm There are 2 major control blocks (loops) within the IC. The first loop controls the duty cycle of the driving waveform. It senses the CCFL current (Figure 1 or 2, resistor R9 and R10) rectifies it, integrates it against an internal reference and adjusts the duty cycle to obtain the desired power. This loop uses error amplifier EA1 whose negative input is pin FB and whose output is COMP. The positive input of EA1 is connected to a 2.5V reference. External components, R7 and C8, set the time constant of the integrator, EA1. In order to slow the response of the integrator increase the value of the product: (R7 X C8). The second control block adjusts the brightness by turning the lamp on and off at varying duty cycles. Each time the lamp turns on and off is referred to as a ” dimming cycle” . At the end of each dimming cycle the SSV pin is pulled low with a 10uA current source, this forces COMP low as well due to the clamping action of Clamp1 shown in Figure 1. At the beginning of a new dimming cycle COMP tries to increase quickly but it is clamped to the voltage at the SSV(soft-start voltage) pin. A capacitor on the SSV pin (C8, Figure 1), which is discharged at the end of every dimming cycle, sets the slew rate of the positive and negative edge of the voltage at the SSV pin, and hence also the maximum positive (and negative) slew rate of the COMP pin. ” Dimming cycle” is explained more fully below] The BRIGHT, CT1 and BRPOL pins A user-provided voltage at the BRIGHT pin is compared with the ramp voltage at the CT1 pin (See Figure 12). If BRPOL is tied to VSS then as the voltage at BRIGHT increases the duty cycle of the dimming cycle and the brightness of the CCFL increase. If BRPOL is tied to VDD then the brightness of the CCFL diminishes as the BRIGHT voltage increases. The frequency of the dimming cycles is set by the value of the capacitor at pin CT1 (C4 in Figure 1 and 2) and it is also proportional to the current set by resistor R2. Setting C4 equal to 0.047uF and R2 equal to 47.5k yields a dimming cycle frequency of approximately 125Hz. The frequency should vary inversely with the value of C4 according to the relation: Frequency(Hz) = 1/[4 X R2 X C4] The brightness may also be controlled by using a variable resistor in place of R10 (See Figure 13). In this case the BRIGHT pin should be pulled to VDD so that the CCFL remains on constantly. This method can lead to flicker at low intensities but it is easy to implement. Harmonic distortion may also increase since the duty cycle of the waveform at the gate of Q2 will vary greatly with brightness. When using burst brightness control the duty cycle of the driving waveforms should not vary because the CCFL is running at 100% power or it is turned off. As long as the battery voltage does not change the duty cycle of the driving waveform also does not change greatly. This means that harmonic distortion can be minimized by optimizing the frequency and transformer characteristics for a particular duty cycle rather than a large range of duty cycle. 20 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller Figure 12. Duty Cycle Dimming Outside Chip Inside Chip BRPOL BRIGHT CHOP + - Brightness control voltage CT1 CHOP causes the CCFL to turn on and off periodically by charging and discharging SSV. SSV, in turn, pulls the COMP pin low, periodically turning off the CCFL. + - 3V C4 50mV S Q R + Figure 13. Alternative Brightness Control Inside Chip Outside Chip BRPOL T1 BRIGHT CHOP Always Hi 5V CT + This method disables duty cycle dimming - K Maximum current= R 1//(2R+R) COMP K FB RF 2.5V 2R R1 R-C-D optional network R2 Minimum current= (R 1+R2)//(2R+R) To PWM Comparator EA1 - + + To Fault Control Logic - CSDET R 1.25V 21 AME, Inc. AME9003 RT2, RDELTA pin nary limi Pre CCFL Backlight Controller The frequency of the drive signal at the gate of Q2 is determined by the VCO shown in Figure1. A detail of the VCO is shown in Figure 14. The user sets the minimum oscillator frequency with the resistor connected to pin RT2 (R2 in the figures). The relation is: Frequency (Hz) = 2.8E9 / R2 (ohms) You can see from the formula that as R2 is increased the frequency gets smaller. Resistor R3 controls how much the oscillator frequency increases as a function of the voltage at FCOMP. The relationship is: Delta frequency (Hz) = 3.44E8 * (5 - V(FCOMP)) / R3 You can see from the formula that the frequency will decrease as the FCOMP voltage increases. The amount of this increase is set by R3. The current in R3 decreases as the voltage at FCOMP increases and hence decreases the charging current into the timing capacitor of Figure 14 thereby decreasing the oscillator frequency. Supply voltage pins, VDD and PNP Most of the circuitry of the AME9003 works at 5V with the exception of one output driver. That driver (OUTA) and its power pad (VBATT) must operate up to 24V although the OUTA pad may never be forced lower than 8 volts away from the VBATT pin. The OUTA pin is internally clamped to approximately 7.5 volts below the Vbatt pin. The AME9003 uses an external PNP device to provide a regulated 5V supply from the battery voltage (See Figure 15). The battery voltage can range from 7V< VBATT < 24V. The PNP pin drives the base of the external PNP device, Q1. The VDD pin is the 5V supply into the chip. A 4.7uF capacitor, C7, bypasses the 5V supply to ground. If an external 5V supply is available then the external PNP would not be necessary and the PNP pin should float. When the CE pin is low ( 3.3V fault check is always enabled after the initial start up period.) At the beginning of the next dimming cycle the SSC pin is pulled to VSS then allowed to ramp upwards again. During steady state operation the SSV pin is pulled to ground with a 10uA current source before the beginning of every dimming cycle. As the dimming cycle starts the SSV pin sources 10uA into external capacitor, C14. This creates a 0 to 5 volt ramp at the SSV pin. This ramp is used to limit the duty cycle of the PWM gate drive signal available at the OUTA pin. The SSV pin accomplishes duty cycle limiting by clamping the COMP voltage to no higher than the SSV voltage. Because the magnitude of the COMP voltage is proportional to the duty cycle of the PWM signal at OUTA the duty cycle starts each dimming cycle at zero and slowly increases to its steady state value as the voltage at SSV increases. At the end of the dimming cycle the SSV pin sinks 10uA out of cap C14 which causes the SSV pin to ramp towards zero, which in turn causes COMP to ramp to zero, which limits the duty cycle and ultimately turns off the lamp for that dimming cycle. (Figure 9 shows this operation.) During the initial start up mode the SSV pin starts at zero volts and ramps up to 5V just as in steady state operation. However, during the start up mode, if OVPH > 3.3V then SSV is pulled to VSS and only allowed to ramp up when OVPH < 3.3V. This action sets the duty cycle back to 0 volts then allows the duty cycle to increase as the SSV voltage increases. This type of duty cycle limiting is commonly called ” soft-start ” operation. Soft start operation lessens overshoot on start up because the power increases gradually rather than immediately. Besides ramping up slowly, the SSV pin also ramps down slowly too. This allows for a ” soft-finish” as well as a ” soft_start ” . A ” soft-finish” is very useful for minimizing audible vibrations that may occur when using duty cycle dimming. Unlike the SSC pin the current sourced or sunk by the SSV pin remains approximately 10uA during ALL dimming cycles. In order to enable the first two fault condition checks then the OVP pin must, indirectly, sense the high voltage at the input of the CCFL. The actual CCFL voltage must be reduced by using either a resistor or capacitor divider such that in normal operation the voltage at OVPL is lower than 2.5V and the voltage at OVPH is lower than 3.3V. The third fault condition check can be used to monitor the CCFL current. Specifically, it checks whether the voltage at the CSDET pin is higher than 1.25V. If CSDET does not cross its 1.25V threshold once during 8 successive clock cycles then this fault will be triggered. (Remember that the clock frequency is twice as fast as the driving frequency of the CCFL). This protection is disabled while the SSC ramp is below 3V, such as at the beginning of every dimming cycle. This fault check is disabled during the start up mode, as are all the fault checks. This fault condition is used to check that a reasonable minimum amount of current is flowing in the tube. Figure 17 is a simplified schematic of the fault protection circuitry used in the AME9003. Most of the signals have been previously defined however some need a little explanation. The VDDOK signal is a power OK signal that goes high when the 5V supply (VDD) is valid. The CHOP signal stops the operation of the switching circuitry once every dimming cycle for burst mode brightness control. The output signal, FIRST, is high during the start up mode then is low during subsequent cycles. It causes the SSC pin to initially source 1000 times less current than on subsequent dimming cycles in order to provide the 1 second initial start up period. The NORM signal is an enable signal to the switching circuitry. When it is high the circuit works normally. When it is low the switching circuitry stops. SSC, SSC1ST and SSV pins Besides defining the initial 1 second start up period the SSC pin sprimary role is to define a time period in which the 2nd and 3rd fault conditions (previously described) are disabled. This period of time is called the blanking interval. During the initial start up period after a power on reset or just after a low to high transition on the CE pin the SSC pin sources 1.5uA into external capacitors, C3 and C31. At this time the SSC1ST pin is connected to VSS through an internal switch so the charging current out of SSC must charge the parallel combination of C3 and C31. For subsequent dimming cycles, after the initial startup period, the SSC pin sources 140uA and the SSC1ST pin is open circuited which means that 23 AME, Inc. AME9003 BATTFB nary limi Pre CCFL Backlight Controller The BATTFB pin is designed to sense the battery voltage and enable the pin OUTA. When the voltage at BATTFB is below 1.25 volts then OUTA is disabled, when the voltage at BATTFB is larger than 1.5V then OUTA is enabled. There is 250mV of hysteresis between the turn on and the turnoff thresholds. This pin does not disable any other portion of the circuit except the OUTA pin. Notably, the other two drivers, OUTAPB and OUTC continue to switch when the voltage at BATTFB is below 1.25V. Ringing Due to the leakage inductances of transformer T1 voltages at the drains of Q3 can potentially ring to values substantially higher than the ideal value (which is twice the battery voltage). The application schematic in Figure 17 uses a snubbing circuit to limit the extent of the ringing voltage. Components C9,R8,D2 and D3 make up the snubbing circuit. The nominal voltage at the common node is approximately twice the battery voltage. If either of the drains of Q3 ring above that voltage then diodes D2 or D3 forward bias and allow the ringing energy to charge capacitor C9. Resistor R8 bleeds off the extra ringing energy preventing the voltage at the common node from increasing substantially higher than twice the battery voltage. The extra power dissipation is: P(dissipated) = Vbatt2 / R8 For the example, in Figure 17, the power dissipation of the snubber circuit with Vbatt=15V is 58mW or approximately 1% of the total input power. The value of R8 can be optimized for a particular application in order to minimize dissipated power. Excessive ringing is usually a sign that the driving frequency is not well matched to the resonant characteristics of the tank circuit. In a well designed application a snubber circuit will not be necessary. Layout Considerations Due to the switching nature of this circuit and the high voltages that it produces this application can be sensitive to board parasitics. In fact, one of the advantages, of this design is that the circuit uses the parasitic elements of the application as resonant components, thus eliminating the need for more added components. Particular care must be taken with the different gounding loops. The best performance has been obtained by using a ” star” ground technique. The star technique re24 turns all significant ground paths back to the center of the ” star” . Ideally we would place the center of the star directly on the VSS pin of the AME9003. The bypass capacitors would, ideally, be connected as close to the center of the star as possible. The schematic in Figure 18 attemps to show this star ground configuration by bringing all the ground returns back to the same point on the drawing. Separate ground returns back to the star are especially important for higher current switching paths. AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller Figure 14. VCO Detail 1µA R3 Vco_Control VDD 0 I_in VDD RDELTA 2.5V OVPL 50:1 curent divider I_out 1.5V RT2 R2 VSS + - 0 RAMP 3.0V + - FCOMP C32 1µF OVPH CLK SSV Inside chip Outside chip 10µA 3.3V Figure 15. LDO Detail Inside Chip Outside Chip PNP 1 R4 Q1 VBATT V DDOK 2 - To Fault Logic VDD 27 < VBATT < 24 + EN 2.5V Start UP CE To user enable circuitry C7 4.7µF 25 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller Figure 16. OUTA Driver Circuitry Inside Chip Vbatt Outside Chip BV=5V BV=4V BV=7.5V OUTA PWM SIGNAL External PMOS, Q2 100nS 100nS 1mA 26 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller Figure 17. Fault Logic CE VD D VDDOK POR BATTFB 1.25V + - CLK/2 SSC 1.25V CSDET OVPL 2.5V SSC 3.0V OVPH 3.3V + - RES 2Bit Counter Q L1 S Q NORM RES_SSC L2 R SSV + - BLK_CS BLNK CHOP OUT + S Q RES_SSV FIRST R S Q RES_FCOMP R 20uA + - L3 VDDOK EN RES Q CT1 C4 Dimming Oscillator 2 Bit Shift D VDD BRIGHT BRPOL FCOMP + CHOPIN 27 AME, Inc. AME9003 Application Component Description nary limi Pre CCFL Backlight Controller Figure 18 shows one typical application circuit for driving 4 tubes. Similar component designations are used on similar components both in figure 2 and Figure 18 as well as throughout this application note. R1 - Weak pull up for the chip enable (CE) pin. The voltage at CE will normally rise to 5 volts for a 12V supply. Pull down on the CE node to disable the chip and put it into a zero Idd mode. If the user wishes to drive node CE with 3.3 or 5.5 volt logic then R1 is not necessary C1 - This capacitor acts to de-bounce the CE pin and to slow the turn on time when using R1 to pull up CE. This can be useful when the battery power is disconnected from the circuit in order to turn the circuit off, when the battery is reconnected the chip does not immediately turn on which allows the battery voltage to stabilize before switching starts. If the user is actively driving the CE pin then the C1 capacitor may not be necessary. R3 - This resistor connected to the RDELTA pin determines how much the oscillator frequency will change with battery voltage. The relation, which is found earlier in the text, is: Delta frequency (Hz) = 3.44e8 * (5 - V(FCOMP)) / R3 C2 - This 1uF capacitor bypasses and stabilizes the internal reference C3, C31 - These two capacitors determine the length of the blanking interval at the beginning of every dimming cycle. At the end of every dimming cycle these capacitors are discharged to VSS then allowed to charge up at a rate controlled by its internal current source and the values of C3 and C31. When the voltage on pin SSC crosses 3 volts the blanking interval is over and all fault checks are enabled. The charging current out of pin SSC is normally 140uA but for the very first cycle after the chip is enabled the current is only 1.5uA. During the first cycle of operation one side of C31 is tied to VSS through the SSC1ST pin. This means that during the first cycle the effective capacitance on the SSC pin is C3 + C31. For subsequent cycles the SSC1ST pin reverts to a high impedance state that effectively removes C31 from the circuit. The larger effective capacitor value plus the lower charging current (1.5uA) determines the duration of the intial start up period (nominally 1 second) and is given by the relation: 28 And for subsequent dimming cycles the blanking interval is: T(seconds) = (C3) * (3volts) / (140e-6amps) R2 - R2 sets the frequency of the oscillator that drives the FETs. The relation between R2 and frequency, that was found previously in the text, is: Frequency (Hz) = 2.8e9/R2 R2 = 56K yields approximately 50khz Note: that this is the frequency of the NMOS(Q3) gate drive. The PMOS(Q2) gate drive is exactly twice this value. R4 - This resistors pulls the base of Q1 up to Vbatt. Coupled with Q1 and C7 it is part of the 5V regulator that supplies the working power to the AME9003. When the PNP pin is turned off the base of Q1 is pulled high through R4, turning off Q1 and allowing the voltage at the VDD node (VSUPPLY) to decay towards zero. Q1 - This common PNP transistor (2n3906 is adequate) forms part of the 5V linear regulator which supplies power to most of the AME9003. R6 - This resistor, together with adjustable resistor R20, form a resistor divider that divides the regulated 5V down to some lower voltage. That lower voltage is used to drive the BRIGHT pin which, in turn, determines the duty cycle of the the dimming cycles and therefore the brightness of the lamps. If the user is driving the BRIGHT pin with his/her own voltage source then R6 and R20 are not necessary. C6 - This capacitor bypasses the BRIGHT pin. A noisy BRIGHT pin can cause unwanted flicker. R20 - see description of R6 C14 - Note that the 9003 has a ” soft finish” as well as a ” soft start ” feature. This capacitor sets the slope of the soft-start (soft-finish) ramp on pin SSV. The voltage at SSV limits the duty cycle of the Q2 gate drive signal available at pin OUTA. The voltage at the COMP node is internally clamped to the SSV node. Therefore the C14 cap limits how fast SSV, and hence, COMP can increase (and decrease). Limiting COMP sincrease (decrease) will limit the rate of increase (or decrease) of the switching duty cycle thereby creating a ” soft start (soft finish)” effect. The charging/discharging current out of SSV is approximately 10uA so the rate of change of the SSV voltage is: SSV(Volts/sec) = (10e-6amps) / C14 T(seconds) =( C3+C31) * (3volts) / (1.5e-6amps) AME, Inc. AME9003 C5 - This is the main battery bypass capacitor. nary limi Pre CCFL Backlight Controller R9A, R10 - The sum of R9A and R10 sets the current in one CCFL tube. As the sum of R9A and R10 decreases the tube current goes up, as the sum of R9A and R10 increase the tube current goes down. The RMS tube current is roughly: Irms = 6V / (R9A + R10) R9A and R10 also form a voltage divider that drives the CSDET pin. The purpose of the voltage divider is to keep the maximum voltage at CSDET under 5 volts under all conditions. The CSDET pin checks to see if there is any current in the CCFL. If the voltage at CSDET is larger than 1.25V once every clock cycle then the AME9003 assumes there is current in the CCFL and allows operation to continue. CSDET is also used to detect when the CCFL first strikes during the initial start up period. D4,D5 - These diodes rectify the current through the CCFL to provide a positive voltage for regulation by the error amplifier, EA1. The following components are only used for multiple tube operation: Q4,Q5 - These bipolar devices buffer the gate of Q2. That allows Q2 to be made much bigger without dissipating more power or increasing the cost of the AME9003. Q4 is an NPN transistor and Q5 is a PNP transistor. R35,R36,D16 etc. - These devices form a voltage divider and rectifier combination to sense higher than normal CCFL operating voltages. ( This operation is explained in more detail below.) You can diode "OR" as many of these divider/rectifier circuits as you have different CCFLs. Each time you add another double output transformer you must add another set of these resistors and diode networks. ( This operation is explained in more detail in the next section.) D20, D21, R42, R40 and C34 etc. - These devices are not strictly necessary for single tube operation. In single tube operation the junction of R9A and R10 can be directly fed into the CSDET pin. However for multiple tube operation these devices are necessary to allow for any one of the different tubes to be able to pull CSDET below 1.25V and allow a fault to be detected. Figure 1, a single tube application, has these devices included in order to facilitate the transition to multiple tube design as well as working quite well for the single tube application. 29 C4 - This capacitor sets the frequency of the dimming cycles according to the relation: Dim Cycle Freq(Hz) = 1 / [(4) * (R2) * (C4)] Note that the frequency is also a function of R2. So the frequency of the main oscillator and the frequency of the dimming oscillator are not independent. C7 - This capacitor is the load capacitor for the 5V linear regulator. As such it also bypasses the 5V supply and should be laid out as close to the AME9003 as possible. C8 - This capacitor, in combination with resistor R7, determines the time constant for the error amplifier (integrator) EA1. The integrator is the primary loop stabilizing element of the circuit. In general this application is tolerant of a large range of integrator time constants. Increase the (C8 X R7) product to slow down the loop response. R7 - see C8 D6 - This diode can catch any negative going spikes on the drain of Q2. This diode is NOT strictly necessary. This is NOT a freewheeling diode such as in a buck regulator. Since the primary windings are tightly coupled to each other the body diodes of Q3-1 and Q3-2 keep their own drains clamped to VSS as well as the drain of Q2. The spikes that diode D6 may catch are of short duration and small energy. Q2 - This is a PMOS device. By modulating its gate drive duty cycle the power into the transformer, and then into the load, can be controlled. The breakdown of this device must be higher than the highest battery voltage that the application will use. The peak current load is roughly twice the average current load. Q3-1, Q3-2 - These are NMOS devices. They are driven alternately with 50% duty cycle gate drive. The frequency of the gate drive is one half of the gate drive frequency of Q2. The gate drive is from 0 to 5 volts. The breakdown voltage of these devices must be at least twice the highest battery voltage. Peak current is roughly twice the average supply current. C9,R8,D2,D3 - These devices form a snubber circuit that can dissipate ringing energy. The snubber circuit is not strictly necessary. In fact a well designed circuit should not require these devices. (These elements were described in more detail earlier.) AME, Inc. AME9003 Multiple Tube Operation nary limi Pre CCFL Backlight Controller The AME9003 is particularly well suited for multiple tube applications. Figure19 shows the power section of a two tube application. The major difference between this application and the single tube application is the addition of another secondary winding on the transformer. The primary side of the transformer and its associated FETs are exactly the same as the single tube case although the FETs may need to be resized due to the increased current in two tube applications. The secondaries are wound so that the outputs to the CCFL are of opposite phase (see Figure 20) although this is not strictly necessary. When the voltage at one secondary output is high (+600 volts) the other secondary output should be low (-600 volts). The other secondary terminals are connected to each other. In a balanced circuit the voltage at the connection of the two secondaries will, ideally, be zero. Of course in a real application the voltage at the connection of the two secondaries will deviate somewhat from zero. The multi-tube configuration is modular. Since each double transformer can drive two CCFLs it is possible to construct 2, 4, 6..... tube solutions using the basic architecture. Of course the FETs must be properly sized to handle the increased current. Figure 21 shows a 4 tube application. In this configuration the common secondary connection (the node NOT connected to the lamp) is made with the opposite transformer. In this way the secondary current from the winding on the first transformer should be equal to the secondary current of its companion winding on the second transformer. In the case of 4 lamps driven by two transformers there are two sets of common secondary nodes. Sensing the current in the multiple tube case requires some extra circuitry. Normally the CSDET pin checks for the existence (or absence) of current in the CCFL. If current is detected then the initial start mode terminates and steady state operation begins. During steady state operation if no current is detected for 8 consecutive clock cycles then the circuit is shutdown. Since there is only one CSDET pin yet there are multiple tubes extra circuitry is required. Take the two tube case of Figure 19 for example. The current through the tube on the right hand side is regulated by the integrator made of R7, C8 and EA1. However, for purposes of fault detection and strike detection it is beneficial to monitor the current through both tubes. In this case R9B senses the current in the left tube in the same way R9A senses the current in the right hand tube. If the current through either tube is zero then R9A or R9B 30 will try to pull node A or B to zero. Resistors R42 and R43 attempt to pull node A and B up but the value of R42 and R43 (nominally 10K) is much larger than the values of resistors R9A and R9B (nominally 221ohms) allowing node A and B to pull close to VSS when there is zero current in their respective CCFL tubes. The absence of current in either tube essentially pulls node A or B to VSS. In normal operation the voltage at nodes A and B should look like alternating, positive half sinusoids. (See figure 22.) If, however, there is no current flowing in one of the tubes then one half of the sinusoids would be missing and the voltage at CSDET would drop compared to its normal value. The values of the RC network made up of R4 and C34 are chosen so that the voltage at CSDET is always larger than 1.25 volts when both half sinusoids are present but is less than 1.25V when only one sinusoid is present. The concept can be applied to any even multiple of tubes. The tube without the current will dominate the voltage at CSDET so a failure in any single tube will cause the circuit to shutdown. In a similar manner, during start up all tubes must have current flowing in them before CSDET will rise above 1.25V and signal that the tubes have struck and that the initial start up mode is over. For every 2 extra tubes that need to be added the user must add one more transformer, and two resistor divider networks plus two diodes (R35, R36, R37, R38, D16, D17) to sense the CCFL voltage as well as two more diodes and two more resistors to sense the tube current (R9A, R9B, D20, D22). Resistors R42, R43, R40, diodes D21, D23 and capacitor C34 do not need to be replicated every time more CCFLs are added because they are shared in common on the CSDET node. Figure 18 shows a complete four tube schematic. Figure 21 shows a detail of the current and voltage sensing circuitry for the four tube application. Analogous components have been given the same numbers as in the single tube schematic. There is really very little difference between the the single tube configuration and the multitube version. Transistors Q4 and Q5 are added to buffer the high side drive OUTA. This may be necessary because the PMOS devices for larger current applications have larger gate drive requirements. The MOS transistors are sized bigger for the 4 tube application as would be expected. The peak currents are much higher so the Vbatt bypassing capacitor must be increased as well. The schematic shows C5 as a 100uF capacitor but higher values such as 220uF are not uncommon in order to minimize ripple on Vbatt. AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller Figure 18. Four Tube Application Schematic BATT R4 2K Q1 PNP R1 1Meg 2N3906 1 Q4 NPN 2N3904 3 R8 C9 1uF Q2 5602 3.9k Q5 PNP 2N3906 R6 SNUB 2, 4 D2 IN914 D3 IN914 BRIGHT 51k 10 10 3 3 4 9 4 9 T1 2XTRANS 12 12 2 2 5 7 5 7 T2 2XTRANS R3 15k LX C2 1uF U 1 Vref 1 2 AME9003 Vref CE SSC RDELTA SSC1ST RT2 VSS OVPH OVPL FCOMP CSDET BATTFB PNP SSV BRIGHT COMP FB CT1 VDD VDD1 VBATT OUTA OUTAPB OUTC 14 13 24 23 22 21 20 19 18 17 16 15 CE 3 C3 4 0.047uF R2 C1 0.1u R40 60K 40k C31 0.47uF C8 47nF R7 VDD 30.1k R20 C14 1000p 100k Q3-1 IRFR3303 Q3-2 IN914 R10 680 R35 IRFR3303 D5 IN914 R37 R39 R51 D19 D18 D17 D16 R36 C6 0.1uF C7 4.7uF 303 D6 1N5819 R9A 221 R9B 221 R38 R9C 221 R50 R52 R9D 221 D4 OUT-1 5 6 7 8 9 10 C32 2200p 11 12 R41 10K C4 C5 + 0.047uF 100uF VDD D20 D21 D22 D23 D24 D25 D26 R42 1 0k R43 1 0k R40 7.5 k C34 0 .0 1u 31 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller Figure 19. Double CCFL Power Section VB att OUTA Q2 T1 OUTB Q3-1 Q3-2 OUTC OVPL/OVPH R37 R38 R35 R36 OVPL/OVPH C8 Outside Chip D5 (B) R9B D22 D23 R42 (C) D4 R10 (A) D21 D20 R9A R43 1.25V R7 FB EA1 COMP Inside Chip 2.5V CSDET To PWM Comparator To Fault Logic VDD R40 C34 Figure 20. Double transformer construction detail Low voltages Secondary Primaries Secondary Large Positive (Negative) Voltage Large Negative (Positive) Voltage Common Core 32 Low voltages in the center AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller Figure 21. Four Tube Power Section VDD R42 OUTA T2 R35 R36 R43 D26 R9D R37 Q2 V Batt R39 R50 D23 D22 R9C R38 D24 D25 R9B R51 OUTAPB Q3-1 T1 To R7 and C8 integrator C34 OUTC Q3-2 R10 R9A D20 D21 D4 D5 R52 R40 To OVPL OVPH To CSDET 33 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller Figure 22. Normal Operation (Filtered Voltage > 1.25V è No Fault) NODE A NODE B unfiltered 1.25 NODE C filtered One Tube Missing Operation (Filtered Voltage < 1.25V è Fault) NODE A NODE B No Current in TUBE B unfiltered NODE C 1.25 filtered 34 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller n Package Dimension QSOP24 Top View D SYMBOLS A A1 E1 E MILLIMETERS MIN 1.524 0.101 INCHES MIN 0.060 0.004 MAX 1.752 0.228 MAX 0.069 0.009 A2 b b1 c c1 D ZD E E1 L 1.473REF 0.203 0.203 0.177 0.177 8.559 0.304 0.279 0.254 0.228 8.737 0.058REF 0.008 0.008 0.007 0.007 0.337 0.012 0.011 0.010 0.009 0.344 Bottom View K 0.838REF 5.791 3.810 0.406 6.197 3.987 1.270 0.033REF 0.228 0.150 0.016 0.244 0.157 0.050 J L1 e J Side View ZD A2 A b e See Detail A 0.254BSC 0.635BSC 1.27REF 1.27REF 0 5 0 o o o 0.010BSC 0.025BSC 0.050REF 0.050REF K θ θ1 θ2 A1 8 o o 0 5 0 o o o 8 o o 15 o 15 o R 0.33 x 45 0.013 x 45 End View Detail A b1 θ1 R θ2 L1 c1 (c) c L θ (b) 35 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller n Package Dimension SOIC24 Top View SYMBOLS E H MILLIMETERS MIN MAX 2.65 0.30 2.31 0.51 0.32 15.60 7.60 INCHES MIN 0.092 0.004 0.089 0.013 0.009 0.598 0.291 MAX 0.104 0.012 0.091 0.020 0.013 0.614 0.299 A A1 Pin No.1 Indentifier 2.35 0.10 2.25 0.33 0.23 15.20 7.40 A2 B C Bottom View D E e H L θ 1.27BSC 10.00 0.40 0 o 0.050BSC 0.394 0.016 0 o 10.65 1.27 8 o 0.419 0.050 8 o Side View D A2 e B A1 A End View Detail A C See Detail A θ L 36 AME, Inc. AME9003 nary limi Pre CCFL Backlight Controller n Package Dimension PDIP24 (300mil) Top View D SYMBOLS A A1 A2 B B1 C MILLIMETERS MIN MAX 4.31 INCHES MIN 0.146 0.020 0.126 0.014 MAX 0.170 E 3.71 0.51 3.20 0.36 3.60 0.56 0.142 0.022 1.27 TYP 0.204 29.25 6.20 0.36 29.85 6.60 0.050 TYP 0.008 1.152 0.244 0.014 1.175 0.260 Side View D E e A L B1 B A2 A1 E1 e L E2 7.62 TYP 2.54 TYP 3.00 8.20 3.60 9.40 0.300 TYP 0.100 TYP 0.118 0.323 0.142 0.370 End View E1 C E2 37 www.ame.com.tw E-Mail: sales@ame.com.tw Life Support Policy: These products of AME, Inc. are not authorized for use as critical components in life-support devices or systems, without the express written approval of the president of AME, Inc. AME, Inc. reserves the right to make changes in the circuitry and specifications of its devices and advises its customers to obtain the latest version of relevant information. © AME, Inc. , March 2005 Document: 2023-DS9003-D Corporate Headquarter AME, Inc. 2F, 302 Rui-Guang Road, Nei-Hu District Taipei 114, Taiwan. Tel: 886 2 2627-8687 Fax: 886 2 2659-2989 U.S.A.(Subsidiary) Analog Microelectronics, Inc. 3100 De La Cruz Blvd., Suite 201 Santa Clara, CA. 95054-2046 Tel : (408) 988-2388 Fax: (408) 988-2489