AP4410AECHJ

[AP4410AEC] AP4410AEC Ultra Low Power Dual Voltage Detector 1. General Description The AP4410AEC is a voltage detector IC for monitoring battery, power supply and system voltage. The circuit includes dual voltage detection with built-in gate logic and MOSFETs. The AP4410AEC offers ultra-low power consumption that is 0.026μA per channel. The built- in CMOS logic circuit can be controlled independently from the voltage detector. The polarity of the voltage detection results is controlled by pins. This function enables the AP4410AEC as a load switch by using the results of the voltage detection. The AP4410AEC achieves better performance and PCB area than conventional CMOS voltage detector ICs, with discrete logics and external MOSFETs. The AP4410AEC is ideal for voltage conversion or load switch of thin and small wearable devices, over charge/discharge protection of Lithium-ion batteries, power management part of energy harvesting applications. 2. Features  Power management function Dual voltage detection circuits Control logic with independent power supply Built in P-channel MOSFETs and N-Channel MOSFETs for each channel  Wide range for detection voltage Detection voltage “High” 1.8 to 2.7V (Options) Detection voltage “Low” 1.7 to 2.65V (Options)  Voltage detection accuracy ±35mV  Ultra-low power consumption 0.026μA typical/ch. 0.050μA maximum/ ch  Response Speed 500μs maximum  On resistance On-chip P-channel MOSFETs 1Ω typical On-chip N-channel MOSFETs 2Ω typical  Operation temperature -40 - +85 °C  Package 20-pin WLCSP (1.955×1.555mm, 0.4mm pitch) 017010700-E-01 -1- 2018/6 [AP4410AEC] 3. Table of Contents 1. 2. 3. 4. 5. General Description ............................................................................................................................. 1 Features............................................................................................................................................... 1 Table of Contents ................................................................................................................................ 2 Block Diagram ..................................................................................................................................... 3 Pin Configuration and Function ........................................................................................................... 4  Pin Configuration ............................................................................................................................. 4  Function ........................................................................................................................................... 4 6. Absolute Maximum Ratings................................................................................................................. 5 7. Recommended Operating Conditions ................................................................................................. 5 8. Electrical Characteristics ..................................................................................................................... 6 9. Description........................................................................................................................................... 7  Voltage Detection Function .............................................................................................................. 7 10. Reference Data ................................................................................................................................ 9  Detection Voltage “High” (VDETH) and “Low” (VDETL) vs VIN ...................................................... 9  Detection Voltage “High” (VDETH) and “Low” (VDETL) vs Ta...................................................... 10  Current consumption vs VIN & VDD ............................................................................................. 11  Power Comsumption vs Ta (VIN=VDD=5.5V) .............................................................................. 11  Response time (tPLH, tPHL) ......................................................................................................... 12 11. Package ......................................................................................................................................... 16  Outline Dimensions ........................................................................................................................ 16  Marking .......................................................................................................................................... 16 12. Revision History ............................................................................................................................. 17 IMPORTANT NOTICE.............................................................................................................................. 18 017010700-E-01 -2- 2018/6 [AP4410AEC] 4. Block Diagram Channel 1 Channel 2 Figure 1. Block Diagram 017010700-E-01 -3- 2018/6 [AP4410AEC] 5. Pin Configuration and Function  Pin Configuration ・20-pin WLCSP TOP View  4 VIN1 EN1 TEST4 EN2 VIN2 3 OUT1 TEST1 TEST3 TEST5 OUT2 2 VDD1 POL1 TEST2 POL2 VDD2 1 PMOS1D NMOS1D VSS NMOS2D PMOS2D A B C D E Function WLCSP Pin A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 E1 E2 E3 E4 Pin Name PMOS1D VDD1 OUT1 VIN1 NMOS1D POL1 TEST1 EN1 VSS TEST2 TEST3 TEST4 I/O Input/Output Power Output Power Output Input Input Ground - NMOS2D POL2 TEST5 EN2 PMOS2D VDD2 OUT2 VIN2 Output Input Input Input / Output Power Output Power 017010700-E-01 Function PMOS drain pin (Channel 1) Power supply(Channel 1) Logic output (Channel 1) Detection input pin (Channel 1) NMOS1 drain pin(Channel 1) Polarity cotrol pin (Channel 1) For test purposes. This pin should be connected to VSS. Enable pin (Channel 1) Ground For test purposes. This pin should be connected to VSS. For test purposes. This pin should be connected to VSS. For test purposes. This pin should be connected to VSS. NMOS drain pin(Channel 2) Polarity cotrol pin (Channel 2) For test purposes. This pin should be connected to VSS. Enable pin (Channel 2) PMOS drain pin (Channel 2) Power supply(Channel 2) Logic output (Channel 2) Detection input pin (Channel 2) -4- 2018/6 [AP4410AEC] 6. Absolute Maximum Ratings Parameter Symbol min VIN1,VIN2, -0.3 VDD1,VDD2 OUT1,EN1,POL1 VSS-0.3 Pin Voltage OUT2,EN2,POL2 VSS-0.3 (Note 1) PMOS1D -0.3 PMOS2D NMOS1D -0.3 NMOS2D Power dissipation Pd Storage Temperature Tstg -55 Note 1. All voltages are with reference to VSS = 0 V. max Unit 6.5 V VDD1 + 0.3 VDD2 + 0.3 V V 6.5 V 6.5 V 0.8 150 W C WARNING: Stresses exceeding Maximum Ratings may damage the device. Normal operation is not guarantee if the condition exceeds the maximum rating. 7. Recommended Operating Conditions Parameter Operation Temperature Power Supply Volgtage 017010700-E-01 Symbol Ta VIN1 VIN2 VDD1 VDD2 -5- min -40 max 85 Unit C 1.3 5.5 V 2018/6 [AP4410AEC] 8. Electrical Characteristics (Ta= -40 - +85C, VIN1, VIN2, VDD1 and VDD2 =1.3V to 5.5V, OUT=open, PMOSD=open, NMOSD=open, unless otherwise specified.) Parameter Detection Voltage “High” Symbol min typ VDETH -0.035 max Unit VDETH +0.035 V VDETH -0.045 VDETH +0.045 V VDETL -0.035 VDETL +0.035 V VDETL +0.045 V VDETH VDETH Detection Voltage ”Low” VDETL VDETL VDETL -0.045 Power Consumption “High”Level Input Voltage “Low” Level Input Voltage EN pin reverse current (Push, Pull) IOH (Note 4) IOL(Note 4) Response Time (Note 5) IVIN - 0.026 0.050 μA IVDD (Note 2) (Note 3) - 0.0001 0.100 μA VIH VDD ×0.8 - - V VIL - - VDD ×0.2 V | IEN | 0.15 - μA IOH 0.15 - - mA IOL 0.2 - - 0.2 0.5 0.2 0.5 tPLH tPHL - Condition Ta=25C VIN= “L”→”H” Please refer 10. Reference data (Detection Voltage vs Ta) Ta=85C VIN= “L”→”H” Please refer 10. Reference data (Detection Voltage vs Ta) Ta=25C VIN= “H”→”L” Please refer 10. Reference data (Detection Voltage vs Ta) Ta=85C VIN= “H”→”L” Please refer 10. Reference data (Detection Voltage vs Ta) Consumption for VIN per channel while the voltage detection circuit is active. Please refer 10. Reference data (Current consumption vs VIN & VDD) Consumption for VDD1 and VDD2. Please refer 10. Reference data (Current consumption vs VIN & VDD) VIN=VDETH+0.1V, OUT=VDD-0.5V VIN=VDETL-0.1V, mA OUT=0.5V ms VIN=VDETH-0.1V→VDETH+0.1V VIN= VDETL+0.1V→VDETL-0.1V ms Please refer 10. Reference data (Response time) P-ch MOSFET RonP 1 2.3 Ω VDD≧1.7V On-resistance N-ch MOSFET RonN 2 5 Ω VDD≧1.7V On-resistance Note 2. Output drive is not included. Note 3. Total power consumption VDD1 and VDD2 (VDD1+VDD2). Note 4. Output current depends on VDD1 and VDD2. IOL shows N-Channel pull current when AP4410AEC OUT1/OUT2 output low. IOH shows P-Channel push current when AP4410AEC OUT1/OUT2 output high. Note 5. Response time for OUT1 pin and OUT2 pin 017010700-E-01 -6- 2018/6 [AP4410AEC] 9. Description  Voltage Detection Function VIN1 pin and VIN2 pin = (Abbreviation ;VIN) VDD1 pin and VDD2 pin = (Abbreviation ;VDD) POL1 pin and POL2 pin = (Abbreviation ;POL) EN1 pin and EN2 pin = (Abbreviation ;EN) 1) When the input volgatge is increasing, The OUT1 pin and OUT2 pin(Abbreviation ;OUT) will be in undefined status when VIN voltage is from VSS to AP4410AEC minimum operating voltage(1.3V). The AP4410AEC internal signal A(Please refer Figure 2) outputs VSS when VIN volgate exceeds minimum operating voltage. When VIN voltage reaches to the detection voltage (VDETH), the internal signal A outputs VIN voltage. 2) When the input voltage is decreasing, When VIN voltage is higher than VDETH, internal signal A outputs VIN. When VIN goes under the detection voltage (VDETL), OUT outputs VSS. The internal signal A will be undefined status when VIN voltege becomes lower than AP4410AEC minimum operating voltage(1.3V). The logic inputs POL and EN become valid when VDD voltage exceeds 1.3V which is the minimum operation voltage. In case of POL = “L”, EN=”H”, OUT behaves as Figure. 3. The AP4410AEC is able to output the inverted results of the voltage detection using POL. EN can control P-channel MOSFET and N-channel MOSFET ON and OFF. EN has latch function so that it keeps its present state if the input becomes Hi-Z. The BULK of the P-channel MOSFET is connected to the higher voltage pin between VDD and PMOSD. POL EN VDD PMOSD VIN VDETH/L OUT NMOSD VSS Figure 2. Block Diagram of Control Logic Part (Each channel) 017010700-E-01 -7- 2018/6 [AP4410AEC] VIN VDETH VDETL Minimum Operating Voltage VSS OUT VSS tPLH tPHL Figure 3.Function of AP4410AEC voltage detection Table 1. Control logic truth table (Note 6) POL input VIN EN input Internal signal A Internal signal B Internal signal C PMOSD NMOSD OUT Note L VINVDETL H H H L H OPEN L H VIN≦VDETL H L L H OPEN L H OUT= negative polarity H VIN≦VDETL L L L H OPEN L H - OUT= positive polarity Note 7. When the VIN voltage is decreasing from VDETH or higher. 017010700-E-01 -8- 2018/6 [AP4410AEC] 10. Reference Data  Detection Voltage “High” (VDETH) and “Low” (VDETL) vs VIN 1) VDETH=2.5V, VDETL=2.1V (POL=”L”) Figure 4. VDD=VIN Figure 5. VDD=5.5V 2) VDETH=1.8V, VDETL=1.7V (POL=”L”) Figure 6. VDD=VIN 017010700-E-01 Figure 7. VDD=5.5V -9- 2018/6 [AP4410AEC]  Detection Voltage “High” (VDETH) and “Low” (VDETL) vs Ta ΔVDET(mV) vs Ta Figure 8. ΔVDET(mV) vs Ta 1) ΔVDET(%) vs Ta Figure 9. ΔVDET(%) vs Ta Note 8. ΔVDET(%)=ΔVDET/ VDET (V) 017010700-E-01 - 10 - 2018/6 [AP4410AEC]  Current consumption vs VIN & VDD 1) VDETH=2.5V, VDETL=2.1V (POL=”L”) Figure 10. VDD=VIN Figure 11. VDD=5.5V 2) VDETH=1.8V, VDETL=1.7V (POL=”L”) Figure 12. IVDD  Figure 13. IVIN Power Comsumption vs Ta (VIN=VDD=5.5V) Figure 14. IVDD 017010700-E-01 Figure 15. IVIN - 11 - 2018/6 [AP4410AEC]  Response time (tPLH, tPHL) 1) VDETH=2.5V, VDETL=2.1V (POL=”L”) Figure 16. tPLH for VDETH=2.5V, VDETL=2.1V (POL=”L”), VDD=1.3V Figure 17. tPLH for VDETH=2.5V, VDETL=2.1V (POL=”L”), VDD=5.5V 017010700-E-01 - 12 - 2018/6 [AP4410AEC] Figure 18. tPHL for VDETH=2.5V, VDETL=2.1V (POL=”L”), VDD=1.3V Figure 19. tPHL for VDETH=2.5V, VDETL=2.1V (POL=”L”), VDD=5.5V 017010700-E-01 - 13 - 2018/6 [AP4410AEC] 2) VDETH=1.8V, VDETL=1.7V (POL=”L”) Figure 20. tPLH for VDETH=1.8V, VDETL=1.7V (POL=”L”), VDD=1.3V Figure 21. tPLH for VDETH=1.8V, VDETL=1.7V (POL=”L”), VDD=5.5V 017010700-E-01 - 14 - 2018/6 [AP4410AEC] Figure 22. tPHL for VDETH=1.8V, VDETL=1.7V (POL=”L”), VDD=1.3V Figure 23. tPHL for VDETH=1.8V, VDETL=1.7V (POL=”L”), VDD=5.5V 017010700-E-01 - 15 - 2018/6 [AP4410AEC] 11. Package  Outline Dimensions 20-pin WLCSP (Unit: mm) When the IC is exposed to light, it might affect the electrical characteristics of the IC due to the light sensitivity of WLCSP package structures.  Marking (1) (2) (3) (4) (5) (6) 0AXX (2) (3) Y WW Z (4) (5) (6) 1 Pin Indication Symbol of the detection voltage of system 1 Symbol of the detection voltage of system 2 Year code (last 1 digit) Week code Management code (1) 017010700-E-01 - 16 - 2018/6 [AP4410AEC] 12. Revision History Date (YY/MM/DD) 2017/09/07 2018/06/04 Revision 00 01 Page 1 6 7 8 16 017010700-E-01 Contents First Edition 1. General Description detection → detector 2. Features -40 - 85 °C → -40 - +85 °C 8. Electrical Characteristics -40 to 85 °C → -40 - +85 °C 8. Electrical Characteristics 5,5V → 5.5V 9. Description AP4410A→ AP4410AEC 9. Description incrasing→ increasing 9. Description Vref →VDET 9. Description incrasing→ increasing 11. Package updated - 17 - 2018/6 [AP4410AEC] IMPORTANT NOTICE 0. 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