ADVANCED
LINEAR
DEVICES, INC.
TM
e
®
EPAD
D
LE
AB
EN
ALD1726E
EPAD® ULTRA MICROPOWER CMOS OPERATIONAL AMPLIFIER
KEY FEATURES
BENEFITS
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EPAD (Electrically Programmable Analog Device)
User programmable VOS trimmer
Computer-assisted trimming
Rail-to-rail input/output
Compatible with standard EPAD Programmer
High precision through in-system circuit precision trimming
Reduces or eliminates VOS, PSRR, CMRR and TCVOS errors
System level “calibration” capability
Application-Specific Programming mode
In-System Programming mode
Electrically programmable to compensate for external
component tolerances
• Achieves 0.01pA input bias current and 50µV input offset
voltage simultaneously
• Compatible with industry standard pinout
• Eliminates manual and elaborate
system trimming procedures
• Remote controlled automated trimming
• In-System Programming capability
• No external components
• No internal chopper clocking noise
• No chopper dynamic power dissipation
• Simple and cost effective
• Small package size
• Extremely small total functional
volume size
• Low system implementation cost
• Micropower and Low Voltage
GENERAL DESCRIPTION
APPLICATIONS
The ALD1726E is a monolithic rail-to-rail ultra-micropower precision
CMOS operational amplifier with integrated user programmable EPAD
(Electrically Programmable Analog Device) based offset voltage adjustment. The ALD1726E is a direct replacement of the ALD1706 operational
amplifier, with the added feature of user-programmable offset voltage
trimming resulting in significantly enhanced total system performance and
user flexibility. EPAD technology is an exclusive ALD design which has
been refined for analog applications where precision voltage trimming is
necessary to achieve a desired performance. It utilizes CMOS FETs as incircuit elements for trimming of offset voltage bias characteristics with the
aid of a personal computer under software control. Once programmed, the
set parameters are stored indefinitely within the device even after powerdown. EPAD offers the circuit designer a convenient and cost-effective
trimming solution for achieving the very highest amplifier/system performance.
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The ALD1726E operational amplifier features rail-to-rail input and output
voltage ranges, tolerance to over-voltage input spikes of 300mV beyond
supply rails, extremely low input currents of 0.01pA typical, high open loop
voltage gain, useful bandwidth of 200KHz, slew rate of 0.17V/µs, and low
typical supply current of 25µA.
ORDERING INFORMATION (“L” suffix denotes lead-free (RoHS))
Operating Temperature Range
0°C to +70°C
0°C to +70°C
-55°C to +125°C
8-Pin
Small Outline
Package (SOIC)
8-Pin
Plastic Dip
Package
8-Pin
CERDIP
Package
ALD1726ESAL
ALD1726EPAL
ALD1726EDA
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Sensor interface circuits
Transducer biasing circuits
Capacitive and charge integration circuits
Biochemical probe interface
Signal conditioning
Portable instruments
High source impedance electrode
amplifiers
Precision Sample and Hold amplifiers
Precision current to voltage converter
Error correction circuits
Sensor compensation circuits
Precision gain amplifiers
Periodic In-system calibration
System output level shifter
PIN CONFIGURATION
8
VE2
7
V+
3
6
OUT
4
5
N/C
VE1
1
-IN
2
+IN
V-
2
TOP VIEW
SAL, PAL, DA PACKAGES
* N/C Pin is internally connected. Do not connect externally.
* Contact factory for leaded (non-RoHS) or high temperature versions.
Rev 2.1 ©2011 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, CA 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286
www.aldinc.com
FUNCTIONAL DESCRIPTION
USER PROGRAMMABLE VOS FEATURE
The ALD1726E uses EPADs as in-circuit elements for trimming of offset voltage bias characteristics. Each ALD1726E
has a pair of EPAD-based circuits connected such that one
circuit is used to adjust VOS in one direction and the other
circuit is used to adjust VOS in the other direction. While each
of the EPAD devices is a monotonically adjustable programmable device, the VOS of the ALD1726E can be adjusted
many times in both directions. Once programmed, the set
VOS levels are stored permanently, even when the device
power is removed.
Each ALD1726E has two pins named VE1 and VE2 which are
internally connected to an internal offset bias circuit. VE1/
VE2 have initial typical values of 1.0V to 1.5V. The voltage
on these pins can be programmed using the ALD E100 EPAD
Programmer and the appropriate Adapter Module. The
useful programming range of VE1 and VE2 is 1.2V to 3.0V.
The ALD1726E is pre-programmed at the factory under
standard operating conditions for minimum equivalent input
offset voltage. It also has a guaranteed offset voltage program range, which is ideal for applications that require
electrical offset voltage programming.
The ALD1726E is an operational amplifier that can be
trimmed with user application-specific programming or insystem programming conditions. User application-specific
circuit programming refers to the situation where the Total
Input Offset Voltage of the ALD1726E can be trimmed with
the actual intended operating conditions.
For example, an application circuit may have +6V and -2.5V
power supplies, and the operational amplifier input is biased
at +0.7V, and an average operating temperature at 55°C.
The circuit can be wired up to these conditions within an
environmental chamber with ALD1726E inserted into a test
socket connected to this circuit while it is being electrically
trimmed. Any error in VOS due to these bias conditions can
be automatically zeroed out. The Total VOS error is now
limited only by the adjustable range and the stability of VOS,
and the input noise voltage of the operational amplifier.
Therefore, this Total VOS error now includes VOS as VOS is
traditionally specified; plus the VOS error contributions from
PSRR, CMRR, TCVOS, and noise. Typically this total VOS
error term (VOST) is approximately ±50µV for the ALD1726E.
The VOS contribution due to PSRR, CMRR, TCVOS and
external components can be large for operational amplifiers
without trimming. Therefore the ALD1726E with EPAD
trimming is able to provide much improved system performance by reducing these other sources of error to provide
significantly reduced VOST.
VE1 and VE2 pins are programming pins, used during
programming mode to inject charge into the internal EPADs.
Increasing voltage on VE1 decreases the offset voltage
whereas increasing voltage on VE2 increases the offset
voltage of the operational amplifier. The injected charge is
permanently stored and determines the offset voltage of the
operational amplifier. After programming, VE1 and VE2
terminals must be left open to settle on a voltage determined
by internal bias currents.
During programming, the voltages on VE1 or VE2 are increased incrementally to set the offset voltage of the operational amplifier to the desired Vos. Note that desired Vos can
be any value within the offset voltage programmable ranges,
and can be zero, a positive value or a negative value. This
VOS value can also be reprogrammed to a different value at
a later time, provided that the useful VE1 or VE2 programming voltage range has not been exceeded. VE1 or VE2 pins
can also serve as capacitively coupled input pins.
Internally, VE1 and VE2 are programmed and connected
differentially. Temperature drift effects between the two
internal offset bias circuits cancel each other and introduce
less net temperature drift coefficient change than offset
voltage trimming techniques such as offset adjustment with
an external trimmer potentiometer.
While programming, V+, VE1 and VE2 pins may be alternately pulsed with 12V (approximately) pulses generated by
the EPAD Programmer. In-system programming requires
the ALD1726E application circuit to accommodate these
programming pulses. This can be accomplished by adding
resistors at certain appropriate circuit nodes. For more
information, see Application Note AN1700.
In-System Programming refers to the condition where the
EPAD adjustment is made after the ALD1726E has been
inserted into a circuit board. In this case, the circuit design
must provide for the ALD1726E to operate in normal mode
and in programming mode. One of the benefits of in-system
programming is that not only is the ALD1726E offset voltage
from operating bias conditions accounted for, any residual
errors introduced by other circuit components, such as
resistor or sensor induced voltage errors, can also be corrected. In this way, the “in-system” circuit output can be
adjusted to a desired level, eliminating the need for another
trimming function.
ALD1726E
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2 of 13
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V+
Differential input voltage range
Power dissipation
Operating temperature range SAL,PAL packages
DA package
Storage temperature range
Lead temperature, 10 seconds
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
10.6V
-0.3V to V+ +0.3V
600 mW
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25oC VS = ±2.5V unless otherwise specified
ALD1726E
Parameter
Symbol
Min
Supply Voltage
VS
V+
Typ
Max
Unit
Test Conditions
±1.0
±5.0
V
2.0
10.0
V
Single Supply
100
µV
RS ≤ 100KΩ
Initial Input Offset Voltage1
VOS i
Offset Voltage Program Range 2
∆VOS
Programmed Input Offset
Voltage Error 3
VOS
50
100
µV
At user specified
target offset voltage
Total Input Offset Voltage 4
VOST
50
100
µV
At user specified
target offset voltage
Input Offset Current 5
IOS
0.01
10
240
pA
pA
TA = 25°C
0°C ≤ TA ≤ +70°C
Input Bias Current 5
IB
0.01
10
pA
TA = 25°C
Input Voltage Range 6
VIR
V
V
V+ = +5V
VS = ±2.5V
Input Resistance
RIN
Input Offset Voltage Drift 7
TCVOS
7
Initial Power Supply
PSRR i
Initial Common Mode
Rejection Ratio 8
CMRR i
Large Signal Voltage Gain
AV
50
±10
±20
-0.3
-2.8
mV
5.3
+2.8
Ω
1014
µV/°C
RS ≤ 100KΩ
80
dB
RS ≤ 100KΩ
83
dB
RS ≤ 100KΩ
V/mV
V/mV
RL =1MΩ
0°C ≤ TA ≤ +70°C
RL =1MΩ V+ = 5V
0°C ≤ TA ≤ +70°C
Rejection Ratio 8
32
100
20
Output Voltage Range
Output Short Circuit Current
VO low
VO high
4.99
VO low
VO high
2.40
ISC
0.001
4.999
0.01
V
V
-2.48
-2.40
V
RL =100KΩ
2.48
V
0°C ≤ TA ≤ +70°C
200
µA
* NOTES 1 through 9, see "Definitions and Design Notes" on page 6.
ALD1726E
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3 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
TA = 25oC VS = ±2.5V unless otherwise specified
Min
1726E
Typ
Parameter
Symbol
Supply Current
IS
Power Dissipation
PD
Input Capacitance
CIN
1
pF
Maximum Load Capacitance
CL
25
pF
Equivalent Input Noise Voltage
en
55
nV/√Hz
f = 1KHz
Equivalent Input Current Noise
in
0.6
fA/√Hz
f =10Hz
Bandwidth
BW
400
KHz
Slew Rate
SR
0.17
V/µs
AV = +1
RL = 1MΩ
Rise time
tr
1.0
µs
RL = 1MΩ
20
%
RL = 1MΩ,
CL = 25pF
10
µs
0.1%
AV = 1,RL=1MΩ
CL = 25pF
Unit
Test Conditions
25
Overshoot Factor
Settling Time
ts
Max
Unit
Test Conditions
40
µA
VIN = 0V
No Load
200
µW
VS = ±2.5V
TA = 25oC VS = ±2.5V unless otherwise specified
1726E
Parameter
Symbol
Average Long Term Input Offset
Voltage Stability 9
∆ VOS
∆ time
Initial VE Voltage
VE1 i, VE2 i
Programmable VE Range
∆VE1, ∆VE2
Programmed VE Voltage Error
e(VE1-VE2)
VE Pin Leakage Current
ieb
ALD1726E
Min
Typ
0.02
Max
µV/
1000 hrs
1.0
1.0
V
2.0
V
0.1
%
-5
µA
Advanced Linear Devices
4 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
VS = ±2.5V -55°C ≤ TA ≤ +125°C unless otherwise specified
1726E
Parameter
Symbol
Min
Typ
Max
Initial Input offset Voltage
VOS i
Input Offset Current
IOS
2.0
nA
Input Bias Current
IB
2.0
nA
Initial Power Supply
PSRR i
75
dB
RS ≤ 1MΩ
Initial Common Mode
Rejection Ratio 8
CMRR i
83
dB
RS ≤ 1MΩ
Large Signal Voltage Gain
AV
15
50
V/mV
RL = 1MΩ
Output Voltage Range
VO low
VO high
2.30
-2.40
2.40
V
V
RL = 1MΩ
Unit
Test Conditions
0.7
Unit
Test Conditions
mV
RS ≤ 100KΩ
Rejection Ratio 8
-2.30
TA = 25oC VS = ±1.0V unless otherwise specified
1726E
Parameter
Symbol
Initial Power Supply
8
Rejection Ratio
PSRR i
70
dB
RS ≤ 1MΩ
Initial Common Mode
8
Rejection Ratio
CMRRi
70
dB
RS ≤ 1MΩ
Large Signal Voltage Gain
AV
50
V/mV
RL = 1MΩ
Output Voltage Range
VO low
V
RL = 1MΩ
VO high
Min
Typ
-0.95
0.9
Max
-0.9
0.95
Bandwidth
BW
0.3
MHz
Slew Rate
SR
0.17
V/µs
ALD1726E
Advanced Linear Devices
AV = +1,
CL = 50pF
5 of 13
DEFINITIONS AND DESIGN NOTES:
ADDITIONAL DESIGN NOTES:
1. Initial Input Offset Voltage is the initial offset voltage of the
ALD1726E operational amplifier when shipped from the factory.
The device has been pre-programmed and tested for programmability.
A. The ALD1726E is internally compensated for unity gain
stability using a novel scheme which produces a single pole role
off in the gain characteristics while providing more than 60
degrees of phase margin at unity gain frequency. A unity gain
buffer using the ALD1726E will typically drive 25pF of external
load capacitance.
2. Offset Voltage Program Range is the range of adjustment of
user specified target offset voltage. This is typically an adjustment in either the positive or the negative direction of the input
offset voltage from an initial input offset voltage. The input offset
programming pins, VE1 or VE2, change the input offset voltage
in the negative or positive direction, respectively. User specified
target offset voltage can be any offset voltage within this programming range.
3. Programmed Input Offset Voltage Error is the final offset
voltage error after programming when the Input Offset Voltage
is at target Offset Voltage. This parameter is sample tested.
4. Total Input Offset Voltage is the same as Programmed Input
Offset Voltage, corrected for system offset voltage error. Usually this is an all inclusive system offset voltage, which also
includes offset voltage contributions from input offset voltage,
PSRR, CMRR, TCVOS and noise. It can also include errors
introduced by external components, at a system level. Programmed Input Offset Voltage and Total Input Offset Voltage is
not necessarily zero offset voltage, but an offset voltage set to
compensate for other system errors as well. This parameter is
sample tested.
5. The Input Offset and Bias Currents are essentially input
protection diode reverse bias leakage currents. This low input
bias current assures that the analog signal from the source will
not be distorted by it. For applications where source impedance
is very high, it may be necessary to limit noise and hum pickup
through proper shielding.
6. Input Voltage Range is determined by two parallel complementary input stages that are summed internally, each stage
having a separate input offset voltage. While Total Input Offset
Voltage can be trimmed to a desired target value, it is essential
to note that this trimming occurs at only one user selected input
bias voltage. Depending on the selected input bias voltage
relative to the power supply voltages, offset voltage trimming
may affect one or both input stages. For the ALD1726E, the
switching point between the two stages occurs at approximately
1.5V below the positive supply voltage.
7. Input Offset Voltage Drift is the average change in Total Input
Offset Voltage as a function of ambient temperature. This
parameter is sample tested.
8. Initial PSRR and initial CMRR specifications are provided as
reference information. After programming, error contribution to
the offset voltage from PSRR and CMRR is set to zero under the
specific power supply and common mode conditions, and becomes part of the Programmed Input Offset Voltage Error.
9. Average Long Term Input Offset Voltage Stability is based on
input offset voltage shift through operating life test at 125°C
extrapolated to TA = 25°C, assuming activation energy of 1.0eV.
This parameter is sample tested.
ALD1726E
B. The ALD1726E has complementary p-channel and n-channel
input differential stages connected in parallel to accomplish railto-rail input common mode voltage range. The switching point
between the two differential stages is 1.5V below positive supply
voltage. For applications such as inverting amplifiers or noninverting amplifiers with a gain larger than 2.5 (5V operation), the
common mode voltage does not make excursions below this
switching point. However, this switching does take place if the
operational amplifier is connected as a rail-to-rail unity gain
buffer and the design must allow for input offset voltage variations.
C. The output stage consists of class AB complementary output
drivers. The oscillation resistant feature, combined with the railto-rail input and output feature, makes the ALD1726E an effective analog signal buffer for high source impedance sensors,
transducers, and other circuit networks.
D. The ALD1726E has static discharge protection. However,
care must be exercised when handling the device to avoid strong
static fields that may degrade a diode junction, causing increased input leakage currents. The user is advised to power up
the circuit before, or simultaneously with, any input voltages
applied and to limit input voltages not to exceed 0.3V of the
power supply voltage levels.
E. VE1 and VE2 are high impedance terminals, as the internal
bias currents are set very low to a few microamperes to conserve
power. For some applications, these terminals may need to be
shielded from external noise coupling sources. For example,
digital signals running nearby may cause unwanted offset voltage fluctuations. Care during the printed circuit board layout, to
place ground traces around these pins and to isolate them from
digital lines, will generally eliminate such coupling effects. In
addition, optional decoupling capacitors of 1000pF or greater
value can be added to VE1 and VE2 terminals.
F. The ALD1726E is designed for use in low voltage, micropower
circuits. The maximum operating voltage during normal operation should remain below 10V at all times. Care should be taken
to insure that the application in which the device is used does not
experience any positive or negative transient voltages that will
cause any of the terminal voltages to exceed this limit.
G. All inputs or unused pins except VE1 and VE2 pins should be
connected to a supply voltage such as Ground so that they do
not become floating pins, since input impedance at these pins is
very high. If any of these pins are left undefined, they may cause
unwanted oscillation or intermittent excessive current drain. As
these devices are built with CMOS technology, normal operating
and storage temperature limits, ESD and latchup handling
precautions pertaining to CMOS device handling should be
observed.
Advanced Linear Devices
6 of 13
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
±6
OUTPUT VOLTAGE SWING (V)
OPEN LOOP VOLTAGE
GAIN (V/mV)
1000
OUTPUT VOLTAGE SWING AS A FUNCTION
OF SUPPLY VOLTAGE
100
10
-55°C ≤ TA ≤ +125°C
RL = 100KΩ
±4
±3
±2
±1
1
±2
0
±4
±6
±2
±3
±4
±5
±6
±7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
100
VS = ±2.5V
100
SUPPLY CURRENT (µA)
INPUT BIAS CURRENT (pA)
±1
0
±8
1000
10
1.0
0.1
0.01
INPUTS GROUNDED
OUTPUT UNLOADED
+25°C
80
-25°C
TA = -55°C
60
40
20
-25
0
25
50
75
100
125
+125°C
+70°C
0
-50
±1
0
±2
±3
±4
±5
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
ADJUSTMENT IN INPUT OFFSET VOLTAGE
AS A FUNCTION OF CHANGE IN VE1 AND VE2
OPEN LOOP VOLTAGE GAIN AS
A FUNCTION OF FREQUENCY
±6
120
6
OPEN LOOP VOLTAGE
GAIN (db)
10
8
VE2
4
2
0
-2
-4
VE1
-6
-8
VS = ±2.5V
TA = 25°C
100
80
60
0
40
45
20
90
0
135
180
-20
-10
1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
10
100
1K
10K 100K
FREQUENCY (Hz)
1M
PHASE SHIFT IN DEGREES
CHANGE IN INPUT OFFSET
VOLTAGE ∆VOS (mV)
-55°C ≤ TA ≤ +125°C
RL = 100KΩ
±5
10M
CHANGE IN VE1 AND VE2 (V)
ALD1726E
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7 of 13
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
LARGE - SIGNAL TRANSIENT
RESPONSE
±7
COMMON MODE INPUT
VOLTAGE RANGE (V)
±6
2V/div
VS = ±1.0V
TA = 25°C
RL = 100KΩ
CL= 25pF
500mV/div
10µs/div
TA = 25°C
±5
±4
±3
±2
±1
0
±1
0
±2
±3
±4
±5
±6
±7
SUPPLY VOLTAGE (V)
OPEN LOOP VOLTAGE GAIN AS AFUNCTION
OF LOAD RESISTANCE
SMALL - SIGNAL TRANSIENT
RESPONSE
1000
VS = ±2.5V
TA = 25°C
RL = 100KΩ
CL= 25pF
OPEN LOOP VOLTAGE
GAIN (V/mV)
100mV/div
100
10
VS = ±2.5V
TA = 25°C
1
10K
100K
1M
50mV/div
10µs/div
10M
LOAD RESISTANCE (Ω)
LARGE - SIGNAL TRANSIENT
RESPONSE
DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE
BEFORE AND AFTER EPAD PROGRAMMING
VS = ±2.5V
TA = 25°C
RL = 100KΩ
CL= 25pF
PERCENTAGE OF UNITS (%)
100
5V/div
80
EXAMPLE A:
VOST AFTER EPAD
PROGRAMMING
VOST TARGET = 0.0µV
EXAMPLE B:
VOST AFTER EPAD
PROGRAMMING
VOST TARGET = -750µV
60
VOST BEFORE EPAD
PROGRAMMING
40
20
2V/div
10µs/div
0
-2500
-2000
-1500
-1000
-500
0
500
1000
1500
2000
2500
TOTAL INPUT OFFSET VOLTAGE (µV)
ALD1726E
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8 of 13
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE (µV)
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
500
PSRR = 80 dB
400
EXAMPLE A:
VOS EPAD PROGRAMMED
AT VSUPPLY = +5V
300
EXAMPLE B:
VOS EPAD
PROGRAMMED
AT VSUPPLY = +8V
200
100
0
1
0
2
3
4
5
6
7
8
9
10
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE (µV)
SUPPLY VOLTAGE (V)
THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE
500
VSUPPLY = ±5V
CMRR = 80dB
400
300
EXAMPLE B:
VOS EPAD
PROGRAMMED
AT VIN = -4.3V
200
EXAMPLE A:
VOS EPAD PROGRAMMED
AT VIN = 0V
100
EXAMPLE C:
VOS EPAD PROGRAMMED
AT VIN = +5V
0
-5
-4
-3
-2
-1
0
1
2
3
4
5
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE (µV)
COMMON MODE VOLTAGE (V)
EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE
FOR A COMMON MODE VOLTAGE RANGE OF 0.5V
50
COMMON MODE VOLTAGE RANGE OF 0.5V
40
30
VOS EPAD
PROGRAMMED
AT COMMON MODE
VOLTAGE OF 0.25V
20
CMRR = 80dB
10
0
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
COMMON MODE VOLTAGE (V)
ALD1726E
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TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING
2500
2500
2000
2000
TOTAL INPUT OFFSET VOLTAGE (µV)
TOTAL INPUT OFFSET VOLTAGE (µV)
Examples of applications where accumulated total input offset voltage from various
contributing sources is minimized under different sets of user-specified operating conditions
1500
1000
VOS BUDGET AFTER
EPAD PROGRAMMING
500
0
-500
+
X
-1000
-1500
-2000
VOS BUDGET BEFORE
EPAD PROGRAMMING
VOS BUDGET AFTER
EPAD PROGRAMMING
1500
1000
500
+
0
X
-500
-1000
VOS BUDGET BEFORE
EPAD PROGRAMMING
-1500
-2000
-2500
-2500
EXAMPLE B
2500
2500
2000
2000
TOTAL INPUT OFFSET VOLTAGE (µV)
TOTAL INPUT OFFSET VOLTAGE (µV)
EXAMPLE A
1500
1000
VOS BUDGET BEFORE
EPAD PROGRAMMING
500
0
-500
-1000
+
X
-1500
-2000
VOS BUDGET AFTER
EPAD PROGRAMMING
1500
1000
500
+
0
X
-500
-1000
-1500
-2000
-2500
VOS BUDGET AFTER
EPAD PROGRAMMING
VOS BUDGET BEFORE
EPAD PROGRAMMING
-2500
EXAMPLE C
EXAMPLE D
Device input VOS
PSRR equivalent VOS
+
Total Input VOS
after EPAD
Programming
CMRR equivalent VOS
TA equivalent VOS
X
Noise equivalent VOS
External Error equivalent VOS
ALD1726E
Advanced Linear Devices
10 of 13
SOIC-8 PACKAGE DRAWING
8 Pin Plastic SOIC Package
E
Millimeters
Dim
S (45°)
D
A
Min
1.35
Max
1.75
Min
0.053
Max
0.069
A1
0.10
0.25
0.004
0.010
b
0.35
0.45
0.014
0.018
C
0.18
0.25
0.007
0.010
D-8
4.69
5.00
0.185
0.196
E
3.50
4.05
0.140
0.160
1.27 BSC
e
A
A1
e
Inches
0.050 BSC
H
5.70
6.30
0.224
0.248
L
0.60
0.937
0.024
0.037
ø
0°
8°
0°
8°
S
0.25
0.50
0.010
0.020
b
S (45°)
H
L
ALD1726E
C
ø
Advanced Linear Devices
11 of 13
PDIP-8 PACKAGE DRAWING
8 Pin Plastic DIP Package
E
E1
Millimeters
D
S
A2
A1
e
b
b1
A
L
Inches
Dim
Min
Max
Min
Max
A
3.81
5.08
0.105
0.200
A1
0.38
1.27
0.015
0.050
A2
1.27
2.03
0.050
0.080
b
0.89
1.65
0.035
0.065
b1
0.38
0.51
0.015
0.020
c
0.20
0.30
0.008
0.012
D-8
9.40
11.68
0.370
0.460
E
5.59
7.11
0.220
0.280
E1
7.62
8.26
0.300
0.325
e
2.29
2.79
0.090
0.110
e1
L
7.37
7.87
0.290
0.310
2.79
3.81
0.110
0.150
S-8
1.02
2.03
0.040
0.080
0°
15°
0°
15°
ø
c
e1
ALD1726E
ø
Advanced Linear Devices
12 of 13
CERDIP-8 PACKAGE DRAWING
8 Pin CERDIP Package
E E1
Millimeters
D
A1
s
A
L
L2
b
b1
e
L1
Min
Inches
Dim
A
3.55
Max
5.08
Min
0.140
Max
0.200
A1
1.27
2.16
0.050
0.085
b
0.97
1.65
0.038
0.065
b1
0.36
0.58
0.014
0.023
C
0.20
0.38
0.008
0.015
D-8
--
10.29
--
0.405
E
5.59
7.87
0.220
0.310
E1
7.73
8.26
0.290
0.325
e
2.54 BSC
0.100 BSC
e1
7.62 BSC
0.300 BSC
L
3.81
5.08
0.150
0.200
L1
3.18
--
0.125
--
L2
0.38
1.78
0.015
0.070
S
--
2.49
--
0.098
Ø
0°
15°
0°
15°
C
e1
ALD1726E
ø
Advanced Linear Devices
13 of 13
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