ALD1726SAL

ADVANCED LINEAR DEVICES, INC. TM e ® EPAD D LE AB EN ALD1726/ALD1726G PRECISION ULTRA MICROPOWER CMOS OPERATIONAL AMPLIFIER GENERAL DESCRIPTION FEATURES & BENEFITS The ALD1726/ALD1726G is a monolithic precision CMOS ultra micropower high slew-rate, high performance operational amplifier intended for a broad range of analog applications using ±1V to ±5V dual power supply systems, as well as +2V to +10V battery operated systems. All device characteristics are specified for +5V single supply or ±2.5V dual supply systems. Supply current is 40µA maximum at 5V supply voltage. • • • • The ALD1726/ALD1726G is designed to offer high performance for a wide range of applications requiring very low power dissipation. It has been developed specifically for the +5V single battery or ±1V to ±5V dual battery user and offers the popular industry standard single operational amplifier pin configuration. • Several important characteristics of the device make application easier to implement at those voltages. First, the operational amplifier can operate with rail to rail input and output voltages. This means the signal input voltage and output voltage can be close to or equal to the positive and negative supply voltages. This feature allows numerous analog serial stages and flexibility in input signal bias levels. Second, the device was designed to accommodate mixed applications where digital and analog circuits may operate off the same power supply or battery. Third, the output stage can typically drive up to 25pF capacitive and 20KΩ resistive loads. These features, combined with extremely low input currents, high open loop voltage gain of 100V/mV, useful bandwidth of 400KHz, a slew rate of 0.17V/µs, low offset voltage and temperature drift, make the ALD1726/ALD1726G a versatile, micropower operational amplifier. The ALD1726/ALD1726G, designed and fabricated with silicon gate CMOS technology, offers 0.01 pA typical input bias current. On chip offset voltage trimming allows the device to be used without nulling in most applications. The ALD1726/ALD1726G is also designed to offer tolerance to overvoltage input spikes of 300mV beyond supply rails, high open loop voltage gain, and robust operation at temperature extremes. Additionally, robust design and rigorous screening make this device especially suitable for operation in temperature-extreme environments and rugged conditions. • • • • • • • • • • • Lead Free - RoHS compatible Robust high-temperature operation 20µA supply current All parameters specified for +5V single supply or ± 2.5V dual supply systems Rail to rail input and output voltage ranges No frequency compensation required -- unity gain stable Extremely low input bias currents -- 0.1pA typical (30pA max.) Ideal for high source impedance applications Dual power supply ±1.0V to ±5.0V operation Single power supply +2V to +10V operation High voltage gain -- typically 100V/mV @ ±2.5V (100dB) Drive as low as a 20KΩ load Output short circuit protected Unity gain bandwidth of 0.4MHz Slew rate of 0.17V/µs Suitable for rugged, temperature-extreme environments APPLICATIONS • • • • • • • • • • • • • • Voltage amplifier Voltage follower/buffer Charge integrator Photodiode amplifier Data acquisition systems High performance portable instruments Biochemical probe interface Signal conditioning circuits Sensor and transducer amplifiers Low leakage amplifiers Precision Sample and Hold amplifiers Active filters Picoammeter Current to voltage converter PIN CONFIGURATION ORDERING INFORMATION (“L” suffix denotes lead-free (RoHS)) 0°C to +70°C Operating Temperature Range 0°C to +70°C -55°C to +125°C 8-Pin Small Outline Package (SOIC) 8-Pin Plastic Dip Package 8-Pin CERDIP Package ALD1726SAL ALD1726GSAL ALD1726PAL ALD1726GPAL ALD1726DA ALD1726GDA * Contact factory for leaded (non-RoHS) or high temperature versions. 8 N/C 7 V+ 3 6 OUT 4 5 N/C N/C 1 -IN 2 +IN V- 2 TOP VIEW TOP VIEW SAL, PAL, DA PACKAGES * N/C pins are internally connected. Do not connect externally. Rev 2.1 ©2011 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, CA 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286 www.aldinc.com ABSOLUTE MAXIMUM RATINGS Supply voltage, V+ Differential input voltage range Power dissipation Operating temperature range SAL, PAL packages DA package Storage temperature range Lead temperature, 10 seconds CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. 10.6V -0.3V to V+ +0.3V 600 mW 0°C to +70°C -55°C to +125°C -65°C to +150°C +260°C OPERATING ELECTRICAL CHARACTERISTICS TA = 25°C VS = ±2.5V unless otherwise specified Min ±1.0 2.0 1726 Typ Test Conditions Dual Supply Single Supply .35 1.0 mV mV RS ≤ 100KΩ 0°C ≤ TA ≤ +70°C .01 10 240 pA pA TA = 25°C 0°C ≤ TA ≤ +70°C .01 10 600 pA pA TA = 25°C 0°C ≤ TA ≤ +70°C 5.3 2.8 V V V+ = +5V VS = ±2.5V Input Offset Voltage VOS .07 .15 0.6 .15 Input Offset Current IOS .01 10 240 Input Bias Current IB .01 10 300 Input Voltage Range VIR 5.3 2.8 Min ±1.0 2.0 Unit V V Symbol VS V+ -0.3 -2.8 Max ±5.0 10.0 1726G Typ Parameter Supply Voltage -0.3 -2.8 Max ±5.0 10.0 Input Resistance RIN Input Offset Voltage Drift TCVOS 1014 1014 7 7 Ω µV/°C RS ≤ 100KΩ Power Supply Rejection Ratio PSRR 65 65 80 80 60 60 80 80 dB dB RS ≤ 100KΩ 0°C ≤ TA ≤ +70°C Common Mode Rejection Ratio CMRR 65 65 83 83 60 60 83 83 dB dB RS ≤ 100KΩ 0°C ≤ TA ≤ +70°C Large Signal Voltage Gain AV 32 20 100 32 20 100 V/ mV V/ mV RL = 1MΩ RL = 1MΩ 0°C ≤ TA ≤ +70°C Output Voltage Range VO low VO high VO low VO high V V V V RL =1MΩ 0°C ≤ TA ≤ +70°C RL =100KΩ 0°C ≤ TA ≤ +70°C 4.99 2.40 0.001 4.999 -2.48 2.48 0.01 4.99 -2.40 2.40 0.001 4.999 -2.48 2.40 0.01 -2.40 Output Short Circuit Current ISC Supply Current IS Power Dissipation PD Input Capacitance CIN 1 1 Bandwidth BW 400 400 KHz Slew Rate SR .17 .17 V/µs ALD1726/ALD1726G 200 25 µA 200 40 25 200 Advanced Linear Devices 50 µA VIN = 0V No Load 250 µW VS = ±2.5V pF AV = +1 RL = 1MΩ 2 of 9 OPERATING ELECTRICAL CHARACTERISTICS (cont'd) TA = 25°C VS = ±2.5V unless otherwise specified (cont'd) 1726 Parameter Symbol Rise time tr Min Overshoot Factor Typ 1726G Max Min Typ Max Unit Test Conditions 1.0 1.0 µs RL = 1MΩ 20 20 % RL = 1MΩ, CL = 25pF Settling Time ts 10.0 µs 10.0 0.1% AV = 1, RL= 1MΩ CL = 25pF TA = 25°C VS = ±1.0V unless otherwise specified 1726 Parameter Symbol Min Power Supply Rejection Ratio PSRR 70 Common Mode Rejection Ratio CMRR Large Signal Voltage Gain AV Output Voltage Range VO low VO high 0.9 Typ 1726G Unit Test Conditions 70 dB RS ≤ 1MΩ 70 70 dB RS ≤ 1MΩ 50 50 V/mV RL = 1MΩ V RL = 1MΩ -0.95 0.95 Max Min -0.9 0.9 Typ -0.95 0.95 Max -0.9 Bandwidth BW 0.3 0.3 MHz Slew Rate SR 0.17 0.17 V/µs AV = +1, CL = 50pF Max Unit Test Conditions RS ≤ 100KΩ VS = ±2.5V -55°C ≤ TA ≤ +125°C unless otherwise specified 1726 Symbol Input Offset Voltage VOS 1.0 2.0 mV Input Offset Current IOS 2.0 2.0 nA Input Bias Current IB 2.0 2.0 nA Power Supply Rejection Ratio PSRR 60 75 60 75 dB RS ≤ 1MΩ Common Mode Rejection Ratio CMRR 60 83 60 83 dB RS ≤ 1MΩ Large Signal Voltage Gain AV 15 50 15 50 V/mV RL = 1MΩ Output Voltage Range VO low VO high -2.40 2.40 2.30 -2.40 2.40 V V RL = 1MΩ 2.30 ALD1726/ALD1726G Min Typ 1726G Parameter Max Min -2.30 Advanced Linear Devices Typ -2.30 3 of 9 Design & Operating Notes: 1. The ALD1726/ALD1726G CMOS operational amplifier uses a 3 gain stage architecture and an improved frequency compensation scheme to achieve large voltage gain, high output driving capability, and better frequency stability. In a conventional CMOS operational amplifier design, compensation is achieved with a pole splitting capacitor together with a nulling resistor. This method is, however, very bias dependent and thus cannot accommodate the large range of supply voltage operation as is required from a stand alone CMOS operational amplifier. The ALD1726/ALD1726G is internally compensated for unity gain stability using a novel scheme that does not use a nulling resistor. This scheme produces a clean single pole roll off in the gain characteristics while providing for more than 70 degrees of phase margin at the unity gain frequency. 2. The ALD1726/ALD1726G has complementary p-channel and nchannel input differential stages connected in parallel to accomplish rail to rail input common mode voltage range. This means that with the ranges of common mode input voltage close to the power supplies, one of the two differential stages is switched off internally. To maintain compatibility with other operational amplifiers, this switching point has been selected to be about 1.5V below the positive supply voltage. Since offset voltage trimming on the ALD1726/ALD1726G is made when the input voltage is symmetrical to the supply voltages, this internal switching does not affect a large variety of applications such as an inverting amplifier or non-inverting amplifier with a gain larger than 2.5 (5V operation), where the common mode voltage does not make excursions below this switching point. The user should, however, be aware that this switching does take place if the operational amplifier is connected as a unity gain buffer and should make provision in his design to allow for input offset voltage variations. 3. The input bias and offset currents are essentially input protection diode reverse bias leakage currents, and are typically less than 1pA at room temperature. This low input bias current assures that the analog signal from the source will not be distorted by input bias currents. Normally, this extremely high input impedance of greater than 1012Ω would not be a problem as the source impedance would limit the node impedance. However, for applications where source impedance is very high, it may be necessary to limit noise and hum pickup through proper shielding. 4. The output stage consists of class AB complementary output drivers, capable of driving a low resistance load. The output voltage swing is limited by the drain to source on-resistance of the output transistors as determined by the bias circuitry, and the value of the load resistor. When connected in the voltage follower configuration, the oscillation resistant feature, combined with the rail to rail input and output feature, makes an effective analog signal buffer for medium to high source impedance sensors, transducers, and other circuit networks. 5. ALD1726/ALD1726G operational amplifier has been designed to provide full static discharge protection. Internally, the design has been carefully implemented to minimize latch up. However, care must be exercised when handling the device to avoid strong static fields that may degrade a diode junction, causing increased input leakage currents. In using the operational amplifier, the user is advised to power up the circuit before, or simultaneously with, any input voltages applied and to limit input voltages to not exceed 0.3V of the power supply voltage levels. 6. The ALD1726/ALD1726G, with its micropower operation, offers numerous benefits in reduced power supply requirements, less noise coupling and current spikes, less thermally induced drift, better overall reliability due to lower self heating, and lower input bias current. It requires practically no warm up time as the chip junction heats up to 0.1°C or less above ambient temperature under most operating conditions. 7. The ALD1726/ALD1726G has an internal design architecture that provides robust high temperature operation. Contact factory for custom screening versions. TYPICAL PERFORMANCE CHARACTERISTICS SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE COMMON MODE INPUT VOLTAGE RANGE AS A FUNCTION OF SUPPLY VOLTAGE 100 ±7 ±6 +25°C 80 COMMON MODE INPUT VOLTAGE RANGE (V) SUPPLY CURRENT (µA) INPUTS GROUNDED OUTPUT UNLOADED -25°C TA = -55°C 60 40 20 +125°C +70°C 0 ±4 ±3 ±2 ±1 0 0 ±1 ±2 ±3 ±4 SUPPLY VOLTAGE (V) ±5 ±6 ±3 ±4 ±5 ±6 ±7 INPUT BIAS CURRENT AS A FUNCTION OF AMBIENT TEMPERATURE 1000 INPUT BIAS CURRENT (pA) 100 10 VS = ±2.5V TA = 25°C VS = ±2.5V 100 10 1.0 0.1 0.01 100K 1M 10M -50 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE (°C) LOAD RESISTANCE (Ω) ALD1726/ALD1726G ±2 SUPPLY VOLTAGE (V) 1000 1 10K ±1 0 OPEN LOOP VOLTAGE GAIN AS AFUNCTION OF LOAD RESISTANCE OPEN LOOP VOLTAGE GAIN (V/mV) TA = 25°C ±5 Advanced Linear Devices 4 of 9 TYPICAL PERFORMANCE CHARACTERISTICS (cont'd) OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF SUPPLY VOLTAGE AND TEMPERATURE OUTPUT VOLTAGE SWING (V) OPEN LOOP VOLTAGE GAIN (V/mV) 1000 OUTPUT VOLTAGE SWING AS A FUNCTION OF SUPPLY VOLTAGE 100 10 -55°C ≤ TA ≤ +125°C RL = 100KΩ ±6 -55°C ≤ TA ≤ +125°C RL = 100KΩ ±5 ±4 ±3 ±2 ±1 1 ±2 0 ±4 ±6 ±8 0 ±1 ±5 ±6 ±7 OPEN LOOP VOLTAGE GAIN (dB) 120 VS = ±2.5V TA = 25°C RL = 100KΩ CL= 25pF 10µs/div VS = ±2.5V TA = 25°C 100 80 60 0 40 45 20 90 0 135 180 -20 1 LARGE - SIGNAL TRANSIENT RESPONSE 10 100 1K 10K 100K FREQUENCY (Hz) 1M 10M SMALL - SIGNAL TRANSIENT RESPONSE 2V/div VS = ±1.0V TA = 25°C RL = 100KΩ CL= 25pF 100mV/div 500mV/div 10µs/div 50mV/div ALD1726/ALD1726G ±4 PHASE SHIFT IN DEGREES 2V/div ±3 OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF FREQUENCY LARGE - SIGNAL TRANSIENT RESPONSE 5V/div ±2 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Advanced Linear Devices VS = ±2.5V TA = 25°C RL = 100KΩ CL= 25pF 10µs/div 5 of 9 TYPICAL APPLICATIONS RAIL-TO-RAIL VOLTAGE FOLLOWER/BUFFER CHARGE INTEGRATOR 1000pF 5V ~ 1012Ω ZIN = 0.1µF - +2.5V 1M VIN OUTPUT VOUT + VIN + -2.5V 0≤ VIN ≤ 5V * See Rail to Rail Waveform HIGH INPUT IMPEDANCE RAIL-TO-RAIL PRECISION DC SUMMING AMPLIFIER RAIL-TO-RAIL VOLTAGE COMPARATOR V+ = +2.5V V1 +5V 10M VIN + 10M +5V VOUT 10M - 10M 0.1µF - 0.1µF V2 0.1µF OUTPUT + 50K V3 V4 10M V- ≤ VOUT ≤ V+ V- = - 2.5V 10M 0 ≤ VIN ≤ V+ 10M VOUT = V1 + V2 - V3 - V4 RIN = 10MΩ Accuracy limited by resistor tolerances and input offset voltage HIGH IMPEDANCE NON-INVERTING AMPLIFIER PHOTO DETECTOR CURRENT TO VOLTAGE CONVERTER RF = 5M 900K 100K I +1V VOUT VIN + RL = 100K + -2.5V -1V WIEN BRIDGE OSCILLATOR MICROPOWER BUFFERED VARIABLE VOLTAGE SOURCE 250K V+ V+ +1.0V VIN VOUT + 0.0015µF C VOUT = 1 X RF +2.5V - PHOTODIODE 2M VOUT + 1µF -1.0V Power Supply = ±1.0V 0.0015µF 100K R C 100K R f≈ 1 2.0V ≤ V+ ≤ 12.0V 0.1 ≤ VOUT ≤ (V+ - 0.1) V OUPUT CURRENT ±200µA ≈ 1.0KHz 2π RC VOUT = SINEWAVE 2V Peak to Peak ALD1726/ALD1726G Advanced Linear Devices 6 of 9 SOIC-8 PACKAGE DRAWING 8 Pin Plastic SOIC Package E Millimeters Dim S (45°) D A Min 1.35 Max 1.75 Min 0.053 Max 0.069 A1 0.10 0.25 0.004 0.010 b 0.35 0.45 0.014 0.018 C 0.18 0.25 0.007 0.010 D-8 4.69 5.00 0.185 0.196 E 3.50 4.05 0.140 0.160 1.27 BSC e A A1 e Inches 0.050 BSC H 5.70 6.30 0.224 0.248 L 0.60 0.937 0.024 0.037 ø 0° 8° 0° 8° S 0.25 0.50 0.010 0.020 b S (45°) H L ALD1726/ALD1726G C ø Advanced Linear Devices 7 of 9 PDIP-8 PACKAGE DRAWING 8 Pin Plastic DIP Package E E1 Millimeters D S A2 A1 e b b1 A L Inches Dim Min Max Min Max A 3.81 5.08 0.105 0.200 A1 0.38 1.27 0.015 0.050 A2 1.27 2.03 0.050 0.080 b 0.89 1.65 0.035 0.065 b1 0.38 0.51 0.015 0.020 c 0.20 0.30 0.008 0.012 D-8 9.40 11.68 0.370 0.460 E 5.59 7.11 0.220 0.280 E1 7.62 8.26 0.300 0.325 e 2.29 2.79 0.090 0.110 e1 L 7.37 7.87 0.290 0.310 2.79 3.81 0.110 0.150 S-8 1.02 2.03 0.040 0.080 0° 15° 0° 15° ø c e1 ALD1726/ALD1726G ø Advanced Linear Devices 8 of 9 CERDIP-8 PACKAGE DRAWING 8 Pin CERDIP Package E E1 Millimeters D A1 s A L L2 b b1 e L1 Min Inches Dim A 3.55 Max 5.08 Min 0.140 Max 0.200 A1 1.27 2.16 0.050 0.085 b 0.97 1.65 0.038 0.065 b1 0.36 0.58 0.014 0.023 C 0.20 0.38 0.008 0.015 D-8 -- 10.29 -- 0.405 E 5.59 7.87 0.220 0.310 E1 7.73 8.26 0.290 0.325 e 2.54 BSC 0.100 BSC e1 7.62 BSC 0.300 BSC L 3.81 5.08 0.150 0.200 L1 3.18 -- 0.125 -- L2 0.38 1.78 0.015 0.070 S -- 2.49 -- 0.098 Ø 0° 15° 0° 15° C e1 ALD1726/ALD1726G ø Advanced Linear Devices 9 of 9