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6811

6811

  • 厂商:

    ALLEGRO(埃戈罗)

  • 封装:

  • 描述:

    6811 - DABiC-IV, 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER - Allegro MicroSystems

  • 数据手册
  • 价格&库存
6811 数据手册
681 1 PRELIMINARY INFORMATION (subject to change without notice) May 15, 2000 A6811xA OUT 11 OUT 12 BLANKING SERIAL DATA OUT SERIAL DATA IN LOGIC SUPPLY CLOCK STROBE OUT 1 OUT 2 1 2 3 4 REGISTER LATCHES DABiC-IV, 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER The A6811– devices combine a 12-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6811– features an increased data input rate (compared with the older UCN/UCQ5811A) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical serial-data input rates are up to 33 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6809– and A6810– (10 bits), A6812– (20 bits), and A6818– (32 bits). The A6811– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Two temperature ranges are available for optimum performance in commercial (suffix S-) or industrial (suffix E-) applications. Package styles are provided for through-hole DIP (suffix -A) and surface-mount SOIC or PLCC (suffix -LW or -EP). Copper lead frames, low logicpower dissipation, and low output-saturation voltages allow all devices to source 25 mA from all outputs continuously at up to 83°C. Data Sheet 26182.120 20 19 BLNK 18 17 VBB 16 15 14 13 12 11 OUT 10 OUT 9 OUT 8 OUT 7 LOAD SUPPLY GROUND OUT 6 OUT 5 OUT 4 OUT 3 5 6 7 8 9 10 VDD CLK ST Dwg. PP-029-5 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Logic Supply Voltage, VDD ................... 7.0 V Driver Supply Voltage, VBB ................... 60 V Continuous Output Current Range, IOUT ......................... -40 mA to +15 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA (Suffix ‘E–’) .................. -40°C to +85°C (Suffix ‘S–’) .................. -20°C to +85°C Storage Temperature Range, TS ............................... -55°C to +125°C FEATURES I Controlled Output Slew Rate I High-Speed Data Storage I I 60 V Minimum Output Breakdown I I High Data Input Rate I PNP Active Pull-Downs I Low Output-Saturation Voltages Low-Power CMOS Logic and Latches Improved Replacements for SN75512B, UCN5811–, and UCQ5811– Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A6811SLW . 6811 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER A6811xEP BLANKING OUT 12 OUT 9 A6811xLW OUT 11 OUT 12 BLANKING 18 17 V BB 16 15 14 OUT 8 OUT 7 LOAD SUPPLY GROUND OUT 6 1 2 3 4 BLNK 20 19 18 17 OUT 10 OUT 9 OUT 8 OUT 7 LOAD SUPPLY GROUND OUT 6 OUT 5 OUT 4 OUT 3 SERIAL DATA OUT SERIAL DATA IN LOGIC SUPPLY CLOCK STROBE 4 5 6 7 8 V DD CLK ST BLNK 20 19 3 2 1 SERIAL DATA OUT SERIAL DATA IN LOGIC SUPPLY CLOCK STROBE REGISTER REGISTER LATCHES LATCHES 5 6 7 8 9 10 VDD CLK ST VBB 16 15 14 13 12 11 12 10 11 13 9 OUT 1 Dwg. PP-059-4 OUT 1 OUT 5 OUT 2 TYPICAL INPUT CIRCUIT VDD Dwg. PP-029-6 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 SUFFIX 'A', R θJA = 55°C/W IN 2.0 SUFFIX 'EP', R θJA = 59°C/W 1.5 Dwg. EP-010-5 TYPICAL OUTPUT DRIVER V BB 1.0 0.5 SUFFIX 'LW', R θJA = 70°C/W OUTN 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. GP-024-5 Dwg. EP-021-19 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, Allegro MicroSystems, Inc. 6811 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER FUNCTIONAL BLOCK DIAGRAM CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT SERIAL-PARALLEL SHIFT REGISTER LATCHES BLANKING MOS BIPOLAR LOAD SUPPLY VBB GROUND OUT 1 OUT 2 OUT 3 OUT N Dwg. FP-013-1 TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X L = Low Logic Level H = High Logic Level X = Irrelevant Latch Contents I1 I2 I3 ... IN-1 IN Blanklng Output Contents I1 I2 I3 ... IN-1 IN R1 R2 R3 ... X X X ... RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L P1 P2 P3 ... PN-1 PN X X ... P = Present State R = Previous State www.allegromicro.com 6811 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C (A6811S-) or over operating temperature range (A6811E-), VBB = 60 V unless otherwise noted. Limits @ VDD = 3.3 V Characteristic Output Leakage Current Output Voltage Symbol ICEX VOUT(1) VOUT(0) Output Pull-Down Current Input Voltage IOUT(0) VIN(1) VIN(0) Input Current IIN(1) IIN(0) Input Clamp Voltage Serial Data Output Voltage VIK VOUT(1) VOUT(0) Maximum Clock Frequency Logic Supply Current fc IDD(1) IDD(0) Load Supply Current IBB(1) IBB(0) Blanking-to-Output Delay tdis(BQ) ten(BQ) Strobe-to-Output Delay tp(STH-QL) tp(STH-QH) Output Fall Time Output Rise Time Output Slew Rate tf tr dV/dt All Outputs High All Outputs Low All Outputs High, No Load All Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF RL = 2.3 kΩ, CL ≤ 30 pF IOUT = ±200 µA VIN = VDD VIN = 0 V IIN = -200 µA IOUT = -200 µA IOUT = 200 µA Test Conditions VOUT = 0 V IOUT = -25 mA IOUT = 1 mA VOUT = 5 V to VBB Mln. — 57.5 — 2.5 2.2 — — — — 2.8 — 10 — — — — — — — — 2.4 2.4 4.0 — Typ.

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