A1130, A1131, and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
2
-
FEATURES AND BENEFITS
DESCRIPTION
The A1130, A1131, and A1132 are vertical Hall-effect sensor
ICs developed in accordance with ISO 26262:2011. The A113x
devices feature integrated continuous diagnostic features and
a safe output state that supports a functional safety level of
ASIL B. The diagnostic features cover critical subsystems of
the IC including the signal path, voltage regulator, sensing
element, and digital subsystem.
• ISO 26262:2011 compliant
□□ Achieves ASIL B as a stand-alone component
□□ A2-SIL™ documentation available including FMEDA
and Safety Manual
□□ Continuously operating background diagnostics
□□ Integrated regulator undervoltage monitor
• Magnetic sensing parallel to surface of package
• Internal current regulator for two-wire operation
• Highly sensitive unipolar switch thresholds
• Operation down to 3 V
• Selection of temperature coefficients (TC) to match
magnet properties
• Small package sizes, 3-pin SOT23W and SIP
• Automotive-grade ruggedness
□□ Qualified per AEC-Q100
□□ Internal protection circuits enable 40 V load dump
compliance
□□ Operation up to 165°C junction temperature
□□ Low temperature drift and high physical stress
resistance
□□ Solid-state reliability
□□ Reverse-battery and overvoltage protection
PACKAGES
Not to scale
These devices feature an output current interface that is
compatible with existing two-wire systems, providing
interconnect open and short diagnosis. These devices also
feature a safe output state to communicate IC diagnostic
information while maintaining compatibility with existing
two-wire systems. Should the diagnostics sense an internal
failure, the output current will be driven to a level that is below
the standard low current level.
This family of unipolar Hall-effect switch ICs feature vertical
Hall sensing elements that are sensitive to magnetic fields that
are parallel to the surface of the IC package. This can provide
additional flexibility in magnetic configuration, as well as the
potential to migrate from SIP-based traditional planar HallContinued on next page...
APPLICATIONS
3-Pin SIP
(Suffix UA)
•
•
•
•
•
•
3-Pin SOT23W
(Suffix LH)
Brake and clutch pedal switches
Fluid float sensor
Seat belt buckles and position
Electronic power steering (EPS) index sensing
Hood/trunk latches
Electronic parking brakes
VDD
Regulator
Under Voltage Monitor
Internal Oscillator
Vertical Hall
and Input
Diagnostics
Dynamic Offset
Cancellation
To All Subcircuits
Schmitt
Trigger
HALL
AMP.
Sample, Hold, &
Averaging
Programming
Diagnostics
Signal Path
Diagnostics
Output
Control
Low-Pass
Filter
Programming
System Diagnostics
Functional Block Diagram
A1130-DS, Rev. 4
MCO-0000161
GND
July 11, 2019
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
DESCRIPTION (continued)
effect sensor ICs to surface-mount vertical Hall-effect sensor ICs
while maintaining the same magnetic orientation.
This family of devices is available in two package styles and in
choices of sensor sensitivity orientations as shown in Figure 2.
Package type LH is a modified SOT23W surface-mount package,
while package type UA is a three-lead ultramini SIP for through-hole
mounting. Both packages are RoHS-compliant and lead (Pb) free
(suffix, -T), with 100% matte-tin-plated leadframes.
In addition to providing integrated diagnostics and standard two-wire
current interface, these sensor ICs are temperature-compensated for
use with ferrite and neodymium iron boron magnets and include
automotive-grade ruggedness features such as reverse-battery
protection, overvoltage protection, and load dump capability of
up to 40 V.
RoHS
COMPLIANT
SPECIFICATIONS
SELECTION GUIDE
Part Number
Packing
Mounting
Sensing
Orientation
A1130LLHLT-T
7" reel, 3000 pieces
3-pin SOT23W surface mount
X
A1130LLHLX-T
13" reel, 10000 pieces
3-pin SOT23W surface mount
X
A1130LUATN-X-T
13" reel, 4000 pieces
3-pin SIP through hole
X
A1130LUATN-Y-T
13” reel, 4000 pieces
3-pin SIP through hole
Y
A1131ELHLT-T
7" reel, 3000 pieces
3-pin SOT23W surface mount
X
A1131ELHLX-T
13” reel, 10000 pieces
3-pin SOT23W surface mount
X
A1132KLHLT-T
7" reel, 3000 pieces
3-pin SOT23W surface mount
X
A1132KLHLX-T
13” reel, 10000 pieces
3-pin SOT23W surface mount
X
BOP
BRP
IDD(HIGH)
IDD(LOW)
Operating
Ambient
Temperature,
TA (°C)
IDD(HIGH)
55
35
14.3
5.9
–40 to 150
IDD(LOW)
95
70
28.1
10.7
–40 to 85
IDD(LOW)
60
35
14.5
3.7
–40 to 125
Output
State for
B > BOP
Typical
Switchpoints (G)
Typical Supply
Current (mA)
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Notes
Rating
Unit
Forward Supply Voltage
VDD
26.5
V
Reverse Supply Voltage
VRDD
–18
V
Magnetic Density Flux
B
A1130
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
TA
Range L
Unlimited
G
–40 to 150
°C
A1131
Range E
–40 to 85
°C
A1132
Range K
–40 to 125
°C
TJ(MAX)
165
°C
Tstg
–65 to 170
°C
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
GND
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
3
VH
Package LH Pinout
2
3
GND
GND
1
GND
2
VDD
1
VDD
VH
Package UA Pinout
Terminal List Table
Pin Number
Symbol
LH
Package
UA
Package
VDD
1
1
Power supply to chip
GND
2
2
Ground
GND
3
3
Ground
Description
Table of Contents
Features and Benefits 1
Description 1
Packages 1
Functional Block Diagram 1
Specifications 2
Selection Guide 2
Absolute Maximum Ratings 2
Pinout Diagrams and Terminal List Table 3
Thermal Characteristics 4
Operating Characteristics 5
Characteristic Performance Data 7
Functional Description 13
Functional Safety 13
Operation 13
Power-On Sequence and Timing 14
Two-Wire Interface 15
Output Polarity 15
Typical Applications 16
Temperature Coefficient and Magnet Selection 16
Diagnostics 17
Diagnostic Mode Fault Operation 18
Chopper Stabilization 19
Power Derating 20
Package Outline Drawings 21
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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3
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
RθJA
Maximum Power Dissipation, PD (mW)
Package Thermal Resistance
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Notes
Rating
Unit
Package LH, 1-layer PCB with copper limited to solder pads
228
°C/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area, each
side connected by thermal vias
110
°C/W
Package UA, 1-layer PCB with copper limited to solder pads
165
°C/W
Package LH, 2-layer PCB
(R JA = 110ºC/W)
Package UA, 1-layer PCB
(R JA = 165ºC/W)
Package LH, 1-layer PCB
(R JA = 228ºC/W)
20
40
60
80
100
120
140
160
180
Temperature (ºC)
Power Dissipation versus Ambient Temperature
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
OPERATING CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ (max),
unless otherwise specified
Characteristics
Supply Voltage [2]
Symbol
VDD
Test Conditions
Supply Current
IDD(HIGH)
Typ. [1]
Max.
Unit
A1130
3
–
24
V
A1131
3
–
6
V
A1132
IDD(LOW)
Min.
3
–
12
V
A1130
B < BRP
5
5.9
6.9
mA
A1131
B > BOP
9.5
10.7
13.6
mA
A1132
B > BOP
2
3.7
4.5
mA
A1130
B > BOP
12
14.3
17
mA
A1131
B < BRP
25.2
28.1
30.9
mA
A1132
B < BRP
13
14.5
16
mA
VRDD = –18 V
–
–
–1.6
mA
VRDD = –9 V
–
–
–50
µA
–
50
70
µs
Reverse Supply Current
IRDD
A1130,
A1131,
A1132
Power-On Time [3]
tON
VDD ≥ VDD (min), B < BRP (min) – 10 G,
B > BOP (max) + 10 G
Power-On State [4]
POS
t < tON (max) ; VDD slew rate > 25 mV/µs
di/dt
RSENSE = 100 Ω, CBYP = 0.01 µF,
IDD(HIGH) → IDD(LOW), IDD(LOW) → IDD(HIGH),
10% to 90% points
–
7.25
–
IDD(LOW) (max) + 3 mA, TA = 25°C
28
A1130
A1131
A1132
Output Slew Rate [5]
Chopping Frequency
fC
Supply Zener Clamp Voltage
VZ
Sensitivity Temperature Coefficient [6]
TCSENS
IDD(HIGH)
–
–
mA/µs
800
–
kHz
–
–
V
–
–0.11
–
%/°C
–
–0.20
–
%/°C
–
–0.19
–
%/°C
Diagnostic Characteristics
Diagnostics Time Slot
tDIAG
–
50
70
µs
Diagnostics Fault Retry Time [7]
tDIAGF
–
2.2
2.75
ms
mA
Fault Mode Supply Current, Base
IDD(BASE)FAULT
–
0.97
–
Fault Mode Supply Current, Peak
IDD(PEAK)FAULT
–
2.5
4
mA
Fault Mode Supply Current, Average [8]
IDD(AVG)FAULT
0.5
1
1.5
mA
See Equations 1 and 2
Typical data are at TA = 25°C and VDD = 12 V (A1130), VDD = 5 V (A1131), VDD = 8 V (A1132).
VDD represents the voltage between the VDD pin and the GND pin.
[3] Power-On Time is the duration from when V
DD rises above VDD(min) until the output has attained a valid state.
[4] POS is undefined for V
DD < VDD(min). Use of a VDD slew rate greater than 25 mV/µs is recommended.
[5] Use of a larger bypass capacitor results in slower current change.
[6] Relative to sensitivity at T = 25°C.
A
[7] The diagnostics fault retry repeats continuously until a fault condition is no longer observed. See Diagnostics Mode Fault section for details.
[8] Average current measured for one fault mode period; t
DIAG + tDIAGF.
[1]
[2]
Equation 1:
Fault Mode Duty Cycle (DC) = tDIAG / (tDIAG + tDIAGF)
Equation 2:
IDD(AVG)FAULT = [IDD(BASE)FAULT × (1 – DC)] + [IDD(PEAK)FAULT × DC]
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
OPERATING CHARACTERISTICS (continued): Valid over full operating voltage and ambient temperature ranges for
TJ < TJ (max), unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ. [8]
Max.
Unit [9]
–
50
70
µs
TA = 25°C
40
55
70
G
TA = –40 to 150°C
25
–
80
G
TA = 25°C
75
95
115
G
TA = –40 to 85°C
50
–
135
G
Magnetic Characteristics
Magnetic Sampling Time Slot
tSAMPLE
A1130
Operate Point
BOP
A1131
A1132
A1130
Release Point
BRP
A1131
A1132
A1130
Hysteresis
BHYS
A1131
A1132
60
85
G
20
35
50
G
TA = –40 to 150°C
5
–
60
G
TA = 25°C
55
70
85
G
TA = –40 to 85°C
30
–
110
G
TA = –40 to 125°C
5
35
65
G
TA = 25°C
5
20
35
G
TA = –40 to 150°C
5
–
35
G
TA = 25°C
15
25
35
G
TA = –40 to 85°C
10
–
42
G
TA = –40 to 125°C
10
25
42
G
Typical data are at TA = 25°C and VDD = 12 V (A1130), VDD = 5 V (A1131), VDD = 8 V (A1132).
1 G (gauss) = 0.1 mT (millitesla).
IDD(HIGH)
I+
IDD(HIGH)
Switch to Low
IDD
Switch to High
Switch to Low
I+
Switch to High
[9]
30
IDD
[8]
TA = –40 to 125°C
TA = 25°C
IDD(LOW)
IDD(LOW)
0
BRP
BRP
B+
BOP
BOP
0
BHYS
BHYS
(A)
(B)
B+
Figure 1: Device switching behavior for A1130 (panel A), A1131 and A1132 (panel B). On the horizontal axis, the B+ direction
indicates increasing south polarity magnetic field strength.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA
SAFE STATE
Average Fault Mode Current versus Ambient Temperature
VDD = 3 V
1.5
IDD(AVG)FAULT (mA)
1.4
1.3
Part
Number
1.2
1.1
A1130
1
0.9
A1131
0.8
A1132
0.7
0.6
0.5
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
CHARACTERISTIC PERFORMANCE DATA
A1130
Average High Supply Current versus Ambient Temperature
17.0
16.5
16.5
16.0
15.5
TA (°C)
15.0
-40
14.5
25
14.0
150
13.5
IDD(HIGH) (mA)
IDD(HIGH) (mA)
Average High Supply Current versus Supply Voltage
17.0
16.0
15.5
12.5
10
14
VDD (V)
18
22
12.0
26
24
13.5
12.5
6
12
14.0
13.0
2
3
14.5
13.0
12.0
VDD (V)
15.0
-60
7.0
6.8
6.8
6.6
0
20
40
60
TA (°C)
80
100
120
140
160
6.6
6.4
TA (°C)
6.2
-40
6.0
25
5.8
150
5.6
6.4
14
VDD (V)
18
22
26
24
5.6
5.2
10
12
5.8
5.2
6
3
6.0
5.4
2
VDD (V)
6.2
5.4
5.0
-20
Average Low Supply Current versus Ambient Temperature
7.0
IDD(LOW) (mA)
IDD(LOW) (mA)
Average Low Supply Current versus Supply Voltage
-40
5.0
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
160
7
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA
A1130 (continued)
Average Operate Point versus Ambient Temperature
TA (°C)
-40
25
BOP (G)
BOP (G)
Average Operate Point versus Supply Voltage
80
75
70
65
60
55
50
45
40
35
30
25
150
2
6
10
14
VDD (V)
18
22
80
75
70
65
60
55
50
45
40
35
30
25
26
VDD(V)
3
12
24
-60
-40
25
BRP (G)
BRP (G)
TA (°C)
150
2
6
10
14
VDD (V)
18
22
60
55
50
45
40
35
30
25
20
15
10
5
26
20
40
60
TA (°C)
80
100
120
140
160
3
12
24
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average Switchpoint Hysteresis versus Ambient Temperature
35
30
TA (°C)
25
-40
20
25
15
150
BHYS (G)
30
BHYS (G)
0
VDD (V)
Average Switchpoint Hysteresis versus Supply Voltage
35
VDD(V)
25
3
20
12
24
15
10
10
5
-20
Average Release Point versus Ambient Temperature
Average Release Point versus Supply Voltage
60
55
50
45
40
35
30
25
20
15
10
5
-40
5
2
6
10
14
VDD (V)
18
22
26
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
160
8
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA
A1131
Average High Supply Current versus Ambient Temperature
TA (°C)
-40
25
85
2.5
3
3.5
4
4.5
VDD (V)
5
5.5
6
IDD(HIGH) (mA)
IDD(HIGH) (mA)
Average High Supply Current versus Supply Voltage
31.0
30.5
30.0
29.5
29.0
28.5
28.0
27.5
27.0
26.5
26.0
25.5
25.0
6.5
31.0
30.5
30.0
29.5
29.0
28.5
28.0
27.5
27.0
26.5
26.0
25.5
25.0
VDD (V)
3
5
6
-60
Average Low Supply Current versus Supply Voltage
14.0
13.5
13.5
13.0
0
20
TA (°C)
40
60
80
100
13.0
12.5
TA (°C)
12.0
-40
11.5
25
11.0
85
10.5
IDD(LOW) (mA)
IDD(LOW) (mA)
-20
Average Low Supply Current versus Ambient Temperature
14.0
12.5
4
4.5
VDD (V)
5
5.5
6
6.5
6
10.5
9.5
3.5
5
11.0
9.5
3
3
11.5
10.0
2.5
VDD (V)
12.0
10.0
9.0
-40
9.0
-60
-40
-20
0
20
TA (°C)
40
60
80
Allegro MicroSystems
955 Perimeter Road
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100
9
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA
A1131 (continued)
Average Operate Point versus Ambient Temperature
Average Operate Point versus Supply Voltage
140
140
130
130
110
-40
100
25
90
80
BOP (G)
BOP (G)
120
TA (°C)
120
85
70
100
3
90
5
80
6
70
60
60
50
VDD (V)
110
50
2.5
3
3.5
4
4.5
VDD (V)
5
5.5
6
6.5
-60
100
100
90
TA (°C)
90
80
-40
80
70
25
60
BRP (G)
BRP (G)
110
85
50
20
TA (°C)
40
60
80
100
VDD (V)
3
70
5
60
6
40
30
2.5
3
3.5
4
4.5
VDD (V)
5
5.5
6
6.5
-60
Average Switchpoint Hysteresis versus Supply Voltage
-40
-20
0
20
TA (°C)
40
60
80
100
Average Switchpoint Hysteresis versus Ambient Temperature
45
45
40
40
35
TA (°C)
30
-40
25
25
20
85
VDD (V)
35
BHYS (G)
BHYS (G)
0
50
40
3
30
5
25
6
20
15
15
10
-20
Average Release Point versus Ambient Temperature
Average Release Point versus Supply Voltage
110
30
-40
2.5
3
3.5
4
4.5
VDD (V)
5
5.5
6
6.5
10
-60
-40
-20
0
20
TA (°C)
40
60
80
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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100
10
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA
A1132
Average High Supply Current versus Ambient Temperature
TA (°C)
-40
25
125
2
4
6
8
VDD (V)
10
12
IDD(HIGH) (mA)
IDD(HIGH) (mA)
Average High Supply Current versus Supply Voltage
16.00
15.75
15.50
15.25
15.00
14.75
14.50
14.25
14.00
13.75
13.50
13.25
13.00
14
16.00
15.75
15.50
15.25
15.00
14.75
14.50
14.25
14.00
13.75
13.50
13.25
13.00
VDD (V)
3
8
12
-60
Average Low Supply Current versus Supply Voltage
4.50
4.25
4.25
4.00
0
20
40
60
TA (°C)
80
100
120
140
160
4.00
3.75
TA (°C)
3.50
-40
3.25
25
3.00
125
2.75
IDD(LOW) (mA)
IDD(LOW) (mA)
-20
Average Low Supply Current versus Ambient Temperature
4.50
3.75
8
VDD (V)
10
12
14
12
2.75
2.25
6
8
3.00
2.25
4
3
3.25
2.50
2
VDD (V)
3.50
2.50
2.00
-40
2.00
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
Allegro MicroSystems
955 Perimeter Road
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160
11
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
CHARACTERISTIC PERFORMANCE DATA
A1132 (continued)
Average Operate Point versus Ambient Temperature
TA (°C)
-40
25
BOP (G)
BOP (G)
Average Operate Point versus Supply Voltage
85
80
75
70
65
60
55
50
45
40
35
30
125
2
4
6
8
VDD (V)
10
12
85
80
75
70
65
60
55
50
45
40
35
30
14
VDD (V)
3
8
12
-60
-40
25
BRP (G)
BRP (G)
TA (°C)
125
2
4
6
8
VDD (V)
10
12
65
60
55
50
45
40
35
30
25
20
15
10
5
14
20
40
60
TA (°C)
80
100
120
140
160
3
8
12
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average Switchpoint Hysteresis versus Ambient Temperature
45
40
40
35
TA (°C)
30
-40
25
25
20
125
VDD (V)
35
BHYS (G)
BHYS (G)
0
VDD (V)
Average Switchpoint Hysteresis versus Supply Voltage
45
3
30
8
25
12
20
15
15
10
-20
Average Release Point versus Ambient Temperature
Average Release Point versus Supply Voltage
65
60
55
50
45
40
35
30
25
20
15
10
5
-40
10
2
4
6
8
VDD (V)
10
12
14
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
Allegro MicroSystems
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160
12
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
FUNCTIONAL DESCRIPTION
Functional Safety
The A1130, A1131, and A1132 were designed in accordance
with the international standard for automotive functional safety,
ISO 26262:2011. This product achieves an ASIL (Automotive Safety Integrity Level) rating of ASIL-B according to the
standard. The A1130, A1131, and A1132 are all classified as
a SEOoC (Safety Element Out of Context) and can be easily
integrated into safety-critical systems requiring higher ASIL ratings that incorporate external diagnostics or use measures such
as redundancy. Safety documentation will be provided to support and guide the integration process. For further information,
contact your local Allegro field applications engineer or sales
representative.
Operation
A1130 – The A1130 output, IDD, switches high (IDD(HIGH)) when
a south polarity magnetic field perpendicular to the Hall-effect
sensor exceeds the operate point threshold, BOP (see panel A of
Figure 1). When the magnetic field is reduced below the release
point, BRP, the device output switches low (IDD(LOW)).
The A1130 is offered in both the LH (3-pin SOT23W) and UA
(3-pin SIP) packages. In the LH package, the vertical Hall element is located near the side of the package closest to pin 1 and
senses magnetic fields parallel with the X-axis (see panel A in
Figure 2). In the UA package, the sensor is located in one of two
positions depending on the configuration selection.
The A1130LUA-X has a vertical Hall-effect sensor located on
the right side of the UA package and detects magnetic fields
parallel with the X-axis (see panel C in Figure 2). The alternative
configuration in the UA package is the A1130LUA-Y, which has
a sensitive element located near the top of the package and senses
fields parallel with the Y-axis (see panel B in Figure 2).
A1131 and A1132 – The output of the A1131 and A1132 devices
switches low (IDD(LOW)) when a south polarity magnetic field
perpendicular to the Hall element exceeds the operate point
threshold, BOP (see panel B of Figure 1). When the magnetic
field is reduced below the release point, BRP, the device output
switches high (IDD(HIGH)).
The A1131 and A1132 are offered exclusively in the LH package.
The vertical Hall element is located near the side of the package closest to pin 1 and senses magnetic fields parallel with the
X-axis (see panel A in Figure 2).
A1130, A1131, and A1132 – The difference in the magnetic operate and release points is the hysteresis (BHYS) of the device. This
built-in hysteresis allows clean switching of the output even in
the presence of external mechanical vibration and electrical noise.
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) will result in an IDD(HIGH) output state. The correct state is attained after the first excursion beyond BOP or BRP.
Refer to Figure 3 for an example of the power-on behavior.
Magnet
N
S
VHD
BX
VHD
S
N
S
N
BX
BY
Magnet
Magnet
(A)
(B)
(C)
Figure 2: Vertical Hall Device (VHD) Sensing Direction for A1130LLH, A1131ELH, and A1132KLH (panel A), A1130LUA-Y (panel
B), and A1130LUA-X (panel C).
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13
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
Power-On Sequence and Timing
The state of the output is only valid when the supply voltage
is within the specified operating range (VDD (min) ≤ VDD ≤
VDD (max)) and the power-on time has elapsed (t > tON). Refer to
Figure 3: Power-On Example for an illustration of the power-on
sequence.
During the power-on time, t < tON, the device output state is
latched in the IDD(HIGH) state. After the first magnetic signal time
slot sample has been processed (t1 in Figure 3), the output will
correspond with the externally applied magnetic field.
During the first diagnostics time slot, the output is latched
according to the magnetic field input from the power-on signal
sampling time slot. A normally operating device will continue
this sampling and diagnostics routine. A device that has a fault
will revert control of the output to the system diagnostics controller and enter the safe state, IDD(AVG)FAULT.
Key
Normal Operation
V+
V+
VDD
VDD(MIN)
VDD
VDD(MIN)
0
tON
0
t
t
tON
IDD(AVG)+
I+
POS
IDD(HIGH)
IDD State
Undefined for
VDD < VDD (min)
t1
POS
IDD(HIGH)
B > BOP
tSAMPLE tDIAG
IDD(LOW)
IDD(LOW)
IDD State
Undefined for
VDD < VDD (min)
t
t1
tSAMPLE tDIAG
IDD(AVG)FAULT
0
tDIAGF
0
t
IDD(AVG)+
I+
IDD(HIGH)
Safe-State
A1130, A1131 and A1132 POS
A1130 IDD
A1131 and A1132 IDD
POS
IDD State
Undefined for
VDD < VDD (min)
t1
POS
IDD(HIGH)
tSAMPLE tDIAG
IDD(LOW)
0
t
Latch Output
(Occurs at end of each tSAMPLE)
BRP < B < BOP
IDD(LOW)
and
B < BRP IDD(AVG)FAULT
IDD State
Undefined for
VDD < VDD (min)
t1
tSAMPLE tDIAG
tDIAGF
0
t
Latch Output
(Occurs at end of each tSAMPLE)
Figure 3: Power-On Example – Normally Operating Device (Left) and Safe-State Device (Right)
Allegro MicroSystems
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14
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
Two-Wire Interface
The regulated current output is configured for two-wire applications, requiring one less wire for operation than switches with
the traditional open-collector output. Additionally, the system
designer inherently gains basic diagnostics because there is
always output current flowing, which should be in either of two
narrow ranges under normal operation, shown in Figure 4 as
IDD(HIGH) and IDD(LOW). Any current level not within these ranges
indicates a fault condition.
If IDD > IDD(HIGH) (max), then a short condition exists, and if
IDD < IDD(LOW) (min), then an open condition exists (except in the
case of an error found during internal diagnostics, in which case
the average supply current is IDD(AVG)FAULT). Any value of IDD
between the allowed ranges for IDD(HIGH) and IDD(LOW) indicates
a general fault condition.
This unique two-wire interface protocol is backward compatible
with legacy systems using two-wire switches. Additionally, the
low fault mode supply current resulting from an internal fault will
fall outside of the low and high supply current ranges, and can be
similarly identified as a sensor fault.
IDD(AVG)
IDD(HIGH) (max)
IDD(HIGH) (min)
Fault
Range for valid I DD(HIGH)
Fault
IDD(LOW) (max)
IDD(LOW ) (min)
Range for valid I DD(LOW)
Fault
IDD(AVG)FAULT
Diagnostics Fault
0
Range for valid I DD(AVG)FAULT
Fault
Figure 4: Diagnostic Characteristics of Supply Current Values
Output Polarity
The output signal may be read as a voltage, VSENSE, by using
a sense resistor, RSENSE, placed either in series with VDD or
with GND (refer to Figure 5). When RSENSE is placed in series
with GND, the output signal voltage is in phase with IDD. When
RSENSE is placed in series with VDD, the output signal voltage is
inverted relative to IDD. Note also that the output of the A1130 is
inverted relative to the outputs of the A1131 and A1132 (refer to
the Selection Guide).
Table 1: Output Signal Polarity
RSENSE Location
(Refer to Figure 5)
IDD State
VSENSE
Logic State
High Side
(VDD Pin Side)
High
Low
Low
High
Low Side
(GND Pin Side)
High
High
Low
Low
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15
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
TYPICAL APPLICATIONS
It is strongly recommended that an external bypass capacitor, CBYP, be connected (in close proximity to the Hall sensor)
between the supply and ground of the device to guarantee correct
performance under harsh environmental conditions and to reduce
noise from internal circuitry. As is shown in Figure 5, a 0.01 µF
capacitor is typical. Use of a larger bypass capacitor may result
in a slower output slew rate, and should be evaluated according
to the requirements set forth by the application. Additionally, an
optional output load capacitor may be added in parallel with the
sense resistor for increased signal filtering and EMC immunity.
The A1130, A1131, and A1132 are designed for functional
safety and comply with ISO 26262:2011 ASIL B. When used in
conjunction with appropriate system-level control, the internal
diagnostic features can assist in meeting the most stringent ASIL
safety requirements. For further information, contact your local
Allegro field applications engineer or sales representative.
Extensive applications information on magnets and Hall-effect
sensors is available in:
Temperature Coefficient and Magnet Selection
The A1130, A1131, and A1132 are designed with a sensitivity
temperature coefficient to compensate for drifts of NdFeB and
ferrite magnets over temperature—as indicated in the specifications table on page 5. This compensation improves the magnetic
system performance over the entire temperature range.
For example, the magnetic field strength from NdFeB decreases
as the temperature increases from 25°C to 150°C. This lower
magnetic field strength means that a lower switching threshold
is required to maintain switching at the same distance from the
magnet to the sensor. Correspondingly, higher switching thresholds are required at cold temperatures, as low as –40°C, due to
the higher magnetic field strength from the NdFeB magnet. The
A1130, A1131, and A1132 compensate the switching thresholds
over temperature as described above. It is recommended that system designers evaluate their magnetic circuit over the expected
operating temperature range to ensure the magnetic switching
requirements are met.
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines For Designing Subassemblies
Using Hall-Effect Devices AN27703.1
• Soldering Methods for Allegro’s Products – SMT and ThroughHole, AN26009
All are provided on the Allegro website:
www.allegromicro.com
1
VDD
A
CBYP
0.01 µF
VSUPPLY
ECU
VSUPPLY
R SENSE
100 Ω
B
CL
(optional)
A113x
VSENSE
GND
2
A
ECU
R SENSE
100 Ω
A
VSENSE
B
CL
(optional)
(A) Low-Side Sensing
CBYP
0.01 µF
A
1
VDD
A113x
GND
2
A
Trace lengths recommended to be
no longer than 5 mm.
B
Optional load capacitor may enhance
EMC immunity.
(B) High-Side Sensing
Figure 5: Typical Application Circuits
Allegro MicroSystems
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16
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
Diagnostics
The A1130, A1131, and A1132 were developed in accordance
with ISO 26262:2011 and feature a proprietary diagnostics routine that enables the achievement of ASIL B safety requirements.
This internal diagnostics routine continuously runs between
magnetic signal sampling time slots during normal operation.
Maximum time slot duration is 70 μs for each of the magnetic
signal sampling and the diagnostics mode.
During the diagnostics time slot, external magnetic signals are
not sampled and the device output will retain the state from the
prior magnetic signal sampling time slot (unless a diagnostics
fault causes the device to enter a safe state). The system provides
continuous fault detection for the internal power supply regulator
and entire signal chain, regardless of the external magnetic field.
The successive operation of the magnetic signal sampling and diagnostics modes results in a Hall signal refresh every 140 µs. This
time slotting technique allows for the proper settling of the signal
during magnetic and diagnostics routines. A channel reset occurs
between slots to force transitions and prevent inter-slot coupling.
During the diagnostics mode time slot, a signal is injected at the
vertical Hall element and checked at the exit of the Schmitt trigger.
During this time, the critical signal path subsystems are monitored
for proper operation. The Hall element biasing circuit and voltage regulator are additionally checked for valid operation. and
the programming block is checked for correct parity. The injected
signal forces two internal state transitions (B > BOP and B < BRP)
under normal operation. In cases when these output transitions do
not occur, or if another internal fault is detected, the average device
supply current will be reduced to IDD(AVG)FAULT (See Diagnostics
Mode Fault Operation section).
When a higher system ASIL rating is required, additional external
safety measures may be employed (e.g. sensor redundancy and
rationality checks, etc.). Refer to the device safety manual for
additional details about the diagnostics.
70 µs
Signal
Diagnostic
Signal
Magnetic
Signal B
OP
BRP
t
Schmitt Output (Internal)
Output Sampling
IDD(HIGH)
Output State
Two Transitions Required
140 µs
IDD(LOW)
Figure 6: Time Slot Multiplexing Diagram (A1130 Polarity Shown)
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17
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
Diagnostics Mode Fault Operation
In the event of a fault, the device will continuously run the
diagnostics routine every 2.75 ms (tDIAGF). The periodic recovery attempt sequence allows the device to continuously check
for fault integrity while maintaining an optimized low supply
current. The recovery period, composed of tDIAG + tDIAGF, is low
duty cycle. In this mode, the current varies from IDD(PEAK)FAULT
while performing the diagnostics test to IDD(BASE)FAULT standby
current.
In the case where the fault is no longer present, normal time-slotting operation will resume, beginning with an internal reset and a
transition to the power-on state. However, if the fault is persistent, the device will remain in fault mode and the supply current
will continue to have an average of IDD(AVG)FAULT. See Equations
1 and 2 (page 5) for determining the fault mode average current.
B
Magnetic Signal
BOP
BRP
0
I
tDIAGF = 2.75 ms
tDIAG = 70 µs
tSAMPLE = 70 µs
t
tDIAGF
tDIAGF
IDD(PEAK)FAULT
IDD(BASE)FAULT
0
tDIAG
Try Recovery Sequence
tDIAG
tSAMPLE/tPO
tDIAG
tSAMPLE
IDD(LOW )
tSAMPLE
tDIAG
tSAMPLE
tDIAG
tSAMPLE
tDIAG
tSAMPLE
tDIAG
IDD(HIGH)
IDD
Failure Detected
Diagnostics Pass
(Internal Reset)
t
Figure 7: Diagnostics Recovery Sequence (A1130 Polarity Shown)
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18
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
CHOPPER STABILIZATION
A limiting factor for switchpoint accuracy when using Hall-effect
technology is the small-signal voltage developed across the Hall
plate. This voltage is proportionally small relative to the offset
that can be produced at the output of the Hall sensor. This makes
it difficult to process the signal and maintain an accurate, reliable
output over the specified temperature and voltage range. Chopper
stabilization is a proven approach used to minimize Hall offset.
The technique, dynamic quadrature offset cancellation, removes
key sources of the output drift induced by temperature and package stress. This offset reduction technique is based on a signal
modulation-demodulation process. Figure 8: Model of Chopper
Stabilization Circuit (Dynamic Offset Cancellation) illustrates
how it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetically induced signal to recover
its original spectrum at baseband while the DC offset becomes
a high-frequency signal. Then, using a low-pass filter, the signal
passes while the modulated DC offset is suppressed.
Allegro’s innovative chopper stabilization technique uses a
high-frequency clock. The high-frequency operation allows a
greater sampling rate that produces higher accuracy, reduced
jitter, and faster signal processing. Additionally, filtering is more
effective and results in a lower noise analog signal at the sensor
output. Devices such as the A1130, A1131, and A1132 that use
this approach have a stable quiescent Hall output voltage, are
immune to thermal stress, and have precise recoverability after
temperature cycling. This technique is made possible through the
use of a BiCMOS process which allows the use of low-offset and
low-noise amplifiers in combination with high-density logic and
sample-and-hold circuits.
Regulator
Clock/Logic
Low-Pass
Filter
Hall
Element
Amp.
Sample, Hold &
Averaging
Figure 8: Model of Chopper Stabilization Circuit (Dynamic Offset Cancellation)
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19
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
POWER DERATING
The device must be operated below the maximum junction temperature of the device, TJ (max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data for each package is also
available on the Allegro MicroSystems website.)
The Package Thermal Resistance, RθJA, is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Thermal radiation from the die through the device case, RθJC, is
relatively small component of RθJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN (1)
∆T = PD × RθJA
(2)
TJ = TA + ∆T
(3)
For example, given common conditions such as:
TA = 25°C, VDD = 8 V, IDD = 3.7 mA, and RθJA = 110°C/W for
the LH package, then:
PD = VDD × IDD = 8 V × 3.7 mA = 29.6 mW
∆T = PD × RθJA = 29.6 mW × 110°C/W = 3.3°C
TJ = TA + ∆T = 25°C + 3.3°C = 28.3°C
A worst-case estimate, PD (max), represents the maximum allowable power level (VDD (max), IDD (max)), without exceeding TJ
(max), at a selected RθJA and TA.
Example: Reliability for VDD at TA = 150°C, package UA, using
low-K PCB. Observe the worst-case ratings for the device, specifically: RθJA = 165°C/W, TJ (max) = 165°C, VDD (max) = 24 V,
and IDD (max) = 17 mA.
Calculate the maximum allowable power level, PD (max). First,
invert equation 3:
∆Tmax = TJ (max) – TA = 165°C – 150°C = 15°C
This provides the allowable increase to TJ resulting from internal
power dissipation.
Then, invert equation 2:
PD (max) = ∆Tmax ÷ RθJA = 15°C ÷ 165°C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
VDD (est) = PD (max) ÷ IDD (max) = 91 mW ÷ 17 mA = 5.4 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤ VDD (est).
Compare VDD (est) to VDD (max). If VDD (est) ≤ VDD (max), then
reliable operation between VDD (est) and VDD (max) requires
enhanced RθJA. If VDD (est) ≥ VDD (max), then operation between
VDD (est) and VDD (max) is reliable under these conditions.
In cases where the VDD (max) level is known, and the system
designer would like to determine the maximum allowable ambient temperature (TA (max)), the calculations can be reversed.
For example, in a worst-case scenario with conditions VDD (max)
= 24 V, IDD (max) = 17 mA, and RθJA = 228°C/W for the LH
package using equation 1, the largest possible amount of dissipated power is:
PD = VIN × IIN
PD = 24 V × 17 mA = 408 mW
Then, by rearranging equation 3:
TA (max) = TJ (max) – ΔT
TA (max) = 165°C – (408 mW × 228°C/W)
TA (max) = 165°C – 93°C = 72°C
In another A1130 example, the maximum supply voltage is equal
to VDD (min). Therefore, VDD (max) = 3 V and IDD (max) = 17
mA. By using equation 1, the largest possible amount of dissipated power is:
PD = VIN × IIN
PD = 3 V × 17 mA = 51 mW
Then, by rearranging equation 3:
TA (max) = TJ (max) – ΔT
TA (max) = 165°C – (51 mW × 228°C/W)
TA (max) = 165°C – 11.6°C = 153.4°C
The example above indicates that at VDD = 3 V and IDD = 17 mA,
the TA (max) can be as high as 153.4°C without exceeding
TJ (max). However the TA (max) rating of the device is 150°C;
the A1130 performance is not guaranteed above TA = 150°C.
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20
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
PACKAGE OUTLINE DRAWINGS
For Reference Only – Not for Tooling Use
(Reference DWG-2840)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.12
2.98 –0.08
4°±4°
3
0.180
+0.020
–0.053
0.96 D
2.90
+0.10
–0.20
1.91
+0.19
–0.06
2.40
0.70
D
0.25 MIN
1.00
2
1
0.55 REF
A
0.25 BSC
0.95
Seating Plane
B
Gauge Plane
8X 10° REF
PCB Layout Reference View
Branded Face
1.00 ±0.13
0.05
0.95 BSC
+0.10
–0.05
0.40 ±0.10
NNN
C
Standard Branding Reference View
N = Last three digits of device part number
A Active Area Depth, 1.00 mm
B Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion
D Hall elements, not to scale
Figure 9: Package LH, 3-Pin SOT23W
(A1130LLH, A1131ELH, A1132KLH)
Allegro MicroSystems
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21
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
For Reference Only – Not for Tooling Use
(Reference DWG-0000404, Rev. 1)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.08
4.09 –0.05
45°
B
C
1.52 ±0.05
+0.08
3.02 –0.05
10°
E
Mold Ejector
Pin Indent
Branded
Face
A
1.02
MAX
45°
0.79 REF
NNN
1
1
2
D Standard Branding Reference View
3
= Supplier emblem
N = Last three digits of device part number
+0.03
0.41 –0.06
14.99 ±0.25
+0.05
0.43 –0.07
A
Dambar removal protrusion (6×)
B
Gate and tie bar burr area
C
Active Area Depth, 1.56 mm
D
Branding scale and appearance at supplier discretion
E
Hall element (not to scale)
1.27 NOM
Figure 10: Package UA, 3-Pin SIP
(A1130LUA-X)
Allegro MicroSystems
955 Perimeter Road
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22
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
For Reference Only – Not for Tooling Use
(Reference DWG-0000404, Rev. 1)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.08
4.09 –0.05
45°
B
1.52 ±0.05
+0.08
3.02 –0.05
C
E
10°
Mold Ejector
Pin Indent
Branded
Face
A
1.02
MAX
45°
0.79 REF
NNN
1
1
2
D Standard Branding Reference View
3
= Supplier emblem
N = Last three digits of device part number
+0.03
0.41 –0.06
14.99 ±0.25
+0.05
0.43 –0.07
A
Dambar removal protrusion (6×)
B
Gate and tie bar burr area
C
Active Area Depth, 0.96 mm
D
Branding scale and appearance at supplier discretion
E
Hall element (not to scale)
1.27 NOM
Figure 11: Package UA, 3-Pin SIP
(A1130LUA-Y)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
23
A1130, A1131,
and A1132
Two-Wire Unipolar Vertical Hall-Effect Switches
with Advanced Diagnostics
Revision History
Number
Date
Description
–
March 16, 2017
Initial release
1
March 22, 2017
Corrected Typical Supply Currents in Selection Guide (page 2)
2
May 25, 2017
Updated Selection Guide packing information (page 2)
3
June 19, 2018
Minor editorial updates
4
July 11, 2019
Minor editorial updates
Copyright 2019, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
24
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