A1184ELHLT-T

A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall-Effect Switches Features and Benefits ▪ Chopper stabilization ▫ Low switchpoint drift over operating temperature range ▫ Low sensitivity to stress ▪ Field programmable for optimized switchpoints ▪ On-chip protection ▫ Supply transient protection ▫ Reverse-battery protection ▫ On-board voltage regulator ▫ 3.5 to 24 V operation Description The A1184 device is a standard, two-wire, unipolar, Hall effect switches. The operate point, BOP, can be field-programmed, after final packaging of the sensor and placement into the application. This advanced feature allows the optimization of the sensor switching performance, by effectively accounting for variations caused by mounting tolerances for the device and the target magnet. This family of devices are produced on the Allegro MicroSystems advanced BiCMOS wafer fabrication process, which implements a patented, high-frequency, chopperstabilization technique that achieves magnetic stability and eliminates the offsets that are inherent in single-element devices exposed to harsh application environments. Commonly found in a number of automotive applications, the A1184 is utilized to sense: seat track position, seat belt buckle presence, hood/trunk latching, and shift selector position. Two-wire unipolar switches are particularly advantageous in price-sensitive applications, because they require one less wire than the more traditional open-collector output switches. Additionally, the system designer gains inherent diagnostics because output current normally flows in either Continued on the next page… Packages: 3 pin SOT23W (suffix LH), and 3 pin SIP (suffix UA) Not to scale Functional Block Diagram V+ VCC Program/Lock Programming Logic Offset Regulator Clock/Logic 0.01 uF Sample and Hold Dynamic Offset Cancellation Low-Pass Filter Amp GND Package UA Only GND A1184-DS, Rev. 4 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch Both devices are offered in two package styles: LH, a SOT-23W miniature low-profile package for surface-mount applications, and UA, a three-lead ultramini Single Inline Package (SIP) for throughhole mounting. Each package is available in a lead (Pb) free version (suffix, –T) with 100% matte tin plated leadframe. Factory-programmed versions are also available. Refer to: A1140, A1141, A1142, A1143, A1145, and A1146. Description (continued) of two narrowly-specified ranges. Any output current level outside of these two ranges is a fault condition. The A1184 also features on-chip transient protection, and a Zener clamp to protect against overvoltage conditions on the supply line. The output current of the A1184 switches HIGH in the presence of a south polarity magnetic field of sufficient strength; and switches LOW otherwise, including when there is no significant magnetic field present. Selection Guide Part Number A1184ELHLT-T A1184EUA-T A1184LLHLT-T A1184LUA-T 1Pb-based Pb-free1 Yes Yes Yes Yes Packing2 7-in. reel, 3000 pieces/reel Bulk, 500 pieces/bag 7-in. reel, 3000 pieces/reel Bulk, 500 pieces/bag Mounting Surface mount 4-pin SIP through hole Surface mount 4-pin SIP through hole Ambient, TA (°C) –40 to 85 Output South (+) Field3 Supply Current at Low Output, ICC(L) (mA) High –40 to 150 5 to 6.9 variants are being phased out of the product line. a. Certain variants cited in this footnote are in production but have been determined to be LAST TIME BUY. This classification indicates that sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: October 31, 2006. Deadlilne for receipt of LAST TIME BUY ORDERS: April 27, 2007. These variants include: A1184EUA and A1184LUA. b. Certain variants cited in this footnote are in production but have been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: May 1, 2006. These variants include:A1184ELHLT and A1184LLHLT. 2Contact Allegro for additional packing options. 3South (+) magnetic fields must be of sufficient strength. Absolute Maximum Ratings Characteristic Supply Voltage Reverse Supply Voltage Magnetic Flux Density Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VCC VRCC B TA TJ(max) Tstg Range E Range L Notes Rating 28 –18 Unlimited –40 to 85 –40 to 150 165 –65 to 170 Units V V G ºC ºC ºC ºC Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch ELECTRICAL CHARACTERISTICS over the operating voltage and temperature range, unless otherwise specified Characteristic Supply Voltage1 Supply Current2 Supply Zener Clamp Voltage Supply Zener Clamp Current3 Reverse Supply Current Output Slew Rate4 Chopping Frequency Power-On Time5 Power-On State6,7 1V CC represents 2Relative values Symbol VCC ICC(L) ICC(H) VZ(supply) IZ(supply) IRCC di/dt fC ton POS Test Conditions Device powered on B BOP ICC = ICC(L)(max) + 3 mA; TA = 25°C VZ(supply) = 28 V VRCC = –18 V No bypass capacitor; capacitance of the oscilloscope performing the measurement = 20 pF After factory trimming; with and without bypass capacitor (CBYP = 0.01 μF) ton ≤ ton(max); VCC slew rate ≥ 25 mV/μs Min. 3.5 5 12 28 – – – – – – Typ. – – – – – – 36 200 – HIGH Max. 24 6.9 17 40 9.9 –1.6 – – 25 – Units V mA mA V mA mA mA/μs kHz μs – the generated voltage between the VCC pin and the GND pin. of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present). 3I ZSUPPLY(max) = ICCL(max) + 3 mA. 4Measured without bypass capacitor between VCC and GND. Use of a bypass capacitor results in slower current change. 5Measured with and without bypass capacitor of 0.01 μF. Adding a larger bypass capacitor causes longer Power-On Time. 6POS is defined as true only with a V CC slew rate of 25 mV / μs or greater. Operation with a VCC slew rate less than 25 mV / μs can permanently harm device performance. 7POS is undefined for t > t or B on RP < B < BOP . MAGNETIC CHARACTERISTICS1 over the operating voltage and temperature range, unless otherwise specified Characteristic Programmable Operate Point Range Initial Operate Point Range Switchpoint Step Size2 Number of Programming Bits Temperature Drift of BOP Hysteresis 1Relative Symbol BOPrange BOPinit BRES – Test Conditions ICC = ICC(H) VCC = 12 V VCC = 5 V, TA = 25°C Switchpoint setting Programming locking Min. 300 – 8 – – – Typ. – 262 16 5 1 – 15 Max. 600 300 24 – – ±20 30 Units G G G Bit Bit G G ∆BOP BHYS BHYS = BOP – BRP 5 values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present). 2The range of values specified for B RES is a maximum, derived from the cumulative programming bit errors. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch Characteristic Data ICC(H) versus Ambient Temperature at Various Levels of VCC (A1184) 20 18 ICC(H) (mA) VCC (V) VCC (V) 16 14 12 10 3.5 12.0 24.0 3.5 12.0 24.0 ICC(L) versus Ambient Temperature at Various Levels of VCC (A1184) 10 8 ICC(L) (mA) 6 4 2 0 -50 0 50 100 150 200 -50 0 50 100 150 200 Ambient Temperature, TA (°C) Ambient Temperature, TA (°C) Average BOP Bits versus Ambient Temperature (A1184) 700 600 500 BOP (G) 400 300 200 100 0 -50 0 50 100 150 200 BOPinit Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 BHYS (G) 30 25 Hysteresis versus Ambient Temperature at Various Levels of VCC (A1184) VCC (V) 20 15 10 5 -50 0 50 100 150 200 3.5 12.0 24.0 Ambient Temperature, TA (°C) Ambient Temperature, TA (°C) Contact Allegro MicroSystems for information. Device Qualification Program EMC (Electromagnetic Compatibility) Requirements Contact your local representative for EMC results. Test Name ESD – Human Body Model ESD – Machine Model Conducted Transients Direct RF Injection Bulk Current Injection TEM Cell Reference Specification AEC-Q100-002 AEC-Q100-003 ISO 7637-2 ISO 11452-7 ISO 11452-4 ISO 11452-3 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch Symbol Test Conditions* Package LH, 1-layer PCB with copper limited to solder pads Package LH, 2-layer PCB with 0.463 in.2 of copper area each side connected by thermal vias Package UA, 1-layer PCB with copper limited to solder pads Value Units 228 110 165 ºC/W ºC/W ºC/W THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance RθJA *Additional thermal information available on Allegro Web site. Power Derating Curve 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 20 VCC(max) Maximum Allowable VCC (V) 2-layer PCB, Package LH (RθJA = 110 ºC/W) 1-layer PCB, Package UA (RθJA = 165 ºC/W) 1-layer PCB, Package LH (RθJA = 228 ºC/W) VCC(min) 120 140 160 180 40 60 80 100 Temperature (ºC) Power Dissipation versus Ambient Temperature 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 20 Power Dissipation, PD (m W) 2l (R aye rP θJ C A= 11 B, P 0 º ac 1-la C/ ka W (R yer PC ) ge L θJA = B H 165 , Pac ºC/ kage W) UA 1-lay er P (R CB, θJA = 228 Packag ºC/W e LH ) 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch Functional Description Operation The output, ICC, of the A1184 device switches high after the magnetic field at the Hall sensor exceeds the operate point threshold, BOP. When the magnetic field is reduced to below the release point threshold, BRP, the device output goes low. The differences between the magnetic operate and release point is called the hysteresis of the device, BHYS. This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. (See figure 1). I+ ICC(H) Switch to High Switch to Low ICC ICC(L) 0 BHYS Figure 1. On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B– direction indicates decreasing south polarity field strength (including the case of increasing north polarity). BOP B– B+ BRP Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch Chopper Stabilization Technique A limiting factor for switchpoint accuracy when using Hall effect technology is the small signal voltage developed across the Hall element. This voltage is proportionally small relative to the offset that can be produced at the output of the Hall sensor device. This makes it difficult to process the signal and maintain an accurate, reliable output over the specified temperature and voltage range. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. The Allegro patented technique, dynamic quadrature offset cancellation, removes key sources of the output drift induced by temperature and package stress. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetically induced signal in the frequency domain through modulation. The subsequent demodulation acts as a modulation process for the offset causing the magnetically induced signal to recover its original spectrum at base band while the dc offset becomes a high frequency signal. Then, using a low-pass filter, the signal passes while the modulated dc offset is suppressed. The chopper stabilization technique uses a 200 kHz high frequency clock. For demodulation process, a sample-and-hold technique is used, where the sampling is performed at twice the chopper frequency (400KHz). The sampling demodulation process produces higher accuracy and faster signal processing capability. Using this chopper stabilization approach, the chip is desensitized to the effects of temperature and stress. This technique produces devices that have an extremely stable quiescent Hall output voltage, is immune to thermal stress, and has precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process which allows the use of low-offset and low-noise amplifiers in combination with high-density logic integration and sample-and-hold circuits. The repeatability of switching with a magnetic field is slightly affected using a chopper technique. The Allegro high frequency chopping approach minimizes the affect of jitter and makes it imperceptible in most applications. Applications that may notice the degradation are those that require the precise sensing of alternating magnetic fields such as ring magnet speed sensing. For those applications, Allegro recommends the “low jitter” family of digital sensors. Regulator Clock/Logic Hall Element Amp Low-Pass Filter Figure 2. Chopper stabilization circuit (dynamic quadrature offset cancellation) Sample and Hold Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch Application Information For additional general application information, visit the Allegro MicroSystems Web site at www. allegromicro.com. Typical Application Circuit The A118x family of devices must be protected by an external bypass capacitor, CBYP, connected between the supply, VCC, and the ground, GND, of the device. CBYP reduces both external noise and the noise generated by the chopper-stabilization function. As shown in figure 3, a 0.01 μF capacitor is typical. Installation of CBYP must ensure that the traces that connect it to the A118x pins are no greater than 5 mm in length. All high-frequency interferences conducted along the supply lines are passed directly to the load through CBYP, and it serves only to protect the A118x internal circuitry. As a result, the load ECU (electronic control unit) must have sufficient protection, other than CBYP, installed in parallel with the A118x. A series resistor on the supply side, RS (not shown), in combination with CBYP, creates a filter for EMI pulses. (Additional information on EMC is provided on the Allegro MicroSystems Web site.) When determining the minimum VCC requirement of the A118x device, the voltage drops across RS and the ECU sense resistor, RSENSE, must be taken into consideration. The typical value for RSENSE is approximately 100 Ω. GND A A B Package UA Only Maximum separation 5 mm V+ VCC B A118x CBYP 0.01 uF GND B RSENSE ECU Figure 3. Typical application circuit Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch Power Derating The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating TJ. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, RθJA, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, RθJC, is relatively small component of RθJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate TJ, at PD. PD = VIN × IIN ΔT = PD × RθJA (2) TJ = TA + ΔT (3) (1) Example: Reliability for VCC at TA = 150°C, package UA, using minimum-K PCB. Observe the worst-case ratings for the device, specifically: RθJA = 165°C/W, TJ(max) = 165°C, VCC(max) = 24 V, and ICC(max) = 17 mA. Calculate the maximum allowable power level, PD(max). First, invert equation 3: ΔTmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165 °C/W = 91 mW Finally, invert equation 1 with respect to voltage: VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 17 mA = 5 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages ≤VCC(est). Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and VCC(max) is reliable under these conditions. For example, given common conditions such as: TA= 25°C, VCC = 12 V, ICC = 4 mA, and RθJA = 140 °C/W, then: PD = VCC × ICC = 12 V × 4 mA = 48 mW ΔT = PD × RθJA = 48 mW × 140 °C/W = 7°C TJ = TA + ΔT = 25°C + 7°C = 32°C A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding TJ(max), at a selected RθJA and TA. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A1184 Programming Protocol Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch V+ VPH The operate switchpoint, BOP , can be field-programmed. To do so, a coded series of voltage pulses through the VCC pin is used to set bitfields in onboard registers. The effect on the device output can be monitored, and the registers can be cleared and set repeatedly until the required BOP is achieved. To make the setting permanent, bitfield-level solid state fuses are blown, and finally, a device-level fuse is blown, blocking any further coding. It is not necessary to program the release switchpoint, BRP , because the difference between BOP and BRP , referred to as the hysteresis, BHYS , is fixed. The range of values between BOP(min) and BOP(max) is scaled to 31 increments. The actual change in magnetic flux (G) represented by each increment is indicated by BRES (see the Operating Characteristics table; however, testing is the only method for verifying the resulting BOP). For programming, the 31 increments are individually identified using 5 data bits, which are physically represented by 5 bitfields in the onboard registers. By setting these bitfields, the corresponding calibration value is programmed into the device. Three voltage levels are used in programming the device: a low voltage, VPL , a minimum required to sustain register settings; a mid-level voltage, VPM , used to increment the address counter in the device; and a high voltage, VPH , used to separate sets of VPM pulses (when short in duration) and to blow fuses (when long in duration). A fourth voltage level, essentially 0 V, is used to clear the registers between pulse sequences. The pulse values are shown in the Programming Protocol Characteristics table and in figure 4. VPM VPL Td(P) 0 Td(0) Td(1) t Figure 4. Pulse amplitudes and durations Additional information on device programming and programming products is available on www. allegromicro.com. Programming hardware is available for purchase, and programming software is available free of charge. Code Programming. Each bitfield must be individually set. To do so, a pulse sequence must be transmitted for each bitfield that is being set to 1. If more than one bitfield is being set to 1, all pulse sequences must be sent, one after the other, without allowing VCC to fall to zero (which clears the registers). The same pulse sequence is used to provisionally set bitfields as is used to permanently set bitfield-level fuses. The only difference is that when provisionally setting bitfields, no fuse-blowing pulse is sent at the end of the pulse sequence. PROGRAMMING PROTOCOL CHARACTERISTICS, over operating temperature range, unless otherwise noted Characteristic Symbol VPL Programming Voltage1 VPM VPH Programming Current2 IPP td(0) Pulse Width td(1) td(P) Pulse Rise Time Pulse Fall Time tr tf tr = 11 μs; 5 V → 26 V; CBYP = 0.1 μF OFF time between programming bits Pulse duration for enable and addressing sequences Pulse duration for fuse blowing VPL to VPM; VPL to VPH VPM to VPL; VPH to VPL Test Conditions Minimum voltage range during programming Min. 4.5 11.5 25.0 20 20 100 5 5 Typ. 5.0 12.5 26.0 190 300 Max. 5.5 13.5 27.0 20 100 Units V V V mA μs μs μs μs μs 1Programming voltages are measured at the VCC pin. 2A bypass capacitor with a minimum capacitance of 0.1 provide the current necessary to blow the fuse. μF must be connected from VCC to the GND pin of the A118x device in order to Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 10 A1184 1. An enable sequence. 2. A bitfield address sequence. Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch vertently setting the bitfield to 1. Instead, blowing the devicelevel fuse protects the 0 bitfields from being accidentally set in the future. When provisionally trying the calibration value, one pulse sequence is used, using decimal values. The sequence for setting the value 510 is shown in figure 5. When permanently setting values, the bitfields must be set individually, and 510 must be programmed as binary 101. Bit 3 is set to 1 (0001002, which is 410), then bit 1 is set to 1 (0000012, which is 110). Bit 2 is ignored, and so remains 0.Two pulse sequences for permanently setting the calibration value 5 are shown in figure 6. The final VPH pulse is maintained for a longer period, enough to blow the corresponding bitfield-level fuse. The pulse sequences consist of the following groups of pulses: 3. When permanently setting the bitfield, a long VPH fuse-blowing pulse. (Note: Blown bit fuses cannot be reset.) 4. When permanently setting the bitfield, the level of VCC must be allowed to drop to zero between each pulse sequence, in order to clear all registers. However, when provisionally setting bitfields, VCC must be maintained at VPL between pulse sequences, in order to maintain the prior bitfield settings while preparing to set additional bitfields. Bitfields that are not set are evaluated as zeros. The bitfield-level fuses for 0 value bitfields are never blown. This prevents inad- V+ VPH VPM VPL 0 Enable Try 510 Address Optional Monitoring Clear t Figure 5. Pulse sequence to provisionally try calibration value 5. V+ VPH VPM VPL Address 0 Enable Address Encode 001002 (410) Blow Enable Blow Encode 000012 (110) t Figure 6. Pulse sequence to permanently encode calibration value 5 (101 binary, or bitfield address 3 and bitfield address 1). Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 11 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch V+ VPH Enabling Addressing Mode. The first segment of code is a keying sequence used to enable the bitfield addressing mode. As shown in figure 7, this segment consists of one short VPH pulse, one VPM pulse, and one short VPH pulse, with no supply interruptions. This sequence is designed to prevent the device from being programmed accidentally, such as by noise on the supply line. VPM VPL 0 t Figure 7. Addressing mode enable pulse sequence V+ VPH Address 1 Address 2 Address n ( ≤ 31) Address Selection. After addressing mode is enabled, the VPM target bitfield address, is indicated by a series of VPM pulses, as shown in figure 8. VPL 0 t Figure 8. Pulse sequence to select addresses V+ Falling edge of final BOP address digit VPH Lock Bit Programming. After the desired BOP calibration value is programmed, and all of the corresponding bitfield-level fuses are blown, the device-level fuse should be blown. To do so, the lock bit (bitfield address 32) should be encoded as 1 and have its fuse blown. This is done in the same manner as permanently setting the other bitfields, as shown in figure 9. VPM VPL 32 pulses 0 Enable Address Encode Lock Bit Blow Figure 9. Pulse sequence to encode lock bit t Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 12 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch Package LH, 3-Pin (SOT-23W) 3.00 .118 2.70 .106 0.15 [.006] M C A B 3.04 .120 2.80 .110 A A 1.49 .059 NOM 8º 0º 0.20 .008 0.08 .003 3 B B 2.10 .083 1.85 .073 Preliminary dimensions, for reference only Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only (reference JEDEC TO-236 AB, except case width and terminal tip-to-tip) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Hall element (not to scale) B Active Area Depth 0.28 [.011] 3X 0.10 [.004] C 3X 0.50 .020 0.30 .012 0.20 [.008] M C A B 0.95 .037 1.90 .075 A 0.96 .038 A NOM 0.60 .024 0.25 .010 1 2 0.25 .010 SEATING PLANE 1.17 .046 0.75 .030 0.15 .006 0.00 .000 C SEATING PLANE GAUGE PLANE Package LH, 3-pin SOT 3 Package UA, 3-pin SIP 1. VCC 2. No connection 3. GND NC 1 2 1. VCC 2. GND 3. GND 1 2 3 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 13 A1184 Standard Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switch Package UA, 3-Pin SIP .164 4.17 .159 4.04 C D .0805 2.04 NOM .0565 1.44 NOM D .062 1.57 .058 1.47 D .122 3.10 .117 2.97 B .085 2.16 MAX .031 0.79 REF A .640 16.26 .600 15.24 .017 0.44 .014 0.35 1 2 3 .019 0.48 .014 0.36 .050 1.27 NOM Dimensions in inches Metric dimensions (mm) in brackets, for reference only A Dambar removal protrusion (6X) B Ejector mark on opposite side C Active Area Depth .0195 [0.50] NOM D Hall element (not to scale) The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright © 2004, 2006 Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 14