A1193

A1190, A1192 and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Features and Benefits ▪ High speed, 4-phase chopper stabilization ▫ Low switchpoint drift throughout temperature range ▫ Low sensitivity to thermal and mechanical stresses ▪ On-chip protection ▫ Supply transient protection ▫ Reverse battery protection ▪ On-board voltage regulator ▫ 3.0 to 24 V operation ▪ Solid-state reliability ▪ Robust EMC and ESD performance ▪ Field programmable for optimized switchpoints ▪ Industry leading ISO 7637-2 performance through use of proprietary, 40-V clamping structure Description The A1190, A1192, and A1193 comprise a family of twowire, unipolar, Hall-effect switches, which can be trimmed by the user at end-of-line to optimize magnetic switchpoint accuracy in the application. These devices are produced on the Allegro® advanced BiCMOS wafer fabrication process, which implements a patented high frequency, 4-phase, chopper-stabilization technique. This technique achieves magnetic stability over the full operating temperature range, and eliminates offsets inherent in devices with a single Hall element that are exposed to harsh application environments. The A119x family has a number of automotive applications. These include sensing seat track position, seat belt buckle presence, hood/trunk latching, and shift selector position. Two-wire unipolar switches are particularly advantageous in cost-sensitive applications because they require one less wire for operation versus the more traditional open-collector output switches. Additionally, the system designer inherently gains diagnostics because there is always output current flowing, which should be in either of two narrow ranges. Any current level not within these ranges indicates a fault condition. All family members are offered in two package styles. The LH is a SOT-23W style, miniature, low profile package for surfacemount applications. The UA is a 3-pin, ultra-mini, single inline package (SIP) for through-hole mounting. Both packages are lead (Pb) free, with 100% matte tin leadframe plating. Packages 3-pin SOT23-W 2 mm × 3 mm × 1 mm (suffix LH) 3-pin ultramini SIP 1.5 mm × 4 mm × 3 mm (suffix UA) Approximate footprint Functional Block Diagram V+ VCC Regulator To all subcircuits Clock/Logic Sample and Hold Dynamic Offset Cancellation 0.01 μF Program / Lock ICC Adjust Offset Adjust Amp Polarity Low-Pass Filter Schmitt Trigger GND UA package only GND A1190-DS, Rev. 3 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Selection Guide Part Number Package Packing1 Output (ICC) in South Polarity Field Low Supply Current at ICC(L) (mA) 2 to 5 Magnetic Operate Point, BOP (G) A1190LLHLT-T2 LH (Surface mount) 7-in. reel, 3000 pieces/reel A1190LLHLX-T LH (Surface mount) 13-in. reel, 10 000 pieces/reel A1190LUA-T3 UA (Through hole) Bulk, 500 pieces/bag A1192LLHLT-T2 LH (Surface mount) 7-in. reel, 3000 pieces/reel A1192LLHLX-T LH (Surface mount) 13-in. reel, 10 000 pieces/reel A1192LUA-T3 UA (Through hole) Bulk, 500 pieces/bag A1193LLHLT-T2 LH (Surface mount) 7-in. reel, 3000 pieces/reel A1193LLHLX-T LH (Surface mount) 13-in. reel, 10 000 pieces/reel A1193LUA-T3 UA (Through hole) Bulk, 500 pieces/bag 1Contact Allegro® for additional packing options. 2These variants available only through authorized distributors. 3Contact factory for availability. Low 5 to 6.9 High 10 to 200 Absolute Maximum Ratings Characteristic Forward Supply Voltage Reverse Supply Voltage Magnetic Flux Density Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VCC VRCC B TA TJ(max) Tstg Range L Notes Rating 28 –18 Unlimited –40 to 150 165 –65 to 170 Unit V V G ºC ºC ºC Pin-out Diagrams 3 Terminal List Table Number Name LH package VCC NC GND UA package VCC GND GND Function Connects power supply to chip; used to apply programming signal LH package: no connection UA package: ground terminal Ground terminal 1 NC 1 2 1 2 3 2 3 LH Package UA Package Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches ELECTRICAL CHARACTERISTICS Valid at TA = –40°C to 150°C, TJ < TJ(max), CBYP = 0.01 μF, through operating supply voltage range; unless otherwise noted Characteristics Supply Voltage1,2 Symbol VCC ICC(L) Supply Current ICC(H) Supply Zener Clamp Voltage Supply Zener Clamp Current Reverse Supply Current Output Slew Rate3 Chopping Frequency Power-Up Time2,4,5 Power-Up 1V Test Conditions Operating, TJ ≤ 165 °C A1190 A1192 A1193 A1190, A1192 A1193 B > BOP B > BOP B < BRP B < BRP B > BOP Min. 3.0 2.0 5 5 12 12 28 – – – – Typ. – – – – – – – – – 90 700 – – ICC(H) Max. 24 5.0 6.9 6.9 17 17 – ICC(L)(max) + 3 mA –1.6 – – 25 25 – Unit V mA mA mA mA mA V mA mA mA / μs kHz μs μs – VZ(sup) IZ(sup) IRCC di/dt fC ton POS ICC = ICC(L)(max) + 3 mA, TA = 25°C VZ(sup) = 28 V VRCC = –18 V No bypass capacitor, capacitance of probe CS = 20 pF A1190, A1192 A1193 CBYP = 0.01 μF, B > BOP + 10 G CBYP = 0.01 μF, B < BRP – 10 G – – – State6,7 ton < ton(max) , VCC slew rate > 25 mV / μs CC represents the generated voltage between the VCC pin and the GND pin. 2The V CC slew rate must exceed 600 mV/ms from 0 to 3 V. A slower slew rate through this range can affect device performance. 3Measured without bypass capacitor between VCC pin and the GND pin. Use of a bypass capacitor results in slower current change. 4Power-Up Time is measured without and with a bypass capacitor of 0.01 μF. Adding a larger bypass capacitor would cause longer Power-Up Time. 5Guaranteed by characterization and design. 6Power-Up State as defined is true only with a V CC slew rate of 25 mV / μs or greater. 7For t > t and B on RP < B < BOP , Power-Up State is not defined. MAGNETIC CHARACTERISTICS1 Valid at TA = –40°C to 150°C, TJ ≤ TJ (max); unless otherwise noted Characteristics Initial Operate Point Programmable Magnetic Operating Point Average Magnetic Step Size3 Switchpoint Temperature Drift Hysteresis 1Relative Symbol BOP(init) BOP STEPBOP ΔBOP BHYS TA = 25°C Test Conditions Min. – 10 3 – 5 Typ. –14 – 4.8 ±20 – Max. 10 200 7.5 – 30 Unit2 G G G G G TA = 25°C, VCC = 5 V values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present). 21 G (gauss) = 0.1 mT (millitesla). 3STEP BOP is a calculated average from the cumulative programmed bits. PROGRAMMABLE PARAMETERS Name BOP Trim Programming Lock Functional Description Fine trim of Programmable Magnetic Operating Point Lock access to programming Quantity of Bits 6 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol RθJA Test Conditions* Package LH, on 4-layer PCB based on JEDEC standard Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side Package UA, on 1-layer PCB with copper limited to solder pads Value 228 110 165 Unit ºC/W ºC/W ºC/W Package Thermal Resistance *Additional thermal information available on the Allegro website Power Derating Curve 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 20 VCC(max) Maximum Allowable VCC (V) 2-layer PCB, Package LH (R JA = 110 ºC/W) 1-layer PCB, Package UA (R JA = 165 ºC/W) 4-layer PCB, Package LH (R JA = 228 ºC/W) VCC(min) 120 140 160 180 40 60 80 100 Temperature (ºC) Power Dissipation versus Ambient Temperature 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 20 Power Dissipation, PD (m W) 2l (R aye rP JA = 1 CB 10 , Pa 1-la ºC ck /W ag (R yer PC eL ) B, P JA = H 165 ack ºC/ age W) UA 4-lay er P (R CB, P JA = 2 28 º ackage C/W LH ) 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Characteristic Performance A1190 A1190 Average Supply Current (Low) versus Temperature 5.0 Average Supply Current (Low) versus Supply Voltage 5.0 Supply Current, ICC(L) (mA) 4.5 4.0 VCC = 24 V 3.5 VCC = 3.0 V 3.0 2.5 2.0 -60 Supply Current, ICC(L) (mA) 4.5 4.0 3.5 TA = –40°C 3.0 2.5 2.0 TA = 25°C TA = 150°C -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26 Ambient Temperature, TA (°C) Supply Voltage, VCC (V) Average Supply Current (Low) versus Temperature 7.0 A1192 and A1193 Average Supply Current (Low) versus Supply Voltage 7.0 A1192 and A1193 Supply Current, ICC(L) (mA) Supply Current, ICC(L) (mA) 6.5 VCC = 24 V 6.0 VCC = 3.0 V 5.5 6.5 TA = 150°C TA = –40°C 6.0 TA = 25°C 5.5 5.0 -60 5.0 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26 Ambient Temperature, TA (°C) Supply Voltage, VCC (V) Average Supply Current (High) versus Temperature 17 A1190/A1192/A1193 Average Supply Current (High) versus Supply Voltage 17 A1190/A1192/A1193 Supply Current, ICC(H) (mA) Supply Current, ICC(H) (mA) 16 VCC = 24 V VCC = 3.0 V 14 16 TA = –40°C TA = 150°C TA = 25°C 15 15 14 13 13 12 -60 12 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26 Ambient Temperature, TA (°C) Supply Voltage, VCC (V) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Average Switchpoint Hysteresis versus Temperature Applied Flux Density at Switchpoint Hysteresis, BHYS (G) 30 A1190/A1192/A1193 25 20 15 VCC = 24 V 10 VCC = 3.0 V 5 -60 -40 -20 0 20 40 60 80 100 120 140 160 Ambient Temperature, TA (°C) Average Operate Point versus Code Average Operate Point, BOP (G) 160 140 120 100 80 60 40 20 0 -20 0 Bit #2 Bit #1 Bit #0 4 8 12 16 20 24 28 32 36 BOP(init) Bit #3 Bit #4 Bit #5 A1190/A1192/A1193 Code Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Functional Description The A1190 and A1192 output, ICC, switches low after the magnetic field at the Hall sensor IC exceeds the operate point threshold, BOP . When the magnetic field is reduced to below the release point threshold, BRP , the device output goes high. This is shown in figure 1, panel A. In the case of the reverse output polarity, as in the A1193, the device output switches high after the magnetic field at the Hall sensor IC exceeds the operate point threshold, BOP . When the magnetic field is reduced to below the release point threshold, BRP, the device output goes low (panel B). The difference between the magnetic operate and release points is called the hysteresis of the device, BHYS . This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. I+ ICC(H) I+ ICC(H) Switch to High ICC(L) 0 Switch to High Switch to Low Switch to Low ICC ICC ICC(L) 0 BRP BHYS BHYS (A) Hysteresis curve for A1190 and A1192 (B) Hysteresis curve for A1193 Figure 1. Alternative switching behaviors are available in the A119x device family. On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B– direction indicates decreasing south polarity field strength (including the case of increasing north polarity). BOP B– B+ B– B+ BRP BOP Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches RSENSE V+ VCC V+ VCC A119x CBYP 0.01 μF A119x CBYP 0.01 μF GND A ECU GND GND A A Package UA Only GND RSENSE (A) Low side sensing (B) High side sensing Figure 2. Typical application circuits Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall sensor IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. The patented Allegro technique, namely Dynamic Quadrature Offset Cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover Regulator its original spectrum at base band, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. The chopper stabilization technique uses a 350 kHz high frequency clock. For demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sampleand-hold circuits. Clock/Logic Hall Element Amp Low-Pass Filter Figure 3. Chopper stabilization circuit (Dynamic Quadrature Offset Cancellation) Sample and Hold Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Programming Guidelines Overview Programming is accomplished by sending a series of input voltage pulses serially through the VCC (supply) pin of the device. A unique combination of different voltage level pulses controls the internal programming logic of the device to select a desired programmable parameter and change its value. There are three voltage levels that must be taken into account when programming. These levels are referred to as high (VPH), mid (VPM), and low (VPL) (see figure 1 and table 1). The A119x family features two programmable modes, Try mode and Blow mode. • In Try mode, programmable parameter values are set and measured. A parameter value is stored temporarily, and reset after cycling the supply voltage. • In Blow mode, the value of a programmable parameter may be permanently set by blowing solid-state fuses internal to the device. Device locking is also accomplished in this mode. The programming sequence is designed to help prevent the device from being programmed accidentally; for example, as a result of noise on the supply line. Although any programmable variable power supply can be used to generate the pulse waveforms, Allegro highly recommends using the Allegro Sensor IC Evaluation Kit, available on the Allegro website On-line Store. The manual for that kit is available for download free of charge, and provides additional information on programming these devices. Definition of Terms Register. The section of the programming logic that controls the choice of programmable modes and parameters. Bit Field. The internal fuses unique to each register, represented as a binary number. Changing the bit field selection in a particular register causes its programmable parameter to change, based on the internal programming logic. Key. A series of VPM voltage pulses used to select a register or mode. tACTIVE VPH Supply Voltage, VCC tPr tPf tBLOW VPM VPL (Supply cycled) 0 Programming pulses Blow pulse tLOW tLOW Figure 4. Programming pulse definition (see table 1) Table 1. Programming Pulse Requirements, Protocol at TA = 25°C (refer also to figure 4) Characteristic Programming Voltage Symbol VPL VPM VPH Measured at the VCC pin. Notes Min. Typ. Max. Unit 4.5 12.5 21 5 – – – – – 100 – – – 5.5 14 27 – – – – 100 100 – V V V mA μs μs μs μs μs mV/ μs Programming Current IPP tLOW tPr = 11 μs, VCC = 5 → 26 V, CBLOW = 0.1 μF (min). Minimum supply current required to ensure proper fuse blowing. CBLOW must be connected between the VCC and GND pins during programming to provide the current necessary for fuse blowing. Duration at VPL separating pulses at VPM or VPH. Duration of pulses at VPM or VPH for key/code selection. Duration of pulse at VPH for fuse blowing. VPL to VPM , or VPL to VPH. VPH to VPL , or VPM to VPL. 175 20 20 90 5 5 375 Pulse Width Pulse Rise Time Pulse Fall Time Blow Pulse Slew Rate tACTIVE tBLOW tPr tPf SRBLOW Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Code. The number used to identify the combination of fuses activated in a bit field, expressed as the decimal equivalent of the binary value. The LSB of a bit field is denoted as code 1, or bit 0. Addressing. Setting the bit field code in a selected register by serially applying a pulse train through the VCC pin of the device. Each parameter can be measured during the addressing process, but the internal fuses must be blown before the programming code (and parameter value) becomes permanent. Fuse Blowing. Applying a VPH pulse of sufficient duration to permanently set an addressed bit by blowing a fuse internal to the device. Once a bit (fuse) has been blown, it cannot be reset. Blow Pulse. A VPH pulse of sufficient duration to blow the addressed fuse. Cycling the Supply. Powering-down, and then powering-up the supply voltage. Cycling the supply is used to clear the programming settings in Try mode. Programming Procedure Programming involves selection of a register, a mode, and then setting values for parameters in the register for evaluation or for fuse blowing. Figure 10 provides an overview state diagram. Register Selection Each programmable parameter can be accessed through a specific register. To select a register, a sequence of voltage pulses consisting of a VPH pulse, a series of VPM pulses, and a VPH pulse (with no VCC supply interruptions) must be applied serially to the VCC pin. The quantity of VPM pulses is called the key, and uniquely identifies each register. The pulses for selection of register key 1, is shown in figure 5. No VPM pulse is sent for key 0. The register selections are shown in table 2. Mode Selection After register selection, the mode is selected, either Try or Blow mode. Try mode is selected by default. To select Blow mode, that mode selection key must be sent. Table 2. Programming Logic Table Register Key Name Bit Field Address (Code) Binary Format [MSB → LSB] Decimal Equivalent Try Mode 0 BOP Trim Up Counting 000000 111111 111111 000000 7 Fuse Check 000111 0 0 11 1 1 0 63 0 63 7 15 Initial value (below minimum |BOP| ) (Try mode sequence starts with code 1); Code corresponds to bit field value (code 1 selects bit field value 000001) Maximum selectable value (above maximum |BOP| ) Initial value (above maximum |BOP| ) (Try mode sequence starts with code 1); Code is automatically inverted (code 1 selects bit field value 111110) Minimum selectable value (below minimum |BOP|) Check integrity of all fuse bits versus low threshold Check integrity of all fuse bits versus high threshold Initial value (below minimum |BOP| ); (Only allows selection of 1 bit per sequence) Maximum selectable value (above maximum |BOP| ); (Only allows selection of 1 bit per sequence) Locks out access to all registers except Fuse Check Description 1 BOP Trim Down Counting Blow Mode 000000 0 BOP Trim 111111 7 Programming Lock 001000 63 8 0 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Blow Mode After the required code is determined for a given parameter, its value can be set permanently by blowing individual fuses in the appropriate register bit field. Blowing is accomplished by selecting the register, then the Blow mode selection key, followed by the appropriate bit field address, and ending the sequence with the Blow pulse. The Blow mode selection key is a sequence of nine VPM pulses followed by one VPH pulse. A complete example is provided in figure 12. The Blow pulse consists of a VPH pulse of sufficient duration, tBLOW , to permanently set an addressed bit by blowing a fuse internal to the device. Due to power requirements, the fuse for each bit in the bit field must be blown individually. The A119x family built-in circuitry allows only one fuse at a time to be blown. During Blow mode, the bit field can be considered a “onehot” shift register. Table 3 relates the quantity of VPM pulses to the binary and decimal values for Blow mode bit field addressing. It should be noted that the simple relationship between the quantity of VPM pulses and the corresponding code is: 2n = Code, where n is the quantity of VPM pulses. The bit field has an initial state of decimal code 0 (binary 000000). Try Mode In Try mode, bit field addressing is accomplished by applying a series of VPM pulses to the VCC pin of the device, as shown in figure 6. Each pulse increases the bit field value for the selected parameter, increasing by one on the falling edge of each additional VPM pulse. When addressing the bit field in Try mode, the quantity of VPM pulses is represented by a decimal number called the code. Addressing activates the corresponding fuse locations in the given bit field by increasing the binary value of an internal DAC, up to the maximum possible code. As the value of the bit field code increases, the value of the programmable parameter changes. Measurements can be taken after each VPM pulse to determine if the required result for the programmable parameter has been reached. Cycling the supply voltage resets all the locations in the bit field that have un-blown fuses to their initial states. When setting the BOP Trim parameter, as an aid to programming, values can be traversed from low to high, or from high to low. To accommodate this direction selection, the value of the bit field (and code) defaults to the value 1, on the falling edge of the final register selection VPH pulse (see figure 5). A complete example is provided in figure 11. VPH Supply Voltage, VCC Bit Field Selection Address Code Format (Decimal Equivalent) Code 5 VPM Code in Binary (Binary) 101 VPL Key 0 Fuse Blowing Target Bits Bit 2 Bit 0 Fuse Blowing Address Code Format Code 4 Code 1 (Decimal Equivalents) Figure 5. Register selection pulse sequence Figure 7. Example of code 5 broken into its binary components Code 2n – 2 Code 2n – 1 Code 2 Code 3 VPH Supply Voltage, VCC Table 3. Blow Mode Bit Field Addressing Quantity of VPM Pulses 1 2 3 4 5 6 Binary Register Setting 000001 000010 000100 001000 010000 100000 Equivalent Code 1 2 4 8 16 32 VPM VPL 0 Figure 6. Try mode bit field addressing pulses Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches To correctly address the fuses to be blown, the code representing the required parameter value must be translated into a binary number. For example, as shown in figure 7, decimal code 5 is equivalent to the binary number 101. Therefore bit 2 must be addressed and blown, the device power supply cycled, and then bit 0 must be addressed and blown. The order of blowing bits, however, is not important. Blowing bit 0 first, and then bit 2 is acceptable. Note: After blowing, the programming is not reversible, even after cycling the supply power. Although a register bit field fuse cannot be reset after it is blown, additional bits within the same register can be blown at any time until the device is locked. For example, if bit 1 (binary 10) has been blown, it is still possible to blow bit 0. The end result would be binary 11 (decimal code 3). Locking the Device After the required code for each parameter is programmed, the device can be locked to prevent further programming of any parameters. To do so, perform the following steps: 1. Ensure that the CBLOW capacitor is mounted. 2. Select the Programming Lock register (key 7). 3. Select Blow mode (key 9). 4. Address bit 3 (001000) by sending four VPM pulses. 5. Send one Blow pulse, at IPP and SRBLOW, and sustain it for tBLOW. 6. Delay for a tLOW interval, then power-down. 7. Optionally check all fuses. Fuse Checking Incorporated in the A119x family is circuitry to simultaneously check the integrity of the fuse bits. The fuse checking feature is enabled by using the Fuse Check register (selection key 7), and while in Try mode, applying the codes shown in table 2. The register is only valid in Try mode and is available before or after the Programming Lock bit is set. Setting the fuse threshold high checks that all blown fuses are properly blown. Setting fuse threshold low checks all un-blown fuses are properly intact. The supply current increases by 250 μA if a marginal fuse is detected. If all fuses are correctly blown or fully intact, there will be no change in supply current. Additional Guidelines The additional guidelines in this section should be followed to ensure the proper behavior of these devices: • A 0.1 μF blowing capacitor, CBLOW, must be mounted between the VCC pin and the GND pin during programming, to ensure enough current is available to blow fuses. • The power supply used for programming must be capable of delivering at least VPH and 175 mA. • Be careful to observe the tLOW delay time before powering down the device after blowing each bit. • Lock the device (only after all other parameters have been programmed and validated) to prevent any further programming of the device. BOP Selection Selecting BOP should be done in two stages. First, Try mode should be used to adjust BOP and monitor the output state. Then the optimum BOP is set permanently using Blow mode. Use the BOP Trim Up Counting register to increase the BOP selection by one Magnetic Step Size, StepBOP , increment with each bit field pulse (see figure 8). Use the BOP Trim Down Counting register to decrease the BOP selection by one StepBOP with each bit field pulse (see figure 9). As an aid to programming, when using down-counting method, the A119x automatically inverts the bit field selection (code 0 in down-counting sets the bit field value 111111, and the actual bit field value decreases until code 63 sets bit field value 000000). Note that the release point, BRP , is a value below BOP . The difference is specified by the Hysteresis, BHYS , which is not programmable. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches (Code 63, Bit value 111111 ) (Code 0, Bit value 111111 ) |BOP(max)| BOP BRP BHYS |BOP(max)| BOP BRP BHYS |BOP(min)| (Code 0, Bit value 000000 ) BOP BRP BHYS (Code 63, Bit value 000000) |BOP(min)| BOP BRP BHYS 0 Figure 8. BOP Selection Up Counting 31 63 0 31 63 Try Mode, Bit Field Code Try Mode, Bit Field Code Figure 9. BOP Selection Down Counting Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Figure 10. Programming state diagram Figure 11. Example of Try mode pulse sequence, Register Key = BOP selection down counting Figure 12. Example of Blow mode pulse sequence, Register Key = BOP selection bit field 2 (code 4) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Power Derating The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating TJ. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, RJA, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, RJC, is relatively small component of RJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate TJ, at PD. PD = VIN × IIN  T = PD × RJA TJ = TA + ΔT For example, given common conditions such as: TA= 25°C, VCC = 12 V, ICC = 4 mA, and RJA = 140 °C/W, then: PD = VCC × ICC = 12 V × 4 mA = 48 mW  T = PD × RJA = 48 mW × 140 °C/W = 7°C TJ = TA + T = 25°C + 7°C = 32°C A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding TJ(max), at a selected RJA and TA. (1) (2) (3) Example: Reliability for VCC at TA = 150°C, package UA, using a low-K PCB. Observe the worst-case ratings for the device, specifically: RJA = 165 °C/W, TJ(max) = 165°C, VCC(max) = 24 V, and ICC(max) = 17 mA. Calculate the maximum allowable power level, PD(max). First, invert equation 3: Tmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = Tmax ÷ RJA = 15°C ÷ 165 °C/W = 91 mW Finally, invert equation 1 with respect to voltage: VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 17 mA = 5 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages ≤VCC(est). Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and VCC(max) is reliable under these conditions. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Package LH, 3-Pin SOT23W +0.12 2.98 –0.08 1.49 D 3 A 4°±4° +0.020 0.180–0.053 0.96 D +0.10 2.90 –0.20 D +0.19 1.91 –0.06 0.25 MIN 1.00 1 2 0.55 REF 0.25 BSC Seating Plane Gauge Plane 8X 10° REF Branded Face 2.40 0.70 0.95 B PCB Layout Reference View 1.00 ±0.13 NNT +0.10 0.05 –0.05 0.95 BSC 0.40 ±0.10 1 C Standard Branding Reference View N = Last two digits of device part number T = Temperature code For Reference Only; not for tooling use (reference DWG-2840) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A B Active Area Depth, 0.28 mm REF Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Branding scale and appearance at supplier discretion Hall element, not to scale C D Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Package UA, 3-Pin SIP +0.08 4.09 –0.05 45° B C E 2.05 NOM 10° E 1.52 ±0.05 Mold Ejector Pin Indent Branded Face 0.79 REF 45° NNN 1.44 NOM +0.08 3.02 –0.05 E 1.02 MAX A 1 D Standard Branding Reference View 1 2 3 = Supplier emblem N = Last three digits of device part number 14.99 ±0.25 +0.03 0.41 –0.06 For Reference Only; not for tooling use (reference DWG-9065) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown +0.05 0.43 –0.07 A B C Dambar removal protrusion (6X) Gate and tie bar burr area Active Area Depth, 0.50 mm REF Branding scale and appearance at supplier discretion Hall element (not to scale) D E 1.27 NOM Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 A1190, A1192, and A1193 Programmable, Chopper-Stabilized, Two Wire Hall-Effect Switches Revision History Revision Rev. 3 Revision Date November 17, 2011 Description of Revision Update product selection and VCC , ton , tBLOW, and programming lock Copyright ©2009-2011, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18