A1325LUA-T

A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output FEATURES AND BENEFITS • Temperature-stable quiescent output voltage and sensitivity • Output voltage proportional to magnetic flux density • Low-noise output increases accuracy • Precise recoverability after temperature cycling • Ratiometric rail-to-rail output • Wide ambient temperature range: –40°C to 150°C • Immune to mechanical stress • Solid-state reliability • Enhanced EMC performance for stringent automotive applications PACKAGES 3-pin ultramini SIP 1.5 mm × 4 mm × 3 mm (suffix UA) 3-pin SOT23-W 2 mm × 3 mm × 1 mm (suffix LH) DESCRIPTION New applications for linear output Hall-effect devices, such as displacement, angular position, and current measurement, require high accuracy in conjunction with small package size. The Allegro™ A1324, A1325, and A1326 linear Hall-effect sensor ICs are designed specifically to achieve both goals. This temperature-stable device is available in a miniature surface mount package (SOT23W) and an ultra-mini through-hole single in-line package. These ratiometric Hall effect sensor ICs provide a voltage output that is proportional to the applied magnetic field. They feature a quiescent voltage output of 50% of the supply voltage. The A1324/25/26 feature factory programmed sensitivities of 5.0 mV/G, 3.125 mV/G, and 2.5 mV/G, respectively. The features of these linear devices make them ideal for use in automotive and industrial applications requiring high accuracy, and operate through an extended temperature range, –40°C to 150°C. Each BiCMOS monolithic circuit integrates a Hall element, temperature-compensating circuitry to reduce the intrinsic sensitivity drift of the Hall element, a small-signal high-gain amplifier, a clamped low-impedance output stage, and a proprietary dynamic offset cancellation technique. These devices are available in a 3-pin ultra-mini SIP package (UA), and a 3-pin surface mount SOT-23 style package (LH). Both are lead (Pb) free, with 100% matte tin leadframe plating. Approximate footprint Functional Block Diagram V+ To All Subcircuits Tuned Filter Dynamic Offset Cancellation VCC Sensitivity and Sensitivity TC VOUT Offset Trim Control GND A1324-DS, Rev. 8 MCO-0000598 June 11, 2020 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Selection Guide Part Number Sensitivity (Typ.) (mV/G) Packing 1 Package A1324LLHLT-T 3,000 pieces per reel 3-pin SOT-23W surface mount A1324LLHLX-T 10,000 pieces per reel 3-pin SOT-23W surface mount A1324LUA-T2 500 pieces per bag 3-pin ultramini SIP through hole mount A1325LLHLT-T 3,000 pieces per reel 3-pin SOT-23W surface mount A1325LLHLX-T 10,000 pieces per reel 3-pin SOT-23W surface mount A1325LUA-T 2 500 pieces per bag 3-pin ultramini SIP through hole mount A1326LLHLT-T 3,000 pieces per reel 3-pin SOT-23W surface mount A1326LLHLX-T 10,000 pieces per reel 3-pin SOT-23W surface mount 500 pieces per bag 3-pin ultramini SIP through hole mount A1326LUA-T 2 5.000 3.125 2.500 1 Contact Allegro™ 2 Contact for additional packing options. factory for availability. Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit Forward Supply Voltage VCC 8 V Reverse Supply Voltage VRCC –0.1 V Forward Output Voltage VOUT 15 V Reverse Output Voltage VROUT –0.1 V Output Source Current IOUT(SOURCE) VOUT to GND 2 mA IOUT(SINK) VCC to VOUT 10 mA Output Sink Current Operating Ambient Temperature TA –40 to 150 ºC Maximum Junction Temperature TJ(max) 165 ºC Tstg –65 to 170 ºC Storage Temperature L temperature range Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* RθJA Package Thermal Resistance Value Unit Package LH, on 4-layer PCB with copper limited to solder pads 228 ºC/W Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side, connected by thermal vias 110 ºC/W Package UA, on 1-layer PCB with copper limited to solder pads 165 ºC/W *Additional thermal information available on the Allegro website Pinout Diagrams Terminal List Table Name 3 1 2 LH Package 1 2 3 Number Function LH UA VCC 1 1 Input power supply; tie to GND with bypass capacitor VOUT 2 3 Output signal; also used for programming GND 3 2 Ground UA Package Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output OPERATING CHARACTERISTICS Valid throughout TA range, CBYPASS = 0.1 µF, VCC = 5 V; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit1 Electrical Characteristics Supply Voltage VCC 4.5 5.0 5.5 V Supply Current ICC No load on VOUT – 6.9 9 mA Power-On Time2 tPO TA = 25°C, CL (PROBE) = 10 pF – 32 – µs Supply Zener Clamp Voltage VZ TA = 25°C, ICC = 12 mA 6 8.3 – V Small signal, –3 dB – 17 – kHz TA = 25°C – 400 – kHz Internal Bandwidth Chopping Frequency3 BWi fC Output Characteristics Quiescent Voltage Output Output Referred Noise VOUT(Q) VN Input Referred RMS Noise Density VNRMS DC Output Resistance ROUT Output Load Resistance Output Load Capacitance Output Saturation Voltage RL CL B = 0 G, TA = 25°C 2.425 2.500 2.575 V A1324, TA = 25°C, CBYPASS = 0.1 µF – 7.0 – mV(p-p) A1325, TA = 25°C, CBYPASS = 0.1 µF – 4.4 – mV(p-p) A1326, TA = 25°C, CBYPASS = 0.1 µF – 3.5 – mV(p-p) TA = 25°C, CBYPASS = open, no load on VOUT, f |B(– )| .  SensB(+)   × 100% SymERR = 1–  SensB(–)  (11) where SensBx is defined as in equation 9, and B(+), B(–) are positive and negative magnetic fields such that |B(+)| = |B(–)|. Ratiometry Error The A132x features a ratiometric output. This means that the quiescent voltage output, VOUT(Q) , magnetic sensitivity, Sens, and clamp voltages, VCLPHIGH and VCLPLOW , are proportional to the supply voltage, VCC. In other words, when the supply voltage increases or decreases by a certain percentage, each characteristic also increases or decreases by the same percentage. Error is the difference between the measured change in the supply voltage, relative to 5 V, and the measured change in each characteristic. The ratiometric error in quiescent voltage output, RatVOUT(Q) (%), for a given supply voltage, VCC, is defined as:  VOUT(Q)VCC ⁄ VOUT(Q)5V   × 100% RatVOUT(Q) = 1– VCC ⁄ 5 V   (12) SensVCC ⁄ Sens5V    × 100% RatVOUT(Q) = 1– VCC ⁄ 5 V   (13) The ratiometric error in magnetic sensitivity, RatSENS (%), for a given supply voltage, VCC, is defined as: Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Typical Characteristics (30 pieces, 3 fabrication lots) Average Supply Current versus Ambient Temperature VCC = 5 V 12 11 ICCav (mA) 10 9 8 7 6 5 4 – 40 25 150 TA (°C) Average Negative Linearity versus Ambient Temperature VCC = 5 V 105 105 104 104 103 103 102 102 Lin–av (%) Lin+av (%) Average Postive Linearity versus Ambient Temperature VCC = 5 V 101 100 99 101 100 99 98 98 97 97 96 96 95 – 40 25 95 150 – 40 TA (°C) Average Quiescent Voltage Output Ratiometry versus Ambient Temperature 102.0 100.6 VCC 5.5 to 5.0 V 100.4 4.5 to 5.0 V 100.2 100.0 99.8 99.6 VCC 5.5 to 5.0 V 101.5 RatSens(av) (%) RatVOUTQ(av) (%) 150 Average Sensitivity Ratiometry versus Ambient Temperature 101.0 100.8 101.0 4.5 to 5.0 V 100.5 100.0 99.5 99.0 99.4 98.5 99.2 99.0 25 TA (°C) – 40 25 TA (°C) 150 98.0 – 40 25 150 TA (°C) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Typical Characteristics, continued (30 pieces, 3 fabrication lots) Average Absolute Quiescent Voltage Output versus Ambient Temperature VCC = 5 V Quiescent Voltage Output versus Supply Voltage TA = 25°C 3.0 2.565 2.525 2.9 A1324 A1325 2.8 A1325 A1326 2.7 A1326 2.505 2.485 VOUT(Q) (V) VOUT(Q)av (V) 2.545 A1324 2.6 2.5 2.4 2.3 2.465 2.2 2.445 2.1 2.0 2.425 – 40 25 150 4.5 TA (°C) 6.0 5.5 A1324 Sensav (mV/G) Sensav (mV/G) 6.0 5.5 4.5 4.0 3.5 A1325 3.0 2.0 A1324 5.0 4.5 4.0 3.5 A1325 3.0 A1326 2.5 2.0 A1326 2.5 1.5 – 40 25 1.0 150 4.5 TA (°C) 10 8 8 6 6 4 4 ∆Sensav (%) 10 2 0 -2 -4 5 VCC (V) 5.5 Average Sensitivity Drift versus Ambient Temperature ∆Sensav values relative to 25°C, VCC = 5 V Average Quiescent Voltage Output Drift versus Ambient Temperature ∆VOUT(Q)av values relative to 25°C, VCC = 5 V ∆VOUT(Q)av (G) 5.5 Average Sensitivity versus Supply Voltage TA = 25°C Average Absolute Sensitivity versus Ambient Temperature VCC = 5 V 5.0 5 VCC (V) 2 0 -2 -4 -6 -6 -8 -8 -10 -10 – 40 25 TA (°C) 150 – 40 25 150 TA (°C) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output V+ 1[1] VCC VOUT 2[3] VOUT A132x CBYPASS 0.1 µF GND 3[2] Pin numbers in brackets refer to the UA package Typical Application Circuit Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switch point accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. Allegro employs a technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at baseband, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. In addition to the removal of the thermal and stress related offset, this novel technique also reduces the amount of thermal noise in the Hall IC while completely removing the modulated residue resulting from the chopper operation. The chopper stabilization technique uses a high frequency sampling clock. For demodulation process, a sample-and-hold technique is used. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample-and-hold circuits. Regulator Clock/Logic Hall Element Amp Anti-Aliasing LP Filter Tuned Filter Concept of Chopper Stabilization Technique Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Package LH, 3-Pin SOT23W +0.12 2.98 –0.08 1.49 D 3 +4° 4° –0° A +0.020 0.180–0.053 0.96 D +0.10 2.90 –0.20 +0.19 1.91 –0.06 2.40 0.70 D 0.25 MIN 1.00 2 1 0.55 REF 0.25 BSC 0.95 Seating Plane Gauge Plane 8X 10° REF B PCB Layout Reference View Branded Face 1.00 ±0.13 0.95 BSC +0.10 0.05 –0.05 0.40 ±0.10 NNN 1 C Standard Branding Reference View N = Last three digits of device part number For Reference Only; not for tooling use (reference DWG-2840) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Active Area Depth, 0.28 mm REF B Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances C Branding scale and appearance at supplier discretion D Hall element, not to scale Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Package UA, 3-Pin SIP +0.08 4.09 –0.05 45° B C E +0.08 3.02 –0.05 2.05 NOM 1.52 ±0.05 1.44 NOM E 10° Mold Ejector Pin Indent E Branded Face A 1.02 MAX 45° NNN 0.79 REF 1 D Standard Branding Reference View 1 2 = Supplier emblem N = Last three digits of device part number 3 +0.03 0.41 –0.06 14.99 ±0.25 +0.05 0.43 –0.07 For Reference Only; not for tooling use (reference DWG-9065) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Dambar removal protrusion (6X) B Gate and tie bar burr area C Active Area Depth, 0.50 mm REF D Branding scale and appearance at supplier discretion E Hall element (not to scale) 1.27 NOM Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Revision History Number Date 3 September 16, 2013 Update product selection Description 4 September 26, 2013 Fixed UA package drawing 5 February 14, 2019 Minor editorial updates 6 February 21, 2020 Minor editorial updates 7 June 8, 2020 Added variant with 3-pin ultramini SIP through hole mount with 2.54 mm lead spacing to Selection Guide (page 2) 8 June 11, 2020 Removed leadform variant (page 2) Copyright 2020, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13