A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
2
-
FEATURES AND BENEFITS
DESCRIPTION
• Contactless 0° to 360° angle sensor IC, for angular
position, rotational speed, and direction measurement
□ Capable of sensing magnet rotational speeds targeting
12b effective resolution with 900 G field
□ Circular Vertical Hall (CVH) technology provides a
single channel sensor system supporting operation
across a wide range of air gaps
• Developed in accordance with ISO 26262:2011
requirements for hardware product development for use
in safety-critical applications
□ Single die version designed to meet ASIL B
requirements when integrated and used in conjunction
with the appropriate system-level control, in the
manner prescribed in the A1333 Safety Manual
□ Dual die version designed to meet ASIL D
requirements when integrated and used in conjunction
with the appropriate system-level control, in the
manner prescribed in the A1333 Safety Manual
• High diagnostic coverage
□ On-chip diagnostics include logic built-in self-test
(LBIST), signal path diagnostics, and watchdogs to
support safety-critical (ASIL) applications
□ 4-bit CRC on SPI
• On-chip EEPROM for storing factory and customer
calibration parameters
□ Single-bit error correction, dual-bit error detection
through the use of error correction control (ECC)
The A1333 is a 360° angle sensor IC that provides contactless
high-resolution angular position information based on magnetic
Circular Vertical Hall (CVH) technology. It has a system-onchip (SoC) architecture that includes: a CVH front end, digital
signal processing, and motor commutation (UVW) or encoder
outputs (A, B, I). It also includes on-chip EEPROM technology,
capable of supporting up to 100 read/write cycles, for flexible
end-of-line programming of calibration parameters. The A1333
is ideal for automotive applications requiring 0° to 360° angle
measurements, such as electronic power steering (EPS), rotary
PRNDLs, and throttle systems.
The A1333 supports customer integration into safety-critical
applications.
The A1333 is available in a dual-die 24-pin eTSSOP and a
single-die 14-pin TSSOP package. The packages are lead (Pb)
free with 100% matte-tin leadframe plating.
PACKAGES:
24-pin eTSSOP (Suffix LP)
Not to scale
Continued on next page...
Dual Independent SoCs
BYP_1
VCC_1
Single SoC
SoC die 1
Regulator
To all internal circuits
EEPROM
CRC Error Detection/
Correction
SPI
Control
S
GND_1
UI_D IAG
.
Control
N
eTSSOP-24
S
N
14-pin TSSOP (Suffix LE)
Magnet oriented
for 0° output
Target
Magnet
CS_1/SA0_1
MISO_1
MOSI_1/SA1_1
SCLK_1
Adjustable
Discon Pt
(0 o Angle)
Temp
Sensor
MS egment
ADC
Circular
Vertical
Hall
ADC
PWM_1
A_1/U_1
B_1/V_1
Digital Processing
UI_DIAG
(Bias Current)
SPI
Interface
w/ 4-bit
CRC
CW/CCW
Rotation
Angle
Compensation
PLL
Angle
Detect
Turns
Count
Field
Measurement
ZCD
Angle
Detect
Data
Registers
I_1/W_1
TEST_1
eTSSOP-14
xxx_2
SoC die 2
Figure 1: A1333 Magnetic Circuit and IC Diagram
A1333-DS, Rev. 9
MCO-0000310
April 20, 2021
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
FEATURES AND BENEFITS (continued)
• Supports harsh operating conditions required for automotive
and industrial applications, including direct connection to
12 V battery
□ Operating temperature range from –40°C to 150°C
□ Operating supply voltage range from 4.0 to 16.5 V
♦ Can support ISO 7637-2 Pulse 5b up to 39 V
• Multiple output formats supported for ease of system
integration
□ ABI/UVW output provides high resolution, low latency, and
PWM for initial position
□ 10 MHz SPI for low latency angle and diagnostic
information; enables multiple independent ICs to be
connected to the same bus
□ Output resolution on ABI and UVW are selectable
• Multiple programming / configuration formats supported
□ The system can be completely controlled and programmed
over SPI, including EEPROM writes
□ For system with limited pins available, writing and reading
can be performed over VCC and PWM pins. This allows
configuring the EEPROM in production line for a device
with only ABI/UVW and PWM pins connected.
• Stacked dual die construction to improve die-to-die matching
for systems that require redundant sensors
• Reduces magnet misalignment impact on die-to-die matching
for a given magnet diameter, relative to “side-by-side” dual
die orientation
SELECTION GUIDE
Part Number
System Die
Package
Packing
Interface Voltage
A1333LLPTR-DD-T
Dual
24-pin eTSSOP
4000 pieces per 13-in. reel
3.3 V
A1333LLETR-T
Single
14-pin TSSOP
4000 pieces per 13-in. reel
3.3 V
A1333LLPTR-5-DD-T
Dual
24-pin eTSSOP
4000 pieces per 13-in. reel
5V
A1333LLETR-5-T
Single
14-pin TSSOP
4000 pieces per 13-in. reel
5V
ABSOLUTE MAXIMUM RATINGS
Rating
Unit
Forward Supply Voltage
Characteristic
Symbol
VCC
Not sampling angles
Notes
26.5
V
Reverse Supply Voltage
VRCC
Not sampling angles
18
V
All Other Pins Forward Voltage
VIN
5.5
V
All Other Pins Reverse Voltage
VR
0.5
V
Operating Ambient
Temperature [1]
Maximum Junction Temperature
Storage Temperature
[1] Maximum
–40 to 150
°C
TJ(max)
TA
L range
170
°C
Tstg
–65 to 170
°C
operational voltage is reduced at high ambient temperatures (TA). See Operating Characteristics, footnote 2.
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Package Thermal Resistance
[2] Additional
Symbol
RθJA
Test Conditions [2]
Value
Unit
LP-24 package
69
°C/W
LE-14 package
82
°C/W
thermal information available on the Allegro website.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
Table of Contents
Device Programming Interfaces............................................ 29
Interface Structure........................................................... 29
SPI................................................................................. 30
Manchester Interface........................................................ 35
EEPROM and Shadow Memory Usage.................................. 41
Enabling EEPROM Access............................................... 41
EEPROM Write Lock........................................................ 41
Write Transaction to EEPROM and Other Extended Locations.41
Read Transaction to EEPROM and Other Extended Locations.45
Shadow Memory Read and Write Transactions.................... 47
Primary Serial Interface Registers Reference......................... 48
EEPROM/Shadow Memory Table.......................................... 62
Safety and Diagnostics........................................................ 71
Built-In Self Tests............................................................. 71
Status and Error Flags...................................................... 71
Application Information........................................................ 75
ESD Performance............................................................ 75
Setting the Zero-Degree Position....................................... 76
Magnetic Target Requirements.......................................... 76
Magnetic Misalignment..................................................... 77
I/O Structures..................................................................... 78
Package Outline Drawings................................................... 79
APPENDIX A: Angle Error and Drift Definition........................A-1
APPENDIX B: SPI Interface Error Flag Description................B-1
Features and Benefits............................................................ 1
Description........................................................................... 1
Packages............................................................................. 1
Simplified Block Diagram....................................................... 1
Selection Guide.................................................................... 2
Absolute Maximum Ratings.................................................... 2
Thermal Characteristics......................................................... 2
Pinout Diagrams and Terminal Lists......................................... 4
Operating Characteristics....................................................... 6
Typical Performance Characteristics........................................ 9
Functional Description......................................................... 14
Overview........................................................................ 14
Angle Measurement......................................................... 14
System Level Timing........................................................ 14
Impact of High Speed Sensing.......................................... 14
Measured Performance Over RPM.................................... 15
Power-Up....................................................................... 18
PWM Output................................................................... 18
Incremental Output Interface (ABI)..................................... 19
Brushless DC Motor Output (UVW).................................... 25
Angle Hysteresis.............................................................. 27
Turns Counting................................................................ 28
VCC2
VCC1
0.1 µF
0.1 µF
0.1 µF
0.1 µF
BYP_1 VCC_1
CS_1/SA0_1
SCLK_1
MOSI_1/SA1_1
MISO_1
TEST_1
Host
Microprocessor
VCC_2
PWM_1
A_1/U_1
B_1/V_1
I_1/W_1
A1333
CS_2/SA0_2
SCLK_2
MOSI_2/SA1_2
MISO_2
TEST_2
BYP_2
PWM_2
A_2/U_2
B_2/V_2
I_2/W_2
GND_1 GND_2
Figure 2: Typical Application Circuit
Both die are electrically separate, and may be operated
simultaneously using different Power/GND sources.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
PINOUT DIAGRAMS AND TERMINAL LIST TABLES
Pinout Diagram
LE 14-Pin TSSOP
LE 14-Pin TSSOP Terminal List Table
Pin Name
Pin Number
Function
BYP
1
External bypass capacitor terminal for internal regulator
VCC
2
Power Supply / Manchester Input
TEST
3
Test pin; bring to GND
PWM Angle Output / Manchester Output
BYP
1
14 I/W
VCC
2
13 B/V
TEST
3
12 A/U
PWM
4
PWM
4
11 MISO
GND
5, 6, 7
GND
5
10 MOSI/SA1
GND
6
9 SCLK
CS /SA0
8
GND
7
8 CS/SA0
SCLK
9
MOSI/SA1
10
MISO
11
SPI Master Input / Slave Output
A/U
12
Option 1: Quadrature A output signal
Option 2: U (phase 1) output signal
B/V
13
Option 1: Quadrature B output signal
Option 2: V (phase 2) output signal
I/W
14
Option 1: Quadrature I (index) output signal
Option 2: W (phase 3) output signal
Device ground terminal
SPI: Chip Select terminal, active low input
Manchester: LSB of ID value. Tie to BYP for “1”, GND for “0”
SPI Clock terminal input
SPI: Master Output, Slave Input
Manchester: MSB of ID value. Tie to BYP for “1”, GND for “0”
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Pinout Diagram
LP 24-Pin eTSSOP
CS_1/SA0_1 1
24 BYP_2
SCLK_1 2
23 VCC_2
MOSI_1/SA1_1 3
22 TEST_2
MISO_1 4
21 PWM_2
A_1/U_1 5
20 GND_2
B_1/V_1 6
19 I_2/W_2
I_1/W_1 7
PAD
18 B_2/V_2
GND_1 8
17 A_2/U_2
PWM_1 9
16 MISO_2
TEST_1 10
15 MOSI_2/SA1_2
VCC_1 11
14 SCLK_2
BYP_1 12
13 CS_2/SA0_2
LP 24-Pin eTSSOP Terminal List Table
Pin Name
Pin Number
Function
SPI: Chip Select terminal, active low input (die 1)
CS_1 /SA0_1
1
SCLK_1
2
MOSI_1/SA1_1
3
MISO_1
4
SPI Master Input / Slave Output (die 1)
A_1/U_1
5
Option 1: Quadrature A output signal signal (die 1)
Option 2: U (phase 1) output signal (die 1)
B_1/V_1
6
Option 1: Quadrature B output signal (die 1)
Option 2: V (phase 2) output signal (die 1)
I_1/W_1
7
Option 1: Quadrature I (index) output signal (die 1)
Option 2: W (phase 3) output signal (die 1)
Manchester: LSB of ID value for die 1. Tie to BYP_1 for “1”, GND_1 for “0”
SPI Clock terminal input (die 1)
SPI: Master Output, Slave Input (die 1)
Manchester: MSB of ID value for die 1. Tie to BYP_1 for “1”, GND_1 for “0”
GND_1
8
Device ground terminal (die 1)
PWM_1
9
PWM Angle Output / Manchester Output (die 1)
TEST_1
10
Test pin; bring to GND (die 1)
VCC_1
11
Power Supply / Manchester Input (die 1)
BYP_1
12
External bypass capacitor terminal for internal regulator (die 1)
CS_2/SA0_2
13
SCLK_2
14
MOSI_2/SA1_2
15
MISO_2
16
SPI Master Input / Slave Output (die 2)
A_2/U_2
17
Option 1: Quadrature A output signal (die 2)
Option 2: U (phase 1) output signal (die 2)
B_2/V_2
18
Option 1: Quadrature B output signal (die 2)
Option 2: V (phase 2) output signal (die 2)
I_2/W_2
19
Option 1: Quadrature I (index) output signal (die 2)
Option 2: W (phase 3) output signal (die 2)
GND_2
20
Device ground terminal (die 2)
SPI: Chip Select terminal, active low input (die 2)
Manchester: LSB of ID value for die 2. Tie to BYP_2 for “1”, GND_2 for “0”
SPI Clock terminal input (die 2)
SPI: Master Output, Slave Input (die 2)
Manchester: MSB of ID value for die 2. Tie to BYP_2 for “1”, GND_2 for “0”
PWM_2
21
PWM Angle Output / Manchester Output (die 2)
TEST_2
22
Test pin; bring to GND (die 2)
VCC_2
23
Power Supply / Manchester Input (die 2)
BYP_2
24
External bypass capacitor terminal for internal regulator (die 2)
PAD
PAD
Exposed pad for thermal dissipation
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
OPERATING CHARACTERISTICS: Valid over the full operating voltage and ambient temperature ranges, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit [1]
4.0
–
16.5
V
ELECTRICAL CHARACTERISTICS
Supply Voltage [2]
VCC
Customer supply
Supply Current
ICC
One die, sampling angles
Undervoltage Flag Threshold [3]
VUVD
dV/dt = 1 V/ms, A1333 sampling enabled,
TA = 25°C
Supply Zener Clamp Voltage
VZSUP
ICC = ICC + 3 mA, TA = 25°C
Reverse Battery Current
Power-On Time [4][6]
Bypass Pin Output Voltage [5]
–
17
19
mA
3.6
–
3.9
V
26.5
–
–
V
IRCC
VRCC = 18 V, TA = 25°C
–
–
5
mA
tPO
Power-on diagnostics disabled
–
15
20
ms
Power-on time; CVH self-test and LBIST enabled
–
45
50
ms
TA = 25°C, CBYP = 0.1 µF, 3.3 V interface
2.97
3.3
3.63
V
TA = 25°C, CBYP = 0.1 µF, 5.0 V interface enabled
and VCC ≥ 5.0 V
4.0
5.0
5.5
V
tPO_D
VBYP
SPI AND ABI (UVW) ELECTRICAL SPECIFICATIONS (3.3 V INTERFACE)
Digital Input High Voltage
VIH
MOSI, SCLK, CS pins
2.8
–
3.63
V
Digital Input Low Voltage
VIL
MOSI, SCLK, CS pins
–
–
0.5
V
Output High Voltage
VOH
MISO, ABI/UVW pins, CL = 20 pF
2.93
3.3
3.63
V
Output Low Voltage
VOL
MISO, ABI/UVW pins, CL = 20 pF
–
0.3
–
V
SPI AND ABI (UVW) ELECTRICAL SPECIFICATIONS (5.0 V INTERFACE)
Digital Input High Voltage
VIH
MOSI, SCLK, CS pins
3.75
–
5.5
V
Digital Input Low Voltage
VIL
MOSI, SCLK, CS pins
–
–
0.5
V
Output High Voltage
VOH
MISO, ABI/UVW pins, CL = 20 pF, VCC ≥ 5.0 V
4
5
5.5
V
Output Low Voltage
VOL
MISO, ABI/UVW pins, CL = 20 pF
–
0.3
–
V
fSCLK
MISO pins, CL = 20 pF
0.1
–
10
MHz
SPI INTERFACE SPECIFICATIONS
SPI Clock Frequency [6]
SPI Clock Duty
Cycle [6]
SPICLKDC
40
-
60
%
SPI Frame Rate [6]
tSPI
16-bit SPI packet
5.8
–
588
kHz
Chip Select to First SCLK Edge [6]
tCS
Time from CS going low to SCLK falling edge
50
–
–
ns
tCS_IDLE
Time CS must be high between SPI message
frames
200
–
–
ns
Chip Select Idle Time [6]
DfSCLK
Data Output Valid Time [6]
tDAV
Data output valid after SCLK falling edge
–
30
–
ns
MOSI Setup Time [6]
tSU
Input setup time before SCLK rising edge
25
–
–
ns
MOSI Hold
tHD
Input hold time after SCLK rising edge
50
–
–
ns
SCLK to CS Hold Time [6]
tCHD
Hold SCLK high time before ¯C¯ ¯S¯ rising edge
5
–
–
ns
Capacitance [6]
CL
Loading on digital output (MISO) pin
–
–
20
pF
Load
Time [6]
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
OPERATING CHARACTERISTICS (continued): Valid over the full operating voltage and ambient temperature ranges, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit [1]
PWM Frequency Min Setting
–
98
–
Hz
PWM Programmable Options (7 bits)
–
128
–
options
PWM Frequency Max Setting
–
3.125
–
kHz
PWM INTERFACE SPECIFICATIONS
PWM Carrier Frequency
fPWM
PWM Output Low Clamp
DPWM(min)
Corresponding to digital angle of 0x000
–
5
–
%
PWM Output High Clamp
DPWM(max)
Corresponding to digital angle of 0xFFF
–
95
–
%
INCREMENTAL OUTPUT, ABI (UVW) SPECIFICATIONS
ABI and UVW Output Angular
Hysteresis [6]
hysANG
Programmable via EEPROM (6 bits)
0
–
1.38
degrees
AB Channel Resolution [6]
RESAB
Programmable via EEPROM, 4 bit field.
Specified in pulses per revolution, PPR
1
–
2048
PPR
RESAB_INT
Equal to 4 × RESAB, specified in counts per
revolution, CPR
4
–
8192
CPR
Npole
DC commutation signals. Programmable via
EEPROM, 4-bit field.
1
–
16
pole pairs
Output voltage ≥ 2.5 V
–
1.5
–
mA
5 V IO setting; output voltage ≈ 0.35 V
–
4.5
–
mA
AB Quadrature Resolution [6]
UVW Pole Pairs [6]
Maximum Sourcing Current
Maximum Sinking Current
ISOURCE
ISINK
MANCHESTER INTERFACE SPECIFICATIONS
Manchester High Voltage
VMAN(H)
Applied to VCC line
7.3
8
VCC(max)
V
Manchester Low Voltage
VMAN(L)
Applied to VCC line
VCC(min)
5
5.7
V
2.2
–
100
kbit/s
fMAN
Line state changes once or twice per bit;
maximum speed is usually limited by VCC line
capacitance
Logic BIST Time
tLBIST
Configurable to run on power-up or on user request.
Runs in parallel with CVH self-test (if enabled).
–
30
–
ms
Circular Vertical Hall Self-Test
Time
tCVHST
Configurable to run on power-up or on user request.
Runs in parallel with LBIST (if enabled).
–
30
–
ms
Manchester Bit Rate
BUILT-IN SELF TEST
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
7
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
OPERATING CHARACTERISTICS (continued): Valid over the full operating voltage and ambient temperature ranges, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit [1]
Range of input field
–
–
1200
G
Both 12 and 15 bit angle values are available via SPI
–
12/15
–
bit
ORATE = 0
–
1.0
–
µs
Angular Latency; valid for ABI or UVW interface;
ORATE = 0
–
7
–
µs
TA = 25°C, ideal magnet alignment, B = 300 G,
target rpm = 0
–1.0
±0.4
+1.0
degrees
TA = 150°C, ideal magnet alignment, B = 300 G,
target rpm = 0
–1.3
±0.6
+1.3
degrees
TA = 150°C, B = 300 G, angle change from 25°C
–1.4
–
1.4
degrees
TA = –40°C, B = 300 G, angle change from 25°C
–
0.9
–
degrees
TA = 25°C, B = 300 G, no internal filtering,
target rpm = 0, 3 sigma noise
–
±0.19
–
degrees
TA = 150°C, no internal filtering, B = 300 G,
target rpm = 0, 3 sigma noise
–
±0.25
–
degrees
B = 300 G, TA = 25°C
–
12.5
–
bits
B = 300 G, average maximum drift observed
following AEC-Q100 qualification testing
–
0.5
–
degrees
MAGNETIC CHARACTERISTICS
Magnetic Field
B
ANGLE CHARACTERISTICS
Output [7]
RESANGLE
Angle Refresh Rate [8]
tANG
Response Time [6]
tRESPONSE
Angle Error
ERRANG
Temperature Drift
ANGLEDRIFT
Angle Noise [9]
NANG
Effective Resolution [10]
Angle Drift Over Lifetime [11]
[1] 1
ANGLEDrift_Life
G (gauss) = 0.1 mT (millitesla).
operational voltage is reduced at high ambient temperatures (TA). See plots below.
[2] Maximum
eTSSOP-24 Thermal Derating Curve
Maximum Operating VCC (V)
Maximum Operating VCC (V)
TSSOP-14 Thermal Derating Curve
16.5
12.84 V
144°C
4
150
-40
Ambient Temperature, TA (°C)
16.5
15.26 V
4
148°C
150
-40
Ambient Temperature, TA (°C)
[3] Undervoltage
flag indicates VCC level below expected operational range. Degraded sensor accuracy may result.
the power-on phase, the A1333 SPI transactions will be valid within ≈ 300 µs of power on (with no self-tests). Angle reading requires full tPO
to stabilize.
[5] The output voltage specification is to aid in PCB design. The pin is not intended to drive any external circuitry. The specifications indicate the peak
capacitor charging and discharging currents to be expected during normal operation.
[6] Parameter is not guaranteed at final test. Determined by design.
[7] RES
ANGLE represents the number of bits of data available for reading from the die registers.
[8] The rate at which a new angle reading will be ready.
[9] This value represents 3-sigma or three times the standard deviation of the measured samples.
[10] Effective Resolution is calculated using the formula below:
[4] During
log2(360) – log2
( )
1
n
n
i=1
i
where σ is the Standard Deviation based on thirty averaged measurements taken at each of the 32 angular positions, I = 11.25, 22.5, … 360.
Maximum observed angle drift following AEC-Q100 stress was 1.37 degrees.
[11]
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
8
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
2
2
1.8
1.8
1.6
1.6
1.4
1.4
Angle Drift in Degrees
Angle Error in Degrees
TYPICAL PERFORMANCE CHARACTERISTICS
1.2
1
0.8
0.6
1.2
1
0.8
0.6
0.4
0.4
0.2
0.2
0
-40
25
0
150
-40
150
Ambient Temperature in °C
Ambient Temperature in °C
Figure 3: Peak Angle Error over Temperature [1]
(300 G)
Figure 4: Maximum Absolute Drift from 25°C Reading [1]
(300 G)
8
12
150°C
25°C
-40°C
10
150°C
-40°C
7
6
Frequency
Frequency
8
6
5
4
3
4
2
2
1
0
0
0.5
1
1.5
Angle Error in degrees
Figure 5: Peak Angle Error Distributions over
Temperature (300 G)
0
0
0.5
1
Angle Drift in Degrees
1.5
Figure 6: Angle Drift from 25°C (300 G)
[1] Central
mark indicates median value. Bottom and top edges of the box indicate the 25th and 75th percentiles. Whiskers extend to the most extreme
data points not defined as outliers. Outliers are shown in red. Outliers are defined as those points outside Q1 or Q3 by more than 1.5 times the interquartile range (≈ 2.7σ away from the center of the distribution).
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
20
0.3
Mean
±3 Sigma
19
0.25
18
ICC in mA
0.2
0.15
17
0.1
16
0.05
15
0
-40
-20
0
20
40
60
80
100
120
140
Ambient Temperature in °C
14
-40
Figure 7: Noise Performance over
Temperature (3 Sigma, 300 G)
-20
0
20
40
60
80
7
150°C
25°C
-40°C
7
100
120
Ambient Temperature in °C
140
Figure 8: ICC over Temperature (VCC = 16.0 V)
8
150°C
25°C
-40°C
6
6
5
Count (%)
5
Frequency (%)
Noise in degrees
Mean
±3 Sigma
4
3
3
2
2
1
1
0
4
0
0.1
Noise in degrees
0.2
Figure 9: Noise Distribution over Temperature
(3 Sigma, 300 G)
0.3
0
15
16
ICC in mA
17
18
Figure 10: ICC Distribution over Temperature
(VCC = 16.0 V)
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
TYPICAL PERFORMANCE OF FIELD AND TEMPERATURE
2.5
300 G
600 G
900 G
Angle Error in Degrees
2
1.5
1
0.5
0
-40
-1
25
Temperature in °C
85
125
150
Figure 11: Average Angle Error over Temperature Across 10 Devices.
Recommended operating range: 300 G and above.
2.5
-40°C
-1°C
25°C
85°C
125°C
150°C
Angle Error in Degrees
2
1.5
1
0.5
0
300
600
Field Strength in Gauss
900
Figure 12: Average Angle Error over Field.
Recommended operating range: 300 G and above.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
0.5
300 G
600 G
900 G
0.45
0.4
3 Sigma Noise in Degrees
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-40
-1
25
Temperature in °C
85
125
150
Figure 13: Average 3 Sigma Angle Noise over Temperature.
Recommended operating range: 300 G and above.
0.5
-40°C
-1°C
25°C
85°C
125°C
150°C
0.45
3 Sigma Noise in Degrees
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
300
600
Field Strength in Gauss
900
Figure 14: Average 3 Sigma Angle Noise over Field.
Recommended operating range: 300 G and above.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
2.5
300 G
600 G
900 G
Angle Drift in Degrees
2
1.5
1
0.5
0
-40
-1
25
Temperature in °C
85
125
150
Figure 15: Average Angle Drift over Temperature Across 10 Devices.
Recommended operating range: 300 G and above.
2.5
-40°C
-1°C
25°C
85°C
125°C
150°C
Angle Drift in Degrees
2
1.5
1
0.5
0
Field in Gauss
Figure 16: Average Angle Drift over Field Across 10 Devices.
Recommended operating range: 300 G and above.
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
FUNCTIONAL DESCRIPTION
Overview
The A1333 is a rotary position Hall-sensor-based device in
a surface-mount package, providing solid-state consistency,
reliability, and supporting a wide variety of automotive
applications. The Hall-sensor-based device measures the direction
of the magnetic field vector through 360° in the x-y plane
(parallel to the branded face of the device) and computes an angle
measurement based on the actual physical reading, as well as any
internal parameters that have been set by the user. The output is
used by the host microcontroller to provide a single channel of
target data.
This device is an advanced, programmable system-on-chip (SoC).
Each integrated circuit includes a Circular Vertical Hall (CVH)
analog front end, a high-speed sampling A-to-D converter, digital
filtering, digital signal processing (which includes two separate
signal paths), SPI, PWM, motor commutation outputs (UVW), and
encoder outputs (A, B, I).
Offset, filtering, and diagnostic adjustment options are available in
the A1333. These options can be configured in onboard EEPROM,
providing a wide range of sensing solutions in the same device.
Device performance can be optimized by enabling individual functions or disabling them in EEPROM to minimize latency.
Angle Measurement
The IC features two digital signal paths. The main signal path
uses a PLL to generate high resolution, low latency angle readings. A secondary, lower power signal path (referred to as the
“ZCD path”) is used for turns counting, magnetic field measurement, and diagnostic comparison.
The A1333 is capable of tracking magnet position at high speed.
Performance up to 12,000 rpm has been verified by testing. Operation up to 30,000 rpm has been verified via design simulation.
When reading the 12-bit angle value, 3 additional status bits are
provided with each packet: a general error flag (EF), undervoltage flag (UV), and a parity bit (P).
PWM output is always resolved to a 12-bit angle value. ABI/
UVW operates on a 15-bit angle representation.
The zero degree position may be adjusted by writing to
EEPROM.
The sensor readout is processed in various steps. These are
detailed in Figure 21.
System Level Timing
Internal registers are updated with a new angle value every
tANG. Due to signal path delay, the angle is tRESPONSE old at
each update. In other words, tRESPONSE is the delay from time of
magnet sampling until generation of a processed angle value. SPI,
which is asynchronously clocked, results in a varying latency
depending on sampling frequency and SCLK speed. The values
which are presented to the user are latched on the first SCLK
edge of the SPI response frame. This results in a variable age of
the angle data, ranging from tRESPONSE + tSPI to tRESPONSE + tANG
+ tSPI, where tSPI is the length of a read response packet, and tANG
is the update rate of the angle register.
Similar to SPI, when using the PWM output, the output packet is
not synchronized with the internal update rate of the sensor. The
angle is latched at the beginning of the carrier frequency period
(effectively at the rising edge of the PWM output). Because of
this, the age of the angle value, once read by the system microcontroller, may be up to tRESPONSE + tANG + 1/fPWM.
Figure 20 shows the update rate and the signal delay of the different angle output paths depending on sensor settings.
The A1333 has a typical refresh rate of 1 MHz.
The value of the “angle_zcd” (ZCD signal path) register is
updated approximately every 32 µs. The field strength reading
(register 0x2A) is updated approximately every 128 µs.
Angle is represented as either a 12- or 15-bit value, based on the
register address accessed.
Impact of High Speed Sensing
12 Bit Angle Value; Serial register 0x20
15 14 13 12 11 10 9
8
0 EF UV P
7
6
5
4
3
2
1
0
3
2
1
0
angle(11:0)
15 Bit Angle Value; Serial Register 0x32
15 14 13 12 11 10 9
0
8
7
6
angle(14:0)
5
4
Due to signal path latency, the angle information is delayed by
tRESPONSE. This delay equates to a greater angle value as the
rotational velocity increases (i.e. a magnet rotating at 20,000 rpm
traverses twice as much angular distance in a fixed time period as a
magnet rotating at 10,000 rpm), and is referred to as angular lag.
The lag is directly proportional to rpm, and may be compensated
for externally, if the velocity is known.
Angular lag can be expressed using the following equation:
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Ang_Lag =
rpm × 6
1,000,000
Measured Performance Over RPM
× tRESPONSE
where rpm represents the rotational velocity of the magnet,
Angle_Lag is expressed in degrees, and tRESPONSE is in µs.
Figure 17 depicts the expected angular lag over rpm.
2.5
Figure 18 depicts the measured angle lag over increasing rpm.
Data was collected by triggering SPI angle reads off a high precision encoder. To present data independent of output protocol,
the delay due to SPI packet transmission has been removed from
the plot. As such the plot shows the angle lag due to signal path
delays only.
Figure 19 depicts the equivalent response time (in µs), derived
from the slope of Figure 18. The measured response times ranges
between 6.5 and 7.6 µs.
1.5
1
0.7
0.5
0
10000
20000
30000
RPM
40000
50000
Figure 17: Expected Angle Lag vs. RPM
60000
Angle Lag (degrees)
0
0.6
0.5
0.4
0.3
Measured Angle Lag
0.2
Expected Angle Lag
0.1
0
0
2000
4000
6000
8000
10000
12000
14000
RPM
Figure 18: Measured Angle Lag vs. RPM
Response Time (µs)
Angle Lag(deg)
2
Figure 18 and Figure 19 show the measured performance of the
A1333 at speeds up to 12,000 rpm. Data taken with no internal
averaging (ORATE = 0).
10
9
8
7
6
5
4
3
2
1
0
0
2000
4000
6000
8000
10000
12000
14000
RPM
Figure 19: Measured Response Time Over RPM
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A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
CVH
Latency: 0 µs
Rate: 1 µs
PLL + processing
Latency 7 µs
Rate 1 µs
Latency: 7 µs
Rate: 1 µs
Op�onal Angle averaging
Reduce rate by 2“orate” �mes
0 ≤ “orate” ≤ 12
Latency: 7 + (2“orate” – 1) µs
Rate: 1 µs × 2“orate”
ABI / UVW pins
Latency ~ ns (push/pull output)
Rate can be limited by “slew_rate”
PWM pin
Latency ≤ 1 PWM cycles of (98...3125 Hz)
Rate (98...3125 Hz)
SPI bus
Latency ≤ 1 µs · 2orate + 16/fSPI (fSPI,max = 10 MHz)
Rate 16/fSPI
µC
Latency: 7 + (2“orate”– 1) µs
Rate: 1 µs × 2“orate”
Latency = fPWM-1 + 7 µs + (2“orate” – 1) µs
Rate = fPWM-1
New data rate = max of [fPWM-1 and 2“orate” µs]
Latency ≤ 7 µs + 2“orate” µs + 16/fSPI
Rate = 16/fSPI
New data rate = max of [16/fSPI and 2“orate”] µs
Figure 20: Update Rate and Signal Delay
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
ZCD path
CVH
PLL path (full power only)
Mixed origin data
ΣΔ-ADC
Filter and ZCD angle
measurement logic
Filter & PLL angle
measurement logic
Field strength
measurement
Angle averaging
(“orate”)
Offset adjust
(“zero_offset”)
Rota�on direc�on
(“ro”)
“gauss” output register
Rota�on direc�on
(“ro”)
“angle_zcd” output register
180° rota�on
(“rd”)
Accumulate angle changes into 21-bit
value, resolu�on 4096 counts/360°
(rela�ve to start-up angle)
Take 13 MSB
of Angle change
Take 15 MSB
of Angle change
“ahe”=0
Angle hysteresis
(“hysteresis”)
“turns” output register
resolu�on 45° or 180°
“phe”=0
ABI / UVW pins
(“uvw”,“ioe”,“plh”,“wdh”,“index_mode”,“inv”,
“abi_slew_�me”,“resolu�on_pairs”)
PWM pin
(“pen”,“pwm_band”,“pwm_freq”,“peo”,“pes”)
“angle” and “angle_15“ output register
“angle_hys” output register
Figure 21: Angle Measurement – Sensor Readout Steps
Names in quotes correspond to EEPROM or serial register fields.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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PWM Output
D = 5%
360
D = 50%
5 % LOW
5 % HIGH
120
Degrees
PWM Period
5 % LOW
5 % HIGH
PWM Period
360 Degrees
240 Degrees
Figure 23: Pulse-Width Modulation (PWM) Examples
The angle is represented in 12-bit resolution and can never reach
360°. The maximum duty cycle high period is:
DutyCycleMax (%) = (4095 / 4096) × 90 + 5 .
PWM CARRIER FREQUENCY
The PWM carrier frequency is controlled via two EEPROM
fields, both of which are found in the PWS row.
D = 95%
CLAMP_HIGH
• PWM_FREQ
• PWM_BAND
CLAMP_LOW
0
PWM Waveform (V)
Magnetic Field Angle (°)
The A1333 provides a pulse-width-modulated open-drain output,
with the duty cycle (DC) proportional to measured angle. The PWM
duty cycle is clamped at 5% and 95% for diagnostics purposes. A 5%
DC corresponds to 0°; a 95% DC corresponds to 360°.
PWM Period
(0 Degrees)
5 % LOW
5 % HIGH
Upon applying power to the A1333, the device automatically runs
through an initialization routine. The purpose of this initialization
is to ensure that the device comes up in the same predictable
operating condition every power cycle. This initialization routine
takes time to complete, which is referred to as Power-On Time,
tPO. Regardless of the state of the device before a power cycle,
the device will re-power with the shadow memory contents
copied from the EEPROM anew, and serial registers in their
default states. For example, on every power-up, the device will
power with the “zero_offset” that was stored in the EEPROM.
The extended write access field “write_adr” will be set back to its
default value, zero.
5 % LOW
5 % HIGH
PWM Period
5 % LOW
5 % HIGH
Power-Up
5 % LOW
5 % HIGH
A1333
D0T
D1T
D2T
D3T
D4T
D5T
D6T
D7T
D8T
D9T
Together, these two fields allow 128 different PWM carrier frequencies to be selected.
D10T
D(x) = tpulse(x) / Tperiod
tpulse(5)
Tperiod
0T
1T
2T
3T
4T
5T
6T
7T
8T
9T
10T
11T
Table 1: PWM Carrier Frequencies in Hz
PWM_BAND
Time
Figure 22: PWM Mode Outputs a Duty-Cycle
Proportional To Sensed Angle
PWM_FREQ
Within each cycle, the output is high for the first 5% and low
for the last 5% of the period. The middle 90% of the period is a
linear interpolation of the angle as sampled the start of the PWM
period.
0
1
2
3
4
5
6
7
0
3125
2778
2273
1667
1087
641
352
185
1
3101
2740
2222
1613
1042
610
333
175
2
3077
2703
2174
1563
1000
581
316
166
3
3053
2667
2128
1515
962
556
301
157
4
3030
2632
2083
1471
926
532
287
150
5
3008
2597
2041
1429
893
510
275
143
6
2985
2564
2000
1389
862
490
263
137
7
2963
2532
1961
1351
833
472
253
131
8
2941
2500
1923
1316
806
455
243
126
9
2920
2469
1887
1282
781
439
234
121
10
2899
2439
1852
1250
758
424
225
116
11
2878
2410
1818
1220
735
410
217
112
12
2857
2381
1786
1190
714
397
210
108
13
2837
2353
1754
1163
694
385
203
105
14
2817
2326
1724
1136
676
373
197
101
15
2797
2299
1695
1111
658
362
191
98
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Incremental Output Interface (ABI)
The A1333 offers an incremental output mode in the form of
quadrature A/B and Index outputs to emulate an optical or
mechanical encoder. The A and B signals toggle with a 50%
duty cycle (relative to angular distance, not necessarily time) at
a frequency of 2N cycles per magnetic revolution, giving a cycle
resolution of (360 / 2N) degrees per cycle, where N is set by the
resolution_pairs field in EEPROM; see Table 2. B is offset from
A by ¼ of the cycle period. The “I” signal is an index pulse that
occurs once per revolution to mark the zero (0) angle position.
One revolution is shown below:
A
B
I
Angle →
0
+R +2R +3R
-3R -2R -R
0
Increase angle – B edge precedes A edge
Decreasing angle – A edge precedes B edge
One full magnetic rotation (360 magnetic degrees)
Figure 24: One Full Magnetic Revolution
Since A and B are offset by ¼ of a cycle, they are in quadrature
and together have four unique states per cycle. Each state represents R = [360 ÷ (4 × 2N)] degrees of the full revolution. This
angular distance is the quadrature resolution of the encoder. The
order in which the states change, or the order of the edge transitions from A to B, allow the direction of rotation to be determined. If a given B edge (rising/falling) precedes the following
A edge, the angle is increasing from the perspective of the
electrical (sensor) angle and the angle position should be incremented by the quadrature resolution (R) at each state transition.
Conversely, if a given A edge precedes the following B edge,
the angle is decreasing from the perspective of the electrical
(sensor) angle and the angle position should be decremented by
the quadrature resolution (R) at each state transition. The angle
position accumulator wraps each revolution back to 0.
The quadrature states are designated as Q1 through Q4 in the following diagrams, and are defined as follows:
State Name
A
B
Q1
0
0
Q2
0
1
Q3
1
1
Q4
1
0
Note that the A/B progression is a grey coding sequence where
only one signal transitions at a time. The state progression must
be as follows to be valid:
Increasing angle: Q1 → Q2 → Q3 → Q4 → Q1 → Q2 → Q3 → Q4
Decreasing angle: Q4 → Q3 → Q2 → Q1 → Q4 → Q3 → Q2 → Q1
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
The duration of one cycle is referred to as 360 electrical degrees,
or 360e. One half of a cycle is therefore 180e and one quarter of
a cycle (one quadrature state, or R degrees) is 90e. This is the terminology used to express variance from perfect signal behavior.
Ideally the A and B cycle would be as shown below for a constant
velocity:
Cycle = 360e
A
B
Q1
90e
Q2
90e
Q3
90e
Q4
90e
Figure 25: Electrical Cycle
In reality, the edge rate of the A and B signals, and the switching
threshold of the receiver I/Os, will affect the quadrature periods:
Cycle = 360e
A
B
Q4
90e
Q1
75e
Q2
90e
Q3
105e
Figure 26: Electrical Cycle
Here, an exaggeration of the switching thresholds shows that Q4
and Q2, which are fall-fall and rise-rise, have the expected 90e
period, whereas Q1 is less than expected and Q3 is greater than
expected due to imbalance in switching thresholds.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
ABI RESOLUTION
ABI INVERSION
The A1333 supports the following ABI output resolutions. This is set via
the “resolution_pairs” field in EEPROM and shadow (EEPROM 0x19,
bits 3:0).
The logic levels of the ABI pins may inverted by setting the ABI.inv bit
within EEPROM. This also applies if using the UVW output logic.
Table 2: ABI Output Resolution
EEPROM
Resolution
Field
Cycle
Resolution
(Bits = N)
Quadrature
Resolution
(Bits = 4 × N)
Cycles per
Revolution
(A or B)
Quadrature
States per
Revolution
0
Factory Use Only
1
Factory Use Only
2
Cycle Resolution
(Degrees)
Quadrature
Resolution (R)
(Degrees)
Factory Use Only
3
11
13
2048
8192
0.176
0.044
4
10
12
1024
4096
0.352
0.088
5
9
11
512
2048
0.703
0.176
6
8
10
256
1024
1.406
0.352
7
7
9
128
512
2.813
0.703
8
6
8
64
256
5.625
1.406
9
5
7
32
128
11.250
2.813
10
4
6
16
64
22.500
5.625
11
3
5
8
32
45.000
11.250
12
2
4
4
16
90.000
22.5
13
1
3
2
8
180.0
45.0
14
0
2
1
4
360.0
90.0
15
n/a
n/a
n/a
n/a
n/a
n/a
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
INDEX PULSE
The index pulse I (or Z in some descriptions) marks the absolute zero
(0) position of the encoder. Under rotation, this allows the receiver to
synchronize to a known mechanical/magnetic position, and then use the
incremental A/B signals to keep track of the absolute position. To support a range of ABI receivers, the ‘I’ pulse has four widths, defined by
the INDEX_MODE EEPROM field, as shown below:
A
B
INDEX_MODE 0
INDEX_MODE 1
INDEX_MODE 2
INDEX_MODE 3
A=-2R
Q3
A=-R
Q4
A=0
Q1
A=+R
Q2
True Zero to 360 Discontinuity
Figure 27: Index Pulse
ABI BEHAVIOR AT POWER-UP
At power-up, the A1333 requires time to acquire a stable angle value;
this is quantified by tPO (or tPO_D, if power-on diagnostics are used).
Because the angle value is not guaranteed to be stable between power-on
and tPO, the output of the ABI should be ignored until at least tPO after
power-on.
tPO or tPO_D
Normal operation
VCC
A
B
I
�me
Figure 28: ABI Startup Behavior
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
magnet is rotated in the opposite direction (or the RO bit is changed in
EEPROM) to produce a decreasing angle value, the 0° position will be
represented by the falling edge of the Index pulse.
ZERO DEGREE POSITION INDICATION
The edge of the index pulse corresponding to the “Zero” position, as
observed by the sensor, will change based on rotation direction, as
shown in Figure 29.
With the magnet rotating such that the observed angle is increasing, the
0° position will be indicated by the rising edge of the Index pulse. If the
The ABI resolution and I pulse mode selection (described above) determine the width of the Index pulse and the corresponding shift in zero
position indication.
Clockwise Rota�on
Ideal view as seen on scope, trigger
on rising edge of I pulse
9 bit AB resolu�on
11 bit quad resolu�on
R = ~0.176 degrees
RO bit = 0
Sensor "Zero" and
Ideal Mechanical "Zero"
0xFF80
to
0xFF9F
16 Bit PLL
Angle
(hex)
0xFFC0
to
0xFFDF
0xFFE0
to
0xFFFF
0x0000
to
0x001F
0x0020
to
0x003F
0x0040
to
0x005F
0x0060
to
0x007F
0x0080
to
0x009F
-2R
-R
0
R
+2R
+3R
+4R
A
B
Scope Trigger
I
…
…
…
-4R
-3R
…
…
…
…
…
…
Counter-Clockwise Rota�on
9 bit AB resolu�on
11 bit quad resolu�on
R = ~0.176 degrees
RO bit = 0
Ideal view as seen on scope, trigger
on rising edge of I pulse
0xFFA0
to
0xFFBF
Sensor "Zero" and
Ideal Mechanical "Zero"
16 Bit PLL
Angle
(hex)
0x009F
to
0x0080
0x007F
to
0x0060
0x005F
to
0x0040
0x003F
to
0x0020
0x001F
to
0x000
0xFFFF
to
0xFFE0
0xFFDF
to
0xFFC0
0xFFBF
to
0xFFA0
0xFF9F
to
0xFF80
+2R
+R
0
-R
-2R
-3R
-4R
A
B
Scope Trigger
I
…
…
…
+4R
+3R
Figure 29: Index Pulse Corresponding to “Zero” Position
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23
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
SLEW RATE LIMITING FOR ABI
EFFECTIVE SPEED OF SLEW TIME
Slew rate limiting is enabled when the “abi_slew_time” field is non-zero.
This option separates the sensor’s observed angle change from the ABI
output rate, and can be used to control two circumstances:
When slew rate limiting occurs, the ABI update rate is no longer
dependent on the observed rotation rate, but instead occurs at
a period set via EEPROM. This change in the edge rate will be
observed as a change in the target velocity. This perceived velocity depends on:
• The angle sample does not monotonically increase or decrease at the
quadrature resolution, thereby “skipping” one or more quadrature
states. In this case, the slew rate limiting logic transitions the ABI
signals in the required valid sequence, at the slew rate, until the
ABI output “catches up” with the angle samples, at which point the
normal sample rate output resumes. This skipping will most likely
occur either at very low velocities, if the noise is high, or at very
high velocities when the angle changes more than the quadrature
resolution in one angle sample period.
• The ABI receiver at the host end cannot reliably detect edge
transitions that are spaced at the sample rate of 1 µs. The slew limit
time can be set greater than the nominal angle sample update period,
providing the velocity of the angle rotation would not on average
require ABI transitions greater than the angle sample rate.
In both cases, the ABI output will correctly track the rotation position;
however, the speed of the ABI edges will be accomplished at the slew
rate limit set in EEPROM. Whenever slew rate limiting occurs, the SRW
flag in the WARN serial register will assert informing the system of the
occurrence.
A
B
ABI State
Actual
Posi�on
• The configured “abi_slew_time” (EEPROM 0x19 bits 21:16)
• The ABI resolution (“resolution pairs” EEPROM 0x19 bits
3:0)
Table 3 shows the equivalent RPMs for select combinations of
slew time and ABI resolution.
When designing a system, it is important to note these RPMs will
occur for any change in rotation direction (i.e. motor transitioning
from CW to CCW rotation), when both hysteresis and ABI slew
rate limiting are enabled, as the IC “back fills” the ABI edges for
the programmed hysteresis window (EEPROM 0x17 bits 17:12).
Table 3
EEPROM Setting
Equivalent RPM based on ABI Resolution
abi_slew_time
(Decimal)
Slew Time
(µs)
12-bit
Quadrature
11-bit
Quadrature
10-bit
Quadrature
1
0.25
58593.8
117187.5
234375.0
2
0.375
39062.5
78125.0
156250.0
3
0.5
29296.9
58593.8
117187.5
4
0.625
23,437.5
46875.0
93750.0
Q1
Q4
Q2
Q4
Q2
Q3
5
0.75
19531.3
39062.5
78125.0
X + R°
X°
X + 2R°
X°
X – 2R°
X – R°
6
0.875
16741.1
33482.1
66964.3
7
1
14648.4
29296.9
58593.8
8 (default)
1.125
13020.8
26041.7
52083.3
Without Slew Rate Limiting
A
Slew
Time
B
ABI State
Q1
Q4
Actual
Posi�on
X + R°
X°
Output
X + R°
X°
Q2
Q1
Q1
X + 2R°
X + R°
X + 2R°
Q4
Q1
X°
X + R°
X°
Q2
X – 2R°
X – R°
X – 2R°
…
…
…
…
…
62
7.875
1860.1
3720.2
7440.5
63
8
1831.1
3662.1
7324.2
Q3
X – R°
X – R°
With Slew Rate Limiting
Figure 30: Slew Rate Limiting
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Brushless DC Motor Output (UVW)
The A1333 offers U, V, and W signals for stator commutation of
brushless DC (BLDC) motors. If hysteresis is enabled (set via
“ahe”, bit 12 of EEPROM address 0x19), the UVW edges will
update based off the rotation direction and hysteresis window.
See the Hysteresis section of this document for greater detail. The
U, V, and W outputs switch when the measured mechanical angle
crosses the value where a change should occur. By default, the
UVW signals are 180° duty cycle waveforms (complete one cycle
every 360°), spaced 120° apart. Options are provided for 1 to 16
pole-pairs, which control how many times the UVW waveforms
are repeated for an observed mechanical rotation. This emulates
the typical Hall switch output, from a multi pole-pair motor. Figure 32 and Figure 33 below show the UVW waveforms for three
and five pole-pair BLDC motors.
U
V
W
Mechanical
Angle
0
120
240
360
Figure 31: U, V, W Outputs for One Pole-Pair BLDC Motor
U
U
V
V
W
W
Mechanical
Mechanical
Angle
Angle
0
0
40
40
80
80
120
120
160
160
200
200
240
240
280
280
320
320
0
0
Figure 32: U, V, W Outputs for Three Pole-Pair BLDC Motor
U
U
V
V
W
W
Mechanical
Mechanical
Angle
Angle
0
0
30
30
60
60
90
90
120
120
150
150
180
180
210
210
240
240
270
270
300
300
330
330
0
0
Figure 33: U, V, W Outputs for Five Pole-Pair BLDC Motor
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A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
Table 4: UVW Pole Pair Settings
resolution_pairs (hex)
Quantity of
Pole-Pairs
Cycle Width
(Mechanical Degrees)
0x0
1
360.00
0x1
2
180.00
0x2
3
120.00
0x3
4
90.00
0x4
5
72.00
0x5
6
60.00
0x6
7
51.43
0x7
8
45.00
0x8
9
40.00
0x9
10
36.00
0xA
11
32.73
0xB
12
30.00
0xC
13
27.69
0xD
14
25.71
0xE
15
24.00
0xF
16
22.50
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Angle Hysteresis
Hysteresis can be applied to the compensated angle to moderate
jitter in the angle output due to noise or mechanical vibration.
In the A1333, the hysteresis field (ANG.hysteresis) defines the
width of an angle window at 14-bit resolution. Mathematically,
the width of this window is:
HYSTERESIS × (360 / 16384) degrees
,
HYSTERESIS is a 6-bit wide EEPROM field, allowing a range
of 0 to 1.384 degrees of hysteresis to be applied.
The hysteresis-compensated angle can be routed to the ABI or
UVW interface by setting the AHE bit in EEPROM to a 1 (bit
12 of address 0x19). On the SPI or Manchester interface, the
hysteresis-compensated angle can be read via an alternate register
(HANG.angle_hys) at 12-bit resolution.
The effect of the hysteresis is shown in Figure 34. The current
angle position as measured by the sensor is at the “head” of
the hysteresis window. As long as the sensor (electrical) angle
Hysteresis
Rotation
advances in the same direction of rotation, the output angle will
be the sensor angle, minimizing latency. If the sensor angle
reverses direction, the output angle is held static until the sensor
angle exits the hysteresis window in either direction. If the exit
is in the opposite direction of rotation where the “head” was, the
head flips to the opposite end of the hysteresis window and that
becomes the new reference direction. The current direction of
rotation, or “head” for the purposes of hysteresis, is viewable via
the STA.rot bit, where 0 is increasing angle direction and 1 is in
decreasing angle direction.
This behavior has the following consequences:
1. If the hysteresis window is greater than the output resolution,
the output angle will skip consecutive resolution steps.
2. If there is jitter due to noise or mechanical vibration, especially
at a static angle position or very slow rotation, the angle will
tend to bias to one side of the window, depending on the direction of rotation as the angular velocity approaches zero (i.e.,
towards the current “head”) rather than to the average position
of the jitter.
Sensor angle position
Output angle
Sensor angle and output angle the same
Window of hysteresis
Direction of rotation as seen by the hysteresis logic
Electrical Angle
1.7
1.8
1.9 2.0
Rotation
Rotation
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
2.7
2.3
2.3
2.3
2.4
2.5
OUTPUT ANGLE
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
Hysteresis
TIME
Rotation
Rotation
Rotation
Rotation
Rotation
Rotation
Rotation
2.1
2.8
2.9
2.9
2.9
2.9
2.9
3.0
3.0
3.0
3.0
3.0
Angle Jump
Figure 34: Effect of Hysteresis
Note: The rotation direction resets to 0, or increasing angle direction. At power-up or after LBIST, the hysteresis window will always be behind the initial angle
position, so if hysteresis is enabled a decreasing angle direction of rotation will not register until the hysteresis window is past.
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Turns Counting
value will not precisely match the primary angle output.
The A1333 uses a secondary, lower power signal path (called the “ZCD”
path) to track rotation turns. The turns counter logic tracks the turns in
either 45 or 180 degree increments, based on the T45 register field. The
signal path which tracks total turns does not implement the same angle
compensation as the primary signal path. Because of this, the turns count
The turns counter saturates at +2047 and –2048 in the 45-degree mode
and +511 and –512 in the 180-degree mode. If this happens, the
Turns Count Warning Flag (bit 0 of serial register 0x26) will assert
and stay asserted until the turns counter is reset via the Control register
(serial register 0x1E). (see Primary Serial Interface Registers Reference
section).
Turns Count
Output
Small Gear Angle
(degrees)
Big Gear Angle
(degrees)
Big Gear (40 Teeth)
300
200
CW
Rotation
100
0
0
t
2t
Big
Gear
CCW
Rotation
3t
Time
4t
5t
6t
7t
Small Gear (8 Teeth)
300
200
100
0
Magnet
0
t
2t
3t
Time
4t
5t
6t
7t
A1333
A1333 Turns Count
40
Small Gear
180 Degree Count
45 Degree Count
30
20
12 V
10
0
0
t
2t
3t
Time
4t
5t
6t
7t
Figure 35: Example of a Turns Counting Application
INVOKING A TURNS COUNTER RESET
Resetting the turns counter is a command invoked using the
“special” field of the CTRL register (Register address 0x1E, see
Primary Serial Interface Reference). Following a reset, turns
are tracked relative to that point, as measured by the signal path
(ZCD).
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
DEVICE PROGRAMMING INTERFACES
The A1333 can be programmed in two ways:
• Using the SPI interface for input and output, while supplying
the VCC pin with normal operating voltage
• Using a Manchester protocol on the supply pin for input, and
the PWM pin for output.
The A1333 does not require special supply voltages to write to
the EEPROM.
All setting fields and all data fields of the sensor can be read
and written using both protocols. If EEPROM locking is used
(detailed in EEPROM lock section), then write access using
either of the protocols will be prevented.
A separate setting to completely disable the Manchester interface
is available in the dm field of the EEPROM. Using this setting
will cause the sensor to ignore any commands entered using
Manchester protocol. The SPI interface will not be disabled by
disabling the Manchester interface.
Interface Structure
The A1333 consists of two memory blocks. The primary serial
interface registers are used for direct writes and reads by the host
controller for frequently required information (for example, angle
data, warning flags, field strength, and temperature). All forms of
communication (even to the extended locations) operate through
the primary registers, whether it be via SPI or Manchester.
The primary serial registers also provide a data and address location for accessing extended memory locations. Accessing these
extended location is done in an indirect fashion: the controller
User
SPI / Manchester IF
Address
02:03
04:05
06:07
08:09
0A:0B
0C:0D
0E:0F
10:11
1E:1F
20:21
…
…
writes into the primary interface to give a command to the sensor
to access the extended locations. The read/write is executed and
the result is again presented in the primary interface.
This concept is shown in Figure 36 below.
For writing extended locations, the primary interface offers the
registers “ewcs”, “ewa”, “ewdh”, and “ewdl”. “ewa” holds the
extended address that should be written, and “ewdh” / “ewdl”
contain the two high bytes and the two low bytes for the extended
location contents. The “ewcs” register is used for commands and
status information. Refer to the section “Read Transaction from
EEPROM” for further information and other register fields associated with read transactions.
For reading extended locations, the primary interface offers
the registers “ercs”, “era”, “erdh”, and “erdl”. “era” holds the
extended address the should be read, and “erdh” / “erdl” contain the two high bytes and the two low bytes for the extended
location contents. The “ercs” register is used for commands and
status information. Refer to the section “Read Transaction from
EEPROM” for further information and other register fields associated with read transactions.
EEPROM writing requires additional procedures. For more information on EEPROM and shadow memory read and write access,
see EEPROM and Shadow Memory section.
The primary serial interface can be accessed using the SPI and
using the Manchester interface. These two interfaces are detailed
in the following sections.
Primary Serial Interface
Function
Extended Write Address
Extended Write Data High
Extended Write Data Low
Extended Write Control/Status
Extended Read Address
Extended Read Control/Status
Extended Read Data High
Extended Read Data Low
Write data
Read data
Extended locations
Shadow EEPROM
Name
address address
–
0x17
CU2
0x58
0x18
PWE
0x59
0x19
ABI
0x60
0x20
MSK
0x61
0x21
PWI
...
...
...
...
...
...
Device Control
Angle
…
…
Figure 36: Serial Registers allow access to extended memory (EEPROM and Shadow)
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
SPI Interface
TIMING
The A1333 provides a full-duplex 4-pin SPI interface for each die,
using SPI mode 3 (CPHA = 1, CPOL = 1). All programming can
be done using this interface, but all programming can also be done
using the Manchester interface. If the SPI interface is not used, do
not leave the chip select line floating but instead follow the recomInput to A1339
mendations in the “Typical Application Diagram” section.
The interface timing parameters from the specification table are
defined in the figures below.
The sensor responds to commands received on the MOSI (Master-Out Slave-In), SCLK (Serial Clock), and CSB (Chip Select)
Input topin.
A1339
pins, and outputs data on the MISO (Master-In Slave-Out)
All three input pins are 3.3 V and 5 V SPI compatible, with
threshold values determined by factory EEPROM settings. MISO
output voltage level will conform to 3.3 V or 5 V SPI levels,
Output
based on factory settings. Regular part are shipped
withfrom
3.3 A1339
V
interface. Contact Allegro for ordering options of the 5 V variant.
The setup for communication using the SPI interface is given
below.
Output from A1339
Fixed supply
voltage, e.g. 5 V
tCS_IDLE
CSx
tCS
tSCLKH
tCHD
SCLKx
CSx
MOSIx
SCLKx
CSx
MOSIx
tCS_IDLE
tSU
tCS
CSx
MISOx
MISOx
tSCLKL
tHD
tSCLKH
R/W
tCHD
tCS_IDLE
Figure t38:
SPI Interface Timings Input
SU tHD
tCS
tSCLKL
tSCLKH
tCHD
R/W
tCS_IDLE
SCLKx
SCLKx
VCC
tSCLKL
tDAV
tCS
tSCLKL
tSCLKH
DO-15
DO-14
DO-x
tCHD
Register Contents
tDAV
DO-15
DO-14
DO-x
Register Contents
Host
Sensor
SPI
SPURIOUS INTERFACE ERROR (IER) WHEN
SHARING SPI LINES
R/W commands and
return data (SPI)
GND
Figure 39: SPI Interface Timings Output
GND
Figure 37: SPI Interface Programming Setup
The IER error flag may provide an erroneous indication when the
SCLK line is shared amongst multiple ICs. Ways to avoid this are
detailed in Appendix B.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
SPI INTERFACE SPECIFICATIONS (for 3.3 V SPI Mode)
Digital Input High Voltage
VIH
MOSI, SCLK, CS pins
2.8
–
3.63
V
Digital Input Low Voltage
VIL
MOSI, SCLK, CS pins
–
–
0.5
V
SPI Output High Voltage
VOH
MISO pins, CL = 20 pF, TA = 25°C,
5 V compliant
2.93
3.3
3.63
V
SPI Output Low Voltage
VOL
MISO pins, CL = 20 pF
–
0.3
–
V
SPI INTERFACE SPECIFICATIONS (for 5.0 V SPI Mode) (Contact Allegro for 5 V SPI ordering information)
Digital Input High Voltage
VIH
MOSI, SCLK, CS pins
3.75
–
5.5
V
Digital Input Low Voltage
VIL
MOSI, SCLK, CS pins
–
–
0.5
V
SPI Output High Voltage
VOH
MISO pins, CL = 20 pF, TA = 25°C, VCC ≥ 5.0V
4
5
5.5
V
SPI Output Low Voltage
VOL
MISO pins, CL = 20 pF
–
0.3
–
V
fSCLK
MISO pins, CL = 20 pF
0.1
–
10
MHz
SPI INTERFACE SPECIFICATIONS
SPI Clock Frequency [1]
SPI Clock Duty
Cycle [1]
DfSCLK
SPI Frame Rate [1]
tSPI
Chip Select to First SCLK Edge [1]
tCS
tCS_IDLE
Chip Select Idle Time [1]
Data Output Valid Time [1]
MOSI Setup
Time [1]
MOSI Hold Time [1]
SCLK to CS Hold
Time [1]
Load Capacitance [1]
[1] Parameter
SPICLKDC
40
-
60
%
5.8
–
588
kHz
Time from CS going low to SCLK falling edge
50
–
–
ns
Time CS must be high between SPI message
frames
200
–
–
ns
tDAV
Data output valid after SCLK falling edge
–
30
–
ns
tSU
Input setup time before SCLK rising edge
25
–
–
ns
tHD
Input hold time after SCLK rising edge
50
–
–
ns
tCHD
Hold SCLK high time before ¯CS rising edge
5
–
–
ns
Loading on digital output (MISO) pin
–
–
20
pF
CL
is not guaranteed at final test. Determined by design.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
MESSAGE FRAME SIZE
21-BIT SPI PACKET
The SPI interface requires either 16, 17, or 20-bit packet lengths.
An extended 20-bit SPI packet allows 4 bits of CRC to accompany every data packet. A 17-bit packet is only allowed if the
EEPROM/Shadow bit “s17” (bit 1 of EEPROM 0x1B) is set to 1.
If sharing an SPI bus, the A1333 may exhibit a false IER flag
when using the standard SPI packet sizes. To prevent this, a
21-bit SPI packet should be used.
CSN
SCLK
SCLK
MOSI
0
W-1 R-0
M_D1
M_D0
M_C3
M_C2
M_C1
M_C0
0
MISO
S_D15
S_D14
S_D1
S_D0
S_C3
S_C2
S_C1
S_C0
S_C3
MISO
MOSI
15
14
1
0
Figure 43: Twenty-One Bit SPI Transaction
Figure 40: Sixteen Bit SPI Transaction
The 21st bit sent from the master should be a logic ‘0’, effectively
left-shifting the standard 20-bit packet by 1 bit. The IC’s response
will repeat the most significant bit of the CRC, shifted out on the
last SCLK edge. See Appendix B for more information.
CSN
SCLK
MISO
MOSI
15
14
1
0
X
WRITE CYCLE
Figure 41: Seventeen Bit SPI Transaction
CSN
SCLK
MISO
MOSI
CSN
15
14
1
0
C3
C2
C1
C0
Figure 42: Twenty Bit SPI Transaction
If more clock pulses than expected were detected by the sensor in
an SPI transaction, the interface warning “warn.ier” will activate.
This warning will not activate on clean SPI transactions with 16
or 20 bit, or with clean 17-bit transactions when “s17” is enabled.
The purpose of the 17-bit SPI option is to allow delayed reading of
the MISO line by the host. Some host allow to sample data from
the slave not on the rising edge, but on the next falling edge of
SCLK. This way, in case of long interface delays caused by large
line capacitance or very long cables, the permissible clock speed
can be increased. However, a 17th falling edge is required to read
the 16th bit coming from the sensor. For the sensor to not display
an error when this 17th clock is found, the bit “s17” must be set.
Write cycles consist of a 1-bit low, a 1-bit R/W (write = high),
6 address bits (corresponding to the primary serial register), 8
data bits, and 4 optional CRC bits. To write a full 16-bit serial
register, two write commands are required (even and odd byte
addresses). MOSI bits are clocked in on the rising edge of the
Master-generated SCLK signal.
READ CYCLE
Reading data always involves at least two SPI frames. In the first
frame, the read command is sent, while in the second frame, the
result from the first read is received. While receiving data from
the last read command, it is possible to send another read command (duplexed read). This way, every frame except the first one
contains data from the sensor. This is useful for very fast reading
of angle information.
When receiving the last frame, the host can transmit a command
with MOSI set to all zeros. This represents a read command from
register 0x00 and will not cause any reaction from the sensor.
Reading from register 0x00 will output the value 0x0000.
In frames where no previous read command was sent, the MISO
data output should be ignored.
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A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
Because an SPI read command can transmit 16 data bits at one
time, and the primary serial registers are built from one even
and one odd byte, the entire 16-bit contents of one serial register
may be transmitted with one SPI frame. This is accomplished by
providing an even serial address value. If an odd value address
is sent, only the contents of the single byte will be returned, with
the eight most significant bits within the SPI packet set to zero.
Example: To read all 16 bits of the error register (0x24:0x25), an
SPI read request using address 0x24 should be sent. If only the
8 LSBs are desired, the address 0x25 should be used. Figure 44
shows examples of both an SPI write and an SPI read request,
using a 16-bit SPI message frame.
CSx
(A) SPI Write example
(duplexed read available)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Input
latched
SCLKx
MOSIx
MISOx
DO-15 DO-14 DO-13 DO-12 DO-11 DO-10 DO-9 DO-8 DO-7 DO-6 DO-5 DO-4 DO-3 DO-2 DO-1 DO-0
Register Contents (previous Read command selection, or Don’t Care)
Input
latched
CSx
1
(B) SPI Read example:
register selection
(duplexed read available)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLKx
MOSIx
MISOx
DO-15 DO-14 DO-13 DO-12 DO-11 DO-10 DO-9 DO-8 DO-7 DO-6 DO-5 DO-4 DO-3 DO-2 DO-1 DO-0
Register Contents (previous Read command selection, or Don’t Care)
CSx
(C) SPI Read example:
data output from
selected register
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLKx
MOSIx
MISOx
DO-15 DO-14 DO-13 DO-12 DO-11 DO-10 DO-9 DO-8 DO-7 DO-6 DO-5 DO-4 DO-3 DO-2 DO-1 DO-0
Register Contents (previous Read command selection, or Don’t Care)
Figure 44: SPI Read and Write Pulse Sequences
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CRC
The CRC can be calculated with the following C code:
If the user want to check the data coming from the sensor, it is possible to use 20-bit SPI frames. Without additional setting required,
a 4-bit CRC is automatically generated and placed on the MISO
line if more than 16 bits are read from the sensor.
/*
* CalculateCRC
*
* Take the 16-bit input and generate a 4-bit CRC
* Polynomial = x^4 + x + 1
* LFSR preset to all 1’s
*/
uint8_t CalculateCRC(uint16_t input)
{
bool CRC0 = true;
bool CRC1 = true;
bool CRC2 = true;
bool CRC3 = true;
int i;
bool DoInvert;
uint16_t mask = 0x8000;
The four additional CRC bits on the MOSI line coming from
the host are ignored by the sensor, unless the “PWI.sc” bit is set
within EEPROM (0x1B, bit 0). When the incoming CRC check
is enabled, an incoming SPI packet with an incorrect CRC will be
discarded, and the CRC error flag set in serial register “warn.crc”.
The CRC is based on the polynomial x4 + x + 1 with the linear
feedback shift register preset to all 1s. The 16-bit packet is shifted
through from bit 15 (MSB) to bit 0 (LSB). The CRC logic is
shown in Figure 45. Data are fed into the CRC logic with MSB
first. Output is sent as C3-C2-C1-C0.
C0
C1
C2
C3
Input Data
Figure 45: SPI CRC
The CRC output by the sensor on the MISO pin will always be
correct. The CRC from the host on the MOSI pin must be correct
if the CRC enable bit PWI.sc in the EEPROM was set.
for (i = 0; i < 16; ++i)
{
DoInvert = ((input & mask) != 0) ^ CRC3;
CRC3 = CRC2;
CRC2 = CRC1;
CRC1 = CRC0 ^ DoInvert;
CRC0 = DoInvert;
mask >>= 1;
}
return (CRC3 ? 8U : 0U) + (CRC2 ? 4U : 0U) + (CRC1 ? 2U
: 0U) + (CRC0 ? 1U : 0U);
}
Note: If the ERD (extended read data) register is read before the
“ERCS.ERD” bit indicates a read has completed, there is a possibility of a CRC error, as the data could change during the read.
Do not read the ERD register until it is known to be stable based
on the done bit indication or waiting sufficient time.
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Manchester Interface
To facilitate addressable device programming when using the
unidirectional PWM, ABI, or UVW protocols, with no need for
additional wiring, the A1333 incorporates a serial interface on the
VCC line (Note: The A1333 may also be programmed via SPI,
with additional wiring connections).
This interface allows an external controller to read and write registers in the A1333 EEPROM and volatile memory. The device uses
a point-to-point communication protocol, based on Manchester
encoding per G.E. Thomas (a rising edge indicates a 0 and a falling
edge indicates a 1), with address and data transmitted MSB first.
The addressable Manchester code implementation uses the logic
states of the SA0/SA1 pins to set address values for each die. In
this way, individual communication with up to four A1333 dies is
possible. To prevent any undesired programming of the A1333, the
serial interface can be disabled by setting the Disable Manchester
bit, “PWI.dm”, to 1. With this bit set, the sensor will ignore any
Manchester input on VCC.
The setup for communication using the Manchester interface is
given in Figure 46.
R/W commands
(Manchester code)
VCC
Set to logic high
or to GND to
choose target ID#
CS/SA0
Sensor
GND
As Manchester commands are sent on the supply line, the speed
is usually limited by capacitances on the supply line. A reduction
of the bit rate, or using a stronger line driver, can help to ensure
stable communication.
If a correct read command was sent, the sensor responds to the
master using the open-drain output on the PWM line. The high
level will be determined by the PWM pull-up (usually 3.3 V or
5 V), and the low level will be close to GND. The PWM uses an
open drain output, setting the logic levels to GND and logic level
high (see Figure 46). A sufficient pull-up resistor (e.g. 4.7 kΩ)
must be used to pull the line to a maximum logic high level VIN.
ENTERING MANCHESTER COMMUNICATION MODE
Provided the Disable Manchester bit is not set in EEPROM, the
A1333 continuously monitors the VCC line for valid Manchester
commands. The part takes no action until a valid Manchester
Access Code is received.
There are two special Manchester code commands used to
activate or deactivate the serial interface and specify the output
format used during Read operations:
to logic high supply
Host
MOSI/SA1
The master can freely choose any supported Manchester communication frequency for each transaction. The sensor will recognize
the transaction speed used by the master and send the response at
the same data rate.
PWM
Return data
(Manchester code)
GND
Figure 46: Manchester Interface Programming Setup
CONCEPT OF MANCHESTER COMMUNICATION
The Manchester interface allows programming and readout with
a minimal number of pins involved. This is beneficial for sensor subassemblies connected to wiring harnesses, because less
connections are needed. The supply level is typically modulated
between 5 and 8 volts (VMAN(H) and VMAN(L)) to produce a “low”
and “high” signal. In the absence of a clock signal, Manchester
encoding is used, allowing the sensor to determine the bit rate
that the host is using.
1. Manchester Access Code: Enters Manchester Communication
Mode; Manchester code output on the PWM pin. See further
paragraphs for example.
2. Manchester Exit Code; returns the PWM pin to normal operation. See further paragraphs for example.
Once the Manchester Communication Mode is entered, the PWM
output pin will cease to provide angle data, interrupting any data
transmission in progress.
TRANSACTION TYPES
The A1333 receives all commands via the VCC pin, and responds
to Read commands via the PWM pin. This implementation of
Manchester encoding requires the communication pulses be
within a high (VMAN(H)) and low (VMAN(L)) range of voltages on
the VCC line. Each transaction is initiated by a command from
the controller; the sensor does not initiate any transactions. Two
commands are recognized by the A1333: Write and Read.
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CONTROLLER MANCHESTER MESSAGE STRUCTURE
The general format of a command message frame is shown in
Figure 47. Note that, in the Manchester coding used, a bit value
of 1 is indicated by a falling edge within the bit boundary, and
a bit value of zero is indicated by a rising edge within the bit
boundary.
When the A1333 is operating in PWM mode, the Die ID value is
determined by the state of the CSN and MOSI pins, as detailed in
Table 6.
Table 6: Pin Values
MOSI/SA1
CS/SA0
ID Value
0
0
ID0
0
1
ID1
1
0
ID2
1
1
ID3
Using the 4 bits of the Chip Select field, die can be selected
via their ID value, allowing up to four die to be individually
addressed and providing for different group addressing schemes.
Figure 47: Manchester Message Format
A brief description of each bit is provided in Table 5.
Table 5: Manchester Command General Format
Bits
Parameter
Name
Description
2
Synchronization
Value '00' sent to identify a command start
and to synchronise sensor clock
1
Read/Write
Example: If Target ID = [1 0 1 0], all die with ID3 or ID1 will be
selected. If Target ID is set to [0 0 0 0], then no ID comparison
will be made, allowing all sensors to be addressed at once. In
case of PWM line sharing for Manchester communication, reading must be done one die at a time.
Table 7: Target ID
Target ID
ID3
ID2
ID1
ID0
0 = write, 1 = read
4
Target ID
Select the target ID for this transaction.
[ID3 ID2 ID1 ID0] are each adressed /
ignored by a 1 / 0 at their address, so that
a write to [0011] will write to ID0 and ID1.
Reading from several sensors at the same
time is not supported.
Writing to [0000] is a broadcast write; it is
written to all sensor dies.
6
Address
Serial address for read/write
16
Data
Only for writes: 16 bit write data. Omit for
read commands
3
CRC
3-bit CRC, needed for all commands
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SENSOR MANCHESTER MESSAGE STRUCTURE
If a read command with the desired register number was sent
from the controller to the sensor, the device responds with a Read
Response frame using the Manchester protocol over the PWM
output.
In addition to the contents of the requested memory location, a
Return Status field is included with every Read Response. This field
provides the ID used to communicate with the part and any errors
which may have occurred during the transaction. These bits are:
• ID – ID (CSN/MOSI) unless BC = 1 (ID will be 00)
The following command messages can be exchanged between the
device and the external controller:
• BC – Broadcast; ID field was zero or SPI mode active
• Manchester Access Code (host to sensor)
• Manchester Exit Code (host to sensor)
• OR– Overrun Error; A new Manchester command has been
received before the previous request could be completed
• Manchester Write Command (host to sensor)
• CS – Checksum error; a prior command had a checksum error
• Manchester Read Command (host to sensor)
For EEPROM address information, refer to the EEPROM
structure section. For serial address locations, refer to the serial
register map.
• Manchester Read Response (sensor to host)
• AE – Abort Error; edge detection failure after sync detect
Table 8: Return Status Bits
Synchronize
0
Return Status
Data (16 Bits)
Return Status Bits (6 bits)
CRC
5
0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 ... 0/1 0/1 C2 C1 C0
4
ID
MSB
3
2
1
0
BC
AE
OR
CS
Figure 48: Manchester Message Format
MANCHESTER ACCESS CODE
Table 9: Manchester Access Code
The Manchester Access Code has to be sent before other Manchester commands.
Bits
Parameter Name
Description
2
Synchronization
‘00’
1
Read/Write
‘0’
4
Target ID
‘0000’ (this command will always be a
broadcast, even if it is addressed)
6
Address
‘111111’ (fixed number for Manchester
access message)
16
Data
0x62D2 (fixed number for Manchester
access message)
3
CRC
3-bit CRC
The Manchester Access Code always operates as a broadcast
pulse, meaning the sensor will not look at the Target ID field. For
example, if two sensors configured with ID0 and ID1 respectively are sharing a common VCC line, a Manchester Access
Code with a Target ID value of [0 0 1 0] results in both sensors
entering Manchester Serial Communication mode.
An example is given below, with target ID = [0 0 0 1], data =
access code = 0x62D2, and CRC = ‘110’.
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0x62
0
0
0
1
0
1
1
0
0xD2
1
0
0
1
0
1
1
0
Figure 49: Target ID = [0 0 0 1], Data = Access code = 0x62D2, CRC = ‘110’ 4.3.5.2
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MANCHESTER EXIT CODE
The Manchester Exit Code can be sent after Manchester access
is complete in order to avoid accidental decoding of Manchester
commands.
Table 10: Manchester Exit Code
The Manchester Exit Code always operates as a broadcast pulse,
meaning the sensor will not look at the Target ID field. For example, if two sensors configured with ID0 and ID1 respectively are
sharing a common VCC line, a Manchester Access Code with a
Target ID value of [0 0 1 0] results in both sensors exiting Manchester Serial Communication mode.
Bits
Parameter Name
Description
2
Synchronization
‘00’
1
Read/Write
‘0’
4
Target ID
‘0000’ (this command will always be a
broadcast, even if it is addressed)
6
Address
‘111111’ (fixed number for Manchester
exit message)
16
Data
0x0000 (any value except 0x62D2 can
be used for Manchester exit message)
3
CRC
3-bit CRC
An example is given below, with target ID = [0 0 0 1], data =
0x0000, and CRC = ‘110’.
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0x00
0
0
0
0
0
0
0
0
0x00
0
0
0
0
0
1
1
0
Figure 50: Target ID = [0 0 0 1], Data = 0x0000, CRC = ‘110’
MANCHESTER READ COMMAND
Determines the serial address within the sensor from which the
next Read Response will transmit data. The sensor must first
receive a Manchester Access Code before responding to a read
command.
This command is sent by the controller.
An example is given below where register 0x20 “angle” is read
from target ID [0 0 0 1] with CRC = ‘111’. The two sync pulses
from the Read Response on the PWM return line are also shown.
0x20
0
0
1
0
0
0
1
1
0
0
0
0
0
1
1
Table 11: Manchester Read Command
Bits
Parameter Name
Description
2
Synchronization
‘00’
1
Read/Write
‘1’
4
Target ID
Depends on targeted sensor ID, e.g. to
target ID0, use ‘0001’
6
Address
Serial Register Address, e.g. 0x10 for
“read_data_lo”, or 0x20 for “angle”
3
CRC
3-bit CRC
1
0
0
Figure 51: Target ID = [0 0 0 1], “angle” = 0x20, CRC = ‘111’
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MANCHESTER READ RESPONSE
The read response transmits data from the sensor to the controller after a read command. These data are sent by the sensor on the
open-drain PWM pin. A pull-up resistor is needed for this to work.
Read from an even address returns even byte [15:8] and odd byte
[7:0].
Read from an odd address returns odd byte [7:0] only. Data bits
[15:8] will be zeroes.
Table 12: Manchester Read Response
Bits
Parameter Name
2
Synchronization
Description
‘00’
2
ID
1
BC flag
Target ID of the responding sensor die. ‘00’ for ID0, ‘01’ for ID1, ‘10’ for ID2, ‘11’ for ID3.
“Broadcast”: Value set to ‘1’ if read command was a broadcast command (Target-ID set to [0 0 0
0]), ‘0’ if not
1
AE flag
“Abort error”: Value set to ‘1’ if a previous transaction was aborted and discarded, typically caused
by incorrect bit lengths, ‘0’ is there was no problem. The error is stored until it can be transmitted
on the next read response, and is cleared afterwards.
1
OR flag
“Overrun error”: If a command is sent to the sensor while the sensor is still sending a read
response, and this command is completely transmitted before the read response was finished, and
overrun error has occurred. This error is then stored until it can be transmitted on the next read
response, and is cleared afterwards.
1
CS flag
“CRC error”: Value set to ‘1’ if a previous transaction had an incorrect CRC, ‘0’ means there was no
problem. The error is stored until it can be transmitted on the next read response, and is cleared
afterwards.
16
data
Read from an Even address: even byte [15:8] and odd byte [7:0].
Read from an Odd address: odd byte [7:0] only. Data bits [15:8] will be zeroes.
3
CRC
3-bit CRC
An example is given below where register 0x20 “angle” is read,
and the response is ID ‘00’ (ID0), the four flags are all zeros (no
errors), the data is “0x5C34”, and the CRC is ‘100’.
0x20
0 0
1
0 0
0 1 1
0 0
0
0 0 1
1 1
0 0
0 0 0
0
0 0 0
1 0
0x5C
1 1 1
0
0
0 0 1
0x34
1 0 1
0
0
1
0 0
Figure 52: ID = ‘00’, error flag = ‘0000’, Data = 0x5C34, CRC = ‘100’
MANCHESTER READ RESPONSE DELAY
The Manchester Read Reponse starts at the end of the Read
Command. The response may start a ¼ bit time before the CRC
is finished transmitting (overlap with last CRC bit) or ¼ after the
CRC finished transmitting.
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CRC
The serial Manchester interface uses a cyclic redundancy check
(CRC) for data-bit error checking of all the bits coming after
the two synchronization bits. The synchronization bits are not
included in the CRC. The CRC algorithm is based on the polynomial:
g(x) = x3 + x + 1.
The calculation is represented graphically in Figure 53. The trailing 3 bits of a message frame comprise the CRC token. The CRC
is initialized at 111. Data are fed into the CRC logic with MSB
first. Output is sent as C2-C1-C0.
C0
1 + x0
C1
1 + x1
C2
1 + x2
Input Data
1 + x3
The 3-bit Manchester CRC can be calculated using the following
C code:
// command: the manchester command, right justified, does
not include the space for the CRC
// numberOfBits: number of bits in the command not including the 2 zero sync bits at the start of the command and the
three CRC bits
// Returns: The three bit CRC
// This code can be tested at http://codepad.org/yqTKnfmD
uint16_t ManchesterCRC(uint64_t data, uint16_t numberOfBits)
{
bool C0 = false;
bool C1 = false;
bool C2 = false;
bool C0p = true;
bool C1p = true;
bool C2p = true;
uint64_t bitMask = 1;
= x3 + x + 1
bitMask = 1)
{
C2 = C1p;
C0 = C2p ^ ((data & bitMask) != 0);
C1 = C0 ^ C0p;
}
0U);
}
C0p = C0;
C1p = C1;
C2p = C2;
return (C2 ? 4U : 0U) + (C1 ? 2U : 0U) + (C0 ? 1U :
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A1333
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EEPROM AND SHADOW MEMORY USAGE
The device uses EEPROM to permanently store configuration
parameters for operation. EEPROM is user-programmable and
permanently stores operation parameter values or customer
information. The operation parameters are downloaded to shadow
(volatile) memory at power-up. Shadow fields are initially loaded
from corresponding fields in EEPROM, but can be overwritten,
either by performing an extended write to the shadow addresses,
or by reprogramming the corresponding EEPROM fields and
power cycling the IC. Use of Shadow Memory is substantially
faster than accessing EEPROM. In situations where many
parameter need to be tested quickly, shadow memory is recommended for trying parameter values before permanently programming them into EEPROM. The shadow memory registers have
the same format as the EEPROM and are accessed at extended
addresses 0x40 higher than the equivalent EEPROM address.
Unused bits in the EEPROM do not exist in the related shadow
register, and will return 0 when read. Shadow registers do not
contain the ECC bits. Shadow registers have the same protection
restrictions as the EEPROM. All registers can be read without
unlocking. The mapping of bits from registers addresses in
EEPROM to their corresponding register addresses in SHADOW
is shown in the EEPROM table (See “EEPROM table” section).
Enabling EEPROM Access
To enable EEPROM write access after power-on-reset, a unlock
code needs to be written to the serial register “keycode”. This
involves five write commands, which should be executed after
each other:
Write 0x00 to register 0x3C[15:8]
Write 0x27 to register 0x3C[15:8]
Write 0x81 to register 0x3C[15:8]
Write 0x1F to register 0x3C[15:8]
Write 0x77 to register 0x3C[15:8]
This needs to be done once after power-on reset if the customer
intends to write to the EEPROM.
EEPROM Write Lock
It is possible to protect the EEPROM against accidental writes.
• Setting the EEPROM field “lock” to value 0xC (‘1100’ binary)
will block any writes to the EEPROM, so that permanent
changes are not possible anymore. Temporary changes to the
setting are still possible by writing to the shadow memory, but
these changes are lost after a power cycle.
This lock is permanent and cannot be reversed. Reading of the
settings is still possible.
• Setting the EEPROM field “lock” to value 0x3 (‘0011’ binary)
will lock EEPROM writes AND shadow memory writes. This
means none of the sensor settings can be changed anymore.
This lock is permanent and cannot be reversed. Reading of the
settings is still possible.
Write Transaction to EEPROM and Other
Extended Locations
Invoking an extended write access is a three-step process:
1. Write the extended address into the “ewa” register (using
SPI or Manchester direct access). “ewa” is the 8-bit extended
address that determines which extended memory address will
be accessed.
2. Write the data that is to be transferred into the “ewd” registers (using SPI or Manchester direct access). This will take
four SPI writes or 2 Manchester packets to load all 32 bits of
data.
3. Invoke the extended access by writing the direct “ewcs.exw”
bit with ‘1’.
The 32-bit of data in “ewd” are then written to the address specified in “ewa”.
The bit “ewcs.wdn” can be polled to determine when the write
completes. This is only necessary for EEPROM writes, which can
take up to 24 ms to complete. Shadow register writes complete
immediately in one system clock cycle after synchronization.
Writing to serial registers and reading from serial registers does
not require anything special after power-on.
Reading all EEPROM cells is always possible.
Device must be unlocked when performing EEPROM margin
checking.
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For example, to write location 0x1F in the EEPROM with 0x00A45678:
• Write 0x1F to lower 8 bits of EWA register (0x1F to EWA+1 Address 0x03)
0x43
0x1F
• Write 0x00A45678 to EWD (0x00 to EWD, 0xA4 to EWD+1, 0x56 to EWD+2, 0x78 to EWD+3)
0x44
0x00
0x45
0xA4
0x46
0x56
0x47
0x78
• Write 0x80 to EWCS
0x48
0x80
• Read EWCS+1 until bit 0 (“wdn”) is set, or wait enough time.
In the example, register 0x08 is read, so that the second output byte is from register 0x09, and we wait for bit 0 to become ‘1’, which
happens in the last read.
0x08
0x00
0x00
0x00
0x08
0x00
0x00
0x00
0x08
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x01
If an access violation occurs (address not unlocked), the transaction will be terminated and the corresponding “rdn” or “wdn” bit set,
and the “xee” warning bit will assert. The “xee” bit in the “err” register will also set if the EEPROM write aborts.
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After writing to the EEPROM, verify that the write was successful by performing an EEPROM margin check.
EEPROM Margin Check
Due to nonidealities in transistors, current will slowly leak into
or out of EEPROM cells and can, over time, cause small changes
in the stored voltage level. Variances in voltage levels of the
charge pump can result in a variety of stored EEPROM cell
voltages when programming. If this value is marginally close to
the threshold, the small drift over lifetime can cause this value to
move across the threshold. This results in a corrupted EEPROM
value. Since this drift happens slowly over time, if there is an
issue, it may not appear for years. For this reason, it is important
to perform margin testing (margining) to verify the internal voltage levels of EEPROM cells after programming, and ensure there
will be no issue in the future.
Margining is performed by Allegro on all registers at final test.
Since EEPROM cell voltages are only modified when writing to
the cell, it is not necessary to perform margining on registers that
have not been modified.
Margining is performed in two steps: the first checks the validity
of the voltage stored on digital ‘1’ cells, and the second checks
the voltage stored on digital ‘0’ cells. It is important to perform
both steps to ensure there are no issues.
In order to perform margining, a value of ‘0b0001’ must be written to the SPECIAL field of the CTRL register. This reduces the
internal threshold value. Once this value is written, an EEPROM
read will use this lower threshold when reading EEPROM values.
Perform a read on all EEPROM registers that are being tested,
and confirm they read correctly. If a stored voltage is marginal
to the normal operating threshold, it will appear as a ‘1’ when it
should be a ‘0’.
Repeat this test with the value of ‘0b0010’ in the SPECIAL register to raise the threshold value above normal operation. Again,
read all EEPROM registers being tested. In this test, any stored
high voltage that is marginal to the normal threshold will appear
as a ‘0’ when they should be ‘1’.
If during either test, a bit is read incorrectly, simply perform
another EEPROM write of the desired values to the register, and
retest the margins.
Unlike other values in the SPECIAL field, these values will
persist and can be read to confirm the write was successful. As a
result, the SPECIAL register must be cleared (or power cycled) to
return the threshold value to its normal level.
In the figure below, VNOM(H) represents the nominal voltage
programmed into EEPROM cells containing a ‘1’, and VNOM(L)
represents the nominal voltage programmed into EEPROM cells
containing a ‘0’. The red and blue lines represent the actual voltage levels in the programmed cells for ‘1’ and ‘0’ values respectively. As can be seen, at time 0 when the margin test is run, both
high and low levels still appear to be the correct value when the
threshold is moved to the margin testing levels.
EEP voltage
VNOM(H)
Margin Test [H]
VTHRESH
Margin Test [L]
VNOM(L)
�me
Figure 54: Example of passing programming voltages
In the figure below, the high and low voltage levels at the time
of programming are further from their target. The drift over time
results in these value crossing VTHRESH, and becoming corrupted.
At time 0 when the margin test is run, these values fail, and
would be reported as errors to be reprogrammed.
EEP voltage
VNOM(H)
Margin Test [H]
VTHRESH
Margin Test [L]
VNOM(L)
�me
Figure 55: Example of failing programming voltages
Allegro MicroSystems
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A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
Margining is shown below as a list of high level steps. For details
on performing individual steps, see the associated sections.
1. Clear the ERR and WARN registers.
2. Write new data to EEPROM as desired.
3. Check the following flags for communication errors: ESE,
EUE, XEE, IER, CRC, BSY.
4. Set CTRL.special to ‘0001’ and confirm by writing 0xA5 to
CTRL.initiate_special.
5. Check the following flags for communication errors: ESE,
EUE, XEE, IER, CRC, BSY.
6. Read all EEPROM registers changed in step 1 and verify
their contents.
7. Set CTRL.special to ‘0010’ and confirm by writing 0xA5 to
CTRL.initiate_special.
8. Check the following flags for communication errors: ESE,
EUE, XEE, IER, CRC, BSY.
9. Read all EEPROM registers changed in step 1 and verify
their contents.
10. If any values read in steps 3/5 are not what was set in step 1,
repeat steps 1-6 for erroneous registers.
11. Set CTRL.special to ‘0000’, or power cycle the part.
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A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
Read Transaction from EEPROM and Other
Extended Locations
Extended access is provided to additional memory space via the
direct registers. This access includes the EEPROM and EEPROM
shadow registers. All extended registers are up to 32 bits wide.
Invoking an extended read access is a three-step process:
1. Write the extended address to be read into the “era” register
(using SPI or Manchester direct access). “era” is the 8-bit
extended address that determines which extended memory
address will be accessed.
2. Invoke the extended access by writing the direct “ercs.ext”
bit with ‘1’. The address specified in “era” is then read, and
the data is loaded into the “erd” registers.
3. Read the “erd” registers (using SPI or Manchester direct access) to get the extended data. This will take multiple packets
to get all 32 bits.
EEPROM read accesses may take up to 2 µs to complete. The
“ercs.rdn” bit can be polled to determine if the read access is
complete before reading the data. Shadow register reads complete
in one system clock cycle after synchronization. Do not attempt
to read the “erd” registers if the read access is potentially in
process, as it could change during the serial access and the data
will be inconsistent. It is also possible that an SPI CRC error will
be detected if the data changes during the serial read via the SPI
interface.
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
For example, to read location 0x1F in the EEPROM:
• Write 0x1F to lower 8 bits of “era” (0x1F to “era+1”, Address 0x0B)
0x4B
0x1F
• Write 0x80 to “ercs”
0x4C
0x80
• Read “ercs”+1 until bit 0 (“rdn”) is set, or wait enough time.
In the example, register 0x0C is read, so that the last bit of the second output byte contains the “rdn” bit.
0x0C
0x00
0x00
0x00
0x52
0x7B
0x00
0x01
• Read “erdh” (upper 16 bits of read data)
• Read “erdl” (lower 16 bits of read data)
In the example below, the result for the data at address 0x1F is 0x58A45678. In this value,
□ Bit [31:26] are the EEPROM CRC
□ Bit [25:24] are unused and zero
□ Bit [23:0] are the EEPROM values that can be used. These are the 24 bits containing the information 0xA45678 that was written
in the EEPROM write example.
0x0E
0x00
0x00
0x00
0x10
0x00
0x00
0x00
0x00
0x00
0x58
0xA4
0x00
0x00
0x56
0x78
Note that it would have been possible to pipeline transactions in this example, i.e. send a new command while reading return data from
the old command. This way the transaction could have been performed in 5 SPI frames instead of 8.
Allegro MicroSystems
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A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
Shadow Memory Read and Write Transactions
Shadow memory Read and Write transactions are identical to
those for EEPROM. Instead of addressing to the EEPROM
extended address, one must address to the Shadow Extended
addresses, which are located at an offset of 0x40 above the
EEPROM. Refer to the EEPROM table for all addresses.
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
PRIMARY SERIAL INTERFACE REGISTER REFERENCE
Table 13: Primary Serial Interface Registers Bits Map
Address* Register Read/
(0x00) Symbol Write
Addressed Byte (MSB)
Addressed Byte + 1 (LSB)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0x00
nop
RO
0
0
0
0
0
0
0
0
0x02
ewa
RW
0
0
0
0
0
0
0
0
0x04
ewdh
RW
write_adr
LSB
Address
0x01
0x03
write_data_hi
0x05
0x06
ewdl
RW
0x08
ewcs
WO/RO
exw
0
0
0
0
0
0
write_data_lo
wip
0x0A
era
RW
0
0
0
0
0
0
0
0
0x0C
ercs
WO/RO
exr
0
0
0
0
0
0
0x0E
erdh
RO
read_data_hi
0x0F
0x10
erdl
RO
read_data_lo
0x11
0x12
0x14
0x16
0x18
0x1A
0x1C
Unused
RO
0x1E
ctrl
RW/WO
0x20
ang
RO
0
ef
uv
p
0x22
sta
RO
1
0
0
0x24
err
RO
1
0
0x26
warn
RO
1
0x28
tsen
RO
1
0x2A
field
RO
0x2C
turns
0x2E
Unused
0x30
0
0
0
0
0x07
0
0
0
0
0
0
0
wdn
read_adr
rip
0
0
0
0
0
0
0
0
0
0
0
rdn
0
0
0x0D
0x13
0x15
0x17
0x19
0x1B
0x1D
0
0
0
0
0
cls
clw
cle
0
0
0
1
0
war
stf
avg
0
1
1
ier
crc
0
1
1
1
temperature
0x29
1
1
1
0
gauss
0x2B
RO
1
1
0
p
RO
0
0
0
0
hang
RO
0
ef
uv
p
0x32
ang15
RO
0
0x34
zang
RO
0
ef
uv
p
0x36
0x38
0x3A
Unused
RO
0
0
0
0
0x3C
ikey
WO/RO
0x3E
Unused
RO
special
0
0
0x09
0x0B
initiate_special
0x1F
angle
dieid
0x21
rot
0
sdn
bdn
lbr
cstr
bip
aok
0x23
abi
plk
zie
eue
ofe
uvd
uva
msl
rst
0x25
srw
xee
tr
ese
sat
tcw
bsy
msh
tov
0x27
turns
0
0
0
0
0
0
0x2D
0
0
0
0
0
0
angle_hys
0x31
angle_15
0
0
0
keycode
0
0
0
0
0x33
angle_zcd
0
0
0
0
0
0x2F
0x35
0
0
0
0
0
0
0
0
0x37
0x39
0x3B
0
0
0
0
0
0
0
cul
0x3D
0
0
0
0
0
0
0
0
0x3F
*Addresses that span multiple bytes are addressed by the most significant byte.
Address 0x00:0x00 (NOP) – Null Register
Address
Bit
0x00
15
14
13
12
0x01
11
10
9
8
7
6
5
4
3
2
1
0
Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Address 0x02:0x03 (EWA) – Extended Write Address
Address
0x02
0x03
Bit
15
14
13
12
11
10
9
8
Name
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
R/W
R/W
R/W
WRITE_ADDR
R/W
R/W
R/W
R/W
R/W
WRITE_ADDR[7:0]:
Address to be used for an extended write. Address ranges:
0x00 - 0x1F: EEPROM (requires ≈ 24 ms following execution of a write)
0x40 - 0x5F: Shadow
Address 0x04:0x05 (EWDH) – Extended Write Data High
Address
Bit
0x04
15
14
13
12
0x05
11
10
9
Name
R/W
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WRITE_DATA_HI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WRITE_DATA_HI[15:0]:
Upper 16 bits of data for an extended write operation.
Address 0x06:0x07 (EWDL) – Extended Write Data Low
Address
Bit
0x06
15
14
13
12
0x07
11
10
9
Name
R/W
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WRITE_DATA_LO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WRITE_DATA_LO[15:0]:
Lower 16 bits of data for an extended write operation.
Address 0x08:0x09 (EWCS) – Extended Write Control and Status
Address
0x08
0x09
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
EXW
0
0
0
0
0
0
WIP
0
0
0
0
0
0
0
WDN
R/W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
EXW[15]:
RDN[0]:
Initiate extended write by writing with ‘1’. Sets WIP, clears WDN. Writeonly, always reads back 0.
Write done when ‘1’, clears when EXR set to ‘1’.
WIP[8]:
Write in progress when ‘1’ .
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x0A:0x0B (ERA) – Extended Read Address
Address
0x0A
0x0B
Bit
15
14
13
12
11
10
9
8
Name
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
R/W
R/W
R/W
READ_ADDR
R/W
R/W
R/W
R/W
R/W
READ_ADDR[7:0]:
Address to be used for an extended read. Address ranges:
0x00 - 0x1F: EEPROM (requires ≈2 µs)
0x40 - 0x5F: Shadow
Address 0x0C:0x0D (ERCS) – Extended Read Control and Status
Address
0x0C
0x0D
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
EXR
0
0
0
0
0
0
RIP
0
0
0
0
0
0
0
RDN
R/W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
EXR[15]:
RDN[0]:
Initiate extended read by writing with ‘1’. Sets RIP, clears RDN. Writeonly, always reads back 0.
Read done when ‘1’, clears when EXR set to ‘1’.
RIP[8]:
Read in progress when ‘1’ .
Address 0x0E:0x0F (ERDH) – Extended Read Data High
Address
Bit
0x0E
0x0F
15
14
13
12
11
10
9
R
R
R
R
R
R
R
Name
R/W
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
READ_DATA_HI
R
R
READ_DATA_HI[15:0]:
Upper 16 bits of data from extended read operation, valid when ERCS.
RDN set to ‘1’ .
Address 0x10:0x11 (ERDL) – Extended Read Data Low
Address
Bit
0x10
15
14
13
12
0x11
11
10
9
Name
R/W
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
READ_DATA_LO
R
R
R
R
R
R
R
R
R
READ_DATA_LO[15:0]:
Lower 16 bits of data from extended read operation, valid when ERCS.
RDN set to ‘1’.
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x1E:0x1F (CTRL) – Device Control
Address
Bit
0x1E
15
14
R/W
R/W
Name
R/W
13
11
10
9
8
0
CLS
CLW
CLE
R/W
R
R/W
W
W
SPECIAL
R/W
0x1F
12
7
6
5
W
W
W
4
3
2
1
0
W
W
W
INITIATE_SPECIAL
W
W
SPECIAL[15:12]:
CLW[9]:
Defines specific actions to be taken by the IC. Many actions will only
be invoked after the CTRL.INITIATE_SPECIAL field is written with the
correct value. Aside from EEPROM margining, this field will return 0x00 on
completion.
Clear warning (WARN) register when set to “1”.
Clears bits that were previously read from the WARN (register 0x26:0x27).
Write-only, always returns 0.
Value
Description
0000
No action.
0001
Enable EEPROM low voltage margin. IC must be unlocked.
Initiate with 0xA5.
0010
Enable EEPROM high voltage margin. IC must be
unlocked. Initiate with 0xA5.
0100
Turns counter reset. Initiate with 0x46.
0101
Reload EEPROM. Requires IC to be unlocked. Initiate with
0xA5.
0110
CLE[8]:
Clear error (ERR) register when set to “1”.
Clears bits that were previously read from the ERR (register 0x24:25).
Write-only, always returns 0.
INITIATE_SPECIAL[7:0]:
Write after setting certain CTRL.SPECIAL bits to initiate the selected
action(s).
Always returns 0’s.
Value
Description
No action.
0xB9
Initiate self-tests.
0111
Hard reset. Requires unlock of part. Initiate with 0xA5.
0x46
Initiate turns counter reset.
1001
Run CVH self-test. Initiate with 0xB9.
0x5A
Initiate hard reset.
1010
Run Logic BIST. Initiate with 0xB9.
1011
Run both CVH self-test and Logic BIST. Tests are run in
parallel. Initiate with 0xB9.
CLS[10]:
Clear Status register bits “SDN” and “BDN”, when set to “1”.
STA.SDN indicates that a “special access” task (i.e. CVH self-test) is
completed.
STA.BDN indicates the IC has booted properly and completed any start-up
self-tests.
Allegro MicroSystems
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51
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x20:0x21 (ANG) – Current Angle Reading (12 bits)
Address
Bit
0x20
15
14
13
12
Name
0
EF
UV
P
R/W
R
R
R
R
0x21
11
10
9
8
7
6
R
R
R
R
R
R
5
4
3
2
1
0
R
R
R
R
R
R
ANGLE
EF[14]:
P[12]:
Error Flag. Will be “1” if any unmasked bit in ERR or WARN is set.
Parity bit. Odd parity is calculated across all bits (EF, UV, ANGLE). Result
is that there should always be an odd number of 1’s in this 16 bit word.
Value
Description
0
No unmasked errors
ANGLE[11:0]:
1
Unmasked error is present
Angle from PLL after processing.
Angle in degrees is 12-bit value × (360/4096).
UV[13]:
Undervoltage Flag (real time). Logical OR of analog and digital UV flags
(UVD and UVA flags). Conditions are realtime, but may be masked by
EEPROM error mask bits.
Value
Description
0
No undervoltage condition detected
1
Undervoltage condition detected
Allegro MicroSystems
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52
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x22:0x23 (STA) – Device Status
Address
0x22
0x23
Bit
15
14
13
12
11
10
Name
1
0
0
0
0
0
R/W
R
R
R
R
R
R
9
8
DIE_ID
R
7
6
5
4
3
2
1
0
ROT
0
SDN
BDN
LBR
CSTR
BIP
AOK
R
R
R
R
R
R
R
R
R
RIDC[15:12]:
LBR[3]:
Register ID bits. Used to distinguish this registers from other serial
registers. Hard-coded value.
Logic BIST (LBIST) running.
Value
Description
1000
Register ID value
DIE_ID[9:8]:
DIE ID, loaded from EEPROM (for multi-die packages). Used for
identification purposes only. No impact on sensor functionality.
Set in factory by Allegro.
ROT[7]:
Indicates observed rotation direction, based on the hysteresis logic. Valid
only if Hysteresis is enabled (see EEPROM 0x1C).
Value
Description
Value
Description
0
LBIST not running
1
LBIST running
CSTR[2]:
CVH Self-test running.
Value
Description
0
CVH self-test not running
1
CVH self-test running
BIP[1]:
Boot in progress. Output values may not be valid.
0
Increasing angles
Value
1
Decreasing angles
0
Boot not in progress
1
Sensor is undergoing its boot sequence
SDN[5]:
Special access (from CTRL register) done. Clears to 0 when a “special
command” is triggered, set 1 when complete. Can clear with CTRL.CLS
bit = 1.
Value
Description
0
“Special” command in progress, unless cleared previously
1
“Special” command completed
Description
AOK[0]:
Angle output is OK. Indicates the PLL is locked and stat-up sequence has
completed.
Value
Description
0
Angle is not valid
1
PLL is locked, angle value is valid
BDN[4]:
Boot complete. EEPROM loaded and any startup self-tests are complete.
Can clear with CTRL.CLS bit = 1.
Value
Description
0
Boot not complete, unless cleared previously.
1
Boot complete
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x24:0x25 (ERR) – Device Error Flags
This is the error register. All errors are latched, meaning they will remain high after they occurred. Errors need to be read and then cleared in order to
remove them. It is important that the user clears errors so that subsequent errors become visible. This is especially important for the “RST” error flag
(reset), which is always enabled after power on. Not removing it means that an unexpected reset cannot be discovered afterwards.
Address
0x24
Bit
15
14
13
0x25
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
1
0
1
0
WAR
STF
AVG
ABI
PLK
ZIE
EUE
OFE
UVD
UVA
MSL
RST
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RIDC[15:12]:
PLK[7]:
Register ID bits. Used to distinguish this registers from other serial
registers. Hard-coded value.
PLL lost lock. This indicates the PLL is not tracking the incoming angle
properly. Angle value is corrupt.
Value
Description
1010
Register ID value
WAR[11]:
Warning. An unmasked bit within the WARN register is asserted.
May be masked by setting MSK.WAR bit in EEPROM.
Value
Description
0
No unmasked flag set in the WARN register (0x26:27)
1
Unmasked flag set in the WARN register
STF[10]:
Self-test failure. Indicates either LBIST or CVH self-test failed.
Value
Description
0
No self-test failure
1
Self-test failure
Angle averaging error. Indicates the ORATE value is too high for the
rotation velocity, and the averaged angle value is corrupted.
The ORATE setting allows multiple angle values to be averaged together,
for improved precision. This reduces the response time of the sensor, and
can result in corrupted angle values is the velocity is too high.
Description
0
No Averaging error
1
Averaging error
ABI[8]:
ABI integrity fault. The quadrature integrity of the ABI could not be
maintained.
Value
Description
0
No ABI integrity fault
1
ABI integrity fault
Description
0
No PLL lock.
1
PLL lost lock. Angle value invalid.
ZIE[6]:
Zero crossing integrity error—a zero crossing did not occur within the
maximum time expected, likely indicating missing magnet, or extreme
rotation.
Value
Description
0
No Zero crossing error
1
Zero crossing error
EUE[5]:
EEPROM uncorrectable error. A multi-bit EEPROM read occurred.
EEPROM bit errors are only checked on EEPROM load (i.e. power-up or
reset).
Value
AVG[9]:
Value
Value
Description
0
No multi-bit EEPROM error
1
Multi-bit EEPROM error
OFE[4]:
Oscillator Frequency Error. One of the oscillator watchdogs circuits,
monitoring the high frequency and low frequency oscillators has tripped.
Value
Description
0
No oscillator error
1
Oscillator watchdog error
UVD[3]:
VCC Undervoltage detector tripped. Will continue to set until fault goes
away (and ERR register is cleared). This is the VCC input pin voltage.
Value
Description
0
No VCC voltage error
1
VCC undervoltage error detected
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54
A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
UVA[2]:
RST[0]:
Undervoltage detector tripped. Will continue to set until fault goes away
(and ERR register is cleared). This is the analog regulator output.
Reset condition. Sets on power-on reset or hard reset. Does not set on
LBIST. Indicates volatile registers have been re-initialized.
Value
Description
Value
Description
0
No voltage error
0
No reset
1
Voltage error on the analog regulator output
1
Device has been reset. Volatile registers are re-initialized.
MSL[1]:
Magnetic sense low fault. Magnetic sense was below the low limit
threshold.
Low limit threshold is set via the COM.MAG_THRES_LO field in
EEPROM.
By default this is set to ≈200 G.
Value
Description
0
No magnetic field low fault
1
Magnetic field lower than threshold
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55
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x26:0x27 (WARN) – Device Warning Flags
This is the warning register. All warnings are latched, meaning they will remain high after they occurred. Warnings need to be read and then cleared in
order to remove them. Warnings indicate either communication type conditions or conditions that may result in a degradation of the angle accuracy, but
are less likely than errors to indicate a corruption of the angle.
Address
0x26
0x27
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
1
0
1
1
IER
CRC
0
SRW
XEE
TR
ESE
SAT
TCW
BSY
MSH
TOV
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RIDC[15:12]:
XEE[7]:
Register ID bits. Used to distinguish this registers from other serial
registers. Hard-coded value.
Extended execute error. A command initiated by an extended write failed.
Write failed due to access error (not unlocked) or EEPROM write failure.
Value
Description
1011
Register ID value
IER[11]:
Interface error. Invalid number of bits in SPI packet, or bit 15 of MOSI
data = ‘1’. Packet was discarded.
Also indicates a Manchester error.
Value
Description
0
No Interface Error
1
Interface Error
CRC[10]:
Incoming SPI CRC error. Packet was discarded.
Incoming CRC is only checked if the PWI.SC bit in EEPROM is set.
Value
Description
0
No incoming SPI CRC error
1
Incoming SPI CRC is bad
SRW[8]:
Slew rate warning. This warning is asserted if the ABI slew rate limiting
is enabled and a condition that requires the limiting to be applied has
occurred.
Purpose of Slew Rate Limiting is to prevent an ABI integrity error.
Value
Description
0
Slew rate limiting is not active.
1
Slew rate limiting is active. ABI output is incrementing at the
designated slew rate.
Value
Description
0
No incoming extended error
1
Extended execute Error
TR[6]:
Temperature out of range. The temperature sensor calculated a
temperature below –60°C or above 180°C. Temperature will saturate at
those limits.
Value
Description
0
Temperature sensor in range
1
Sensed temperature is below -60° or above 180°C
ESE[5]:
EEPROM soft error. A correctable (single-bit) EEPROM read occurred.
EEPROM bit errors are only checked on EEPROM load (power-on or
reset).
Value
Description
0
No single bit EEPROM error
1
EEPROM single bit error detected and corrected
SAT[4]:
Aggregate saturation flag. Shows that any internal signals have saturated,
likely to have been cause by extremely strong or weak fields.
Value
Description
0
No saturation detected within the signal chain.
1
Saturation conditions detected within the signal chain.
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56
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
TCW[3]:
MSH[1]:
Turns counter warning. Over 135° of angle change between turns count
updates. Indicates an unexpectedly large angle step between ZCD angle
readings. Most likely cause is a loss of valid magnetic signal (i.e. magnet
absent). Check measured field strength (register 0x2A).
Magnetic sense high fault. Magnetic sense was above the high limit
threshold.
High limit threshold is set via the COM.MAG_THRES_HI field in
EEPROM.
By default this is set to ≈1200 G.
Value
Description
Value
0
No turns count warning
1
Angle difference between two successive ZCD samples
is > 135°
Description
0
No magnetic field high fault
1
Magnetic field above threshold
BSY[2]:
TOV[0]:
Extended access overflow. An Extended write or Extended read was
initiated before previous was done.
Turns Counter Overflow Error.
The turns counter surpassed its maximum value of +255/-256 full
rotations.
This is equivalent to an Turns register value of ±511/-512 or +2047/-2048,
depending on the resolution (180° or 45°).
Must be cleared with a turns count reset (See special commands in the
CTRL register description, 0x1E).
Value
Description
0
No extended access error
1
extended access error
Value
Description
0
No turns count overflow error
1
Turns count overflow error
Address 0x28:0x29 (TSEN) – Temperature Sensor
Address
0x28
Bit
15
14
13
12
Name
1
1
1
1
R/W
R
R
R
R
0x29
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
TEMPERATURE
R
R
R
R
R
R
R
RIDC[15:12]:
TEMPERATURE[11:0]:
Register ID bits. Used to distinguish this registers from other serial
registers. Hard-coded value.
Current junction temperature from internal temperature sensor relative
to room temperature (signed value, 2’s complement). Value is in 1/8 of a
degree. Temperature °C ≈ (TSEN.TEMPERATURE / 8) + 25.0.
Value
Description
1111
Register ID value
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57
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x2A:0x2B (FIELD) – Field Strength (in gauss)
Address
0x2A
Bit
15
14
13
12
Name
1
1
1
0
R/W
R
R
R
R
0x2B
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
GAUSS
R
R
R
R
R
R
R
RIDC[15:12]:
GAUSS [11:0]:
Register ID bits. Used to distinguish this registers from other serial
registers. Hard-coded value.
Measured field strength in gauss. Updated every 128 µs. Field reading
is used for signal path adjustments internal to the IC, and provided
for convenient comparison of field readings over magnetic air gap. No
guarantee of accuracy is made.
Value
Description
1110
Register ID value
900
In general, the A1333 field reading is ≈11% below actual gauss levels.
Sensed Field Over Field
20
% Error
15
800
10
Sensed Field (G)
700
Error (%)
600
500
400
5
0
-5
-10
300
200
300
Sensed Field % Error Over Field
Measured Field
1:1 Field
400
500
600
700
800
Field Strength in Gauss
900
-15
-20
300
400
500
600
700
800
Field Strength in Gauss
Allegro MicroSystems
955 Perimeter Road
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900
58
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x2C:0x2D (TURNS) – Turns Counter
Address
0x0C
Bit
15
14
13
12
Name
1
1
0
P
R/W
R
R
R
R
0x0D
11
10
9
8
7
6
R
R
R
R
R
R
5
4
3
2
1
0
R
R
R
R
R
R
TURNS
RIDC[15:13]:
Register ID bits. Used to distinguish this registers from other serial
registers. Hard-coded value.
Value
110
Description
Register ID value
P[12]:
Parity bit. Odd parity is calculated across all bits. Result is that there
should always be an odd number of 1’s in this 16-bit word.
TURNS [11:0]:
Signed 2’s complement value. Indicates total number of turns relative to
angle observed on power-up. Turns resolution set via EEPROM to either
180° or 45°.
The A1333 is capable of tracking up to 256 full mechanical rotations,
independent of the resolution selected.
Bit Value
Turns in 180° mode
(Actual mechanical
full rotations)
Turns in 45° mode
(Actual mechanical full
rotations)
0000 0000 0000
0 (0)
0 (0)
0000 0000 0001
+1 (+1/2)
+1 (+1/8)
0001 1111 1111
+511 (255.5)
+511 (+63.875 )
0010 0000 0000
N/A
+512 (+64)
0111 1111 1111
N/A
+2047(+255.875)
1111 1111 1111
-1 (-1/2)
-1 (-1/8th)
1110 0000 0000
-512 (-256)
-512 (-64)
1000 0000 0000
N/A
-2048 (-256)
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x30:0x31 (HANG) – Hysteresis Angle Value (12 bits)
Address
Bit
0x30
15
14
13
12
Name
0
EF
UV
P
R/W
R
R
R
R
0x31
11
10
9
8
7
6
R
R
R
R
R
R
No unmasked errors
Unmasked error is present
1
0
R
R
R
R
R
R
ANGLE_HYS[11:0]:
UV[13]:
Angle from PLL after hysteresis processing.
Angle in degrees is 12-bit value × (360/4096).
Undervoltage Flag (real time). Logical OR of analog and digital UV flags
(UVD and UVA flags). Conditions are realtime, but may be masked by
EEPROM error mask bits.
Value
2
Parity bit. Odd parity is calculated across all bits (EF, UV, ANGLE_HYS).
Result is that there should always be an odd number of 1’s in this 16 bit
word.
Description
1
3
P[12]:
Error Flag. Will be “1” if any unmasked bit in ERR or WARN is set.
0
4
ANGLE_HYS
EF[14]:
Value
5
Description
0
No undervoltage condition detected
1
Undervoltage condition detected
Address 0x32:0x33 (ANG15) – Current Angle Reading (15 bits)
Address
0x32
Bit
15
Name
0
R/W
R
14
13
12
0x33
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
ANGLE_15
R
R
R
ANGLE_15[14:0]:
R
R
R
R
R
.
15-bit compensated angle (not rounded).
Angle in degrees is a 15-bit value × (360/32768)
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60
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x34:0x35 (ZANG) – ZCD Angle
Angle from the ZCD signal path is used for turns counting. This angle is not compensated over temperature and will not exactly match the PLL angle
value.
Address
Bit
0x34
15
14
13
12
Name
0
EF
UV
P
R/W
R
R
R
R
0x35
11
10
9
8
7
6
R
R
R
R
R
R
5
4
3
2
1
0
R
R
R
R
R
ANGLE_ZCD
R
EF[14]:
P[12]:
Error Flag. Will be “1” if any unmasked bit in ERR or WARN is set.
Parity bit. Odd parity is calculated across all bits (EF, UV, ANGLE_ZCD).
Result is that there should always be an odd number of 1’s in this 16 bit
word.
Value
Description
0
No unmasked errors
1
Unmasked error is present
ANGLE_ZCD[11:0]:
Angle from the ZCD signal path. Not compensated.
Angle in degrees is 12-bit value × (360/4096).
UV[13]:
Undervoltage Flag (real time). Logical OR of analog and digital UV flags
(UVD and UVA flags). Conditions are realtime, but may be masked by
EEPROM error mask bits.
Value
Description
0
No undervoltage condition detected
1
Undervoltage condition detected
Address 0x3C:0x3D (KEY) – Key Register
Address
Bit
0x3C
15
14
13
12
W
W
W
W
Name
R/W
0x3D
11
10
9
8
7
0
0
0
0
0
W
W
W
R
R
R
R
R
KEYCODE
W
6
5
4
KEYCODE[15:8]:
CUL[0]:
Unlock code is entered here. Once unlocked EEPROM and Shadow
registers may be written. In addition some “special” commands require a
device unlock.
Unlocking requires five successive writes to the KEYCODE field, following
the unlock sequence shown below.
The CUL indicates a successful unlock.
Indicates the device is unlocked.
Write #
Code
1
0x00
2
0x27
3
0x81
4
0x1F
5
0x77
Value
3
2
1
0
0
0
CUL
R
R
R
Description
0
Device is not unlocked
1
Device is unlocked
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61
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
EEPROM/SHADOW MEMORY TABLE
The EEPROM/Shadow register bitmap is shown below.
All EEPROM and shadow contents can be read by the user, without unlocking. Writing requires device unlock.
Table 14: EEPROM / Shadow Memory Map
Shadow
EEPROM
Register
Memory
Address
Name
31:26
Address
0x18
0x58
Bits
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWE
ECC
–
–
–
–
–
–
–
–
–
–
–
–
–
TOV
TR
MSH
SAT
ESE
MSL
UV
AVG
ZIE
PLK
STF
EUE
OFE
INV
-X-
-X-
AHE
–
–
INDEX_MODE WDH
PLH
IOE
UVW
-X-
SRW
ESE
SAT
TCW
BSY
MSH
TOV
WAR
STF
AVG
ABI
PLK
ZIE
EUE
OFE
UVD
UVA
MSL
RST
–
PHE
PEO
PES
–
–
–
–
–
–
–
–
DM
–
S17
SC
–
–
–
–
0x19
0x59
ABI
ECC
–
–
–
–
0x1A
0x5A
MSK
ECC
–
–
IER
CRC
ABI_SLEW_TIME
0x1B
0x5B
PWI
ECC
–
–
PEN
0x1C
0x5C
ANG
ECC
–
–
0x1D
0x5D
LPC
ECC
–
–
0x1E
0x5E
COM
ECC
–
–
0x1F
–
CUS
ECC
–
–
XEE
PWM_BAND
PWM_FREQ
ORATE
T45
–
TR
RD
–
–
LOCK
RO
HYSTERESIS
RESOLUTION_PAIRS
ZERO_OFFSET
–
–
–
–
–
–
–
–
LBE
CSE
–
–
–
–
DST
DHR
–
–
–
–
–
–
–
–
MAG_THRES_HI
MAG_THRES_LO
Customer EEPROM Space
Address 0x18 (PWE) – PWM Error Enable
This address space contains the PWM error enable bits. When set to
“1”, the PWM output will respond to errors, as set via the PWI.PEO and
PWI.PES bits.
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
–
–
–
–
–
–
–
–
–
–
–
TOV
TR
MSH
SAT
ESE
MSL
UV
AVG
ZIE
PLK
STF
EUE
OFE
Default
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
TOV[12]:
MSH[10]:
PWM turns counter overflow error enable.
Duty cycle 72.5%, if PWI.PEO and PWI.PES are “1”.
PWM magnetic sense high error enable.
Duty cycle 61.25%, if PWI.PEO and PWI.PES are “1”.
Value
Description
Value
Description
0
PWM does not respond to a TOV error
0
PWM does not respond to a MSH error
1
PWM output respond to a TOV error
1
PWM output respond to a MSH error
TR[11]:
SAT[9]:
PWM Temperature out of range error enable.
Duty cycle 66.875%, if PWI.PEO and PWI.PES are “1”.
PWM saturation error enable.
Duty cycle 55.625%, if PWI.PEO and PWI.PES are “1”.
Value
Description
Value
Description
0
PWM does not respond to a TR error
0
PWM does not respond to a SAT error
1
PWM output respond to a TR error
1
PWM output respond to a SAT error
Allegro MicroSystems
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62
A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
ESE[8]:
PLK[3]:
PWM EEPROM soft error enable.
Duty cycle 50%, if PWI.PEO and PWI.PES are “1”.
PWM PLL lost lock error enable.
Duty cycle 21.875%, if PWI.PEO and PWI.PES are “1”.
Value
Description
Value
Description
0
PWM does not respond to a ESE error
0
PWM does not respond to a PLK error
1
PWM output respond to a ESE error
1
PWM output respond to a PLK error
MSL[7]:
STF[2]:
PWM magnetic sense low error enable.
Duty cycle 44.375%, if PWI.PEO and PWI.PES are “1”.
PWM Self test error enable.
Duty cycle 16.25%, if PWI.PEO and PWI.PES are “1”.
Value
Description
Value
Description
0
PWM does not respond to a MSL error
0
PWM does not respond to a STF error
1
PWM output respond to a MSL error
1
PWM output respond to a STF error
UV[6]:
EUE[1]:
PWM undervoltage error enable.
Duty cycle 38.75%, if PWI.PEO and PWI.PES are “1”.
PWM EEPROM uncorrectable error enable.
Duty cycle 10.625%, if PWI.PEO and PWI.PES are “1”.
Value
Description
Value
Description
0
PWM does not respond to an UV error
0
PWM does not respond to a EUE error
1
PWM output respond to a UV error
1
PWM output respond to a EUE error
AVG[5]:
OFE[0]:
PWM averaging error enable.
Duty cycle 33.125%, if PWI.PEO and PWI.PES are “1”.
PWM Oscillator frequency error enable.
Duty cycle 5%, if PWI.PEO and PWI.PES are “1”.
Value
Description
Value
Description
0
PWM does not respond to a AVG error
0
PWM does not respond to a OFE error
1
PWM output respond to a AVG error
1
PWM output respond to a OFE error
ZIE[4]:
PWM zero crossing error enable.
Duty cycle 27.5%, if PWI.PEO and PWI.PES are “1”.
Value
Description
0
PWM does not respond to a ZIE error
1
PWM output respond to a ZIE error
Allegro MicroSystems
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63
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
Address 0x19(ABI) – ABI Control
Bit
23
22
Name
–
–
Default
–
–
21
20
19
18
17
16
ABI_SLEW_TIME
0
0
1
0
0
15
14
13
12
11
10
INV
-X-
-X-
AHE
–
–
0
–
–
1
0
0
0
9
8
INDEX_MODE
0
7
6
5
4
WDH
PLH
IOE
UVW
0
0
1
0
0
3
0
ABI_SLEW_TIME[21:16]:
INDEX_MODE[9:8]:
ABI slew time rate. “0” disables slew limiting.
Minimum edged-to-edge time for ABI output is defined by:
Defines the width and placement of the “I” pulse in ABI.
Value
(N + 1) × 125 ns
where “N” is the value of ABI_SLEW_TIME.
This limits the maximum ABI velocity. Reducing the ABI resolution can be
used to counteract this.
Value
Description
00 0000
Slew limiting disable
00 0001
250 ns of slew control
…
11 1111
1
0
0
“I” pulse is set only at 0° to +R
1
“I” pulse set between –R to +R
2
“I” pulse set between –R to +2R
3
“I” pulse set between -2R and +2R
A
B
8 µs of slew control
Mode 0
Mode 1
Value
Mode 2
Description
Mode 3
ABI/UVW signals behave as shown below for an increasing
angle value. Q1 through Q4 represent changes in angle at
the ABI resolution.
State Name
A
B
Q1
0
0
Q2
0
1
Q3
1
1
Q4
1
0
ABI/UVW signals are inverted and behave as shown below
for an increasing angle value. Q1 through Q4 represent
changes in angle at the ABI resolution.
A=-2R
Q3
A=-R
Q4
A=0
Q1
A=+R
Q2
True Zero to 360 Discontinuity
WDH[7]:
Enable ABI all high (before inversion) as error mode if oscillator frequency
watchdog error trips.
Value
Description
0
ABI pins do not respond to an OFE Flag
1
ABI outputs go high if an OFE is detected
PLH[6]:
State Name
A
B
Q1
1
1
Q2
1
0
Value
Q3
0
0
0
ABI pins do not respond to an PLK Flag
1
1
ABI outputs go high if the PLK flag is set
Q4
0
Enable ABI all high (before inversion) as error mode if a PLL loss of lock is
detected.
Description
IOE[5]:
AHE[12]:
ABI hysteresis enable. When “1” hysteresis is applied to the ABI or UVW angle.
Value
0
Description
0
…
Invert ABI/UVW signals.
1
1
“R” indicates the ABI quadrature resolution.
INV[15]:
0
2
RESOLUTION_PAIRS
Description
0
Hysteresis is not applied to ABI or UVW
1
Hysteresis applied to ABI or UVW outputs
Incremental output enable.
Value
Description
0
ABI/UVW pins are not active
1
ABI/UVW pins are active. Behavior defined by ABI.UVW bit
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
UVW[4]:
Define behavior of the ABI/UVW pins. If ABI.IOE = 1.
Value
Description
0
ABI active
1
UVW active
RESOLUTION_PAIRS[3:0]:
Defines resolution of ABI/UVW outputs.
In ABI mode, cycle resolution = 2(14-n) where “n” is the
RESOLUTION_PAIRS value.
In UVW mode, the number of pole pairs is n + 1.
Value
AB Cycles per Rev
UVW Pole Pairs
0000
N/A
1
0001
N/A
2
0010
N/A
3
0011
211
= 2048
4
0100
210 = 1024
5
…
…
…
1110
20 = 1
15
1111
N/A
16
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Address 0x1A (MSK) – Mask Bits
This address range contains error mask bits. When set, the applicable
error condition will not assert the “EF” bit in the various angle and turns
count registers.
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
IER
CRC
-X-
SRW
XEE
TR
ESE
SAT
TCW
BSY
MSH
TOV
WAR
STF
AVG
ABI
PLK
ZIE
EUE
OFE
UVD
UVA
MSL
RST
Default
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IER[23]:
Masks the IER flag from setting the “EF” bit.
STF[10]:
Masks the STF flag from setting the “EF” bit.
CRC[22]:
Masks the CRC flag from setting the “EF” bit.
AVG[9]:
Masks the AVG flag from setting the “EF” bit.
SRW[20]:
Masks the SRW flag from setting the “EF” bit.
ABI[8]:
Masks the ABI flag from setting the “EF” bit.
XEE[19]:
Masks the XEE flag from setting the “EF” bit.
PLK[7]:
Masks the PLK flag from setting the “EF” bit.
TR[18]:
Masks the TR flag from setting the “EF” bit.
ZIE[6]:
Masks the ZIE flag from setting the “EF” bit.
ESE[17]:
Masks the ESE flag from setting the “EF” bit.
EUE[5]:
Masks the EUE flag from setting the “EF” bit.
SAT[16]:
Masks the SAT flag from setting the “EF” bit.
OFE[4]:
Masks the OFE flag from setting the “EF” bit.
TCW[15]:
Masks the TCW flag from setting the “EF” bit.
UVD[3]:
Masks the UVD flag from setting the “EF” bit.
BSY[14]:
Masks the BSY flag from setting the “EF” bit.
UVA[2]:
Masks the UVA flag from setting the “EF” bit.
MSH[13]:
Masks the MSH flag from setting the “EF” bit.
MSL[1]:
Masks the MSL flag from setting the “EF” bit.
TOV[12]:
Masks the TOV flag from setting the “EF” bit.
RST[0]:
Masks the RST flag from setting the “EF” bit.
WAR[11]:
Masks the WAR flag from setting the “EF” bit.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Address 0x1B (PWI) – PWM Interface Control
Bit
23
Name
PEN
Default
0
22
21
20
19
0
0
PWM_BAND
1
18
17
16
PWM_FREQ
1
1
1
1
15
14
13
12
11
10
9
8
–
PHE
PEO
0
0
0
7
PES
–
–
–
–
–
0
0
0
0
1
0
6
5
4
3
2
1
0
–
–
–
DM
–
S17
SC
0
0
0
0
0
0
0
PEN[23]:
PWM_BAND[22:20]:
PWM Enable.
PWM frequency band. Defines the PWM carrier frequency when combined
with PWM_FREQ.
Value
Description
0
PWM pin tri-stated
PWM_FREQ[19:16]:
1
PWM enabled
PWM frequency select. Defines the PWM carrier frequency when
combined with PWM_BAND.
Table 15: Nominal PWM Carrier Frequencies
PWM_FREQ
PWM_BAND
0
1
2
3
4
5
6
7
0
3125
2778
2273
1667
1087
641
352
185
1
3101
2740
2222
1613
1042
610
333
175
2
3077
2703
2174
1563
1000
581
316
166
3
3053
2667
2128
1515
962
556
301
157
4
3030
2632
2083
1471
926
532
287
150
5
3008
2597
2041
1429
893
510
275
143
6
2985
2564
2000
1389
862
490
263
137
7
2963
2532
1961
1351
833
472
253
131
8
2941
2500
1923
1316
806
455
243
126
9
2920
2469
1887
1282
781
439
234
121
10
2899
2439
1852
1250
758
424
225
116
11
2878
2410
1818
1220
735
410
217
112
12
2857
2381
1786
1190
714
397
210
108
13
2837
2353
1754
1163
694
385
203
105
14
2817
2326
1724
1136
676
373
197
101
15
2797
2299
1695
1111
658
362
191
98
PHE[14]:
PES[12]:
PWM Hysteresis enable.
PWM Error Select, if PEO = 1.
Value
Description
0
No hysteresis applied to PWM output
1
Hysteresis settings applied to PWM output
PEO[13]:
Value
Description
0
PWM output tri-states for all enabled error conditions (See
PWE address space).
1
For all enabled errors the PWM carrier frequency is halved
and the highest priority error is identified by a specific duty
cycle. See the PWE address space description.
PWM Error Output Enable. If “1” PWM will respond to errors, as defined
by the PES bit.
Value
Description
0
PWM output does not respond to error flags
1
PWM output will respond to errors, as defined by the PWI.
PES field.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
DM[3]:
SC[0]:
Disable Manchester Interface.
A1333 monitors the incoming CRC.
Value
Description
Value
Description
0
Manchester functions normally
0
No monitoring of the incoming CRC
1
A1333 will no longer respond to Manchester command on
the VCC line
1
A1333 monitors incoming CRC. Discards packet if corrupt.
S17[1]:
A1333 ignores the 17th SPI clock. Allows negative edge sampling at the
MCU (host).
Address 0x1C (ANG)
Bit
23
22
Name
21
20
ORATE
Default
0
0
0
0
19
18
RD
RO
0
0
17
16
15
14
13
12
11
10
9
8
7
6
HYSTERESIS
1
0
1
5
4
3
2
1
0
0
0
0
0
0
ZERO_OFFSET
0
0
0
0
0
0
0
0
0
0
ORATE[23:20]:
RD[19]:
Reduces the output rate by averaging samples. 2ORATE samples will
be averaged. ORATE values above 12 are reduced to 12 in the logic,
meaning that up to 4096 samples = 4 ms can be selected as averaging
time.
Rotates die. Rotates final angle 180°. Last step in the angle algorithm.
This is a convenient setting to adjust one die in a dual die package for
conformance to the other die. Occurs after the Zero_offset and RO
adjustments.
Value
Description
Value
Description
0000
1 sample. 1 µs update rate.
0
No rotation applied
0001
2 samples. 2 µs update rate.
1
180° added to final angle
0010
4 samples. 4 µs update rate.
…
RO[18]:
…
1100
4096 samples. ≈4 ms update rate.
The majority of angle noise is composed of low-frequency content. Due to
this, noticeable improvements in IC resolution are not observed until relativity high values of ORATE (8 or above, corresponding to 256 samples).
Because of this, non-zero ORATE settings are not recommended, except
in cases where sensor response time is not a major concern (i.e. low rpm
applications).
3 Sigma Noise vs. Orate Settings
TA = 25°C
0.5
Value
0
Output angle increases with a clockwise rotation (when
viewed from above the magnet and device)
1
Output angle increases with a counter-clockwise rotation
(when viewed from above the magnet and device)
Angle Hysteresis threshold. In 14bit resolution. Provides ≈0 to 1.384° of
hysteresis.
0.4
Value
0.35
0.3
0.25
0.2
No Hysteresis
00 0001
≈0.022° of Hysteresis
…
0.1
11 1111
0.05
0
2
4
6
ORATE Level
8
10
12
Description
00 0000
0.15
0
Description
HYSTERESIS[17:12]:
300 G
600 G
0.45
Noise in Degrees
Rotation Direction. If set to 0, increasing angle movement is in the
clockwise direction when looking down on the top of the die. If set to 1,
increasing angle movement is in the counter-clockwise direction.
Occurs after the Zero_offset adjust and prior to the RD manipulation.
…
≈1.384° of Hysteresis
ZERO_OFFSET[11:0]:
Post-compensation zero offset (or DC adjust), at 12-bit resolution.
This value is subtracted from the measured angle value.
Operation occurs prior to the RD and RO manipulations.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Address 0x1D (LPC)
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
T45
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Default
1
–
0
0
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
1
1
1
1
1
T45[23]:
Defines the resolution of the turns counter.
Value
Description
0
Turns counter measures 180° of rotation
1
Turns counter measures 45° of rotation
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Address 0x1E (COM)
Bit
23
22
Name
21
20
LOCK
Default
0
0
0
0
19
18
17
16
15
14
13
12
LBE
CSE
–
–
–
–
DST
DHR
1
1
–
–
–
–
0
0
11
10
9
8
7
6
5
1
0
0
1
0
1
0
DHR[12]:
EEPROM and Shadow memory lock.
Permanent lock.
Disable Hard reset from the serial register.
Value
Description
1100
Writing to EEPROM is locked
0011
Writing to EEPROM and Shadow memory is locked
3
2
1
0
0
1
MAG_THRES_LO
LOCK[23:20]:
Value
4
MAG_THRES_HI
0
1
1
Description
0
A Hard reset may be initiated via a “special” serial register
command.
1
Prevents initiating a Hard reset from the CTRL register.
LBE[19]:
MAG_THRES_HI[11:6]:
Power-up Logic BIST enable.
LBIST requires ≈30 ms to run.
Magnetic threshold high value. Determine set-point of the MSH flag. When
set to 0, check is disabled.
Limit increases in 32 G increments. Set to 1184 G at factory.
Value
Description
0
LBIST isn’t run on power-up
1
LBIST is run on power-up
Value
LBIST and CVH self-test are run in parallel. Therefore if both are enabled
on power-up, power-on time is ≈30 ms.
Description
00 0000
High field flag disabled
00 0001
32 G
00 0010
64 G
…
CSE[18]:
…
10 0101
Power-up CVH self-test enable.
CVH self-test requires ≈30 ms to run.
Value
…
…
11 1111
Description
1184 G
2016 G
0
CVH is not run on power-up
MAG_THRES_LO[5:0]:
1
CVH is run on power-up
Magnetic threshold low value. Determine set-point of the MSL flag. When
set to 0, check is disabled.
Limit increased in 16 G increments. Set to 208 G at factory.
LBIST and CVH self-test are run in parallel. Therefore, if both are enabled
on power-up, power-on time is ≈30 ms.
Value
DST[13]:
Disable Self-test initiation from the serial register.
Value
Description
0
Self-tests may be initiated via a “special” serial register
command.
1
Prevents running either LBIST or CVH self-test from the
CTRL register.
Description
00 0000
Low field flag disabled
00 0001
16 G
00 0010
32 G
…
…
00 1101
…
208 G
…
11 1111
1008 G
Address 0x1F (CUST)
Bit
23
22
21
20
19
18
17
16
15
14
13
0
0
0
0
0
0
0
0
0
0
0
Name
Default
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
Customer EEPROM Space
0
0
0
CUSTOMER[23:0]:
Customer EEPROM space.
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A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
SAFETY AND DIAGNOSTICS
The A1333 was developed in accordance with the ASIL design
flow (ISO 26262) and incorporates several internal diagnostics as
well as error/warning/status flags enabling the host microntroller
to assess the operational status of the die.
sured angle is monitored to determine a passing or failing device.
A short summary of the A1333 diagnostics is provided below. A
complete listing and discussion of the A1333 safety features may
be found in the “A1333 Safety Manual”, which is available upon
request.
LOGIC BUILT-IN SELF-TEST (LBIST)
Built-In Self-Tests
The A1333 features two built-in-self-tests (BISTS) which may
be configured to run at power-up and may also be initiated at any
time by the system microcontroller via a serial register write. A
failure of any one of the self-tests will assert the Self-Test Failure
Flag, STF, within the Error register.
CVH self-test typically takes 30 ms to run (when run in parallel
with LBIST, entire test time is 30 ms).
Logic BIST is implemented to verify the integrity of the A1333
logic. It can be executed in parallel with the CVH self-test.
LBIST is effectively a form of auto-driven scan. The logic to be
tested is broken into 31 scan chains. The chains are fed in parallel by a 31-bit linear feedback shift register (LFSR) to generate
pseudo-random data. The output of the scan chains are fed back
into a multiple input shift register (MISR) that accumulates the
shifted bits into a 31-bit signature.
LBIST takes ≈30 ms to complete (when run in parallel with CHV
self-test, the entire test time is ≈30 ms).
CVH SELF-TEST
Status, Error, and Warning Flags
CVH self-test is a method of verifying the operation of the CVH
transducer without applying an external magnetic field. This
feature is useful for both manufacturing test and for integration
debug. The CVH self-test is implemented by changing the switch
configuration from the normal operating mode into a test configuration, allowing a test current to drive the CVH in place of the
magnetic field. By changing the direction of the test current and
by changing the elements in the CVH that are driven, the self-test
circuit emulates a changing angle of magnetic field. The mea-
The A1333 features many flags used to detect faulty external or
internal conditions. Table 16 briefly describes a selection.
All flags may be read through the serial registers via SPI or
Manchester communication. All unmasked error flags will assert
the “General Error” flag which is included in the angle register
(0x20), providing a “snapshot” of the sensor’s status.
Error reporting when using PWM or ABI is more limited and
discussed later on.
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A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
Table 16: Status and Error Flags
Fault Condition
Description
Sensor Response
VCC < VUVD
Indicates VCC is below expected level.
UVD flag set in ERR register
UV flag set in ANG register
EF flag set in ANG register
Field > High Threshold
Sensor monitors field level in case of mechanical failure.
High Level is programmable from 0-2016 G in 32 G steps.
By default set to ≈1184 G.
MSH flag set in WARN register
EF flag set in ANG register
Field < Low Threshold
Sensor monitors field level in case of mechanical failure.
Low Level is programmable from 0-1008 G in 16 G steps.
By default set to ≈208 G.
MSL flag set in ERR register
EF flag set in ANG register
TA < –60°C or TA > 180°C
Ambient temperature beyond maximum detectable value.
TR flag set in WARN register
EF flag set in ANG register
Oscillator Frequency Discrepancy
The A1333 cross-checks the high and low frequency oscillators
for proper functionality.
OFE flag set in ERR register
EF flag set in ANG register
Single Bit EEPROM Error (correctable)
Detects and corrects single bit EEPROM errors.
ESE bit set in WARN register
EF flag set in ANG register
Multi-Bit EEPROM failure (uncorrectable)
Detects multi-bit EEPROM errors.
EUE bit set in ERR register
EF flag set in ANG register
Signal Path Failure
Multiple comparisons and checks within the signal path:
• Main signal path output compared to the ZCD signal path
• PLL lock status monitored
• Main signal path is checked for saturation
PLK or ZIE set within the ERR register
EF flag set within the ANG register
Loss of VCC
Determines if system power was lost. Indicates all volatile
registers have been reset (such as turns count).
RST bit set in ERR register
EF flag set in ANG register
ABI Integrity Fault
Excessive noise or excessive rotational velocity for a given ABI
resolution. IC monitors state of ABI and flags skipped states.
ABI bit set in ERR register
EF flag set in ANG register
Analog regulator drift
IC monitors output of analog regulator, ensuring transducer is
supplied with proper voltage.
UVA bit set in ERR register
UV flag set in ANG register
EF flag set in ANG register
Excessive magnet travel
Sensor detects when > 256 rotations have occurred, indicating
the turns counter has saturated.
TOV bit set in WARN register
EF flag set in ANG register
Excessive magnet velocity for turns
counting
If the sensor detects > 135° travel between successive turns
count updates.
TCW bit set in WARN register
EF flag set in ANG register
Excessive magnet velocity for a given
ORATE setting
Indicates the angle reading spanned more than 2 quadrants
during the ORATE sample period, therefore the average may be
incorrect. Can occur under extreme velocity and high averaging,
or with no magnetic field and the samples out of the CVH are
random.
AVG bit set in ERR register
EF flag set in the ANG register
Incoming SPI Packet Corruption
IER error detects an invalid number of SCLKs, or a ‘1’ in the
MSB on MOSI.
If using 20-bit SPI packets and incoming CRC validation is
enabled (SC bit in EEPROM 0x1B), the CRC flag will assert.
Depending on implementation and
amount of corruption:
IER bit set in WARN register
CRC bit set in WARN register
EF flag set in ANG register
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Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
ERROR REPORTING IN PWM
The PWM output can be configured to change state if certain
errors occur. There are three options:
• No error reporting
Table 18: PWM Error Select (PES)
Code
0
PWM tristates on an error.
1
PWM carrier frequency halved and highest
priority error output on PWM as selected duty
cycle.
• Tristate the PWM
• Halve the carrier frequency and represent the error via
different duty cycles
Two EEPROM bits, “PEO” and “PES” control how errors are
reported in PWM mode, both of which are in the PWS address
row of EEPROM:
Table 17: PWM Error Output Enable Option (PEO)
Code
Description
The error priority and corresponding duty cycle are shown in
Table 19 below, with the high priority error dictating the PWM
duty cycle.
Each error code must be enabled via EEPROM. This prevents
losing the PWM output due to a spurious error.
The enable bits can be found within the PWE (0x18) EEPROM
row.
Description
0
PWM does not respond to errors.
1
PWM output responds to errors as selected with
the PES field.
Table 19: PWM Error Duty Cycle and Priority
Error
Priority
Duty Cycle %
Description / Persistence
OFE
1 (highest)
5
EUE
2
10.625
Watchdog error. Permanent.
EEPROM uncorrectable error. Permanent.
STF
3
16.25
Self-test failure. Permanent.
PLK
4
21.875
PLL not locked. Persists until PLL locks.
ZIE
5
27.5
AVG
6
33.125
Zero-crossing integrity error. Persists until goes away.
Angle averaging error. Outputs once then clears.
UV
7
38.75
Undervoltage (UVA and/or UVCC dependent on serial error masks).
Persists until no unmasked undervoltage.
MSL
8
44.375
Persists until field strength higher than low threshold.
EEPROM correctable error. Outputs once then clears.
ESE
9
50
SAT
10
55.625
Persists until no saturation warnings.
MSH
11
61.25
Persists until field strength lower than high threshold.
TR
12
66.875
Persists until temperature within range.
TOV
13 (lowest)
72.5
Turns counter overflow. Persists until cleared via CTRL register.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
ERROR REPORTING IN ABI/UVW
Error reporting when using ABI/UVW requires the transmission of angle information to be interrupted. As a result, only the
two most severe errors are allowed to interrupt the pulse stream,
preventing potential spurious errors from interrupting the primary
mission of the IC.
As further insurance against undesired ABI/UVW interruption,
error reporting must be individually enabled in EEPROM. The
error conditions which may be reported are:
• Oscillator Frequency Error
• PLL Loss of Lock Error
When enabled, and an error occurs, all three ABI lines will be
brought high (prior to inversion, if enabled). This is an undefined
state in both ABI (if using default I mode width) and UVW.
Error reporting is enabled via the following two EEPROM bits,
housed within address row 0x19.
WDH[7]:
Enable ABI all high (before inversion) as error mode if oscillator frequency watchdog error trips.
Value
Description
0
ABI pins do not respond to an OFE Flag
1
ABI outputs go high if an OFE is detected
PLH[6]:
Enable ABI all high (before inversion) as error mode if a PLL
loss of lock is detected.
Value
Description
0
ABI pins do not respond to an PLK Flag
1
ABI outputs go high if the PLK flag is set
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A1333
APPLICATION INFORMATION
The A1333 features SPI, PWM, ABI/UVW, and Manchester outputs. Basic reference circuits for connecting the A1333 are shown
below in Figure 56.
A1333 PWM/ABI
A1333 SPI
VCC
VCC
VS
0.1 µF
0.1 µF
RP
VCC
VCC
PWM
BYP
PWM Out
PWM
BYP
0.1 µF
0.1 µF
A1333
A1333
MISO
CS/SA0
MOSI/SA1
SCLK
GND
Optional, enabled/disabled
via EEPROM
A
B
I
Optional, enabled/disabled
via EEPROM
MISO
CS/SA0
MOSI/SA1
SCLK
GND
Host Micro
A
B
I
Optional, enabled/disabled
via EEPROM
Optional I/O Pull-Ups
≈100 kΩ
Typical A1333 configuration using PWM output.
Digital reads/writes requests transmitted via Manchester encoding on the VCC line.
SA0/SA1 brought to BYP or GND to configure Manchester address.
Typical A1333 configuration using SPI interface.
A1333 EMC Circuit
External Protection
For Load Dump
(Battery Only)
VBatt
50 Ω
39 V
Vs
0.1 µF
VCC
125 Ω
PWM Out
PWM
BYP
4.7 kΩ
1.2 nF
0.1 µF
A1333
MISO
CS/SA0
MOSI/SA1
SCLK
GND
Host Micro
A
Optional, enabled/disabled
via EEPROM*
B
I
Optional I/O Pull-Ups
≈100 kΩ
A1333 reference design for stringent EMC requirements.
*If using ABI outputs, a 10 nF capacitor to GND on each line is recommended
(this added capacitance will reduce the edge rates on ABI).
Figure 56: A1333 PWM/ABI, SPI, and EMC Application Circuits
ESD Performance
Table 20: HBM ESD Rating (per AEC-Q100 002)
Table 20 shows the ESD performance of the A1333 device.
Contact Allegro for questions regarding ESD optimization.
[1]
Package
ESD Rating
TSSOP-14
5 kV
eTSSOP-24
3 kV [1]
With GND pins of both die shorted together, IC performs
to a 4 kV level.
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
Setting the Zero-Degree Position
When shipped from the factory, the default angle value when
oriented as shown in Figure 57 is 0° for both die. In some cases,
the end user may want to program an angle offset in the A1333 to
compensate for variations in magnetic assemblies, or for applications where absolute system-level readings are required.
The internal algorithm for computing the output angle is as follows:
Angleout = AngleRAW – ZERO_OFFSET
where ZERO_OFFSET is a 12-bit field in EEPROM.
beyond this range will not result in long term damage). Due to
the greater signal-to-noise ratio provided at higher field strengths,
performance inherently increases with increasing field strength.
Typical angle performance over applied field strength is shown in
Figure 59 and Figure 60.
Table 21: Target Magnet Parameters
Magnetic Material
Diameter
(mm)
Thickness
(mm)
Neodymium (sintered)*
10
2.5
Neodymium (sintered)
8
3
Neodymium / SmCo
6
2.5
To “zero out” the A1333 reported angle, during final application
calibration, position the magnet above the A1333 in the desired
zero-degree position and read the reported angle. This angle
becomes the necessary ZERO_OFFSET value to “zero-out” the
angle.
In some cases, it may be convenient to have a 180° offset
between die. The RD field (bit 19 of EEPROM location 0x19)
allows a 180° offset to be applied. When set, this bit adds 180° to
the output of the die (occurs after ZERO_OFFSET and rotation
adjustments).
Target poles aligned with
A1333 elements
S
N
Thickness
Diameter
* A sintered Neodymium magnet with 10 mm (or greater) diameter
and 2.5 mm thickness is the recommended magnet for redundant
applications.
1600
S
Pin 1
E1
Magnetic Field (G)
1400
N
E2
Figure 57: Orientation of Magnet Relative to
Primary and Secondary Die
Magnetic Target Requirements
The A1333 is designed to operate with magnets constructed with
a variety of magnetic materials, geometries, and field strengths.
See Table 21 for a list of common magnet dimensions.
1200
1000
800
NdFe30
600
SmCo24
400
200
0
Ceramic
(Ferrite)
0.5
2.5
4.5
6.5
8.5
Air Gap (mm)
Figure 58: Magnetic Field versus Air Gap for a magnet 6 mm
in diameter and 2.5 mm thick.
Allegro can provide similar curves for customer application magnets
upon request. Allegro recommends larger magnets for applications
that require optimized accuracy performance.
The A1333 actively measures and adapts to its magnetic environment. This allows operation throughout a large range of
field strengths (recommended range is 300 to 1000 G, operation
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Magnet Misalignment
Magnetic misalignment with the A1333 package impacts the
linearity of the observed magnetic signal and consequently the
resulting accuracy. The influence of mechanical misalignment
may be minimized by reducing the overall airgap and by choos-
ing a larger magnet diameter. Figure 59 shows the influence of
magnet diameter of eccentricity error.
The dual die variant of the A1333 uses a stacked die approach,
resulting in a common eccentricity value for both die. This
eliminates the “native misalignment” present in “side-by-side”
packaging options.
2
6.00 mm Diameter
8.00 mm Diameter
10.00 mm Diameter
1.8
1.6
Angle Error
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
0.5
Misalignment (mm)
1
1.5
Figure 59: Simulated Error versus Eccentricity for different size magnet diameters, at 2.0 mm air gap
Typical Systemic Error versus magnet to sensor eccentricity (daxial), Note: “Systemic Error” refers to application errors in alignment
and system timing. It does not refer to sensor IC device errors. The data in this graph is simulated with ideal magnetization.
Target rotation axis
Target counter clockwise rotation
(decreasing angles, with
default EEPROM settings)
Target clockwise rotation
(Increasing angle, with
default EEPROM settings)
Figure 60: Rotation Direction Definition
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A1333
Precision, High Speed, Hall-Effect Angle Sensor IC
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I/O STRUCTURES
A/U, B/V, I/W, MISO
33 Ω
PWM
33 Ω
SCK/CSN/MOSI
1 kΩ
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PACKAGE OUTLINE DRAWINGS
For Reference Only – Not for Tooling Use
(Reference MO-153 ADT)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
7.80 ±0.10
4.32 NOM
8º
0º
24
0.20
0.09
E1 E
E2
B
3 NOM
E 2.20 ±0.15
4.40 ±0.10 6.40 ±0.20
F F2
F F1
A
0.60 ±0.15 1.00 REF
1
2
E 3.90 ±0.15
0.25 BSC
24X
1.20 MAX
0.10 C
0.30
0.19
0.65 BSC
0.45
SEATING PLANE
C
GAUGE PLANE
SEATING
PLANE
0.15
0.00
XXXXXXXXX
Date Code
Lot Number
0.65
1
D
Standard Branding Reference View
Lines 1, 2, 3: Maximum 9 characters per line
1.65
Line 1: Part number
Line 2: Logo A, 4-digit date code
Line 3: Characters 5, 6, 7, 8 of
Assembly Lot Number
3.00
C
6.10
A
Terminal #1 mark area.
B
Exposed thermal pad (bottom surface); dimensions may vary with device.
C
Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias can improve thermal dissipation
(reference EIA/JEDEC Standard JESD51-5).
4.32
D
Branding scale and appearance at supplier discretion.
PCB Layout Reference View
E
Hall elements (E1, E2), corresponding to respective die; not to scale.
F
Active Area Depth. F1 (die 1): 0.64 ±0.10 mm; F2 (die 2): 0.49 ±0.10 mm.
Figure 61: Package LP, 24-Pin TSSOP with Exposed Thermal Pad
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For Reference Only – Not for Tooling Use
(Reference Allegro DWG-0000381, Rev. 1)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
5.00 ±0.10
8º
0º
D
2.50 ±0.15
14
D
E
0.20
0.09
D1
4.40 ±0.10
D
6.40 BSC
0.60
2.20 ±0.15 D
A
D1
+0.15
–0.10
1.00 REF
1
2
0.25 BSC
Branded Face
D
14×
0.10
E1
0.95
0.85
C
1.10 MAX
0.15
0.00
0.30
0.19
SEATING PLANE
GAUGE PLANE
C
SEATING
PLANE
0.65 BSC
XXXXXXX
Date Code
Lot Number
0.45
0.65
1
14
C
Standard Branding Reference View
Lines 1, 2: Maximum 7 characters per line
Line 3: Maximum 5 characters per line
1.70
Line 1: Part number
Line 2: Logo A, 4-digit date code
Line 3: Characters 5, 6, 7, 8 of
Assembly Lot Number
6.00
1
B
2
PCB Layout Reference View
A
Terminal #1 mark area.
B
Reference land pattern layout (reference IPC7351 TSOP65P640X120-14M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5).
C
Branding scale and appearance at supplier discretion.
D
Hall element (D1); not to scale.
E
Active Area Depth 0.3325 ±0.10 mm.
Figure 62: Package LE, 14-Pin TSSOP
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A1333
APPENDIX A: ANGLE ERROR AND DRIFT DEFINITION
Angle error is the difference between the actual position of the
magnet and the position of the magnet as measured by the angle
sensor IC (without noise). This measurement is done by reading
the angle sensor IC output and comparing it with a high resolution encoder (refer to Figure 63).
Angle Error
E [º]
Angle Drift
Angle drift is the change in the observed angular position over
temperature, relative to 25°C.
During Allegro’s factory trim, drift is measured at 150°C. The
value is calculated using the following formula:
AngleDrift = Angle25°C – Angle150°C
0º
Emax
0º
36
E = α Sensor – α Real
Reference Angle
α Real
where each Angle value is an array corresponding to 16 angular
positions around a circle.
Angle Drift of 150°C in Reference to 25°C
Error 25°C
Error 150°C
No Error
Eminl
Angle Error Definition
Throughout this document, the term “angle error” is used extensively. Thus, it is necessary to introduce a single angle error
definition for a full magnetic rotation. The term “angle error” is
calculated according to the following formula:
Angle Error (Deg)
Figure 63: Angle Error Definition
Ideal
Drift of data point 2
AngleError = max( |Emax| , |Emin| )
In other words, it is the maximum deviation from a perfect
straight line between 0 and 360 degrees. For the purposes of a
generic definition, the offset of the IC angle profile is removed
prior to the error calculation (this can be seen in Figure 63). The
offset itself will depend on the starting IC angle position relative
to the encoder 0° and thus can differ anywhere from 0-360°.
Drift of data point 1
Reference Angle
Figure 64: Angle Drift of 150°C in Reference to 25°C [1]
Note that the data above is simply a representation of angle
drift and not real data.
[1]
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Precision, High Speed, Hall-Effect Angle Sensor IC
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A1333
APPENDIX B: SPI INTERFACE ERROR FLAG DESCRIPTION
IER Flag
The IER flag is located in bit 11 of the WARN serial register
(0x26:0x27). This flag is designed to assert when the IC detects
an improper communication frame, via either SPI or Manchester.
For the purposes of this appendix, only the behavior in regards
to the SPI bus will be discussed. The IER flag will assert on the
following conditions:
• An improper number of SPI clocks are detected
• The MSB of the MOSI packet is a logic ‘1’
Table 22: WARN Serial Register
Address
0x26
0x27
Bit
15
14
13
12
11
Name
1
0
1
1
IER CRC
R/W
R
R
R
R
R
10
R
9
0
R
8
7
SRW XEE
R
R
6
TR
R
5
4
3
2
1
0
ESE SAT TCW BSY MSH TOV
R
R
R
R
R
R
Behavior When Sharing SPI lines
The IER flag may provide an erroneous indication when sharing
the SCLK line among multiple ICs. In the case where an IC is
held inactive by bringing the CS line high, the inactive IC(s) will
continue to count falling SCLK edges. This results in an invalid
number of observed SCLK edges, and the IER flag to assert on
the next SPI transaction of the IC. False IER flag assertions differ
based on the size of the SPI packet.
SIXTEEN AND SEVENTEEN BIT SPI PACKETS
The IER flag will always assert if, during the CS high period, the
SCLK line is brought low as follows:
• At least one time if using a 16-bit SPI packet and the S17 bit is
set to ‘0’ (EEPROM 0x1B, bit 1).
□ Default setting for S17 is ‘0’.
• At least twice if using a 16-bit packet and the S17 bit is a ‘1’.
□ Based on signal timing, there is a possibility that the IER
flag will assert if SCLK is brought low only once with S17
set.
• At least once if using a 17-bit packet and the S17 bit is a ‘1’.
Impact of IER flagging with 16/17 Bit Packets
When an incorrect number of SCLK edges is observed by the IC,
the following occurs:
1. The IER flag will trigger.
2. If the packet preceding the CS high time is a read:
A. If SCLK drops low within 70 ns of the CS rising edge,
there is a possibility the read will be discarded. If this
occurs, the output will correspond to the last valid read
request for that device.
B. If the SCLK edge occurs after 70 ns of the CS rising
edge, the read is not discarded, potentially corrupting the
next immediate response from the device.
3. If the packet preceding the CS high time is a write:
A. If SCLK drops low within 70 ns of the CS rising edge,
there is a possibility the write will be discarded.
B. If the SCLK edge occurs after 70 ns of the CS rising
edge, the write will occur, but the IER flag will still assert.
TWENTY BIT SPI PACKETS
When using 20-bit SPI packets, the IER flag may occur when the
SCLK line is brought low while CS is high. The probability of a
false IER flag asserting is timing dependent and will differ from
device to device, but should not occur on more than 3.2% of all
SPI transactions. Lab characterization has shown significantly
lower assertion rates, with false flags on 0.00% to 0.80% of all
SPI transactions.
Impact of IER flagging with a 20-Bit Packet
When using a 20-bit SPI packet, the following will occur if an
incorrect number of SCLK edges is observed:
1. The IER flag will trigger.
2. If the packet preceding the CS high time is a read:
A. If SCLK drops low within 70 ns of the CS rising edge,
there is a possibility the read will be discarded. If this
occurs, the output will correspond to the last valid read
request for that device.
B. If the SCLK edge occurs after 70 ns of the CS rising
edge, the read will take place as expected.
3. If the packet preceding the CS high time is a write:
A. If SCLK drops low within 70 ns of the CS rising edge,
there is a possibility the write will be discarded.
B. If the SCLK edge occurs after 70 ns of the CS rising
edge, the write will occur, but the IER flag will still assert.
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Avoiding IER Flag Assertion
21 SCLK pulses during the CS low period. The format of the SPI
message is shown in Figure 66.
The following methods may be used to avoid false IER flag
assertions:
The Master Output Slave In (MOSI) signal consists of: a 1-bit
Sync bit defined as a logic ‘0’, 1-bit R̅ /W, 6 address bits, 8 data
bits, 4 CRC bits, and an additional logic ‘0’. The extra logic ‘0’
sent on the 21st clock tick effectively shifts the standard 20-bit
packet left by one place value.
1. Use dedicated SCLK lines for each IC and hold the SCLK
line high when CS is high.
A. This prevents the IC from seeing SCLK edge transitions
when CS is high.
Vcc
The Master Input Slave Out (MISO) signal consists of: 16 data
bits, the contents of which are determined by the address of the
register being read, 4 CRC bits, and a repeat of the MSB of the
CRC value shown in bold in Figure 66). The repeated CRC bit
shifted out on the 21st clock edge should be ignored by the master
when processing the CRC to validate the message contents
Vcc
0.1 µF
Vcc_1
0.1 µF
Vcc_2
MISO_1
CS_1
MOSI_1
SCLK_1
A1333
POWER-ON BEHAVIOR WITH A 21-BIT SPI PACKET
MISO_2
CS_2
MOSI_2
SCLK_2
Host Micro
If the SCLK line is shared on two or more ICs, the IER flag
will assert on all idle A1333 die (CS held high) after the first
SPI transaction (on the bus), following power-up. This occurs
independent of the 21-bit SPI packet. This spurious IER flag
asserts, on the idle die, only during the first SPI transaction. All
subsequent SPI transactions will process correctly. This spurious
assertion will not affect any future reads or writes to the device
while power is maintained. If the IC is programmed to validate
the CRC on MOSI, a CRC error flag (Bit 10 of the WARN serial
register) will also assert, related to the spurious detection of a bad
SPI packet
GND
Figure 65: Separate SCLK Lines
2. Use a 21-bit SPI packet.
A. When using a 21-bit SPI packet, the IC does not count
SCLK edges when the CS pin is held high. This prevents
the IER flag from improperly asserting, with the exception of power-on.
USING A 21-BIT SPI PACKET
No special EEPROM programming is required for the A1333 to
support a SPI packet size of 21 bits; the master must simply send
1
2
3
4
5
6
7
8
9
Due to the initial assertion of the IER flag, it is recommended
to clear all error and warning flags on all A1333 ICs following
power-on (this is “good practice”, independent of the false IER
flag assertion). By doing this, the false IER flag is cleared, preventing it from masking a real SPI communication issue.
10
11
12
13
14
15
16
17
18
19
20
21
SCLK
CS
MOSI
0
R/W
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
M_D[7]
M_D[6]
M_D[5]
M_D[4]
M_D[3]
M_D[2]
M_D[1]
M_D[0]
M_CRC[3] M_CRC[2] M_CRC[1] M_CRC[0]
MISO
S_D[15]
S_D[14]
S_D[13]
S_D[12]
S_D[11]
S_D[10]
S_D[9]
S_D[8]
S_D[7]
S_D[6]
S_D[5]
S_D[4]
S_D[3]
S_D[2]
S_D[1]
S_D[0]
S_CRC[3]
S_CRC[2]
S_CRC[1]
0
S_CRC[0] S_CRC[3]
Figure 66: 21-bit SPI Packet Format
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Additional SPI Examples
The examples below show differing SPI implementations. All
figures assume a shared SPI bus (MISO, MOSI, SCLK) between
two sensors, with individual CS lines.
Figure 67 shows an example of pipelining SPI reads between
two sensors, which can result in discarded packets or corrupted
data when used with 16- or 17-bit SPI packets. In this example,
SPI reads are bounced between Sensor 1 and Sensor 2, one frame
at a time. During the interval in which the CS lines are high,
the inoperative sensor will detect an incorrect number of edges,
asserting the IER flag, and potentially corrupting the following
read response.
Figure 68 is a modified version of the pipelining shown in Figure
67. The first read response from each sensor is known to be
corrupt, and is ignored. Because of this, the second read request
(which results in the first read response on the next sequence)
can be a NOP command, resulting in all zeros from the device (a
NOP command is a read of serial register 0x0, which is hard-
coded with all 0s). Inserting a NOP command between each valid
read response ensures the data placed in the SPI buffers prior to
the second response is valid.
It should be noted that the IER flag will assert on every changeover to a new die (CS line) when using this implementation due
to the incorrect number of SCLK edges detected during the CS
high period.
Figure 69 shows a 20-bit SPI packet. This removes the potential
for incorrect read data (assuming the SCLK edge occurs 70 ns or
later following the CS rising edge), allowing the two sensors to
be addressed in a sequential manner, one frame per each sensor.
This implementation has the added advantage of including a 4-bit
CRC within each response. The IER flag may still assert when
using a 20-bit packet.
Figure 70 shows implementation of a 21-bit SPI packet. This
removes the false IER flag assertion and any potential for incorrect data interpretation. Allegro recommends using a 21-bit SPI
packet when sharing SPI lines.
Figure 67: Implementation of SPI using 16- or 17-bit packets resulting in IER flag assertion and potentially corrupted data
Figure 68: Implementation of SPI using 16- or 17-bit packets; valid data, IER flag will still assert
Figure 69: SPI Implementation using 20-bit packets; data contents are valid however IER flag may still assert
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Figure 70: SPI Implementation using 21-bit packets; data contents are valid; no false IER flag generation
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A1333
Revision History
Number
Date
–
September 25, 2017
1
February 23, 2018
Description
Initial release
Updated Response Time value (p. 8), Typical Performance Characteristics section (p. 9-10), Figure
12 (p. 13), Figure 13 (p. 14), Device Programming Interfaces section (p. 26-42), Table 12 heading (p.
43), TCW[3] (page 52), Mag_Thresh_Hi and Mag_Thresh_Lo descriptions (p. 64), Table 15 (p. 66),
Setting the Zero-Degree Position section (p. 70), Magnetic Target Requirements section (p. 70-71), I/O
Structures (p. 73), and Package Outline Drawings active area depths (p. 74-75).
Added 5 V interface voltage part variant, Manchester Interface Specifications (p. 7), Impact of High
Speed Sensing section (p. 11-12).
Removed CRC Documentation appendix.
2
August 1, 2018
3
October 15, 2018
Added A1333LLPTR-5-DD-T to Selection Guide (page 2).
Updated ASIL Status
4
November 1, 2019
Minor editorial updates
5
January 10, 2020
Updated Figure 1 (p. 1), Table of Contents (p. 3);
Added SPI Frame Rate test condition (p. 6);
Added Maximum Sourcing Current and Maximum Sinking Current characteristics (p. 7);
Updated Response Time (p. 8), Figure 3 and 4 (p. 9);
Added Figures 11 to 14 (p. 11-12);
Updated Impact of High Speed Sensing section (p. 15);
Added Measured Performance over RPM section (p. 15);
Updated Figure 20 (p. 16), Figure 21 (p. 17);
Added ABI Behavior at Power-Up section (p. 22);
Updated Figure 29 (p. 23), Slew Rate Limiting for ABI section (p. 24);
Added Effective Speed of Slew Time section (p. 24);
Updated Brushless DC Motor Output section (p. 25-26);
Added Spurious Interface Error (IER) When Sharing SPI Lines section (p. 30);
Added 21-Bit SPI Packet section (p. 32);
Updated Figure 53 (p. 40), Enabling EEPROM Access section (p. 41);
Added EEPROM Margin Check section (p. 43-44);
Updated INITIATE_SPECIAL description (p. 51), GAUSS description (p. 58),
ABI_SLEW_TIME bit range (p. 64), ORATE (p. 68); Figure 56 and Table 20 (p. 75),
Figure 63 (p. 80), Figure 64 (p. 81), Figure 65 (p. A-1), Angle Error equation (p. A-1);
Added Appendix B (p. B-1 to B-4).
6
July 1, 2020
Updated LE-14 and LP-24 package drawing Hall element tolerances (p. 79-80)
7
October 8, 2020
Updated SPI Interface section (p. 30)
8
February 1, 2021
Updated LE-14 package drawing (p. 80).
9
April 20, 2021
Updated Power-On Time maximum values and footnote (p. 6), Angle Measurement section (page 14),
and Table 8 (page 37)
Copyright 2021, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
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