A2550

A2550 Relay Driver with 5 V Regulator for Automotive Applications Features and Benefits ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Three independent low-side DMOS output drivers Short-circuit protection of drivers Eliminates need for flyback diodes on relays Thermal shutdown Separate precision 5 V regulator (2%) Current clamp on 5 V regulator 16-pin TSSOP package with exposed thermal pad Programmable reset (NPOR) delay time Programmable watchdog Automotive voltage and temperature ranges Active clamps for automotive load dump specifications Lead (Pb) free Description Large numbers of relay-based applications require the use of a microprocessor which implements complex system control. In these systems, there is the need for microprocessor logic supply voltage, power-on reset circuitry, and watchdog capabilities. The Allegro® A2550 combines the functions of voltage regulator, watchdog, and reset, as well as three low-side DMOS relay driver outputs. Primarily targeted at automotive applications, this IC is designed to provide robust performance over extended voltage and temperature ranges. Three low-side DMOS drivers can drive inductive loads, such as relay coils. Each driver integrates rugged voltage clamps which survive automotive load dump pulses up to 48 V. The 40 V rating on VBB also ensures adequate survival in harsh automotive environments. A 5 V linear regulator provides 40 mA of output current, with a tolerance of 2% over the operating temperature range. To enhance the usefulness of the IC in automotive applications, the 5 V regulator output, as well as the three low-side driver outputs are protected against overcurrent conditions. Package: 16 pin TSSOP (suffix LP) with exposed pad Approximate Scale Continued on the next page… Typical Application 1 2 IN1 IN2 IN3 LGND NPOR WDI EN VREG5 OUT1 OUT2 16 15 14 13 12 11 10 9 System Logic 3 4 5 6 7 8 A2550 OUT3 PGND CWD CPOR ENBAT VBB Relays or other inductive loads 0.47 μF X7R 2550-DS A2550 Description (continued) The A2550 also includes power-on reset circuitry (NPOR) as well as an integrated watchdog circuit. Combined, they service the monitoring and reset requirements of a system microprocessor. The A2550 is supplied in a 16-pin TSSOP package with exposed thermal pad (package LP).The package is lead (Pb) free, with 100% matte tin leadframe plating. Relay Driver with 5 V Regulator for Automotive Applications Selection Guide Part Number A2550KLP-T A2550KLPTR-T Packing 96 pieces / tube 13-in. reel, 4000 pieces / reel Absolute Maximum Ratings Characteristic Supply Voltage High Voltage Enable Output Driver Output Load Clamp Maximum Energy at Outputs Peak Power Dissipation at Outputs All other pins ESD Rating – Human Body Model ESD Rating – Charged Device Model Operating Ambient Temperature Maximum Junction Temperature Storage Temperature TA TJ (max) Tstg AEC-Q100-002; all pins AEC-Q100-011; all pins Range K Symbol VBB VENBAT VOUT VOUT(CL) EOUT PPK Continuous rating; outputs off Transient rating Single Pulse, TJ(initial) = 125°C Single pulse, TJ(initial) = 125°C, ∆t = 1 ms; see figure 2 for different durations and TJ(initial) Notes Rating –0.3 to 60 –0.3 to 60 –1.4 to 48 60 100 1.7 –0.3 to 7 2.5 1050 –40 to 125 150 –55 to 150 Units V V V V mJ W V kV V ºC ºC ºC Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A2550 Relay Driver with 5 V Regulator for Automotive Applications Functional Block Diagram CBB Hi-V Enable ENBAT VBB VBAT A2550 Hi-V Protection VREG5 CREG5 0.47 μF X7R TSD 5V Linear Regulator Enable Internal Reference Vref EN NPOR Adjustable Delay CPOR Relays or Other Inductive Loads PGND A LGND CWD WDI Watchdog VREG5 UVLO TSD Vdc Coil 1 OUT1 Micro Controller IN1 200 k Overcurrent Protection Coil 2 Coil 3 OUT2 IN2 200 k Overcurrent Protection OUT3 IN3 200 k Fault Logic Overcurrent Protection A LGND and PGND must be connected externally. Component Selection Table Name Suitable Characteristics CBB CREG5 CWD, CPOR 33 μF, 63 V electrolytic 0.47 μF, 25 V, X7R ceramic 0.22 μF, 16 V, X7R ceramic United Chemi-Con EGHA630E–560MJC5S Representative Device Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A2550 Relay Driver with 5 V Regulator for Automotive Applications ELECTRICAL CHARACTERISTICS, –40°C ≤ TJ ≤ 150°C, VBB within operating limits, unless otherwise noted Characteristics Symbol Test Conditions Min. Supply VBB Operating Voltage1 VBB 7 All OUTx Off; EN = 5 V, VBB = ENBAT = 14 V – IBBQ IBB VBB Supply Current All OUTx On; EN = 5 V, VBB = ENBAT= 14 V – IBBS Sleep mode, EN = ENBAT = 0 – Logic Inputs HIGH input level 3.5 ENBAT Input Voltage2 VENBAT LOW input level 0 HIGH input level 3.5 VIH EN, WDI, and INx Input Voltage VIL LOW input level 0 ENBAT, EN, WDI, INx Input Voltage VIhys 200 Hysteresis HIGH input level, VBB = VBB(max) – ENBAT Input Current2,3 HIGH input level, VBB = 14 V IENBAT – LOW input level –50 HIGH input level – EN Input Current2 IEN LOW input level –50 HIGH input level – WDI Input Current2 IWDI LOW input level –10 HIGH input level – INx Input Current2 IINx LOW input level –10 Drivers tp(ON) INx change to unloaded output change – Propagation Delays tp(OFF) INx change to unloaded output change – IOUTx = 250 mA, VBB = 14 V – Driver On-Resistance RDS(on) IOUTx = 250 mA, VBB = 9 V – IOUTx = 250 mA, VBB = 7 V – Driver Leakage Current IDSS VOUTx = 40 V – Diode Forward Voltage VF IOUTx = –250 mA – Output Clamp Voltage VCL IOUTx = 100 μA 50 Low-Side Driver Overcurrent (O.C.) IOUT(OC) 275 Threshold Blanking Time Before Overcurrent Detect tBLANK IOUT = 500 mA 2 Regulator CREG5 ≥ 0.47 μF (X7R Ceramic, ESR ≤ 0. 5Ω), Voltage Regulator Output Voltage VREG5 4.9 1 mA ≤ IREG5 ≤ 40 mA 1 Pass Transistor On-Resistance RREG5 IREG5 = 40 mA – Line Regulation Voltage VLNR IREG5 = 1 mA – 1 mA ≤ IREG5 ≤ 40 mA, VBB = 7 V – Load Regulation Voltage VLDR – 1 mA ≤ IREG5 ≤ 40 mA, VBB ≥ 9 V VREG5 = 4.63 V, VBB = 7 V 40 Current Limit Level4 IREG5Lim VREG5 = 4.63 V, VBB ≥ 9 V 65 VREG5 = 0 V 65 VREG5 falling 4.25 Under Voltage Lockout Threshold VUVREG5 VREG5 rising 4.36 Under Voltage Lockout Hysteresis VUVREG5hys – Typ. – – – – – – – – – – – – – – – – – – 1 0.5 – – – – –1.3 – – – 5.0 – – – – – – – 4.38 4.50 0.12 Max. 40 4 5 10 VBB 1.5 5.5 1.5 – 400 70 10 50 10 50 10 50 10 2 1 5 5.5 6 10 –1.4 60 500 20 5.1 55 20 100 40 150 200 200 4.63 4.75 – Units V mA mA μA V V V V mV μA μA μA μA μA μA μA μA μA μs μs Ω Ω Ω μA V V mA μs V Ω mV mV mV mA mA mA V V V Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A2550 Relay Driver with 5 V Regulator for Automotive Applications ELECTRICAL CHARACTERISTICS, continued –40°C ≤ TJ ≤ 150°C, VBB within operating limits, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Watchdog and Power-On Reset NPOR Active Voltage VNPOR INPOR = 1 mA; VREG5 = 1.5 V; 1.5 V ≤ VBB ≤ 40 V – – 400 NPOR Inactive Leakage Current INPOR(Off) VNPOR = 5 V – – 10 VTRIP(H) VTRIP(H) = VREF – 1.2 – CWD and CPOR Trip Voltage VTRIP(L) – 0.2 – 2.5 5 7.5 CPOR Charge Current IPOR Power-On Reset Cycle Time5 tPOR CPOR = 0.22 μF – 44 – Charging 2.5 5 7.5 CWD Charge Current ICWD Discharging – 70 – Thermal Protection Thermal Shut Down Threshold TTSD – 175 – Thermal Shut Down Hysteresis TTSDhys – 15 – 1See Applications 2For Units mV μA V V μA ms μA μA °C °C Information section for operation with VBB < 7 V. For VBB > 24 V, thermal constraints limit regulator current. input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 3When V ENBAT exceeds VBB it is clamped with a diode. (VENBAT – VBB) ≤ 1.2 V at 40 mA. 4Defined as the maximum current level allowed during excessive load condition. 5See Applications Information section for calculations. Values guaranteed by design, and depend on capacitor tolerances. THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Thermal Resistance, Junction to Pad Thermal Resistance, Junction to Ambient Symbol RθJP RθJA 4-layer PCB based on JEDEC standard 2-layer PCB with 2 in.2 copper both sides, connected by thermal vias RθJA = 44 ºC/W (estimated), 2-layer PCB with 2.0 TA = 125°C in.2 of 2 oz. copper, Test Conditions* Value 2 34 44 0.57 1.48 Units ºC/W ºC/W ºC/W W W Maximum Allowable Power Dissipation PD RθJA = 44 ºC/W (estimated), 2-layer PCB with 2.0 in.2 of 2 oz. copper, TA = 85°C *Additional thermal data available on the Allegro Web site. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A2550 Relay Driver with 5 V Regulator for Automotive Applications Dynamic Thermal Impedance Square Wave Power Pulse in a Single Output Stage 20 18 16 Impeda nce (°C/W) 14 12 10 8 6 4 2 0 0.01 0.1 1 Time (ms) 10 100 Figure 1. Dynamic thermal impedance of an individual output stage during active clamp of an inductive load Nonrepetitive Output Active Clamp Power Dissipation 100 POUT (W) 10 TJ = 25°C TJ = 125°C 1 0.01 0.1 1 10 100 Time (ms) Figure 2. Peak power dissipation curves for nonrepetitive clamped outputs. Output voltage is clamped during turn-off of inductive loads while current decays. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A2550 Relay Driver with 5 V Regulator for Automotive Applications Thermal Resistance with 2 oz. Copper (Additional thermal information is available on the Allegro Web site) Thermal Resistance (RθJA) vs. Copper Area on PWB 140 Thermal Resistance ( °C/W ) 120 100 80 60 40 20 0 1 One layer of copper Two layers of copper 2 3 4 Area of Copper per Zone per Layer (in.2) The exposed copper area must be soldered to the exposed thermal pad of the device. For the board with two layers of copper, the copper areas on both sides of the substrate are identical. The two layers are thermally connected by vias placed on each ground lead. See JEDEC Standard JESD 51-5 for recommended via geometry. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A2550 Relay Driver with 5 V Regulator for Automotive Applications Functional Description Pin Descriptions EN Enable pin; logical OR with ENBAT. This logic-level input enables the A2550. If there are no faults, the regulator is live and outputs can be switched. When both the EN and ENBAT pins are held low, the A2550 enters Sleep mode. ENBAT Enable pin; logical OR with EN. Same as EN, except that this pin is high-voltage protected, and specified up to VBB so it can be tied to the battery or power source. Not to exceed VBB because the ESD structure places a diode between the ENBAT and VBB pins. WDI Watchdog Input. Monitors the microcontroller to detect when it stops functioning. This pin is connected to an edge trigger. To avoid a fault, the latter must be triggered before CWD times-out. When not used, WDI is defeated by tying it to NPOR and shorting CWD. CWD Watchdog timer capacitor terminal. Used with WDI. A current source charges the external capacitor tied to this pin. A reverse current source discharges the capacitor when either WDI transitions or the high Trip Voltage, VTRIP(H) , is reached (see specification table for values). The charge-up time defines the maximum period allowed WDI to toggle before a fault is issued; the charge-down time defines the width of NPOR pulses issued to wake-up the microcontroller. NPOR NOT Power On Reset. This active-low pin indicates a fault. Except for watchdog faults, NPOR is held low during the fault state. Refer to the Fault Logic table to determine which faults are latched. Watchdog faults generate a train of pulses to “wake up” the microcontroller. CPOR Power-On Reset timer capacitor terminal. Whenever VREG5 first charges up (at start-up or when a fault is cleared) a “fault” condition remains in effect until the onboard current source drives CPOR to the high Trip Voltage, VTRIP(H) . This allows external circuits, such as a microcontroller, to be initialized before activating the outputs. CPOR is defeated by pulling it high to VREG5 with a 50 kΩ resistor. INx Input pin. Active-high CMOS input. Internally tied to 200 kΩ pull-down resistors. OUTx Output pin. Open drain DMOS. Clamps to a voltage greater than VBB when an inductive load is switched off. Includes current mirror for overcurrent protection. VBB Power pin, or “battery.” Specified for automotive voltages. VREG5 5 V Regulator output. Clamped at the Current Limit Level (IREG5Lim) for excessive loads. As load resistance decreases, VREG5 is pulled below the UVLO level. In that case, a fault is generated (NPOR low). LGND Logic Ground. The reference pin for the logic circuits. Must be connected to PGND externally. PGND Power Ground. The reference pin for the outputs (OUTx). Must be connected to LGND externally. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A2550 Relay Driver with 5 V Regulator for Automotive Applications Timing Diagram: Initial Start-up and Exiting Sleep Mode VBB VREG5 WDI Internal Vref CWD EN or ENBAT tPOR Internal Vref tPOR CPOR NPOR OUTx 1 2 ~INx 3 4 ~INx 1. 2. 3. 4. 5 V signal to wake up microcontroller. OUTx enabled with first watchdog pulse. Power ramp-up sequence with watchdog active. NPOR inactive, but outputs not enabled until watchdog detected. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A2550 Relay Driver with 5 V Regulator for Automotive Applications Timing Diagram: Watchdog Monitoring VREG5 WDI internal Vref CWD tWD tWDR CPOR NPOR OUTx outputs enabled 1 2 3 ~INx 4 1. 2. 3. 4. Missing watchdog detected (WDI low). NPOR pulses generated periodically. NPOR inactive, but outputs not enabled until watchdog detected. Missing watchdog detected (WDI low, steps 2 and 3 repeat). Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 10 A2550 Relay Driver with 5 V Regulator for Automotive Applications Timing Diagram: VREG5 UVLO and TSD Monitoring VBB VREG5 VUVREG5 WDI Internal Vref CWD Internal VREG5 UVLO Internal Vref CPOR NPOR Internal TSD OUTx outputs enabled 1 2 3 ~INx 4 5 ~INx 1. 2. 3. 4. 5. VREG5 undervoltage detected. VREG5 recovers, and after it rises above VUVREG5 + VUVREG5(Hys), UVLO flag is deactivated and CPOR recharges. NPOR inactive, but outputs not enabled until watchdog detected. TSD event detected and NPOR is activated. When VREG5 ≤ VUVREG5 , VREG5 shuts down. TSD flag deactivated (VREG5 allowed to rise; steps 2 and 3 repeat) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 11 A2550 Relay Driver with 5 V Regulator for Automotive Applications Applications Information Dropout Voltage For operation with VBB below the specified range of operating voltages, use the Pass Transistor On-Resistance RREG5 to determine the maximum allowed regulator current, IREG5(max). This current is limited by the difference between VBB and VREG5, according to the following equation: IREG5 < VBB − VREG5 R REG5 (1) NPOR The following faults generate a RESET state: • watchdog alarm • VREG5 falls below the UVLO level In addition, the following conditions cause a low NPOR signal if the NPOR pin is pulled up by VREG5 (because these conditions disable VREG5): • overtemperature (Thermal Shut Down) • no ENABLE signal (EN = ENBAT = 0) 70 60 Figure 3 shows the results of this condition combined with the rated regulator current, in normal operation. IREG5(max) ( mA) Note that, although the regulator is specified for normal operation with VBB well above normal automotive voltages, in general thermal constraints will limit maximum operational VBB. 50 40 30 20 10 0 0 5 10 VBB ( V) 15 20 Fault Logic The A2550 offers several protection and fault detection features. The operation of thermal shutdown, watchdog monitoring of the microcontroller, and regulated voltage undervoltage lockout are described in the Timing Diagrams section. The fault logic is described in table 1. Table 1. Fault Logica Inputs Internal 5V Watchdog alarm EN OR ENBATb Outputs Figure 3. Current Capability of the 5 V Regulator (VREG5) VREG5 NPOR Mode of Operation OUTx INx Z Z Z Z Z Sleep mode. NPOR = 0 when pulled up by VREG5 because VREG5 = 0. Normal Operation: OUTx active for INx active. OCx disables OUTx only. OUTx latched OFF until INx removed and reapplied. NPOR periodically pulses to attempt RESET of microcontroller. NPOR remains active after UVLO recovers until POR delay expires. UVLO 1 1 1 1 1 0 aX bThis 0 0 0 0 1 X 0 0 0 1 X X 0 0 1 X X X OCx 0 1 X X X X TSD 1 1 1 1 1 0 1 1 1 1 0 0 1 1 Pulse 0 0 Off indicates “don’t care,” Z indicates high impedence. entry is a logical OR of the EN and ENBAT pins. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 12 A2550 Relay Driver with 5 V Regulator for Automotive Applications Applications Information NPOR is pulsed for a watchdog fault. For the remaining faults, NPOR is held low for the duration of the fault. After the fault condition is removed, NPOR remains low during the tPOR period. The latter is set by the value of the external capacitor fed by a current source at the CPOR pin, according to the following formula: t POR = ⎛200 ms ⎞ CPOR µF ⎠ ⎝ (2) Output Overcurrent When the OC (overcurrent) protection is triggered in a driver, that driver is disabled for self-protection. No other functions are affected; NPOR and VREG5 operate normally. A disabled output driver remains shut down until the respective INx is brought low, then high again; at which time OUTx turns on. OUTx will switch on again the next time INx is applied. If a short-to-battery still exists, the overcurrent will trip each time INx is reapplied. The scaling factor is simply derived from the specifications using the typical value of IPOR: t POR CPOR = VREF − VTRIP(L) I POR (3) Sleep The A2550 is put to sleep by holding both EN and ENBAT low. In sleep mode all functions are shut down, including VREG5. If the VREG5 regulator is required at all times, disable sleep mode by tying ENBAT to VBB. Watchdog The watchdog monitors the microcontroller to detect if it locks up. To do so, the watchdog checks for pulses on the Watchdog Input pin (WDI), and if they are absent for longer than the timeout period, tWD , the watchdog activates NPOR, which pulses periodically. tWD is proportional to the external capacitor fed by a current source at the CWD pin. The voltage change is 1 V, so using the typical value of ICWD(charging) we have: tWD = ⎛200 ms ⎞ CWD µF ⎠ ⎝ (4) Power Limits Power dissipation, PD , is limited by thermal constraints. The maximum allowed power dissipation, PD(max) , is found from the formula: TJ = (PD(max) R θJA+ TA ) ≤ TJ(max) (6) The pulse width for NPOR active, tWDR, also scales proportionally to the value of the external capacitor at the CWD pin. Using the typical value of ICWD(discharging) we have: tWDR = ⎛14 ms ⎞ CWD ⎝ µF ⎠ See the specification tables for tolerances. When not used, disable watchdog by tying WDI to NPOR and tying CWD low. Table 2 shows watchdog timing for the nominal capacitances listed. Table 2. Timing Set by Capacitors C (μF) 0.1 0.22 0.47 1 tPOR (ms) 20 44 94 200 tWD (ms) 20 44 94 200 tWDR (ms) 1 3 7 14 The maximum junction temperature, TJ(max) , and the thermal resistance, RθJA , are given in the specification tables. The three main contributors to power dissipation are: • PBIAS from the supply bias current • PREG from the linear regulator voltage drop • PLS from low-side driver conduction For example, to determine if TJ is in an acceptable range, given: RθJA = 55°C/W , and TA = 125°C ; and PBIAS = VBB × IBBQ = 14 V × 3 mA = 42 mW , and PREG = (VBB – VREG5(min)) × IREG5 = (14 V – 4.9 V) × 20 mA= 182 mW , and Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com (5) (7) (8) 13 A2550 Relay Driver with 5 V Regulator for Automotive Applications PLS = (RDS(on) × I2LS1) + (RDS(on) × I2LS2) + (RDS(on) × I2LS3) . Because ILS1 = ILS2 = ILS3 = 110 mA , and given that RDS(on) = 5 Ω, then PLS = 3 (5 Ω) * (110 mA) 2 = 182 mW . Given also: PD = PBIAS + PREG + PLS = 42 mW+ 182 mW+ 182 mW = 406 mW . TJ can be calculated by substitution into equation 6: TJ = 0.406 W × 55°C/W +125°C = 147°C . (9) The output voltage is clamped to protect the driver. The active clamp works as follows. The voltage at the driver output is pushed high by the inductive current. Once the clamp voltage, VCL , is reached, a Zener diode conducts current to the internal FET gate driver block. Therefore, the FET turns partially on, in order to limit any further increase in voltage at the output pin. The output is then held at this clamp voltage until the current decays to zero, as shown in figure 4. Energy loss in the chip, E, may be calculated as follows. Load coil resistance, RCOIL , is usually a significant value, but a worst case scenario takes RCOIL = 0 for simplicity. With active clamping at VCL , the output current (with initial value IOUT0) is driven low and the upper limit on energy loss in the driver is calculated as: Emax = 1 IOUT0 VCL Δ t . 2 From figure 4: Δt = and –1 2 Emax = 1 L COIL IOUT0 (1– Vdc / VCL ) . 2 (10) Reverse Battery The low-side driver outputs can withstand reverse battery when the load (RLOADx) is connected to limit current. Power dissipation (PD = PLS(rvrs)) is limited by thermal constraints, according to the following formula: PLS(rvrs) = VF1× IF1+ VF2× IF2+ VF3× IF3 , where: IFx = VBB(rvrs) −VFx . RLOADx (12) (11) (14) LCOIL IOUT0 , VCL – Vdc (15) (16) Active Clamp on Outputs The driver section includes an active clamp that prevents an overvoltage when an inductive load is switched off. Zener diodes are connected at the output pins. This removes the need for external freewheeling diodes across inductive loads. The coil current, ICOIL , is quenched by allowing the output pin voltage, VOUTx , to exceed the battery voltage at the load, Vdc. This applies a negative voltage drop across the load. Therefore the current gradient is driven negative, as shown in the following formula: IOUT IOUT0 = Vdc RCOIL m= –(VCL – Vdc) LCOIL Δt dICOIL dt = Vdc − VOUT − ICOIL×RCOIL L COIL