A3282ELHLT-T

A3282 Chopper-Stabilized Hall-Effect Latch Features and Benefits ▪ Chopper stabilization ▫ Superior temperature stability ▫ Extremely low switchpoint drift ▫ Insensitive to physical stress ▪ Reverse battery protection ▪ Output short circuit protection ▪ Solid state reliability ▪ Small size ▪ Robust EMC capability ▪ High ESD ratings (HBM) Description The A3282 Hall-effect sensor is a temperature stable, stressresistant latch. Superior high-temperature performance is made possible through an Allegro® patented dynamic offset cancellation that utilizes chopper-stabilization. This method reduces the offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. The A3282 complements the current Allegro family of chopperstabilized latching sensors. The A3282 includes the following on a single silicon chip: voltage regulator, Hall-voltage generator, small-signal amplifier, chopper stabilization, Schmitt trigger, and a short circuit protected open-drain output. Advanced BiCMOS wafer fabrication processing is used to take advantage of low-voltage requirements, component matching, very low input-offset errors, and small component geometries. This device requires the presence of both south and north polarity magnetic fields for operation. In the presence of a south polarity field of sufficient strength, the device output latches on, and only switches off when a north polarity field of sufficient strength is present. Packages: 3 pin SOT23W (suffix LH), and 3 pin SIP (suffix UA) Continued on the next page… Not to scale Functional Block Diagram VCC Regulator To All Subcircuits Sample and Hold Dynamic Offset Cancellation Low-Pass Filter VOUT Amp Control Current Limit BOP B > BOP VCC > 3.6 V RLOAD = 820 Ω, CS = 20 pF RLOAD = 820 Ω, CS = 20 pF B > BOP B < BRP VRCC = –18 V ICC = 6.5 mA; TA = 25°C VS = 28 V South pole adjacent to branded face of device North pole adjacent to branded face of device BOP – BRP Min. 3.6 – – 30 – – – – – – – 28 – 70 –150 140 Typ. – – 250 – 8 200 0.2 0.2 1.6 1.6 – – – 110 –110 220 Max. 24 10 500 60 50 – 1 1 3.5 3.5 –2 – 6.5 150 –70 300 Units V μA mV mA μs kHz μs μs mA mA mA V mA G G G Maximum voltage must be adjusted for power dissipation and junction temperature, see Power Derating section. 2 C = oscilloscope probe capacitance. S 3 Maximum current limit is equal to the maximum I CC(MAX) + 3 mA. 4 Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and as a positive value for south-polarity magnetic fields. This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the field is indicated by the absolute value of B, and the sign indicates the polarity of the field (for example, a –100 G field and a 100 G field have equivalent strength, but opposite polarity). DEVICE QUALIFICATION PROGRAM Contact Allegro for information. EMC (Electromagnetic Compatibility) REQUIREMENTS Contact Allegro for information. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A3282 Chopper-Stabilized Hall Effect Latch Electrical Characteristic Data Supply Current (On) versus Ambient Temperature 5.0 4.0 5.0 4.0 Supply Current (On) versus Supply Voltage ICCON (mA) 3.0 2.0 1.0 0 –50 0 50 TA (°C) 100 150 ICCON (mA) VCC (V) 24 3.6 TA (°C) –40 25 150 3.0 2.0 1.0 0 0 5 10 VCC (V) 15 20 25 Supply Current (Off) versus Ambient Temperature Supply Current (Off) versus Supply Voltage 5.0 4.0 5.0 4.0 ICCOFF (mA) ICCOFF (mA) VCC (V) 3.0 2.0 1.0 0 –50 0 50 TA (°C) 100 150 24 3.6 TA (°C) –40 25 150 3.0 2.0 1.0 0 0 5 10 VCC (V) 15 20 25 Output Voltage (On) versus Ambient Temperature 500 450 400 350 500 450 400 350 Output Voltage (On) versus Supply Voltage VOUT(SAT) (mV) VOUT(SAT) (mV) 300 250 200 150 100 50 0 –50 0 50 TA (°C) 100 150 VCC (V) 24 3.6 300 250 200 150 100 50 0 0 5 10 VCC (V) 15 20 25 TA (°C) –40 25 150 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A3282 Chopper-Stabilized Hall Effect Latch Magnetic Characteristic Data Operate Point versus Ambient Temperature 150 140 130 120 VCC (V) 24 3.8 150 140 130 120 Operate Point versus Supply Voltage TA (°C) –40 25 150 BOP (G) 110 100 90 80 79 –50 0 50 TA (°C) 100 150 BOP (G) 110 100 90 80 79 0 5 10 VCC (V) 15 20 25 Release Point versus Ambient Temperature -70 -80 -90 -100 VCC (V) 24 3.8 -70 -80 -90 -100 Release Point versus Supply Voltage TA (°C) –40 25 150 BRP (G) -110 -120 -130 -140 -150 –50 0 50 TA (°C) 100 150 BRP (G) -110 -120 -130 -140 -150 0 5 10 VCC (V) 15 20 25 Hysteresis versus Ambient Temperature 300 280 260 300 280 260 Hysteresis versus Supply Voltage BHYS (G) BHYS (G) 240 220 200 180 160 140 –50 0 50 TA (°C) 100 150 VCC (V) 24 3.8 240 220 200 180 160 140 0 5 10 VCC (V) 15 20 25 TA (°C) –40 25 150 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A3282 Chopper-Stabilized Hall Effect Latch THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Package LH, 1-layer PCB with copper limited to solder pads Package Thermal Resistance RθJA Package LH, 2-layer PCB with 0.463 in.2 of copper area each side connected by thermal vias Package UA, 1-layer PCB with copper limited to solder pads *Additional thermal information available on Allegro Web site. Value Units 228 110 165 ºC/W ºC/W ºC/W Power Derating Curve 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 20 VCC(max) Maximum Allowable VCC (V) 2-layer PCB, Package LH (RθJA = 110 ºC/W) 1-layer PCB, Package UA (RθJA = 165 ºC/W) 1-layer PCB, Package LH (RθJA = 228 ºC/W) VCC(min) 120 140 160 180 40 60 80 100 Temperature (ºC) Power Dissipation versus Ambient Temperature 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 20 Power Dissipation, PD (m W) 2l (R aye rP θJ C A= 11 B, P 0 º ac 1-la C/ ka W (R yer PC ) ge L θJA = B H 165 , Pac ºC/ kage W) UA 1-lay er P (R CB, θJA = 228 Packag ºC/W e LH ) 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A3282 Chopper-Stabilized Hall Effect Latch Functional Description Operation The output of these devices switches low (turns on) when a magnetic field perpendicular to the Hall sensor exceeds the operate point threshold, BOP. After turn-on, the output voltage is VOUT(SAT). The output transistor is capable of sinking current up to the short circuit current limit, IOM, which is a minimum of 30 mA. Note that the device latches, that is, a south pole of sufficient strength towards the branded surface of the device turns the device on. The device remains on if the south pole is removed. When the magnetic field is reduced below the release point, BRP , the device output turns off (goes high). The difference in the magnetic operate and release points is the hysteresis, BHYS , of the device. This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. Powering-on the device in the hysteresis region (less than BOP and higher than BRP) allows an indeterminate output state. The correct state is attained after the first excursion beyond BOP or BRP . Applications It is strongly recommended that an external bypass capacitor be connected (in close proximity to the Hall sensor) between the supply and ground of the device to reduce both external noise and noise generated by the chopper stabilization technique. As is shown in Panel B of figure 1, a 0.1μF capacitor is typical. Extensive applications information on magnets and Hall-effect sensors is available in: • Hall-Effect IC Applications Guide, AN27701, • Hall-Effect Devices: Gluing, Potting, Encapsulating, Lead Welding and Lead Forming, AN27703.1 • Soldering Methods for Allegro’s Products – SMT and ThroughHole, AN26009 All are provided in Allegro Electronic Data Book, AMS-702 and the Allegro Web site: www.allegromicro.com (A) V+ VCC VS (B) Switch to High Switch to Low VCC CBYP 0.1 µF RLOAD Sensor Output VOUT A3282 VOUT VOUT(SAT) 0 GND BRP B– 0 B+ BOP BHYS Figure 1: Switching Behavior of Latches. In Panel A, on the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B– direction indicates decreasing south polarity field strength (including the case of increasing north polarity). This behavior can be exhibited when using a circuit such as that shown in panel B. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A3282 Chopper-Stabilized Hall Effect Latch Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall sensor. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. The patented Allegro technique, namely Dynamic Quadrature Offset Cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulationdemodulation process. The undesired offset signal is separated from the magnetic-field-induced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic-fieldinduced signal to recover its original spectrum at baseband, while the dc offset becomes a high-frequency signal. The magnetic-field-induced signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. This configuration is illustrated in figure 2. The chopper stabilization technique uses a 200 kHz high-frequency clock. For demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency (400 kHz). This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample-and-hold circuits. The repeatability of magnetic-field-induced switching is affected slightly by a chopper technique. However, the Allegro highfrequency chopping approach minimizes the affect of jitter and makes it imperceptible in most applications. Applications that are more likely to be sensitive to such degradation are those requiring precise sensing of alternating magnetic fields; for example, speed sensing of ring-magnet targets. For such applications, Allegro recommends its digital sensor families with lower sensitivity to jitter. For more information on those devices, contact your Allegro sales representative. Regulator Clock/Logic Hall Element Amp Sample and Hold Figure 2. Chopper Stabilization Circuit (Dynamic Quadrature Offset Cancellation) Low-Pass Filter Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A3282 Chopper-Stabilized Hall Effect Latch Power Derating The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating TJ. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, RθJA, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, RθJC, is relatively small component of RθJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate TJ, at PD. PD = VIN × IIN ΔT = PD × RθJA (2) TJ = TA + ΔT (3) (1) Example: Reliability for VCC at TA = 150°C, package LH, using a low-K PCB. Observe the worst-case ratings for the device, specifically: RθJA = 228 °C/W, TJ(max) = 165°C, VCC(max) = 24 V, and ICC(max) = 5 mA. Calculate the maximum allowable power level, PD(max). First, invert equation 3: ΔTmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 228 °C/W = 66 mW Finally, invert equation 1 with respect to voltage: VCC(est) = PD(max) ÷ ICC(max) = 66 mW ÷ 5 mA = 13 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages ≤VCC(est). Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and VCC(max) is reliable under these conditions. For example, given common conditions such as: TA= 25°C, VCC = 12 V, ICC = 1.5 mA, and RθJA = 165 °C/W, then: PD = VCC × ICC = 12 V × 1.5 mA = 18 mW ΔT = PD × RθJA = 18 mW × 165 °C/W = 3°C TJ = TA + ΔT = 25°C + 3°C = 28°C A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding TJ(max), at a selected RθJA and TA. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A3282 Chopper-Stabilized Hall Effect Latch Package LH, 3-Pin SOT23-W 3.00 .118 2.70 .106 0.15 [.006] M C A B 3.04 .120 2.80 .110 A A 1.49 .059 NOM 8º 0º 0.20 .008 0.08 .003 3 B B 2.10 .083 1.85 .073 Preliminary dimensions, for reference only Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only (reference JEDEC TO-236 AB, except case width and terminal tip-to-tip) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Hall element (not to scale) B Active Area Depth 0.28 [.011] 3X 0.10 [.004] C 3X 0.50 .020 0.30 .012 0.20 [.008] M C A B 0.95 .037 1.90 .075 A 0.96 .038 A NOM 0.60 .024 0.25 .010 1 2 0.25 .010 SEATING PLANE 1.17 .046 0.75 .030 0.15 .006 0.00 .000 C SEATING PLANE GAUGE PLANE Pin-out Drawings Package LH 3 Package UA 1 2 1 2 3 Terminal List Name VCC VOUT GND Description Connects power supply to chip Output from circuit Ground Number Package LH 1 2 3 Package UA 1 3 2 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 10 A3282 Chopper-Stabilized Hall Effect Latch Package UA, 3-Pin SIP .164 4.17 .159 4.04 C D 2.04 .0805 NOM .062 1.57 .058 1.47 D .122 3.10 .117 2.97 .0565 1.44 NOM D B .085 2.16 MAX .031 0.79 REF A .640 16.26 .600 15.24 .017 0.44 .014 0.35 1 2 3 .019 0.48 .014 0.36 .050 1.27 NOM Dimensions in inches Metric dimensions (mm) in brackets, for reference only A Dambar removal protrusion (6X) B Ejector mark on opposite side C Active Area Depth .0195 [0.50] NOM D Hall element (not to scale) The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright © 2005, 2006 Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 11