A3931

A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Features and Benefits ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ High current 3-phase gate drive for N-channel MOSFETs Synchronous rectification Cross-conduction protection Charge pump and top-off charge pump for 100% PWM Integrated commutation decoder logic Operation over 5.5 to 50 V supply voltage range Extensive diagnostics output Provides +5 V Hall sensor power Low-current sleep mode Description The A3930 and A3931 are 3-phase brushless dc (BLDC) motor controllers for use with N-channel external power MOSFETs. They incorporate much of the circuitry required to design a cost effective three-phase motor drive system, and have been specifically designed for automotive applications. A key automotive requirement is functionality over a wide input supply range. A unique charge pump regulator provides adequate (>10 V) gate drive for battery voltages down to 7 V, and allows the device to operate with a reduced gate drive at battery voltages down to 5.5 V. Power dissipation in the charge pump is minimized by switching from a voltage doubling mode at low supply voltage to a dropout mode at the nominal running voltage of 14 V. A bootstrap capacitor is used to provide the above-battery supply voltage required for N-channel MOSFETs. An internal charge pump for the high-side drive allows for dc (100% duty cycle) operation. Internal fixed-frequency PWM current control circuitry can be used to regulate the maximum load current. The peak load current limit is set by the selection of an input reference voltage and external sensing resistor. The PWM frequency is set by a user-selected external RC timing network. For added flexibility, the PWM input can be used to provide speed and Continued on the next page… Package: 48 Lead LQFP with exposed thermal pad (suffix JP) Typical Application 3930-DS Preliminary Data Sheet Subject to Change Without Notice April 6, 2006 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver combination on the Hall inputs. In this state, the A3930 indicates a logic fault, but the A3931 prepositions the motor in an unstable starting position suitable for start-up algorithms in microprocessordriven “sensor-less” control systems. Both devices are supplied in a 48-pin LQFP with exposed thermal pad. This is a small footprint (81 mm2) power package, that is lead (Pb) free, with 100% matte tin leadframe plating. Description (continued) torque control, allowing the internal current control circuit to set the maximum current limit. Efficiency is enhanced by using synchronous rectification. The power FETs are protected from shoot-through by integrated crossover control with dead time. The dead time can be set by a single external resistor. The A3930 and A3931 only differ in their response to the all-zero Selection Guide Part Number A3930KJP-T A3931KJP-T Option Hall short detection Prepositioning Packing 250 pieces/tray Terminals 48 Package LQFP surface mount Absolute Maximum Ratings Parameter Load Supply Voltage Logic Input/Output Voltage Symbol VBB VRESET VGHx VGLx VCx VBB pin Conditions RESET pin input Remaining logic pins GHA, GHB, and GHC pins GLA, GLB, and GLC pins CA, CB, and CC pins SA, SB, and SC pins CSP, CSN, and LSS pins CSO, VDSTH pins VDRAIN pin Min. –0.3 –0.3 –0.3 VSx –5 – –5 –4 –0.3 – –40 – –55 Typ. – – – – – – – – – – – – Max. 50 6 7 VSx+ 15 16 VSx+ 15 45 6.5 6.5 55 135 150 150 Units V V V V V V V V V °C °C °C Output Voltage Range VSx Operating Temperature Range (K) Junction Temperature Storage Temperature Range TA TJ TS Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Functional Block Diagram VBAT+ CP VBB CP2 CP1 P QV5 V5BD +5V Ref V5 CV5 Charge Pump Regulator VREG CREG VDRAIN MODE Phase A of three phases COAST Charge Pump CA CBOOTA H1 H2 H3 V5 BRAKE RESET Boostrap Monitor GHA DIR High-Side Drive RGHA B C H1 Control Logic SA H2 A H3 VREG Low-Side Drive GLA RGLA RDEAD LSS PWM TACHO TEST R DIRO Q S ESF Diagnostics and Protection –UVLO –TSD –Short to Supply –Short to Ground –Shorted Winding –Low Load Pad VDSTH RT RC CT Blanking OSC CSP RSENSE CSN FF1 FF2 REF P CSOUT AGND Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1 Characteristics Supply and Reference VBB Functional Operating Range6 VBB Quiescent Current V5 Quiescent Current VREG Output Voltage Symbol VBB IBBQ IBBS IV5Q VREG Test Conditions Function correct, parameters not guaranteed RESET = High, outputs = Low RESET = Low, sleep mode RESET = High, outputs = Low VBB > 7.5 V, IREG = 0 to 15 mA 6 V < VBB < 7.5 V IREG = 0 to 15 mA 5.5 V < VBB < 6 V, IREG < 10 mA ID = 10 mA ID = 100 mA rD(100 mA) = (VfBOOT(150 mA) – VfBOOT(50 mA)) / 100 mA Min. 5.5 – – – 12.5 2 × VBB –2.5 9 0.4 1.5 6 250 – 40 4.75 – – – – 3 5 1 1.5 – – VCx – 0.2 VREG – 0.2 From input change to unloaded gate output change RDEAD = 5 kΩ RDEAD = 50 kΩ RDEAD = 400 kΩ RDEAD = tied to V5 – – 815 – – Typ. – 11 – – 13 – 10 0.7 2.2 10 500 200 – 5 – – 60 40 4 6 1.5 2.3 –500 850 – – 90 180 960 3.3 6 Max. 50 14 10 5 13.75 – – 1.0 2.8 20 750 – – 5.25 1 –2 – – 5 7 2 3 – – – – 150 – 1110 – – Units V mA μA mA V V V V V Ω mA μA μA V V mA ns ns Ω Ω Ω Ω mA mA V V ns ns ns μs μs Bootstrap Diode Forward Voltage Bootstrap Diode Resistance Bootstrap Diode Current Limit Top-off Charge Pump Current Limit Cx Top-off Charge Pump Source Current V5 Output Voltage VBE of External Transistor QV5 V5BD Base Drive Capability for QV52 Gate Output Drive Turn-On Rise Time Turn-Off Fall Time Pull-Up On Resistance Pull-Down On Resistance Short-Circuit Current – Source2 Short-Circuit Current – Sink GHx Output Voltage GLx Output Voltage Turn-Off Propagation Delay VfBOOT rD IDBOOT ITOCPM ICx V5 VBEEXT I5BD tr tf RDS(on)UP RDS(on)DN ISC(source) ISC(sink) VGHx VGLx tp(off) VCx-VSx = 8 V, VBB = 14 V, GHx = High CLOAD = 3300 pF, 20% to 80% points CLOAD = 3300 pF, 80% to 20% points TJ = 25°C, IGHx = –150 mA TJ = 150°C, IGHx = –150 mA TJ = 25°C, IGLx = 150 mA TJ = 150°C, IGLx = 150 mA TJ = 25°C TJ = 25°C tw < 10 μs Bootstrap capacitor fully charged Dead Time (turn-off to turn-on delay) tDEAD Continued on the next page... Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 Subject to Change Without Notice April 6, 2006 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1 Characteristics Logic Inputs and Outputs FFx Fault Output (Open Drain) FFx Fault Output Leakage Current2 TACHO and DIRO Output High Voltage TACHO and DIRO Output Low Voltage Input Low Voltage Input High Voltage (Except RESET) RESET Input High Voltage Input Hysteresis Input Current (Except H1, H2, H3, and RESET)2 RESET Input Pull-Down Resistor Hx Input Pull-Up Resistor Current Sense Differential Amplifier Input Bias Current2 Input Offset Current2 CSP Input Resistance CSN Input Resistance Differential Input Voltage Output Offset Voltage Output Offset Voltage Drift Input Common Mode Range Differential Input Voltage Gain Low Output Voltage Error DC Common Mode Gain Source Resistance Output Dynamic Range Output Current – Sink Output Current – Source2 Supply Rejection Small Signal 3dB Bandwidth Frequency Settling Time Symbol VOL IOH VOH VOL VIL VIH VIHR VIHys IIN RPD RPU IIBS IIOS RCSP RCSN VID VOOS VOOS(Δt) VCM AV Verr ACMdc rCSOUT VCSOUT ICSOUT(sink) ICSOUT(source) PSRR f3dB tSETTLE VIN = 5 V VIN = 0 V CSP = CSN = 0 V CSP = CSN = 0 V Measured with respect to AGND Measured with respect to AGND VID = CSP – CSN, –1.3 V < CSP < 4 V, –1.3 V < CSN < 4 V CSP = CSN = 0 V CSP = CSN = 0 V CSP = CSN 40 mV < VID < 175 mV, VCM in range 0 < VID < 40 mV, VCSOUT = (19 × VID) + VOOS + Verr CSP = CSN = 200 mV VCSOUT = 2.0 V, ICSOUT = [TBD] μA –100 μA < ICSOUT < 100 μA VCSOUT= 2 V ±5% VCSOUT= 2 V ±5% CSP = CSN = AGND, 0 to 300 kHz VID=10 mVpp To within 10%, VCSOUT = 1 Vpp square wave Test Conditions IOL = 1 mA, fault asserted VO = 5 V, fault not asserted IOH = –1 mA IOL = 1 mA Min. – –1 V5 – 1 V – – 2 2.2 300 –1 – – –95 –20 – – 0 150 – –1.5 18.2 –20 – – 0.1 – – – – – Typ. – – – – – – – 500 – 50 100 –145 – 80 4 – 375 100 – 19 – –30 30 – 1 –19 45 1.6 400 Max. 0.4 1 – 0.4 0.8 – – – 1 – – –205 20 – – 200 600 – 4 19.4 20 – – 4.8 – – – – – Units V μA V V V V V mV μA kΩ kΩ μA μA kΩ kΩ mV mV μV/°C V V/V mV dB Ω V mA mA dB MHz ns Continued on the next page… Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1 Characteristics AC Common Mode Gain Common Mode Recovery Time Output Slew Rate Input Overload Recovery Time Current Limit Reference Comparator Input Offset Voltage Reference Input Clamp Voltage Comparator Blank Time REF Input Bias Current RC Charge Current2 RC HIgh Voltage Threshold RC Low Voltage Threshold Protection VREG Undervoltage Lockout Bootstrap Capacitor Undervoltage Lockout Bootstrap Capacitor Undervoltage Lockout Hysteresis V5 Undervoltage Lockout V5 Undervoltage Lockout Hysteresis VDSTH Input Voltage Range VDSTH Input Current2 VDRAIN Input Voltage Range Short-to-Ground Threshold Offset3,5 Short-to-Battery Threshold Offset4,5 Low Load Current Detection Voltage Overtemperature Flag Overtemperature Flag Hysteresis 1Parameters 2For Symbol ACMac tCMrec SR tIDREC VIOC VREFC tRC IIBREF IRC VRCH VRCL VREGUV VBOOTUV Test Conditions VICR= 250 mVpp, 0 to 1 MHz To within 100 mV, VICR= +4.1 to 0 V step 10% to 90% points, VID= 0 to 175 mV step To within 10%, VID=250 mV to 0 V step Min. – – – – –15 Typ. –28 1 20 500 0 4 TBD 0 –1 2.0 0.7 8 7.25 – 13 3.65 400 Max. – – – – 15 4.2 – – –0.9 2.5 0.8 8.5 7.75 69 – 4.0 500 4 1 45 – 150 – 150 – – – Units dB μs V/μs ns mV V μs μA mA V V V V % % V mV V μA V mV mV mV mV mV ºC ºC External pull-up to 5 V RREF = 200 kΩ RT= 56 kΩ, CT = 470 pF 3.8 – – –1.1 1.8 0.6 7.5 6.75 59 – 3.4 300 0.3 –1 7 – –150 – –150 – – – VREG rising VREG falling VBOOT falling, VCx – VSx VBOOTUVHys VBOOTUVHys = %VREG V5UV V5UVHys VDSTH IDSTH VDRAIN VSTGO VSTBO VCSOL TJF TJFHys V5 falling VDSTH > 1 V VDSTH < 1 V VDSTH > 1 V VDSTH < 1 V Temperature increasing Recovery = TJF – TJFHys VBB ±300 – ±300 – 500 165 15 are tested at 135°C. Values at 150°C are guaranteed by design or correlation. input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 3High side on. As V SX decreases, fault occurs if VBAT -VSX>VSTG 4Low side on. As V SX increases, fault occurs if VSX -VLSS>VSTB 5V STG threshold is VDTSTH + VSTGO. VSTB threshold is VDTSTH+VSTBO. 6Function is correct but parameters not guaranteed above or below general limits (7 to 45 V). Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Thermal Characteristics THERMAL CHARACTERISTICS may require derating at maximum conditions, see Applications Information section Characteristic Package Thermal Resistance Die-to-Exposed Pad Thermal Resistance Symbol RθJA RθJP 2-layer PCB, with 3 by thermal vias Test Conditions* 4-layer PCB, based on JEDEC standard in.2 of copper area each side connected Value Units 23 44 2 ºC/W ºC/W ºC/W *Additional thermal information available on Allegro Web site. Power Dissipation verus Ambient Temperature ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 6.0 5.0 4.0 3.0 R JA = 23 °C /W 2.0 R JA = 44° C/W 1.0 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Functional Description Basic Operation The A3930 and A3931 devices provide commutation and current control for 3-phase brushless dc (BLDC) motors with integrated Hall-effect (HE) sensors. The motor current is provided by an external 3-phase N-channel MOSFET bridge which is controlled by the A3930/A3931, using fixed-frequency pulse width modulation (PWM). The use of PWM with N-channel MOSFETs provides the most cost-effective solution for a high-efficiency motor drive. The A3930/A3931 provides all the necessary circuits to ensure that the gate-source voltage of both high-side and low-side external MOSFETs are above 10 V, at supply voltages down to 7 V. For extreme battery voltage drop conditions, functional operation is guaranteed down to 5.5 V but with a reduced gate drive. The A3930/A3931 also decodes the commutation sequence from three HE sensors spaced at 120° in the electrical cycle, and ensure no cross-conduction (shoot through) in the external bridge. Individual pins provide direction, brake and coast control. Motor current can be sensed by a low-value sense resistor, RSENSE, in the ground connection to the bridge, amplified and compared to a reference value. The A3930/A3931 then limits the bridge current on a cycle-by-cycle basis. Bridge current can also be controlled using an external PWM signal with the internal current control either disabled or used to set the absolute maximum motor current. Specific functions are described more fully in the following sections. AGND. If an external 5 V supply is not required, the V5BD pin and the V5 pin should be connected together. CP1, CP2, and VREG The gate drive outputs are powered by an internal charge pump, which requires a pump capacitor, typically 470 nF, CP, connected between the CP1 and CP2 pins. The output from the charge pump, 13 V nominal, is used to power each of the three high- and low-side driver pairs and is also available on the VREG pin. A sufficiently large storage capacitor, CREG, must be connected to this pin to provide the transient charging current to the low-side drivers. The charge pump also provides the charging current for the bootstrap capacitors, CBOOTx. An additional “top-off” charge pump is provided for each highside drive which allows the high-side drive to maintain the gate voltage on the external FET indefinitely, ensuring so-called 100% PWM if required. This is a low-current trickle charge pump (< 100 μA typical), and is only operated after a high-side driver has been signaled to turn on. There is a small amount of bias current (< 20 μA) drawn from the C x pin to operate the floating high-side circuit, and the charge pump simply provides enough drive to ensure that the bootstrap voltage, and hence the gate voltage, will not droop due to this bias current. The charge required for initial turn-on of the high-side gate is always supplied by bootstrap capacitor charge cycles. Hall Effect Sensor Inputs H1, H2, and H3 Hall-effect sensor inputs are configured for motors with 120° electrically-spaced HE sensors, but may be used for 60° electrical spacing with an external inverter. HE sensors usually require an additional pull-up resistor to be connected between the sensor output and 5 V. This 5 V can be provided by the integrated 5 V regulator. HE inputs have a hysteresis of typically 500 mV to reduce the effects of switching noise on the HE connections to the motor. These inputs are also filtered to further reduce the effects of switching noise. The HE inputs are pulledup to 5 V inside the A3930/A3931 through a high value (100 kΩ typical) resistor in series with a diode. This internal pull-up makes the HE input appear high if the Hall sensor signal is missing, allowing detection of an HE input logic fault. Power Supplies Only one power connection is required because all internal circuits are powered by integrated regulators. The main power supply should be connected to VBB through a reverse battery protection circuit. V5 and V5BD A 5 V supply for external pull-up and bias currents is provided by an integrated 5 V regulator controller and an external NPN transistor, QV5. The A3930/A3931 provides the base drive current on the V5BD pin, and the 5 V reference on the V5 pin. This regulator is also used by the internal logic circuits and must always be decoupled by at least a 200 nF capacitor, CV5, between the V5 pin and AGND. For stability, a 100 nF capacitor, C5BD, also should be connected between V5BD and Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver which should have low-impedance traces to the FET bridge. GHA, GHB, and GHC High-side gate drive outputs for external NMOS drivers. External series-gate resistors, RGATE, can be used to control the slew rate seen at the power-driver gate, thereby controlling the di/dt and dv/dt of the Sx inputs. Referring to table 3, GHx = 1 (high) means that the upper half (PMOS) of the driver is turned on, and that its drain will source current to the gate of the high-side FET in the external motor-driving bridge. GHx = 0 (low) means that the lower half (NMOS) of the driver is turned on, and that its drain will sink current from the corresponding external FET gate circuit to the respective Sx pin. CA, CB, and CC High-side connections for the bootstrap capacitors and positive supply for high-side gate drivers. The bootstrap capacitors, CBOOTx, are charged to approximately VREG when the corresponding Sx terminal is low. When the Sx output swings high, the voltage on the Cx pin rises with the output to provide the boosted gate voltage needed for the high-side N-channel power MOSFETs. VDRAIN High impedance sense input (Kelvin connection) to the top of the external FET bridge. This input allows accurate measurement of the voltage at the drain of the high-side FETs and should be connected directly to the bridge, close to the drain connections of the high-side FETs, with an independent trace. LSS Low-side return path for discharge of the gate capacitors. It is connected to the common sources of the low-side external FETs through an independent low-impedance trace. In order to provide a known start-up position for the motor, an optional prepositioning function is available in the A3931. When the Hall inputs are all driven low (H1 = H2 = H3 = 0), the power FETs in the A phase source current from the supply, and those in both the B and C phases sink current. This forces the motor to move to an unstable position midway between two detent points and allows any start-up algorithm to ensure correct initial direction of rotation. Note that this is only available in the A3931. The A3930 will indicate a logic fault when all Hall inputs are driven low. The commutation truth table for these inputs is shown in table 3. The inputs can also be driven directly from a microcontroller or similar external circuit. Gate Drive The A3930/A3931 is designed to drive external N-channel power MOSFETs. They supply the large transient currents necessary to quickly charge and discharge the gate capacitance of the external FETs in order to reduce dissipation in the external FETs during switching. The charge and discharge rate can be controlled using external resistors in series with the connections to the gate of the FETs. RDEAD Cross-conduction is prevented by the gate drive circuits which introduce a dead time, tDEAD, between switching one FET off and the complementary FET on. The dead time is derived from the value of a resistor, RDEAD, connected between the RDEAD pin and AGND. If RDEAD is connected to V5, tDEAD defaults to 6 μs typical. GLA, GLB, and GLC Low-side gate drive outputs for external NMOS drivers. External series-gate resistors, RGATE, (as close as possible to the NMOS gate) can be used to control the slew rate seen at the power-driver gate, thereby controlling the di/dt and dv/dt of the Sx outputs. Referring to table 3, GLx = 1 (high) means that the upper half (PMOS) of the driver is turned on, and that its drain will source current to the gate of the low-side FET in the external motor-driving bridge. GLx = 0 (low) means that the lower half (NMOS) of the driver is turned on, and that its drain will sink current from the corresponding external FET gate circuit to the LSS pin. SA, SB, and SC Directly connected to the motor, these terminals sense the voltages switched across the load. These terminals are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drivers. The discharge current from the highside FET gate capacitance flows through these connections, Logic Control Inputs Additional logic-level inputs are provided to enable specific features described below. These logic inputs all have a nominal hysteresis of 500 mV to improve noise performance. RESET Allows minimum current consumption from the VBB supply. When RESET is low, all internal circuitry is disabled including the V5 output. When coming out of sleep state, the protection logic ensures that the gate drive outputs are off until the charge pump reaches proper operating conditions. The charge pump stabilizes in approximately 3 ms under nominal conditions. RESET has an internal pull-down resistor, 50 kΩ typical. However, to allow the A3930/A3931 to start-up without the need for an external logic input, the RESET pin can be pulled to the battery voltage with an external pull-up resistor. Because RESET also has an internal clamp diode, 6 V typical, to limit the input current, the value of the external pull-up resistor should be Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver RSENSE, connected between CSP and CSN, the output of the sense amplifier will be approximately: VCSOUT ≈ (ILOAD × AV × RSENSE) + VOOS , where VOOS is the output offset voltage (the voltage at zero load current), and AV is the differential voltage gain of the sense amplifier, 19 typical. Internal Current Control: REF A fixed reference voltage can be applied to provide a maximum current limit. A variable reference voltage will provide a variable torque control. The output voltage of the current sense differential amplifier, VCSOUT , is compared to the reference voltage available on the REF pin. When the outputs of the MOSFETs are turned on, current increases in the motor winding until it reaches a trip point value, ITRIP, given by: ITRIP = (VREF – VOOS) / (RSENSE × AV) . At the trip point, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate until the start of the next PWM period. The current path during recirculation is determined by the configuration of the MODE pin. Torque control can therefore be implemented by varying the voltage on the REF pin, provided that the PWM input remains high. If direct control of the torque or current by PWM input is desired, a voltage can be applied to the REF pin to set an absolute maximum current limit. The REF input is internally limited to 4 V, which allows the use of a simple pull-up resistor to V5, RREF, to set the maximum reference voltage, avoiding the need for an externally generated reference voltage. RREF should have a value between 20 kΩ and 200 kΩ. Internal PWM Frequency The internal oscillator frequency, fOSC, is determined by an external resistor, RT, and capacitor, CT, connected in parallel from the RC pin to AGND. The frequency is approximately: fOSC ≈ 1 / (RTCT + tBLANK + tDEAD) . where fOSC in the range 20 to 50 kHz. PWM Input Can be used to control the motor torque by an external control circuit signal on the PWM pin. Referring to table 4, when PWM = 0, the selected drivers are turned off and the load inductance causes the current to recirculate. The current path during recirculation is determined by the configuration of the MODE pin. Setting PWM = 1 will turn on selected drivers as determined by the Hx input logic (see table 3). Holding PWM=1 allows speed and torque control solely by the internal currentlimit circuit, using the voltage on the REF pin. 10 greater than 20 kΩ. The upper limit for the resistor must be low enough to ensure that the input voltage reaches the input high threshold, VINR. COAST An active-low input which turns all FETs off without disabling the supplies or control logic. This allows the external FETs and the motor to be protected in case of a short circuit. MODE Sets the current-decay method. Referring to table 4, when in slow-decay mode, MODE = 1, only the high-side MOSFET is switched off during a PWM-off cycle. In the fast-decay mode, MODE = 0, the device switches both the high-side and low-side MOSFETs. Slow decay allows a lower ripple current in the motor at the PWM frequency, but reduces the dynamic response of the current control. It is suitable for motors which run at a more-or-less constant speed. Fast decay provides improved current-control dynamic response, but increases the motor current ripple. It is suitable for motors used in start-stop and positioning applications. DIR Determines the direction of motor torque output, as shown in table 3. For an unloaded, low-inertia motor, this will also usually be the direction of mechanical rotation. With a motor that has a high inertial load, the DIR input can be used to apply a controlled breaking torque, when fast decay is used (MODE = 0). BRAKE An active-low input that provides a braking function. When BRAKE = 0 (see table 4), all the low-side FETs are turned on and the high-side FETs are turned off. This effectively shortcircuits the back EMF in the windings, and brakes the motor. The braking torque applied depends on the speed. RESET = 0 or COAST = 0 overrides BRAKE and coasts the motor. Note that when BRAKE is used to dynamically brake the motor, the windings are shorted with no control over the winding current. ESF The state of the enable stop on fault (ESF) pin determines the action taken when a short is detected. See the Diagnostics section for details. TEST Test is for Allegro production use and must be connected to AGND. Current Regulation Load current can be regulated by an internal fixed frequency PWM control circuit or by external input on the PWM pin. Current Sense Amplifier: CSP, CSN, and CSOUT A differential current sense amplifier with a gain, AV, of 19 typical, is provided to allow the use of low-value sense resistors or current shunts as the current sensing elements. Because the output of this sense amplifier is available at CSOUT, it can be used for either internal or external current sensing. With the sense resistor, Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver In some circumstances, it may be desirable to completely disable the internal PWM control. This can be done by pulling the RC pin directly to AGND. This will disable the internal PWM oscillator and ensure that the output of the PWM latch is always high. Blank Time When the source driver is turned on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the current-control comparator output is blanked for a short period of time, tBLANK, when the source driver is turned on. The length of tBLANK is different for internal versus external PWM. It is set by the value of the timing capacitor, CT, according to the following formulas: for internal PWM: tBLANK (μs) = 1260 × CT (μF), and for external PWM: tBLANK (μs) = 2000 × CT (μF) . A nominal CT value of 680 pF yields a tBLANK of 1.3 μs for external PWM, and 860 ns for internal PWM. The user must ensure that CT is large enough to cover the current spike duration when using the internal sense amplifier. Note that there are some circumstances in which the direction reported on the DIRO output pin and the direction demanded on the DIR input pin may not be the same. This may happen if the motor and load have reasonably high inertia. In this case, changing the state of the DIR pin will cause the torque to reverse, braking the motor. During this braking, the direction indicated on the DIRO output will not change. ESF The state of the enable stop on fault (ESF) pin will determine the action taken when a short is detected. For other fault conditions, the action is defined by the type of fault. The action taken follows the states shown in table 2. When ESF = 1, any short fault condition will disable all the gate drive outputs and coast the motor. This disabled state will be latched until the next phase commutation or until COAST or RESET go low. When ESF = 0, under most conditions, although the fault flags, FF1 and FF2, are still activated, the A3930/A3931will not disrupt normal operation and will therefore not protect the motor or the drive circuit from damage. It is imperative that the master control circuit or an external circuit take any necessary action when a fault occurs, to prevent damage to components. If desired, the active low COAST input can be used as a crude disable circuit by connecting the fault flags FF1 and FF2 to the COAST input and a pull-up resistor to V5. FF1, FF2, and VDSTH Fault conditions are indicated by the state of two open drain output fault flags, FF1 and FF2, as shown in table 1. In addition to internal temperature, voltage, and logic monitoring, the A3930/A3931 monitors the state of the external MOSFETs and the motor current to determine if short circuit faults occur or a low load condition exists. In the event that two or more faults are detected simultaneously, the state of the fault flags will be determined by a logical AND of the fault states of each flag. • Undervoltage VREG supplies the low-side gate driver and the bootstrap charge current. It is critical to ensure that the voltages are sufficiently high before enabling any of the outputs. The undervoltage circuit is active during power-up, and will pull both fault flags low and coast the motor (all gate drives low) until VREG is greater than approximately 8 V. Note that this is sufficient to turn on the external power FETs at a battery voltage as low as 5.5 V, but will not normally provide the rated on-resistance of the FET. This could lead to excessive power dissipation in the external FET. Diagnostics Several diagnostic features integrated into the A3930/A3931 provide speed and direction feedback and indications of fault conditions. TACHO and DIRO These outputs provide speed and direction information based on the HE inputs from the motor. As shown in figure 1, at each commutation point, the TACHO output changes state independent of motor direction. The DIRO output is updated at each commutation point to show the motor direction. When the motor is rotating in the “forward” or positive direction, DIRO will be high. When rotation is in the “reverse” or negative direction, DIRO will be low. The actual direction of rotation is determined from the sequence of the three Hall inputs, Hx. Forward is when the sequence follows table 3 top-to-bottom and reverse when the sequence follows table 3 bottom-to-top. DIRO TACHO Commutation Points "Forward" Motor Rotation "Reverse" Motor Rotation Figure 1. Direction Indication Outputs Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 11 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver In addition to a monitor on VREG, the A3930/A3931 also monitors both the bootstrap charge voltage, to ensure sufficient high-side drive, and the 5 V reference voltage at V5, to ensure correct logical operation. If either of these fall below the lockout voltage level, the fault flags are set. • Overtemperature This event pulls both fault flags low but does not disable any circuitry. It is left to the user to turn off the device to prevent overtemperature damage to the chip and unpredictable device operation. • Logic Fault: Hall Invalid The A3930 and the A3931 differ slightly in how they handle error conditions on the Hall inputs, Hx. When all Hx are 1s, both devices evaluate this as an illegal code, and they pull both fault flags, FFx, low and coast the motor. This action can be used, if desired, to disable all FET drives under bridge or motor fault conditions. The Hall logic fault condition is not latched, so if the fault occurs while the motor is running, the external FETs will be reenabled, according to the commutation truth table (table 3), when the Hx inputs become valid. When all Hx are 0s, the A3930 handles this in the same manner as all 1s, described in the preceding paragraph. The A3931, however, evaluates this as a prepositioning code, and does not register it as a fault. The Hx inputs have pull-up resistors to ensure that a fault condition will be indicated in the event of an open connection to a Hall sensor. • Short to Ground A short from any of the motor phase connections to ground is detected by monitoring the voltage across the top FETs in each phase using the appropriate Sx pin and the voltage at VDRAIN. This drain-source voltage is then compared to the voltage on the VDSTH pin. If the drain source voltage exceeds the voltage at the VDSTH pin, FF2 will be pulled low. • Short to Supply A short from any of the motor phase connections to the battery or VBB connection is detected by monitoring the voltage across the bottom FETs in each phase using the appropriate Sx pin and the LSS pin. This drain-source voltage is then compared to the voltage on the VDSTH pin. If the drain source voltage exceeds the voltage at the VDSTH pin, FF2 will be pulled low. • Shorted Motor Winding A short across the motor phase winding is detected by monitoring the voltage across both the top and bottom FETs in each phase. This fault will pull FF2 low. • Low Load Current The sense amplifier output is monitored independently to allow detection of a low load current. This can be used to detect if an open load condition is present. If, during a commutation period, the output from the sense amplifier does not go above a minimum value, VCSOL, FF1 will go low. No further action will be taken. Short Fault Operation Because motor capacitance may cause the measured voltages to show a fault as the phase switches, the voltages are not sampled until one tDEAD interval after the external FET is turned on. If a short circuit fault occurs when ESF = 0, the external FETs are not disabled by the A3930/A3931. Under some conditions, some measure of protection will be provided by the internal current limit but in many cases, particularly for a short to ground, the current limit will provide no protection for the external FETs. To limit any damage to the external FETs or the motor, the A3930/A3931 can either be fully disabled by the RESET input or all FETs can be switched off by pulling the COAST input low. Alternatively, setting ESF = 1 will allow the A3930/A3931 to disable the outputs as soon as the fault is detected. The fault will be latched until any of the following conditions occur: • a phase commutation • RESET goes low • COAST goes low This will allow a running motor to coast to the next phase commutation without the risk of damage to the external power MOSFETs. Low Load Current Fault Operation No action is taken for a low load current condition. If the low load occurs due to an open circuit on a phase connection while the motor is running, the A3930/A3931 will continue to commutate the motor phases according to the commutation truth table, table 3. In some cases, this will allow the motor to continue operating at a much reduced performance. The low load condition is checked during a commutation period and is only flagged at the next commutation event. The flag is cleared at the end of any subsequentcommutation period where no low load current fault is detected. If the motor stalls or is stationary, then the remaining phase connections will usually be insufficient to start rotating the motor. At start-up or after a reset, the low load condition is flagged until the first time the motor current exceeds the threshold value, VCSOL. This allows detection of a possible open phase from startup, even if the motor is not able to start running. Note that a low load current condition can also exist if the motor being driven has no mechanical load. Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 12 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Table 1. Fault Action Table Action* ESF = 0 ESF = 1 0 0 Undervoltage Disable Disable 0 0 Overtemperature No Action No Action 0 0 Logic Fault Disable Disable 1 0 Short to ground No Action Disable 1 0 Short to supply No Action Disable 1 0 Shorted motor winding No Action Disable 0 1 Low load current No Action No Action 1 1 None No Action No Action *Disable indicates that all gate outputs are low and all MOSFETs are turned off. FF1 FF2 Fault Table 2. Commutation Truth Table* Device Both Both Both Both Both Both A3930 A3931 Both Both Both Both Both Both Both H1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 H2 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 H3 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 DIR 1 1 1 1 1 1 X X X 0 0 0 0 0 0 GLA 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 GLB 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 GLC 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 GHA 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 GHB 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 GHC 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 SA High Z Low Low Z High Z High Z Low Z High High Z Low SB Z High High Z Low Low Z Low Z Z Low Low Z High High SC Low Low Z High High Z Z Low Z High High Z Low Low Z *X indicates “don’t care,” Z indicates high impedance state Table 3. INPUT LOGIC MODE 0 0 1 1 X X X PWM 0 1 0 1 X X X BRAKE 1 1 1 1 0 X X COAST 1 1 1 1 1 0 X RESET 1 1 1 1 1 1 0 Decay Fast Fast Slow Slow n/a X X Mode of Operation PWM chop – current decay with opposite of selected drivers ON Peak current limit – selected drivers ON PWM chop – current decay with both low-side drivers ON Peak current limit – selected drivers ON Brake mode - All low-side gates ON Coast mode - All gates OFF Sleep mode – All gates OFF, low power state, 5 V OFF *X indicates “don’t care” Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 13 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Applications Information Power All supply connections to the A3930/A3931 should have capacitors mounted between the supply pins and the ground pin. These capacitors will provide the transient currents which occur during switching and decouple any voltage transients on the pin from the main supply. VBB Decouple with at least a 100 nF ceramic capacitor mounted between the VBB pin and the AGND pin. A larger electrolytic capacitor, typically 10 μF, in parallel with the ceramic capacitor is also recommended. VREG Supplies current for the gate-drive circuit. As the gates are driven high, they require current from an external capacitor connected to VREG to support the transients. This capacitor should be placed as close as possible to the VREG pin with the ground connection close to the AGND pin. Its value should be at least 20 times larger than the bootstrap capacitor. The capacitor should have a very low series resistance (ESR) and inductance (ESL) to avoid large voltage drops during the initial transient. The optimum capacitor type is a high quality ceramic such as X7R. However, when the required capacitance is too large, an aluminium electrolytic capacitor may be used, with a smaller ceramic capacitor (≈100 nF) in parallel. V5 When the 5V regulator is used with an external pass transistor to provide power to other circuits, a 10 μF decoupling capacitor should be connected between the V5 pin and AGND as close to the pins as possible. If an electrolytic capacitor is used, then a 100 nF ceramic capacitor should be added in parallel. To improve stability, a 100 nF capacitor also should be connected between the V5BD pin and AGND. If 5V is not required for external circuits, the external pass transistor may be omitted, but in that case, V5 must connected directly to V5BD and decoupled with at least a 220 nF capacitor between V5 and AGND. AGND The A3930/A3931 has a single ground connection at the AGND pin. The design ensures that only the operating current for the controller stage passes through this pin. The charge and discharge current for the external FETs does not pass though this pin. The AGND pin is the ground reference for the current trip threshold, the VDS monitor threshold, and the timing components. It should therefor be kept as quiet as possible. A suggested ground connection scheme is described in the layout section below. Power Dissipation In applications where a high ambient temperature is expected the on-chip power dissipation may become a critical factor. Careful attention should be paid to ensure the operating conditions allow the A3930/A3931 to remain in a safe range of junction temperature. The power consumed, PTOT , by the A3930/A3931 can be estimated using the following formulas: PTOT = PBIAS + PCPUMP + PSWITCHING , PBIAS = VBB × IBB , where IBB is 3 mA, typical, and PCPUMP = (2 × VBB–VREG) × IAV where VBB < 15 V, or PCPUMP = (VBB–VREG) × IAV where VBB > 15 V, and IAV = QGATE × N × fPWM , PSWITCHING = QGATE × VREG × N × fPWM × Ratio where N = 2 for slow decay, or N = 4 for fast decay, and Ratio = 10 / (RGATE + 10) Bootstrap Capacitors Bootstrap Capacitor Selection The value for CBOOT must be correctly selected to ensure proper operation of the device. If the value is too large, time will be wasted charging the capacitor, resulting in a limit on the maximum duty cycle and PWM frequency. If the value is too small, there can be a large voltage drop at the time when the charge is transferred from CBOOT to the MOSFET gate. To keep the voltage drop small, QBOOT o QGATE . A factor of 20 is a reasonable value. To calculate CBOOT, the following formulas can be used: QBOOT = CBOOT × VBOOT , = QGATE × 20, therefore CBOOT = QGATE × 20 / VBOOT The voltage drop on the Cx pin as the MOSFET is being turned on can be approximated by: ΔV = QGATE / CBOOT Bootstrap Charging It is good practice to ensure that the highside bootstrap capacitor, CBOOT, is completely charged before a Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 14 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver high-side PWM cycle is requested. The minimum time required to charge the capacitor is approximated by: tCHARGE(min) ≈ CBOOT × ΔV /250 mA At power-on, and when the drivers have been disabled for a long time, the CBOOT may be completely discharged. In these cases, ΔV can be considered to be the full high-side drive voltage, 12 V. Otherwise, ΔV is the amount of voltage dropped during the charge transfer, which should be 400 mV or less. The capacitor is charged whenever the Sx pin is pulled low via a GLx PWM cycle, and current flows from VREG through the internal bootstrap diode circuit to CBOOT. Bootstrap Charge Monitor The A3930 and A3931 provide automatic bootstrap capacitor charge management. The bootstrap capacitor voltage for each phase, VBOOTx , is continuously checked to ensure that it is above the bootstrap undervoltage threshold, VBOOTUV. If VBOOT drops below this threshold, the A3930 and A3931 will turn on the necessary low-side FET until the VBOOT exceeds VBOOTUV plus the hysteresis, VBOOTUVHys . The minimum charge time is typically 7 μs, but may be longer for very large values of the bootstrap capacitor (CBOOT >1000 nF). If VBOOT does not exceed VBOOTUV within approximately 200 μs, an undervoltage fault will be flagged, as shown in table 2. PWM Control The A3930 and A3931 have the flexibility to be used in many different motor control schemes. The internal PWM control can be used to provide fully integrated, closed-loop current control. Alternatively, current-mode or voltage-mode control are possible using external control circuits with either the DIR or the PWM input pins. Internal PWM Control The internal PWM current control function is useful in applications where motor torque control or simple maximum current limitation is required. However, for motor speed control applications, it is usually better to use external PWM control either as a closed- or open-loop system. External PWM Control When external PWM control is used, it is possible to completely disable the internal PWM control circuit by connecting the RC pin to AGND. With the internal control disabled, however, care should be taken to avoid excessive current in the power FETs because the A3930/ A3931 will not limit the current. Short-circuit detection will still be available in case of faults. The output of the sense amplifier is also available, but provision must be made in the external control circuits to ignore (blank) the transients at the switching points. External and Internal Combined PWM Control Where external PWM control is used but current limitation is still required, internal PWM current control can be used at the same time as external PWM control. To do so, usually the internal PWM frequency is set lower than the external PWM frequency. This allows the external PWM signal to dominate and synchronize the internal PWM circuit. It does this by discharging the timing capacitor, CT, when the PWM pin is low. When internal and external PWM control are used together, all control features of the A3930/A3931 are available and active, including: dead time, current comparator, and comparator blanking. PWM Frequency Should be set high enough to avoid any audible noise, but low enough to ensure adequate charging of the boot capacitor, CBOOT. The external resistor RT and capacitor CT, connected in parallel from the RC pin to AGND, set the PWM frequency to approximately: fOSC ≈ 1 / (RTCT + tBLANK + tDEAD) . RT should be in the range of 5 to 400 kΩ. PWM Blank The timing capacitor, CT, also serves as the means to set the blank time duration. tBLANK. At the end of the PWM off-cycle, a high-side gate selected by the commutation logic turns on. At this time, large current transients can occur during the reverse recovery time of the intrinsic source drain body diodes of the external power MOSFETs. To prevent false tripping of the current-sense comparator, the output of the current comparator is ignored during the blank time. The length of tBLANK is different for internal versus external PWM. It is set by the value of the timing capacitor, CT, according to the following formulas: for internal PWM: tBLANK (μs) = 1260 × CT (μF), and for external PWM: tBLANK (μs) = 2000 × CT (μF) . A nominal CT value of 680 pF will give a blanking time of 1.3 μs for external PWM and 860 ns for internal PWM. The user must ensure that CT is large enough to cover the current-spike duration. Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 15 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Note that this blank time is only used to mask the internal current comparator. If the current sense amplifier output, CSOUT, is being used in an external PWM control circuit, then it will be necessary to externally generate a blank time for that control loop. Dead Time The potential for cross-conduction occurs with synchronous rectification, direction changes, PWM, or after a bootstrap capacitor charging cycle. To prevent cross-conduction in any phase of the power FET bridge, it is necessary to have a dead-time delay, tDEAD, between a high- or low-side turn-off and the next turn-on event. tDEAD is in the range of between 96 ns and 6.3 μs, and is set by the value of a resistor, RDEAD, between the RDEAD pin and the GND pin. The maximum dead time of typically 6μs can be set by leaving the RDEAD pin unconnected, or connected to the V5 pin. At 25°C, the value of tDEAD (μs) can be approximated by: tDEAD(nom) ≈ 0.1 + 33 / (5 + IDEAD), IDEAD = 2000 / RDEAD where IDEAD is in μA, and RDEAD is between 5 and 400 kΩ. The greatest accuracy is obtained with values of RDEAD between 10 and 100 kΩ. The choice of power MOSFET and external series gate resistance determines the selection of RDEAD. The dead time should be made long enough to cover the variation of the MOSFET gate capacitance and the tolerances of the series gate resistance, both external and internal to the A3930/A3931. Current Trip Points Synchronous Rectification To reduce power dissipation in the external MOSFETs, the A3930/A3931 control logic turns on the appropriate low-side and high-side driver during the load current recirculation PWM-off cycle. Synchronous rectification allows current to flow through the FET selected by the MODE pin setting during the decay time, rather than through the sourcedrain body diode. The body diodes of the recirculating power FETs conduct only during the dead time that occurs at each PWM transition. For internal current control using fast decay mode, reversal of load current is prevented by turning off synchronous rectification when a zero current level is detected. For external PWM control using fast decay mode, the load current will not be limited to zero but will rise to the set current limit in the reverse direction before disabling synchronous rectification. Braking. The A3930 and A3931 provide dynamic braking by forcing all low-side MOSFETs on, and all high-side MOSFETs off. This effectively short-circuits the back EMF of the motor, which forces a reverse current in the windings, and creating a breaking torque. During braking, the load current can be approximated by: IBRAKE ≈ VBEMF / RLOAD Because the load current does not flow through the sense resistor, RSENSE, during a dynamic brake, care must be taken to ensure that the power MOSFET maximum ratings are not exceeded. It is possible to apply a PWM signal to the BRAKE input to limit the motor braking current. However, because there is no measurement of this current, the PWM duty cycle must be determined for each set of conditions. Typically the duty cycle of such a brake PWM input would start at a value which limits the current and then drops to 0%, that is, BRAKE goes to low, to hold the motor stationary. Setting RESET = 1 and COAST = 0 overrides BRAKE and turns all motor bridge FETs off, coasting the motor. Driving a Full-Bridge. The A3930 and A3931 may be used to drive a full-bridge (for example, a brush dc motor load) by hard-wiring a single state for the Hall inputs and leaving the corresponding phase driver outputs floating. For example, with a configuration of H1 = H2 = 1, and H3 = 0, the outputs CC, GHC, SC, and GLC would be floated, according to the commutation truth table, table3, which indicates a state of high-impedence (Z) for SC with that Hall input configuration. The DIR input controls the motor rotation, while the PWM and MODE inputs control the motor current behavior, as described in the input logic table, table 4. GHx tDEAD GLx +V tDEAD VRCH RC VRCL 0 tRC tOSC tBLANK Note: For reasons of clarity, t DEAD is shown exaggerated. Figure 2. Internal PWM RC Timing Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 16 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Circuit Layout Because this is a switch-mode application, where rapid current changes are present, care must be taken during layout of the application PCB. The following points are provided as guidance for layout (refer to figure 3). Following all guidelines will not always be possible. However, each point should be carefully considered as part of any layout procedure. Ground connection layout recommendations: 1. Sensitive connections such as RDEAD and VDSTH, which have very little ground current, should be referenced to the Quiet ground, which is connected independently closest to the AGND pin. The components associated with these sensitive pins should never be connected directly to the Supply common or to the Power ground; they must be referenced directly to the AGND pin. Supply decoupling for the supply pins VBB, VREG, and V5 should be connected to Controller Supply ground, which is connected independently, close to the AGND pin. The decoupling capacitors should also be connected as close as possible to the corresponding supply pin. The oscillator timing components can be connected to Quiet ground or Controller Supply ground. They should not be connected to the Supply common or the Power ground. The exposed thermal pad on the package should be connected to the AGND pin and may form part of the Controller Supply ground. If the layout space is limited, then the Quiet ground and the Controller Supply ground may be combined, provided that the ground return of the dead-time resistor, RDEAD, is close to the AGND pin. 6. 7. The AGND pin should be connected by an independent low impedance trace to the Supply common at a single point. Check the peak voltage excursion of the transients on the LSS pin with reference to the AGND pin using a closegrounded (tip and barrel) probe. If the voltage at LSS exceeds the absolute maximum specified in this datasheet, add additional clamping, capacitance or both between the LSS pin and the AGND pin. Other layout recommendations: 1. Gate charge drive paths and gate discharge return paths may carry large transient current pulses. Therefore, the traces from GHx, GLx, Sx, and LSS should be as short as possible to reduce the inductance of the circuit trace. Provide an independent connection from LSS to the common point of the power bridge. It is not recommended to connect LSS directly to the AGND pin, as this may inject noise into sensitive functions such as the dead-timer. The LSS connection should not be used for the CSP connection. The inputs to the sense amplifier, CSP and CSN, should be independent traces and for best results should be matched in length and route. Minimize stray inductance by using short, wide copper runs at the drain and source terminals of all power FETs. This includes motor lead connections, the input power bus, and the common source of the low-side power FETs. This will minimize voltages induced by fast switching of large load currents. Consider the use of small (100 nF) ceramic decoupling capacitors across the source and drain of the power FETs 2. 2. 3. 3. 4. 4. 5. 5. Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 17 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver to limit fast transient voltage spikes caused by trace inductance. 6. Ensure that the TEST pin is connected to AGND. This pin is used for production test only. The above are only recommendations. Each application is different and may encounter different sensitivities. A driver running with a few amperes will be less susceptible than one running with 150 A, and each design should be tested at the maximum current, to ensure any parasitic effects are eliminated. VBB VREG VDRAIN GHC GHB GHA + Supply V5 A3930 A3931 SA SB SC GLA GLB GLC Motor RC VDSTH RDEAD AGND LSS RSENSE Optional components to limit LSS transients Power Ground Quiet Ground Controller Supply Ground Supply Common Figure 3. Supply and Ground Connections Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 18 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Gate Drive Outputs Cx 18 V GHx 18 V 19 V Sx 20 V VREG 18 V GLx 20 V LSS 18 V 18 V 18 V Sense Amplifier VREG 76k 22V 160μA 4 kΩ CSN 22V 160μA 4 kΩ CSP 2V 32.4 kΩ 72 kΩ 8.5 V 8.5 V 3 kΩ CSOUT 4.6 kΩ Supplies CP1 CP2 VDRAIN VBB V5 V5BD REF 3 kΩ REF 19 V 19 V 19 V 20 V 6V 10 V 8V 8.5 V 18 V 19 V 20 V Logic Inputs COAST ESF BRAKE DIR PWM MODE Hall Sensor Inputs V5 Reset Input 3 kΩ H1 H2 H3 8V 100 kΩ 3 kΩ RESET 3 kΩ 8V 8.5 V 8.5 V 6V 6V 50 kΩ VDS Monitor Threshold Input Oscillator RC Pin V5 Fault Output FF1 FF2 1 kΩ 100 Ω 1 kΩ VDSTH 40 kΩ RC 8V 8.5 V 8V 8.5 V 8V 8V RDEAD Logic Output V5 100 Ω RDEAD 8V 8.5 V 2V TACHO DIRO 8V 100 Ω 8V Figure 3. Input and Output Structures Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 19 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Pin-out Diagrams JP Package 26 GHC 32 GHA 29 GHB 34 GLC 36 GLA 35 GLB 27 CC 33 CA 30 CB 25 SC 24 VDRAIN 23 VDSTH 22 CSP 21 CSN 20 REF 19 CSOUT 18 RDEAD 17 TEST 16 RC 15 MODE 14 PWM 13 NC H3 12 31 SA NC 37 LSS 38 ESF 39 VREG 40 AGND 41 CP1 42 CP2 43 DIRO 44 VBB 45 COAST 46 NC 47 NC 48 Low Side Drives Bootstrapped High-Side Drives Current Sense Charge Pump Control Logic Hall H1 10 H2 11 NC 1 RESET 2 V5BD 3 V5 4 FF2 5 FF1 6 TACHO 7 BRAKE 8 Terminal List Table Number Name Description Number Name Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 N.C. RESET V5BD V5 FF2 FF1 TACHO BRAKE DIR H1 H2 H3 N.C. PWM MODE RC TEST RDEAD CSOUT REF CSN CSP VDSTH VDRAIN No connection Control for sleep mode 5V regulator base drive 5V regulator reference Fault flag 2 Fault flag 1 Speed output Brake input Direction control input Hall sensor input Hall sensor input Hall sensor input No connection Control input Decay control input PWM oscillator control input Test pin; tie to AGND Dead time setting Current sense output Current limit setting Current sense input – Current sense input + Fault threshold voltage High-side drain voltage sense DIR 9 28 SB 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SC GHC CC SB GHB CB SA GHA CA GLC GLB GLA N.C. LSS ESF VREG AGND CP1 CP2 DIRO VBB COAST N.C. N.C. Motor connection phase C High-side gate drive phase C Bootstrap capacitor phase C Motor connection phase B High-side gate drive phase B Bootstrap capacitor phase B Motor connection phase A High-side gate drive phase A Bootstrap capacitor phase A Low-side gate drive phase C Low-side gate drive phase B Low-side gate drive phase A No connection Low-side source Enable stop on fault input Gate drive supply output Analog ground Pump capacitor Pump capacitor Direction output Supply voltage Coast input No connection No connection Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 20 A3930 and A3931 Automotive 3-Phase BLDC Controller and MOSFET Driver Package JP, 48-pin LQFP with Exposed Thermal Pad A B 9.20 .362 8.80 .346 7.20 .283 6.80 .268 7º 0º 0.20 .008 0.09 .004 9.20 .362 8.80 .346 7.20 .283 6.80 .268 B 5.08 .200 NOM 0.75 .030 0.45 .018 48 A 1 .039 REF 1 2 5.08 .200 NOM 0.25 .010 SEATING PLANE GAGE PLANE 48X 0.08 [.003] C 48X 0.27 .011 0.17 .007 0.08 [.003] M C B A 0.50 .020 SEATING PLANE C 1.60 .063 MAX 1.45 .057 1.35 .053 0.15 .006 0.05 .002 Preliminary dimensions, for reference only (reference JEDEC MO-026 BBC) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2006, Allegro MicroSystems, Inc. Subject to Change Without Notice April 6, 2006 Preliminary Data Sheet Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 21