A3938SLQ

A3938 Three-Phase Power MOSFET Controller The A3938 is a three-phase, brushless dc motor controller. The A3938 high-current gate drive capability allows driving of a wide range of power MOSFETs and can support motor supply voltages to 50 V. The A3938 integrates a bootstrapped high-side driver to minimize the external component count required to drive N-channel MOSFET drivers. Internal fixed off-time, PWM current-control circuitry can be used to regulate the maximum load current to a desired value. The peak load current limit is set by the user’s selection of an input reference voltage and external sensing resistor. A user-selected external RC timing network sets the fixed off-time pulse duration. For added flexibility, the PWM input can provide speed/torque control where the internal current control circuit sets a limit on the maximum current. The A3938 includes a synchronous rectification feature. This shorts out the current path through the power MOSFET reverse body diodes during PWM off-cycle current decay. This can minimize power dissipation in the MOSFETs, eliminate the need for external power clamp diodes, and potentially allow a more economical choice for the MOSFET drivers. The A3938 provides commutation logic for Hall sensors configured for 120-degree spacing. The Hall input pins are pulled-up to an internallygenerated 5 V reference. Power MOSFET protection features include: bootstrap capacitor charging current monitor, regulator undervoltage monitor, motor lead short-to-ground, and thermal shutdown. The LD package is available in a lead-free version (100% matte tin plated leadframe). ABSOLUTE MAXIMUM RATINGS Load Supply Voltage, VBB ................................... 50 V VREG (Transient) ...............................................15 V Logic Input Voltage Range, VIN ...–0.3 V to VLCAP +0.3 V Sense Voltage, VSENSE ........................... –5 V to 1.5 V Pins: SA, SB, SC................................... –5 V to 50 V Pins: GHA, GHB, GHC .................. –5 V to VBB + 17 V Pins: CA, CB, CC ...........................SA/SB/SC + 17 V Operating Temperature Range Ambient Temperature, TA............. –20°C to +85°C Junction Temperature, TJ............................ +150°C Storage Temperature, TS .......... –55°C to +150°C Thermal Impedance (Typical), at TA = +25ºC; measured on a JEDEC-standard "High-K" PCB A3938EQ, RθJA ........................................ 37°C/W A3938LD, RθJA ........................................ 38°C/W A3938LQ, RθJA ........................................ 44°C/W 26301.104B Data Sheet A3938EQ, 32-pin PLCC A3938LQ, 36-pin QSOP A3938LD, 38-pin TSSOP FEATURES Drives wide range of N-channel MOSFETs Low-side synchronous rectification Power MOSFET protection Adjustable dead time for cross-conduction protection Selectable coast or dynamic brake on power-down or RESET input Fast/slow current decay modes Internal PWM current control Motor lead short-to-ground protection Internal 5 V regulator Fault diagnostic output Thermal shutdown Undervoltage protection Use the following complete part numbers when ordering: Part Number A3938SEQ A3938SLQ A3938SLD A3938SLD-T Pins 32 36 38 38 Package PLCC QSOP TSSOP TSSOP, Lead-free 26301.104B Three-Phase Power MOSFET Controller Functional Block Diagram (This diagram shows only one of the three outputs) A3938 Data Sheet FAULT Short to GND TSD O.D. Invalid Hall VREG Undervoltage VBB A + VREG Regulator + 10 uF CA CBOOT 0.1 uF 0.1 uF LCAP + 0.1 uF H1 Charge Pump H2 H3 PWM Control Logic High-Side Protection Logic Turn-On Delay High-Side Driver GHA To Phase C DIR RESET SA BRAKE VREG MODE Low-Side Protection Logic RC CT RT RC Blanking Fixed Off-Time Turn-On Delay Low-Side Driver GLA To Phase B SENSE RS REF VREG DEAD Dead-Time Adjust VREGUVLO RESET AGND Power Loss Brake PGND BRKCAP + 4.7uF BRKSEL A For 12 V applications, VBB must be shorted to VREG. For this condition, the absolute maximum rating of 15 V on VREG must be maintained to prevent damage to the A3938. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 2 26301.104B Three-Phase Power MOSFET Controller ELECTRICAL CHARACTERISTICS1,2 Unless otherwise noted: TA = 25°C, VBB = 18 V to 50 V, CLCAP = 0.1 µF, CBOOT = 0.1 µF, CVREG = 10 µF, PWM = 22.5 kHz, square wave, two phases active Characteristics Quiescent Current LCAP Regulator VREG =VBB Supply Voltage Range VREG Output Voltage VREG Load Regulation VREG Line Regulation Control Logic Logic Input Voltage VIN(1) VIN(0) Logic Input Current Gate Drive Low-Side Drive, Output High High-Side Drive, Output High Pull-Up Switch Resistance Pull-Down Switch Resistance Low-Side Switching, 10/90 Rise Time Low-Side Switching, 10/90 Fall Time High-Side Switching, 10/90 Rise Time High-Side Switching, 10/90 Fall Time Propagation Delay; GHx,GLx Rising Propagation Delay; GHx,GLx Falling Dead Time, Maximum Dead Time, Minimum VHGL VHGH RDS(ON) RDS(ON) trGL tfGL trGH tfGH Tpr Tpf tDEAD tDEAD Igx = 0 Igx = 0 Igx = –50 mA Igx = 50 mA Cload = 3300 pF Cload = 3300 pF Cload = 3300 pF Cload = 3300 pF PWM to gate drive out, Cload = 3300 pF PWM to gate drive out, Cload = 3300 pF Vdead = 0, GHx to GLx, Cload = 0 IDEAD = 780 µA, GLx to GHx, Cload = 0 VREG – 0.8 VREG – 0.5 10.4 – – – – – – – – 3.5 50 11.6 14 4 120 60 120 60 220 110 5.6 100 – 12.8 – – – – – – – – 7.6 150 V V Ω Ω ns ns ns ns ns ns µs ns IIN(1) IIN(0) Minimum high level for logical 1 Maximum low level for logical 0 VIN = 2.0 V VIN = 0.8 V 2.0 – –30 –50 – – – – – 0.8 –90 –130 V V µA µA Symbol IVBB VLCAP VREG VREG VREGLOAD VREGLIN Test Conditions RESET = 1, Coast mode, stopped Ilcap = –3.0 mA VREG = VBB, observe maximum rating = 15 V VBB = 13.2 V to 18 V, Ivreg = –10 mA VBB = 18 V to 50 V, Ivreg = –10 mA Ivreg = –1 mA to –30 mA, Coast mode Ivreg = –10 mA, Coast mode Min. – 4.75 10.8 – 12.4 – – Typ.1 – 5 – VBB – 2.5 13 25 40 Max. 8.0 5.25 13.2 – 13.6 – – Units mA V V V V mV mV A3938 Data Sheet Continued on next page... www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3 26301.104B Three-Phase Power MOSFET Controller A3938 Data Sheet ELECTRICAL CHARACTERISTICS1,2 (continued) Unless otherwise noted: TA = 25°C, VBB = 18 V to 50 V, CLCAP = 0.1 µF, CBOOT = 0.1 µF, CVREG = 10 µF, PWM = 22.5 kHz, square wave, two phases active Characteristics Bootstrap Capacitor Bootstrap Capacitor Voltage Bootstrap ROUT Charge Current (Source) Current Limit Circuitry Input Offset Voltage Input Current , Sense pin Input Current , Reference pin Blank Time RC Charge Current RC Voltage Threshold Protection Circuitry Bootstrap Charge Threshold Short to Ground, Drain-Source Monitor VREG Undervoltage Threshold Fault Output Voltage Brake Capacitor Supply Current Low Side Gate Voltage Thermal Shutdown Temperature Thermal Shutdown Hysteresis 1 Symbol Test Conditions Min. Typ.1 Max. Units VCX RCX ICX Icx = 0, Vsx = 0, Vreg = 13 V Icx = –50 mA 10.4 – 100 11.6 9 – 12.8 12 – V Ω mA VIO IB IB tBLANK IRC VRCL VRCH 0 V < Vcmr < 1.5 V 0 V < Vcm, Vdiff < 1.5 V 0 V < Vcm, Vdiff < 1.5 V R = 56 kΩ, C = 470 pF – – – – –0.9 1.0 2.7 – –25 0 0.91 –1 1.1 3.0 ±5 – – – –1.1 1.2 3.3 mV µA µA µs mA V V Icx Vdsh UVLO VOUT IBRAKE VGLBH TJ ∆TJ GHx turns on, and GLx turns off, at Icx VBB – VSX, high side on VREG increasing VREG decreasing IOL = 1 mA VBB = 8 V, BRKSEL = 1 VBB=0, BRKCAP = 8V – 1.3 9.2 8.6 – – – – – –9 2.0 9.7 9.1 – 30 6.6 165 10 – 2.7 10.2 9.6 0.5 – – – – mA V V V V µA V °C °C Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 2 Negative current is defined as conventional current coming out of (sourced from) the specified device terminal. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 4 26301.104B Three-Phase Power MOSFET Controller Pin Descriptions RESET. A logic input that enables the device. Has internal 50 kΩ pull-up to LCAP. Setting RESET to 1 coasts or brakes the motor, depending on the state of the BRKSEL pin. Setting RESET to 0 enables the gate drive to follow commutation logic. Setting RESET to 1 overrides the BRAKE pin. GLA/GLB/GLC. Low-side gate drive outputs for external MOSFET drivers. External series gate resistors can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of Sx outputs. the motor depending on stored setting for BRKSEL). • Thermal shutdown (coasts the motor). • Motor lead (SA/SB/SC) connected to ground (turns off only the high-side power MOSFETs). Only the “short-to-ground” fault is latched, but it is cleared at each commutation. If the motor has stalled due to a shortto-ground being detected, toggling the RESET pin or repeating a power-up sequence clears the fault. A3938 Data Sheet SA/SB/SC. Directly connected to the motor terminals, these pins sense the voltages switched across the load. The pins are also connected to the negative side of the bootstrap capacitors and the negative supply connections for the floating high-side drivers. BRAKE. Logic input for braking function. Setting BRAKE to 1 turns on low-side MOSFETs, and turns off the high-side MOSFETs. This effectively shorts the BEMF in the windings and brakes the motor. Internal 50 kΩ pull-up to LCAP. Setting RESET to 1 overrides this BRAKE pin. See also BRKSEL. GHA/GHB/GHC. High-side gate drive outputs for N-channel MOSFET drivers. External series gate resistors can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of Sx outputs. BRKCAP. This pin is for connection of the reservoir capacitor used to provide the positive power supply for the sink drive outputs for a power-down condition. This allows predictable braking, if desired. Using a 4.7 µF capacitor will provide 6.5 V gate drive for 300 ms. If the power-down braking option is not needed (i.e., BRKSEL = 0), then this pin should be tied to VREG. CA/CB/CC. High-side connections for bootstrap capacitors, providing positive supply for high-side gate drivers. The bootstrap capacitors are charged to approximately VREG when the output Sx terminals go low. When the outputs swing high, the voltages on these pins rise with the outputs to provide the boosted gate voltages needed for the N-channel power MOSFETs. MODE. Logic input to set current-decay mode. In response to a PWM Off command, Slow Decay mode (MODE = 1) switches off the high-side FET, and Fast Decay mode (MODE = 0) switches off the high-side and low-side FETs. Has an internal 50 kΩ pull-up to LCAP. BRKSEL. Logic input to enable/disable braking upon power-down condition or RESET = 1. Internal 50 kΩ pull-up to LCAP. Setting BRKSEL to 0 enables Coast mode. Setting BRKSEL to 1 enables Brake mode. PWM. Speed control input. Setting PWM to 1 turns on MOSFETs selected by Hall input logic. Setting PWM to 0 turns off the selected MOSFETs. Keep the PWM input held high to utilize internal current control circuitry. Internal 50 kΩ pull-up to LCAP. H1/H2/H3. Hall sensor inputs with internal, 50 kΩ pull-ups to LCAP. Configured for 120-degree electrical spacing. RC. Analog input. Connection for RT and CT to set the DIR. Logic input to reverse rotation (see the table Commutation Truth Table, on the next page). Has internal, 50 kΩ pull-up to LCAP. fixed off-time. CT also sets the BLANK time (see the section Application Information). It is recommended that the fixed off-time should not be less than 10 µs. The resistor should be in the range between 10 kΩ and 500 kΩ. VREG. Regulated 13 V supply for the low-side gate drive and the bootstrap capacitor charge circuit. As a regulator, use a 10 µF decoupling/storage capacitor (ESR < 1 Ω) from this pin to AGND, as close to the device pins as possible. Note: For 12 V applications, the VREG pin should be shorted to VBB. FAULT. Open-drain output to indicate fault condition. Will be pulled high (usually by 5.1 kΩ external pull-up) for any of the following fault conditions: • Invalid Hall sensor input code (coasts the motor). • Undervoltage condition detected at VREG (coasts or brakes www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5 26301.104B Three-Phase Power MOSFET Controller A3938 Data Sheet VBB. Motor power supply connection for the A3938 and for power MOSFETs. It is good practice to connect a decoupling capacitor from this pin to AGND, as close to the device pins as possible. DEAD. Analog input. A resistor between DEAD and LCAP is selected to adjust turn-off time to turn-on time. This delay is needed to prevent cross-conduction in the external power MOSFETs. See the section Application Information for details on setting dead time. REF. Analog input to current limit comparator. Voltage applied here sets the peak load current according to the following equation: ITRIP = VREF / RSENSE SENSE. Analog input to the current limit comparator. Voltage representing load current appears on this pin. Voltage transients that are seen at this pin when the drivers turn on are ignored for period of time, tBLANK. LCAP. 5 V reference to power internal logic and provide low current for DEAD pin and FAULT pin. Connection for 0.1 µF external capacitor for decoupling. AGND. Analog reference ground. PGND. Return for low-side gate drivers. This should be connected to the PCB power ground. Commutation Truth Table H1 1 1 1 0 0 0 1 1 1 0 0 0 H2 0 0 1 1 1 0 0 0 1 1 1 0 H3 1 0 0 0 1 1 1 0 0 0 1 1 DIR 1 1 1 1 1 1 0 0 0 0 0 0 GLA 0 0 1 1 0 0 1 0 0 0 0 1 GLB 0 0 0 0 1 1 0 1 1 0 0 0 GLC 1 1 0 0 0 0 0 0 0 1 1 0 GHA 1 0 0 0 0 1 0 0 1 1 0 0 GHB 0 1 1 0 0 0 0 0 0 0 1 1 GHC 0 0 0 1 1 0 1 1 0 0 0 0 SA HI Z LO LO Z HI LO Z HI HI Z LO SB Z HI HI Z LO LO Z LO LO Z HI HI SC LO LO Z HI HI Z HI HI Z LO LO Z Input Logic Mode of Operation** PWM chop – current decay with opposite of selected low0* 0 0 Fast decay side drivers ON. Selected drivers ON. If current limiting, opposite of selected 0* 1 0 Fast Decay low-side drivers ON. 1 0 0 Slow decay PWM chop – current decay with both low-side drivers ON. 1 1 0 Slow Decay Selected drivers ON. If current limiting, both low-side drivers ON. All high-side drivers OFF, low-sides see BRKSEL stored. X X 1 X Clears storable faults. * Low-side, only, Synchronous Rectification mode. **See Commutation Truth Table for meaning of “both” and "selected." MODE PWM RESET Quadrant www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6 26301.104B Three-Phase Power MOSFET Controller Application Information Synchronous Rectification. To reduce power consumption in the external MOSFETs, during the load current recirculation PWM-off cycle, the A3938 control logic turns on the appropriate low-side driver only. The reverse body diode of the power MOSFET conducts only during the dead time required at each PWM transition, as usual. However, unlike full synchronous rectification, the opposite high-side FET’s body diode (not the RdsON) will carry the re-circulating current, be self-extinguishing, and not force the motor to reverse direction. A3938 Data Sheet Decoupling. The internal reference VREG supplies current for the gate drive circuit. As the gates are driven high, they will require current from an external decoupling capacitor to support the transients. This capacitor should be placed as close as possible to the VREG pin. The value of the capacitor should be at least 20 times larger than the bootstrap capacitor. Additionally, a 1 nF (or larger) ceramic monolithic capacitor should be connected between LCAP and AGND, as close to the device pins as possible. Dead Time. To prevent cross-conduction, it is required to have a delay between a high-side or low-side turn-off, and the next turn-on event. The potential for cross-conduction occurs with synchronous rectification, direction changes, PWM, or after a bootstrap capacitor charging cycle. This dead-time is set via a resistor from the DEAD pin to LCAP and can be varied from 100 ns to 5.5 µs. For a nominal case, given: • 25°C ambient temperature, and • 5.6 kΩ < Rdead < 470 kΩ, tdead (nom,ns) = 37 + [(11.9 Protection Circuitry. The A3938 has several protection features: • Bootstrap Monitor. The bootstrap capacitor is charged whenever a sink-side MOSFET is on, an Sx output goes low, or load current recirculates. This happens constantly during normal operation. Note: The high side will not be allowed to turn on before the charging has decayed to less than approximately 9 mA. • Undervoltage. VREG supplies the low-side gate driver and the bootstrap charge current. It is critical to ensure that the voltages are at a proper level before enabling any of the outputs. The undervoltage circuit is active during power-up and signals a fault, and also coasts or brakes (depending on the stored BRKSEL setting) the motor during that time period, until VREG is greater than approximately 10 V. On powering down, a fault is signaled and the motor is coasted or braked, depending on the stored setting for BRKSEL. • Hall Invalid. Illegal codes for the Hall sensor inputs (0,0,0 or 1,1,1) force a fault and coast the motor. Noisy Hall lines may cause Hall code errors, and therefore faults. Additional external pull-up loading and filtering may be required in some systems. Hint: Use dividers to the VREG terminal, than to the LCAP terminal, because the VREG terminal has more current capability. • Thermal Shutdown. Junction temperatures greater than 165°C cause the A3938 to signal a fault and coast the motor. ×10 ) × (R -3 dead + 500)] For predicting worst-case overvoltage and temperature extremes, use the following equations: tdead (min,ns) = 10 + [(6.55 ×10 ) × (R -3 dead + 350)] + 650)] tdead (max,ns) = 63 + [(17.2 ×10 ) ×(R -3 dead For nominal comparison with Idead currents, also at 25°C ambient temperature: Idead = (Vlcap – Vbe) / (Rdead + Rint) where Vlcap = 5 V, Vbe = 0.7 V, and Rint = 500 Ω. Rather than use Rdead values near 470 kΩ, set Vdead = 0 V, which activates an internal (Idead = 10 µA) current source. The choice of power MOSFET and external gate resistance determines the selection of the dead-time resistor. The dead time should be made long enough to cover the variation of the MOSFET capacitance and gate resistor tolerances (both external and internal to the A3938). • Motor Lead. The A3938 signals a fault if the motor lead is shorted to ground. A short-to-ground is assumed after a high- side is turned on and greater than 2 V is measured between the drain (VBB) and source (Sx) of the high-side power MOSFET. This fault is cleared at the beginning of www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 7 26301.104B Three-Phase Power MOSFET Controller each commutation. If a stalled motor results from a fault, the fault can only be cleared by toggling the RESET pin or by a power-up sequence. of the power MOSFETs. To prevent false tripping of the sense comparator, the BLANK function disables the comparator for a time period defined by: tBLANK = 1.9 A3938 Data Sheet Current Regulation. Load current can be regulated by an internal fixed off-time, PWM-control circuit. When the outputs of the MOSFETs are turned on, current increases in the motor winding until it reaches a value given by: ITRIP = VREF / RSENSE At the trip point, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for the fixed offtime period. The current path during recirculation is determined by the configuration of the MODE and SR input pins. The fixed off-time is determined by an external resistor, RT, and capacitor, CT, connected in parallel from the RC terminal to AGND. The fixed off-time is approximated by: tOFF = RT ×C T / (1 × 10 -3 – [2 / RT]) The user must ensure that CT is large enough to cover the current spike duration. Braking. The A3938 dynamically brakes the motor by forcing all low-side power MOSFETs on, and all high-side power MOSFETs off. This effectively short-circuits the BEMF and brakes the motor. During braking, the load current can be approximated by: IBRAKEPEAK = VBEMF / RLOAD As the current does not flow through the sense resistor during a dynamic brake, care should be taken to ensure that the maximum ratings of the power MOSFETs are not exceeded. Note: On its rising edge, a RESET setting of 1 overrides the BRAKE input pin and latches the condition selected by the BRKSEL pin. ×C T tOFF should be in the range between 10 µs and 50 µs. Larger values for tOFF could result in audible noise problems. For proper circuit operation, 10 kΩ < RT < 500 kΩ. Torque control can be implemented by varying the REF input voltage as long as the PWM input stays high. If direct control of the torque/current is desired by PWM input, a voltage can be applied to the REF pin to set an absolute maximum current limit. Power Loss Brake. The BRKCAP and BRKSEL pins provide a power-down braking option. A Power-Loss Brake Trigger Event, which is either an undervoltage on VREG or a RESET = 1 rising edge, is sensed by the A3938, which then dynamically brakes or coasts (depending on the stored BRKSEL setting) the motor. The reservoir capacitor on the BRKCAP pin provides the positive voltage that forces the low-side gates of the power MOSFETs high, keeping them on, even after supply voltage is lost. A stored setting of BRKSEL = 1 brakes the motor, but a stored setting of BRKSEL = 0 coasts it. The combined effect of these settings is shown in the table Brake Control. PWM Blank. The capacitor CT also serves as the means to set the BLANK time duration. At the end of a PWM off-cycle, a high-side gate selected by the commutation logic turns on. At this time, large current transients can occur during the reverse recovery time, trr, of the intrinsic body diodes Brake Control BRAKE 0 0 1 1 BRKSEL 0 1 0 1 Before Power Loss Brake Trigger Event Normal run mode Normal run mode Brake mode – All low-side gate drivers ON Brake mode – All low-side gate drivers ON After Power Loss Brake Trigger Event Coast mode – All gate drive outputs OFF Brake mode – All low-side gate drivers ON Coast mode – All gate drive outputs OFF Brake mode – All low-side gate drivers ON www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8 26301.104B Three-Phase Power MOSFET Controller Terminal List Name PGND RESET GLC SC GHC CC GLB SB GHB CB GLA SA GHA CA VREG LCAP FAULT MODE VBB H1 H3 H2 DIR BRAKE BRKCAP BRKSEL PWM RC SENSE REF DEAD AGND N/C Description Low-Side Gate Drive Return Control Input Low-Side Gate Drive Output, Phase C Motor Connection, Phase C High-Side Gate Drive Output, Phase C Bootstrap Capacitor, Phase C Low-Side Gate Drive Output, Phase B Motor Connection, Phase B High-Side Gate Drive Output, Phase B Bootstrap Capacitor, Phase B Low-Side Gate Drive Output, Phase A Motor Connection, Phase A High-Side Gate Drive Output, Phase A Bootstrap Capacitor, Phase A Gate Drive Supply 5 V Output Diagnostic Output Control Input Load Supply Hall Control Input Hall Control Input Hall Control Input Control Input Control Input Power Loss Brake Reservoir Capacitor Control Input Control Input Connection for Fixed Off-Time R and C Sense Resistor Current Limit Adjust Dead Time Adjust Ground Not Connected 32-Lead A3938EQ PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 36-Lead A3938LQ QSOP 36 1 2 3 6 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 24 25 26 27 28 29 30 31 32 33 34 35 4,5,18,23 38-Lead A3938LD TSSOP 36 1 2 3 6 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 24 25 26 27 28 29 30 31 32 33 34 35 4, 5, 18, 23, 37, 38 A3938 Data Sheet www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 9 26301.104B Three-Phase Power MOSFET Controller A3938EQ, 32-pin PLCC .495 12.57 .485 12.32 2 RESET 1 PGND 32 AGND 31 DEAD 3 GLC 30 REF .453 11.51 .447 11.35 1 32 .013 0.32 .008 0.19 A3938 Data Sheet GHC 5 CC 6 GLB 7 SB 8 GHB 9 CB 10 GLA 11 SA 12 GHA 13 CA 14 VREG 15 LCAP 16 FAULT 17 MODE 18 VBB 19 H1 20 Fault 4 SC 29 SENSE 28 RC 27 PWM 26 BRKSEL 25 BRKCAP 24 BRAKE Control Logic 23 DIR 22 H2 21 H3 .015 0.38 MIN Seating Plane Base Plane .021 0.53 .013 0.33 .050 1.27 BSC .553 14.05 .547 13.89 .595 15.11 .585 14.86 .140 3.56 .125 3.18 .095 2.41 .060 1.52 Dimensions in inches Metric dimensions (mm) in brackets, for reference only If unit is intended to be socketed, it is advisable to review lead profile with socket supplier A3938LQ, 36-pin QSOP 15.40 .606 15.20 .598 RESET 1 GLC 2 SC 3 N/C 4 N/C 5 GHC 6 CC 7 GLB 8 SB 9 GHB 10 CB 11 GLA 12 SA 13 GHA 14 CA 15 VREG 16 LCAP 17 N/C 18 Fault 36 PGND 35 AGND 34 DEAD 33 REF 32 SENSE 31 RC 30 PWM 29 BRKSEL 28 BRKCAP 27 BRAKE Control Logic 26 DIR 25 H2 24 H3 23 N/C 22 H1 21 VBB 20 MODE 19 FAULT 0.51 .020 0.28 .011 0.85 .033 BSC 7.60 .299 7.40 .291 10.51 .414 10.11 .398 36 8º 0º 0.32 .013 0.23 .009 1.27 .050 0.40 .016 1 2 .355 0.014 BSC Seating Plane Gauge Plane 2.64 .104 2.44 .096 0.30 .012 0.10 .004 0.80 .031 REF Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 10 26301.104B Three-Phase Power MOSFET Controller A3938 Data Sheet A3938LD, 38-pin TSSOP RESET 1 GLC 2 SC 3 N/C 4 N/C 5 GHC 6 CC 7 GLB 8 SB 9 GHB 10 CB 11 GLA 12 SA 13 GHA 14 CA 15 VREG 16 LCAP 17 N/C 18 FAULT 19 Fault 38 N/C 37 N/C 36 PGND 35 AGND 34 DEAD 33 REF 32 SENSE 31 RC 30 PWM 29 BRKSEL Control Logic 28 BRKCAP 27 BRAKE 26 DIR 25 H2 24 H3 23 N/C 22 H1 21 VBB 20 MODE 0.27 0.011 0.17 0.007 1 2 4.5 0.177 4.3 0.169 6.4 0.252 BSC 38 9.8 9.6 0.386 0.378 8º 0º 0.20 0.008 0.09 0.004 1 0.039 REF 0.75 0.030 0.45 0.018 .25 0.010 BSC Seating Plane Gauge Plane .50 .020 BSC 0.15 0.05 Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only 1.10 0.043 MAX 0.006 0.002 The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2003 AllegroMicrosystems, Inc. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 11