A3940KLW

3940 FULL-BRIDGE POWER MOSFET CONTROLLER — For Automotive Applications 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28 27 26 25 24 23 22 21 20 19 18 17 16 15 The A3940KLP and A3940KLW are designed specifically for automotive applications that require high-power motors. Each provides four high-current gate drive outputs capable of driving a wide range of n-channel power MOSFETs in a full-bridge configuration. Bootstrap capacitors are utilized to provide the above-battery supply voltage required for n-channel FETs. An internal charge pump for the high side allows for dc (100% duty cycle) operation of the bridge. Protection features include supply under/overvoltage, thermal shutdown, and motor lead short-to-battery and short-to-ground fault notification, and a programmable dead-time adjustment for crossconduction prevention. The overvoltage trip point is user adjustable. The A3940 is supplied in a choice of two power packages, a 28-pin TSSOP with an exposed thermal pad (package type LP), and a 28-pin wide-body SOIC (package type LW). Both package types are available in lead (Pb) free versions, with 100 % matte-tin leadframe plating (suffix –T). Data Sheet 29319.100i 4 5 6 7 8 9 10 11 12 13 14 A3940KLP (TSSOP with exposed thermal pad) A3940KLW (SOIC) Approx. 2X actual size. ABSOLUTE MAXIMUM RATINGS Load Supply Voltage Range, VBB, VDRAIN, CP1 .......... -0.6 V to +40 V Output Voltage Ranges, LSS .............................. -2 V to +6.5 V GHA/GHB, VGHX ........ -2 V to +55 V SA/SB, VSX .................. -2 V to +45 V GLA/GLB, VGLX .......... -2 V to +16 V CA/CB, VCX .............. -0.6 V to +55 V CP2,VCP, VIN .......... -0.6 V to +52 V Logic Input/Output Voltage Range VIN, VOUT ................... -0.3 V to +6.5 V Operating Temperature Range, TA ........................... -40°C to +135°C Junction Temperature, TJ ......... +150°C* Storage Temperature Range, TS ........................... -55°C to +150°C * Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided. FEATURES Drives wide range of n-channel MOSFETs Charge pump to boost gate drive at low-battery-input conditions Bootstrapped gate drive with charge pump for 100% duty cycle Synchronous rectification Fault diagnostic output Adjustable dead-time cross-conduction protection Motor lead short-to-battery and short-to-ground protection Undervoltage/overvoltage protection -40°C to +150°C, TJ operation Thermal shutdown Always order by complete part number Part Number A3940KLP-T A3940KLP A3940KLW-T A3940KLW Pb-free Yes – Yes – Package 28-pin TSSOP 28-pin TSSOP 28-pin SOICW 28-pin SOICW 3940 FULL-BRIDGE POWER MOSFET CONTROLLER Functional Block Diagram See pages 7 and 8 for terminal assignments and descriptions. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2003 Allegro MicroSystems, Inc. 2 3940 FULL-BRIDGE POWER MOSFET CONTROLLER A3940KLP (TSSOP) A3940KLW (SOIC) * Measured on “High-K” multi-layer PWB per JEDEC Standard JESD51-7. † Measured on typical two-sided PWB . The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. www.allegromicro.com 3 3940 FULL-BRIDGE POWER MOSFET CONTROLLER ELECTRICAL CHARACTERISTICS: unless otherwise noted at TA = -40°C to +135°C, TJ = -40°C to +150°C, VIN ≤ VBB = 7 V to 40 V, Cp = 0.47 µF, Cr = 1 µF, CREG5 = 0.1 µF, CREG13 = 10 µF, CBOOT = 0.1 µF, PWM = 22.5 kHz square wave. Characteristics Power Supply VBB Quiescent Current IBB RESET = 1, VBB = VIN = 40 V, VIN ≠ VCP, coast, stopped, CP disabled, IDEAD = 170 µA RESET = 1, VBB = VIN = 15 V, VIN ≠ VCP, coast, stopped, CP disabled, IDEAD = 170 µA RESET = 1, VBB = VIN = 40 V, VIN ≠ VCP, coast, stopped, IDEAD = 170 µA, ICP = 0 mA RESET = 1, VBB = VIN = 15 V, VIN ≠ VCP, coast, stopped, IDEAD = 170 µA, ICP = 0 mA RESET = 1, VBB = VIN = 40 V, VIN ≠ VCP, coast, stopped, IDEAD = 170 µA, ICP = 15 mA RESET = 1, VBB = VIN = 15 V, VIN ≠ VCP, coast, stopped, IDEAD = 170 µA, ICP = 15 mA RESET = 0 No load IREG5 = 4.0 mA IREG5 = 0 - 4.0 mA, VBB = 40 V VBB = 40 V, VREG5 = 0 VBB = 14 - 40 V, ICP = 15 mA VBB = 7 V, ICP = 15 mA SR = 1, MODE = 0, ENABLE = PWM ICP = 15 mA, VBB = 14 V - 40 V VIN = VCP, VBB = 14 V - 40 V VIN = VCP, VBB = 7 V RESET = 1, VBB = VIN = 40 V, coast, stopped VIN = 15 V, no load IREG13 = 15 mA, VIN = 11 V - 14 V VIN = 15 V - 40 V, IREG13 = 15 mA VIN = 40 V, IREG13 = 0 - 15 mA VIN = 40 V, VREG13 = 0 (pulse) RESET = 0 to VREG5 = 4 V RESET = 1 to VREG13, UV cleared – – – – – – – 4.5 – – – 11.7 15 – – – – 12.6 – – – – 10 – 4.8 4.3 5.0 4.8 35.4 35.1 – 5.0 5.0 5.0 28 13 – 500 2.5 3.5 1.4 13.3 0.7 2.0 2.0 60 30 1.4 7.0 7.0 7.0 7.0 40.0 40.0 1.0 5.5 – – – 13.8 – – – – – 14.0 – – – – – – mA mA mA mA mA mA µA V mV mV mA V V mA mV ms ms mA V V mV mV mA µs ms Symbol Conditions Min Limits Typ Max Units VREG5 Output Voltage VREG5 Line Regulation VREG5 Load Regulation VREG5 Short-Circuit Current VCP Output Voltage Level VCP Gate Drive VCP Output Voltage Ripple VCP Pump-Up time VREG13 Quiescent Input Current VREG13 Output Voltage VREG13 Dropout Voltage VREG13 Line Regulation VREG13 Load Regulation VREG13 Short-Circuit Current Go-to-Sleep Response Time Wake-Up Response Time VREG5 VREG5 VREG5 IREG5M VCP ICP VCP(PP) tup IREG13 VREG13 VREGDV VREG13 VREG13 IREG13M tsleep twake VBB+9.5 VBB+10.7 VBB+11.8 NOTES: Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. Continued next page … 4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3940 FULL-BRIDGE POWER MOSFET CONTROLLER ELECTRICAL CHARACTERISTICS: unless otherwise noted at TA = -40°C to +135°C, TJ = -40°C to +150°C, VIN ≤ VBB = 7 V to 40 V, Cp = 0.47 µF, Cr = 1 µF, CREG5 = 0.1 µF, CREG13 = 10 µF, CBOOT = 0.1 µF, PWM = 22.5 kHz square wave. Characteristics Control Logic Logic Input Voltage VIN(1) VIN(1) VIN(0) IIN(1) IIN(0) IIN(0) VDSL(H) IxU rSDU(on) tr VDSL(L) IxL rDSL(on) tf tpd tsk(o) tdead HIGH level input (Logic 1), except RESET. HIGH level input (Logic 1) for RESET LOW level input (Logic 0) VIN = 2.0 V VIN = 0.8 V, except RESET(0) VIN = 0.8 V, RESET(0) GHx: IxU = -10 mA, Vsx = 0 GLx: IxU = -10 mA, Vlss = 0 VSDU = 10 V, TJ = 25°C VSDU = 10 V, TJ = 135°C IxU = -150 mA, TJ = 25°C IxU = -150 mA, TJ = 135°C Measure VDSL, 20% to 80%, CL = 3300 pF GHx: IxL = 10 mA, Vsx = 0 GLx: IxL = 10 mA, Vlss = 0 VDSL = 10 V, TJ = 25°C VDSL = 10 V, TJ = 135°C IxL = +150 mA, TJ = 25°C IxL = +150 mA, TJ = 135°C Measure VDSL, 80% to 20%, CL = 3300 pF Logic input to unloaded GHx, GLx Grouped by rising or falling edge LONG = 0, RDEAD = 12.1 kΩ (IDEAD = 167 µA) LONG = 0, RDEAD = 499 kΩ (IDEAD = 4 µA) LONG = 1, RDEAD = 12.1 kΩ (IDEAD = 167 µA) LONG = 1, RDEAD = 499 kΩ (IDEAD = 4 µA) 2.0 2.2 – – – – – – – 40 16 – – – 0.8 100 40 1.0 VREG13 VREG13 – – 13 23 – 150 150 – – 6.0 7.5 – 225 50 – 11.0 – 345 V V V µA µA µA V V mA mA Ω Ω ns mV mV mA mA Ω Ω ns ns ns µs µs µs µs Symbol Conditions Min Limits Typ Max Units Logic Input Current Gate Drives, GHx, GLx ( internal SOURCE or upper switch stages) Output High Voltage Source Current (pulsed) Source ON Resistance Source Load Rise Time Output Low Voltage Sink Current (pulsed) Sink ON Resistance Sink Load Fall Time Gate Drives, GHx, GLx (General) Propagation Delay Output Skew Time Dead Time (Shoot-Through Prevention) Between GHx, GLx transitions of same phase – – 0.3 – 8.3 – – – – – – – VREG13 - 2.2 – VREG13 - 0.2 – – 700 400 – 4.0 – 7.0 – – 90 – – – 550 1.8 3.0 – – – 800 – – – 70 Gate Drives, GHx, GLx ( internal SINK or lower switch stages) NOTES: Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. For GHX: VSDU = VCX – VGHX, VDSL = VGHX – VSX, VDSL(H) = VCX – VSDU – VSX. For GLX: VSDU = VREG – VGLX, VDSL = VGLX – VLSS, VDSL(H) = VREG – VSDU – VLSS. Continued next page … www.allegromicro.com 5 3940 FULL-BRIDGE POWER MOSFET CONTROLLER ELECTRICAL CHARACTERISTICS: unless otherwise noted at TA = -40°C to +135°C, TJ = -40°C to +150°C, VIN ≤ VBB = 7 V to 40 V, Cp = 0.47 µF, Cr = 1 µF, CREG5 = 0.1 µF, CREG13 = 10 µF, CBOOT = 0.1 µF, PWM = 22.5 kHz square wave. Characteristics Bootstrap Circuit Diode Forward Current Limit Diode Forward Drop Diode Resistance Top-off CP Source Current at Cx Fault Logic VBB Undervoltage VBB Undervoltage Hysteresis VREG13 Undervoltage VREG13 Undervoltage Hyst. VBB Overvoltage VBB(uv) ∆VBB(uv) VREG13(uv) ∆VREG13(uv) VBB(ov) Decreasing VBB VBB(recovery) - VBB(uv) Decreasing VIN VREG13(recovery) - VREG13(uv) Increasing VBB, FAULT = 0 to 1, VOVSET = 0 V Increasing VBB, FAULT = 0 to 1, VOVSET = 0.45 V Increasing VBB, FAULT = 0 to 1, VOVSET = 0.9 V VBB(ov) - VBB(recovery) 0 V < VSET(ov) < 0.9 V 0.3 V < VDSTH < 3 V VDSTH = 0.3 V VDSTH = 1.0 V VDSTH = 3.0 V VDSTH = 0.3 V VDSTH = 1.0 V VDSTH = 3.0 V If VDRAIN < VDO(th), FAULT = 0 to 1 RESET = 0 RESET = 1, VDSTH < 3 V RESET = 0, pulse From RESET = 1 to FAULT = 0 Iout = 5 mA, faults negated Vout = 5 V, open-drain, fault asserted TJ increasing TJ decreasing 4.5 200 7.5 200 16 24 32.5 2.1 – – VDSTH-0.14 VDSTH-0.18 VDSTH-0.39 VDSTH-0.20 VDSTH-0.24 VDSTH-0.37 1.0 – – 0.15 – – – – – – 5.25 450 8.25 450 19.6 28 36.4 3.1 – – – – – – – – – – – – 2.0 1.7 – – 172 12 6.0 700 9.0 700 22 30.5 39 4.1 1.4 1.0 VDSTH+0.10 VDSTH+0.13 VDSTH+0.26 VDSTH+0.30 VDSTH+0.30 VDSTH+0.30 3.0 1.0 500 2.0 – – 0.4 1.0 – – V mV V mV V V V V µA µA V V V V V V V µA µA µs µs µs V µA °C °C ICX VF RF Icx 3 V < [(VREG13 = 13.5 V) - VCX] < 12 V IF = 10 mA RF(100) = [VF(150) - VF(50)]/100 VCX - VSX = 8 V, VBB = 40 V, GHx = 1(no load) 140 0.8 1.5 40 – – – – 1000 2.0 6.5 – mA V Ω µA Symbol Conditions Min Limits Typ Max Units VBB Overvoltage Hysteresis OVSET Input Current VDSTH Input Current Short-to-Ground Threshold ∆VBB(ov) ISET(ov) IDSTH VSTG(th) y Short-to-Battery Threshold VSTB(th) VDRAIN /Open Bridge Threshold VDRAIN /Open Bridge Current Fault Fault Fault Fault Latch Clear Pulsewidth Clear Propagation Delay Detection Noise Filter Output VDO(th) IVDRAIN tlatch tpd tnoise Vout(0) Iout(1) TJ ∆TJ Thermal Shutdown Temperature Thermal Shutdown Hysteresis NOTES: Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. 6 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3940 FULL-BRIDGE POWER MOSFET CONTROLLER Terminal Functions Terminal Name VDRAIN LSS GLB SB GHB CB VIN VREG13 CA GHA SA GLA VBB CP2 VCP CP1 GND FAULT OVSET VREG5 MODE SR ENABLE PHASE RESET LONG IDEAD VDSTH Function Kelvin connection to MOSFET high-side drains Gate-drive source return, low-side Gate-drive B output, low-side Motor phase B input Gate-drive B output, high-side Bootstrap capacitor B Regulated 13 V gate drive supply input Regulated 13 V gate drive supply output Bootstrap A capacitor Gate-drive A output, high-side Motor phase A input Gate-drive A output, low-side Battery supply Charge pump connection for pumping capacitor Charge pump output Charge pump connection for pumping capacitor Common ground and dc supply returns Electrically connected to exposed thermal pad of LP package Open-drain fault output DC input, overvoltage threshold setting for VBB Regulated 5 V supply output Control input Control input Control input Control input Control input Control input, long or short deadtime Adjust current for basic deadtime DC input, drain-to-source monitor threshold voltage Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 www.allegromicro.com 7 3940 FULL-BRIDGE POWER MOSFET CONTROLLER Terminal Descriptions CA/CB. High-side connection for bootstrap capacitor, positive supply for high-side gate drive. The bootstrap capacitor is charged to VREG13 – 1.5 V when the output Sx terminal is low. When the output swings high, the voltage on this terminal rises with the output to provide the boosted gate voltage needed for nchannel power MOSFETs. RESET. Control input to put device into minimum power consumption mode and to clear latched faults. Logic “1” enables the device; logic “0” triggers the sleep mode. Internally pulled down via 50 kΩ resistor. ENABLE. Logic “1” enables direct control of the output drivers via the PHASE input, as in PWM controls, and ignores the MODE and SR inputs. Internally pulled down via 50 kΩ resistor. MODE. Logic input to set the current decay mode. Logic “1” (slow-decay mode) switches off the high-side MOSFET in response to a PWM “off” command. Logic “0” (fast-decay mode) switches off both the high-side and low-side MOSFETs. Internally pulled down via 50 kΩ resistor. PHASE. Motor direction control. When logic “1”, enables gate drive outputs GHA and GLB allowing current flow from SA to SB. When logic “0”, enables GHB and GLA allowing current flow from SB to SA. Internally pulled down via 50 kΩ resistor. SR. When logic “1”, enables synchronous rectification; logic “0” disables the synchronous rectification. Internally pulled down via 50 kΩ resistor. FAULT. Open drain, diagnostic logic output signal. When logic “1”, indicates that one or more fault conditions have occurred. Use an external pullup resistor to VREG5 or to digital controller. Internally causes a coast when asserted. See also Functional Description, next page. IDEAD. Analog current set by resistor (12 kΩ