A3941KLPTR-T

A3941 Automotive Full Bridge MOSFET Driver Features and Benefits ▪ High current gate drive for N-channel MOSFET full bridge ▪ High-side or low-side PWM switching ▪ Charge pump for low supply voltage operation ▪ Top-off charge pump for 100% PWM ▪ Cross-conduction protection with adjustable dead time ▪ 5.5 to 50 V supply voltage range ▪ Integrated 5 V regulator ▪ Diagnostics output ▪ Low current sleep mode Description The A3941 is a full-bridge controller for use with external N-channel power MOSFETs and is specifically designed for automotive applications with high-power inductive loads, such as brush DC motors. A unique charge pump regulator provides full (>10 V) gate drive for battery voltages down to 7 V and allows the A3941 to operate with a reduced gate drive, down to 5.5 V. A bootstrap capacitor is used to provide the above-battery supply voltage required for N-channel MOSFETs. An internal charge pump for the high-side drive allows DC (100% duty cycle) operation. The full bridge can be driven in fast or slow decay modes using diode or synchronous rectification. In the slow decay mode, current recirculation can be through the high-side or the lowside FETs. The power FETs are protected from shoot-through by resistor adjustable dead time. Integrated diagnostics provide indication of undervoltage, overtemperature, and power bridge faults, and can be configured to protect the power MOSFETs under most short circuit conditions. The A3941 is supplied in a 28-pin TSSOP power package with an exposed thermal pad (suffix LP). This package is lead (Pb) free, with 100% matte-tin leadframe plating. Package: 28-pin TSSOP with exposed thermal pad (suffix LP) Not to scale Typical Application VBAT PWM Direction A3941 Fault Flags 3941-DS, Rev. 2 A3941 Automotive Full Bridge MOSFET Driver Selection Guide Part Number A3941KLP-T A3941KLPTR-T Packing 50 pieces per tube 4000 pieces per reel Absolute Maximum Ratings* Characteristic Load Supply Voltage Logic Inputs and Outputs V5 Pin LSS Pin VDSTH Pin SA and SB Pins VDRAIN Pin GHA and GHB Pins GLA and GLB Pins CA and CB Pins Operating Temperature Range Junction Temperature Transient Junction Temperature Storage Temperature Range ESD Rating, Human Body Model ESD Rating, Charged Device Model *With respect to GND. TA TJ(max) TtJ Tstg AEC-Q100-002, all pins AEC-Q100-011, all pins Overtemperature event not exceeding 1 s, lifetime duration not exceeding 10 hr; guaranteed by design characterization Range K Symbol VBB Notes Rating –0.3 to 50 –0.3 to 6.5 –0.3 to 7 –4 to 6.5 –0.3 to 6.5 –5 to 55 –5 to 55 Sx to Sx+15 –5 to 16 –0.3 to Sx+15 –40 to 150 150 175 –55 to 150 2000 1050 Units V V V V V V V V V V ºC ºC ºC ºC V V THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Package Thermal Resistance Symbol RθJA RθJP *Additional thermal information available on Allegro website. Test Conditions* 4-layer PCB based on JEDEC standard 2-layer PCB with 3.8 in.2 of copper area each side Value 28 32 2 Units ºC/W ºC/W ºC/W Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A3941 Automotive Full Bridge MOSFET Driver Functional Block Diagram Battery + CP VBB CP2 CP1 Charge Pump Regulator VBAT VREG CREG V5 +5V Reg FF1 FF2 VDSTH Diagnostics and Protection Charge Pump Bootstrap Monitor VDRAIN CA GHA CBOOTA High Side RGHA SA RGHB PWMH PWML Low Side GLA RGLA LSS RGLB Control Logic PHASE Charge Pump Bootstrap Monitor CB CBOOTB SR High Side GHB SB RESET Low Side LSS RDEAD GND PAD GLB Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A3941 Automotive Full Bridge MOSFET Driver ELECTRICAL CHARACTERISTICS valid at TJ = –40°C to 150°C, VBB = 7 to 50 V, unless noted otherwise Characteristics Supply and Reference Load Supply Voltage Functional Operating Range1 Load Supply Quiescent Current VBB IBBQ IBBS RESET = high, outputs = low, VBB = 12 V RESET = low, Sleep mode, VBB = 12 V VBB > 9 V, IREG = 0 to 10 mA 7.5 V < VBB ≤ 9 V, IREG = 0 to 7 mA VREG Output Voltage VREG 6 V < VBB ≤ 7.5 V, IREG = 0 to 7 mA 5.5 V < VBB ≤ 6 V, IREG < 5.5 mA V5 Output Voltage V5 Line Regulation V5 Load Regulation V5 Short-Circuit Current Bootstrap Diode Forward Voltage Bootstrap Diode Resistance Bootstrap Diode Current Limit Top-off Charge Pump Current Limit High-Side Gate Drive Static Load Resistance V5(out) V5(line) V5(load) I5M VfBOOT rD IDBOOT ITOCPM RGSH tr tf RDS(on)UP RDS(on)DN VGHX VGLX tP(off) tP(on) ∆tPP ∆tOO Input change to unloaded gate output change Input change to unloaded gate output change Measured between corresponding transition points on both phases Measured across one phase RDEAD = 3 kΩ Dead Time2 tDEAD RDEAD = 30 kΩ RDEAD = 240 kΩ RDEAD tied to V5 CLOAD = 1 nF, 20% to 80% CLOAD = 1 nF, 80% to 20% TJ = 25°C, IGHx = –150 mA TJ = 150°C, IGHx = –150 mA TJ = 25°C, IGLx = 150 mA TJ = 150°C, IGLx = 150 mA Bootstrap capacitor fully charged No load I5 = –2 mA I5 = 0 to –2 mA VBB = 40 V, V5 = 0 V ID = 10 mA ID = 100 mA rD(100mA) = (VfBOOT(150mA) – VfBOOT(50mA)) / 100 mA 5.5 – – 12.5 12.5 2×VBB – 2.5 8.5 4.5 – – – 0.4 1.5 6 250 – 250 – – 6 10 2 3 VCx – 0.2 VREG – 0.2 60 60 – – – 815 – – – 10 – 13 13 – 9.5 5 15 50 28 0.7 2.2 10 500 400 – 35 20 8 13 3 4.5 – – 90 90 10 10 180 960 3.5 6 50 14 10 13.75 13.75 – – 5.5 40 100 30 1.0 2.8 20 750 – – – – 12 16 4 6 – – 150 150 – – – 1110 – – V mA μA V V V V V mV mV mA V V Ω mA μA kΩ ns ns Ω Ω Ω Ω V V ns ns ns ns ns ns μs μs Symbol Test Conditions Min. Typ. Max. Units Gate Output Drive Turn-On Time Turn-Off Time Pullup On Resistance Pulldown On Resistance GHx Output Voltage GLx Output Voltage Turn-Off Propagation Delay2 Turn-On Propagation Delay2 Propagation Delay Matching, Phase-to-Phase Propagation Delay Matching, On-to-Off Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A3941 Automotive Full Bridge MOSFET Driver ELECTRICAL CHARACTERISTICS (continued) valid at TJ = –40°C to 150°C, VBB = 7 to 50 V, unless noted otherwise Characteristics Logic Inputs and Outputs FF1 and FF2 Fault Output (Open Drain) FF1 and FF2 Fault Output Leakage Current3 RDEAD Current3 Input Low Voltage Input High Voltage Input Hysteresis (Except RESET Pin) Input Hysteresis (RESET Pin) Input Current (Except RESET Pin)3 Input Pulldown Resistor (RESET Pin) RESET Pulse Time VFF(L) IFF(H) IDEAD VIN(L) VIN(H) VINhys VINRSThys IIN RPD tRES VREGUVon VREGUVoff VBOOTUV VBOOTUVhys V5UVoff V5UVhys VDSTH IDSTH VDSDIS VDRAIN IDRAIN VSTGO VSTBO TJF TJFhys 0 V < VDSTH < 2 V When not connected directly to V5 VDSTH = 2 V, VBB = 12 V, VDSTH = 2 V, VBB = 12 V, 0 V < VDRAIN < VBB High-side on, VDSTH ≥ 1 V High-side on, VDSTH < 1 V Low-side on, VDSTH ≥ 1 V Low-side on, VDSTH < 1 V Temperature increasing Recovery = TJF – TJFhys V5 falling VREG rising VREG falling Cx with respect to Sx 0 V < VIN < V5 IFF = 1 mA, fault not present VFF = 5 V, fault present RDEAD = GND – –1 –200 – 3.5 300 200 –1 – 0.1 7.5 6.75 59 – 3.4 300 0.1 – 4.95 7 – – –150 – –150 150 – – – – – – 500 – – 50 – 8 7.25 – 13 3.6 400 – 10 – VBB – ±100 ±50 ±100 ±50 170 15 0.4 1 –70 1 – – – 1 – 3.5 8.5 7.75 69 – 3.8 500 2 30 – 50 250 – 150 – 150 – – V μA μA V V mV mV μA kΩ μs V V %VREG %VREG V mV V μA V V μA mV mV mV mV ºC ºC Symbol Test Conditions Min. Typ. Max. Units Protection VREG Undervoltage Lockout Threshold Bootstrap Undervoltage Threshold Bootstrap Undervoltage Hysteresis V5 Undervoltage Turn-Off Threshold V5 Undervoltage Hysteresis VDSTH Input Range VDSTH Input Current VDSTH Disable Voltage VDRAIN Input Voltage VDRAIN Input Current Short-to-Ground Threshold Offset4 Short-to-Battery Threshold Offset5 Overtemperature Fault Flag Threshold Overtemperature Fault Hysteresis 1Functions correctly, but parameters are not guaranteed, below the general limits (7 V). 2See Gate Drive Timing diagrams. 3For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 4As V Sx decreases, fault occurs if VBAT –VSx > VSTG. STG threshold, VSTG = VDSTH + VSTGO . 5As V Sx increases, fault occurs if VSx – VLSS > VSTB . STB threshold, VSTB = VDSTH+VSTBO . Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A3941 Automotive Full Bridge MOSFET Driver Timing Diagrams PWMH PWML tDEAD GHx GLx tP(off) Synchronous Rectification tDEAD tP(off) xHI xLO tP(on) GHx GLx tP(off) xHI xLO GHx GLx tP(on) tP(off) Low-Side PWM High-Side PWM Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A3941 Automotive Full Bridge MOSFET Driver Functional Description The A3941 is a full-bridge MOSFET driver (pre-driver) requiring a single unregulated supply of 7 to 50 V. It includes an integrated 5 V logic supply regulator. The four high current gate drives are capable of driving a wide range of N-channel power MOSFETs, and are configured as two high-side drives and two low-side drives. The A3941 provides all the necessary circuits to ensure that the gate-source voltage of both high-side and low-side external FETs are above 10 V, at supply voltages down to 7 V. For extreme battery voltage drop conditions, correct functional operation is guaranteed at supply voltages down to 5.5 V, but with a reduced gate drive voltage. The A3941 can be driven with a single PWM input from a microcontroller and can be configured for fast or slow decay. Fast decay can provide four-quadrant motor control, while slow decay is suitable for two-quadrant motor control or simple inductive loads. In slow decay, current recirculation can be through the high-side or the low-side MOSFETs. In either case, bridge efficiency can be enhanced by synchronous rectification. Crossconduction (shoot through) in the external bridge is avoided by an adjustable dead time. A low power sleep mode allows the A3941, the power bridge, and the load to remain connected to a vehicle battery supply without the need for an additional supply switch. The A3941 includes a number of protection features against undervoltage, overtemperature, and power bridge faults. Fault states enable responses by the device or by the external controller, depending on the fault condition and logic settings. Two fault flag outputs, FF1 and FF2, are provided to signal detected faults to an external controller. used by the internal logic circuits and must always be decoupled by at least a 100 nF capacitor between the V5 pin and GND. The 5 V regulator is disabled when RESET is held low. Gate Drives The A3941 is designed to drive external, low on-resistance, power N-channel MOSFETs. It supplies the large transient currents necessary to quickly charge and discharge the external FET gate capacitance in order to reduce dissipation in the external FET during switching. The charge and discharge rate can be controlled using an external resistor in series with the connection to the gate of the FET. Gate Drive Voltage Regulation The gate drives are powered by an internal regulator which limits the supply to the drives and therefore the maximum gate voltage. When the VBB supply is greater than about 16 V, the regulator is a simple linear regulator. Below 16 V, the regulated supply is maintained by a charge pump boost converter, which requires a pump capacitor connected between the CP1 and CP2 pins. This capacitor must have a minimum value of 220 nF, and is typically 470 nF. The regulated voltage, nominally 13 V, is available on the VREG pin. A sufficiently large storage capacitor must be connected to this pin to provide the transient charging current to the low-side drives and the bootstrap capacitors. Top-off Charge Pump An additional top-off charge pump is Power Supplies A single power supply connection is required to the VBB pin through a reverse voltage protection circuit. The supply should be decoupled with a ceramic capacitor connected close to the VBB and ground pins. The A3941 operates within specified parameters with a VBB supply from 7 to 50 V and functions correctly with a supply down to 5.5 V. This provides a very rugged solution for use in the harsh automotive environment. V5 Pin A 5 V low current supply for external pullup resistors is provided for each phase. The charge pumps allow the high-side drives to maintain the gate voltage on the external FETs indefinitely, ensuring so-called 100% PWM if required. This is a low current trickle charge pump, and is operated only after a high-side FET has been signaled to turn on. The floating high-side gate drive requires a small bias current (1000 nF). If the bootstrap capacitor voltage does not reach the threshold within approximately 200 μs, an undervoltage fault will be flagged. Supply Decoupling Because this is a switching circuit, there are current spikes from all supplies at the switching points. As with all such circuits, the power supply connections should be decoupled with a ceramic capacitor, typically 100 nF, between the supply pin and ground. These capacitors should be connected as close as possible to the device supply pins VBB and V5, and the ground pin, GND. Power Dissipation In applications where a high ambient temperature is expected, the on-chip power dissipation may become a critical factor. Careful attention should be paid to ensure the operating conditions allow the A3941 to remain in a safe range of junction temperature. The power consumed by the A3941, PD, can be estimated by: PD = PBIAS + PCPUMP + PSWITCHING , given: PBIAS = VBB × IBB ; (8) (7) VREG Capacitor Selection The internal reference, VREG, supplies current for the low-side gate drive circuits and the charging current for the bootstrap Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A3941 Automotive Full Bridge MOSFET Driver PCPUMP = [( 2 VBB) – VREG] IAV or = [VBB – VREG] IAV where: IAV = QGATE × N × fPWM , , for VBB < 15 V, , for VBB ≥ 15 V, (9) (10) PSWITCHING = QGATE × VREG × N × fPWM × Ratio ; N is the number of FETs switching during a PWM cycle, and 10 . Ratio = RGATE + 10 N = 1 for slow decay with diode recirculation, N = 2 for slow decay with synchronous rectification or for fast decay with diode recirculation, and N = 4 for fast decay with synchronous rectification. Layout Recommendations Careful consideration must be given to PCB layout when designing high frequency, fast switching, high current circuits. The following are recommendations regarding some of these considerations: • The A3941 ground, GND, and the high-current return of the external FETs should return separately to the negative side of the motor supply filtering capacitor. This will minimize the effect of switching noise on the device logic and analog reference. • The exposed thermal pad should be connected to the GND pin and may form part of the Controller Supply ground (see figure 4). • Minimize stray inductance by using short, wide copper traces at the drain and source terminals of all power FETs. This includes motor lead connections, the input power bus, and the common source of the low-side power FETs. This will minimize voltages induced by fast switching of large load currents. • Consider the use of small (100 nF) ceramic decoupling capacitors across the sources and drains of the power FETs to limit fast transient voltage spikes caused by the inductance of the circuit trace. • Keep the gate discharge return connections Sx and LSS as short as possible. Any inductance on these traces will cause negative transitions on the corresponding A3941 pins, which may exceed the absolute maximum ratings. If this is likely, consider the use of clamping diodes to limit the negative excursion on these pins with respect to GND. • Sensitive connections such as RDEAD and VDSTH, which have very little ground current, should be connected to the Quiet ground (refer to figure 4), which is connected independently, closest to the GND pin. These sensitive components should never be connected directly to the supply common or to a common ground plane. They must be referenced directly to the GND pin. • The supply decoupling for VBB, VREG, and V5 should be connected to the Controller Supply ground, which is independently connected close to the GND pin. The decoupling capacitors should also be connected as close as practicable to the relevant supply pin. • If layout space is limited, then the Quiet and Controller Supply grounds may be combined. In this case, ensure that the ground return of the dead time resistor is close to the GND pin. • Check the peak voltage excursion of the transients on the LSS pin with reference to the GND pin, using a close grounded (tip and barrel) probe. If the voltage at LSS exceeds the absolute maximum shown in this datasheet, add either or both of additional clamping and capacitance between the LSS pin and the GND pin, as shown in figure 4. • Gate charge drive paths and gate discharge return paths may carry a large transient current pulse. Therefore, the traces from GHx, GLx, Sx, and LSS should be as short as possible to reduce the circuit trace inductance. • Provide an independent connection from LSS to the common point of the power bridge. It is not recommended to connect LSS directly to the GND pin, as this may inject noise into sensitive functions such as the timer for dead time. • A low-cost diode can be placed in the connection to VBB to provide reverse battery protection. In reverse battery conditions, it is possible to use the body diodes of the power FETs to clamp the reverse voltage to approximately 4 V. In this case, the additional diode in the VBB connection will prevent damage to the A3941 and the VDRAIN input will survive the reverse voltage. Note that the above are only recommendations. Each application is different and may encounter different sensitivities. A driver running a few amps will be less susceptible than one running with 150 A, and each design should be tested at the maximum current to ensure any parasitic effects are eliminated. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 A3941 Automotive Full Bridge MOSFET Driver Optional reverse battery protection VBB VDRAIN VREG GHB GHA + Supply A3941 VS SA SB Motor GLA VDSTH RDEAD GND GLB LSS RS Optional components to limit LSS transients Quiet Ground Controller Supply Ground Power Ground Supply Common Figure 4. Supply routing suggestions Input and Output Structures CP1 CP2 VDRAIN VBB VS VBB 20 V 18 V Cx 18 V 19 V GHx 18 V Sx VREG 18 V 18 V 19 V 18 V 20 V 6V ESD (B) Supply protection structures ESD 18 V GLx 10 Ω FFx LSS 6V RESET 50 kΩ 6V 3 kΩ (A) Gate drive outputs ESD (C) Fault output ESD (D) RESET input ESD 1.2 V PWMx SR PHASE 3 kΩ VDSTH 1 kΩ RDEAD 100 Ω 8.5 V 8.5 V 8.5 V (E) Logic inputs, no pulldown (F) VDS monitor threshold input (G) RDEAD Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 A3941 Automotive Full Bridge MOSFET Driver Pin-out Diagram VDRAIN LSS GLB SB GHB CB VREG VREG CA GHA SA GLA VBB VBB 1 2 3 4 5 6 Control Logic 28 tDEAD 27 26 25 24 23 22 21 Reg 20 19 18 17 Charge Pump 16 15 VDSTH RDEAD FF2 FF1 RESET PWMH PWML SR V5 PHASE GND GND CP1 CP2 7 8 9 10 11 12 13 14 Reg Terminal List Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name VDRAIN LSS GLB SB GHB CB VREG VREG CA GHA SA GLA VBB VBB CP2 Description High-side common drain Low-side common source Low-side gate drive B Load connection B High-side gate drive B Bootstrap capacitor B Regulated 13 V Regulated 13 V Bootstrap capacitor A High-side gate drive A Load connection A Low-side gate drive A Main supply Main supply Pump capacitor Number 16 17 18 19 20 21 22 23 24 25 26 27 28 – Name CP1 GND GND PHASE V5 SR PWML PWMH RESET FF1 FF2 RDEAD VDSTH PAD Ground Ground Phase control input 5 V regulator SR control input Low-side PWM control input High-side PWM control input Reset input Fault Flag 1 output Fault Flag 2 output Dead time setting input VDS threshold level Input Exposed pad for enhanced thermal dissipation (underside) Description Pump capacitor Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 A3941 Automotive Full Bridge MOSFET Driver Package LP 28-Pin TSSOP with Exposed Thermal Pad 9.70 ±0.10 28 4° ±4 +0.05 0.15 –0.06 1.65 28 0.45 0.65 B 3.00 A 4.40 ±0.10 6.40 ±0.20 0.60 ±0.15 (1.00) 3.00 6.10 1 2 5.00 0.25 SEATING PLANE 0.65 1.20 MAX 0.10 MAX For reference only (reference JEDEC MO-153 AET) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) C SEATING PLANE GAUGE PLANE 12 5.00 C PCB Layout Reference View 28X 0.10 C +0.05 0.25 –0.06 Copyright ©2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20