A3958SLB

3958 A3958SLB CP CP2 CP1 PHASE OSC GROUND GROUND LOGIC SUPPLY ENABLE DATA CLOCK STROBE CHARGE PUMP DMOS FULL-BRIDGE PWM MOTOR DRIVER Designed for pulse-width modulated (PWM) current control of dc motors, the A3958SB and A3958SLB are capable of continuous output currents to ±2 A and operating voltages to 50 V. Internal fixed offtime PWM current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed current-decay modes. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM-control signals. The ENABLE input can be programmed via the serial port to PWM the bridge in fast or slow current decay. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, and crossover-current protection. Special power-up sequencing is not required. The A3958SB/SLB is supplied in a choice of two power packages, a 24-pin plastic DIP with a copper batwing tab (package suffix ‘B’), and a 24-lead plastic SOIC with a copper batwing tab (package suffix ‘LB’). In both cases, the power tab is at ground potential and needs no electrical isolation. Data Sheet 29319.31 1 2 3 4 5 θ 24 23 NC 22 21 VBB 20 19 18 VREG RANGE NO CONNECTION OUTB LOAD SUPPLY GROUND GROUND SENSE OUTA NO CONNECTION MODE REF 6 7 8 9 9 V CC LOGIC 17 16 SERIAL PORT 10 11 12 NC 15 14 ÷ 13 Dwg. PP-069 Note that the A3958SLB(SOIC) and A3958SB (DIP) do not share a common terminal assignment. ABSOLUTE MAXIMUM RATINGS Load Supply Voltage, VBB .................. 50 V Output Current, IOUT ........................ ±2.0 A Logic Supply Voltage, VDD ................ 7.0 V Input Voltage, VIN .... -0.3 V to VDD + 0.3 V Sense Voltage, VS ............................ 0.5 V Reference Voltage, VREF .................. 2.7 V Package Power Dissipation (TA = 25°C), PD A3958SB ................................. 3.1 W* A3958SLB ............................... 2.2 W* Operating Temperature Range, TA ............................... -20°C to +85°C Junction Temperature, TJ ............................................ +150°C Storage Temperature Range, TS ............................. -55°C to +150°C Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. * Per SEMI G42-88 Specification. FEATURES I I I I I I I ±2 A, 50 V Continuous Output Rating Low rDS(on) Outputs (270 mΩ, Typical) Programmable Mixed, Fast, and Slow Current-Decay Modes Serial Interface Controls Chip Functions Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal-Shutdown Circuitry Crossover-Current Protection Always order by complete part number: Part Number A3958SB A3958SLB Package 24-pin batwing DIP 24-lead batwing SOIC RθJA 40°C/W 56°C/W RθJT 6°C/W 6°C/W 3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER FUNCTIONAL BLOCK DIAGRAM VDD LOGIC SUPPLY CHARGE PUMP BANDGAP VDD CREG TSD VBB + CP1 CP2 LOAD SUPPLY BANDGAP REGULATOR VREG UNDERVOLTAGE & FAULT DETECT CHARGE PUMP CONTROL LOGIC OUTA PHASE ENABLE SYNC RECT MODE SYNC RECT DISABLE PWM MODE INT PWM MODE EXT MODE PHASE ENABLE GATE DRIVE CP OUTB SENSE ZERO CURRENT DETECT CS RS OSC FIXED OFF PROGRAMMABLE BLANK DECAY PWM TIMER CLOCK DATA STROBE RANGE SERIAL PORT SLEEP MODE CURRENT SENSE RANGE REFERENCE BUFFER & DIVIDER REF VREF Dwg. FP-048 CP2 CP1 PHASE OSC GROUND GROUND GROUND GROUND LOGIC SUPPLY ENABLE DATA CLOCK 1 2 3 4 5 θ CHARGE PUMP 24 23 22 21 VBB 20 19 18 17 CP VREG RANGE OUTB LOAD SUPPLY GROUND GROUND SENSE OUTA MODE REF STROBE Dwg. PP-069-1 A3958SB Note that the A3958SLB (SOIC) and A3958SB (DIP) do not share a common terminal assignment. 6 7 8 9 9 10 11 12 V DD LOGIC 16 15 ÷ SERIAL PORT 14 13 2 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, Allegro MicroSystems, Inc. 3958 DMOS FULL-BRIDGE PWM MOTOR DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise) Limits Characteristics Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance Body Diode Forward Voltage Load Supply Current VBB IDSS rDS(on) VF IBB Operating During sleep mode VOUT = VBB VOUT = 0 V Source driver, IOUT = -2 A Sink driver, IOUT = 2 A Source diode, IF = -2 A Sink diode, IF = 2 A fPWM < 50 kHz Charge pump on, outputs disabled Sleep Mode Control Logic Logic Supply Voltage Range Logic Input Voltage Logic Input Current (all inputs except ENABLE) ENABLE Input Current OSC input frequency OSC input duty cycle OSC input hysteresis Input Hysterisis Reference Input Volt. Range Reference Input Current Comparator Input Offset Volt. VDD VIN(1) VIN(0) IIN(1) IIN(0) IIN(1) IIN(0) fOSC dcOSC – – VREF IREF VIO VIN = 2.0 V VIN = 0.8 V VIN = 2.0 V VIN = 0.8 V Operating Operating Operating All digital inputs except OSC Operating VREF = 2.5 V VREF = 0 V Operating 4.5 2.0 – – – – – 2.9 40 200 50 0.0 – – 5.0 – –