A3977SLPTR-T

A3977 Microstepping DMOS Driver with Translator FEATURES AND BENEFITS • • • • • • • • • ±2.5 A, 35 V output rating Low RDS(on) outputs, 0.28 Ω source, 0.22 Ω sink typical Automatic current decay mode detection/selection 3.0 to 5.5 V logic supply voltage range Mixed, fast, and slow current decay modes Home output Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection Package: 28-pin TSSOP (suffix LP) with Exposed Thermal Pad DESCRIPTION The A3977 is a complete microstepping motor driver with built-in translator. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 35 V and ±2.5 A. The A3977 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This currentdecay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A3977. Simply inputting one pulse on the STEP input drives the motor one step (two logic inputs determine if it is a full-, half-, quarter-, or eighth-step). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The A3977 interface is an ideal fit for applications where a complex microprocessor is unavailable or overburdened. Internal synchronous-rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-up sequencing is not required. Not to scale The A3977 is supplied in a thin ( 30 ns –0.3 to VDD+ 0.3 V Pulsed, tw < 30 ns –1.0 to VDD+ 1 V VDD V 0.5 V ±2.5 A Range K –40 to 125 °C Range S –20 to 85 °C VREF VSENSE IOUT Rating Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Operating Ambient Temperature TA Maximum Junction Temperature TJ(max) 150 °C Tstg –55 to 150 °C Value Units 28 °C/W Storage Temperature THERMAL CHARACTERISTICS Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* Package LP, on 4-layer PCB based on JEDEC standard *Additional thermal information available on the Allegro website. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A3977 Microstepping DMOS Driver with Translator VREG LOGIC SUPPLY 2V UVLO AND FAULT VDD REF. SUPPLY DAC SENSE1 CP1 CHARGE PUMP REGULATOR BANDGAP REF CP2 VCP LOAD SUPPLY VBB1 VCP DMOS H BRIDGE + OUT 1A RC1 PWM LATCH BLANKING OUT1B MIXED DECAY PWM TIMER 4 STEP HOME SLEEP VPFD GATE DRIVE MS 1 MS 2 CONTROL LOGIC RESET SENSE1 TRANSLATOR DIR DMOS H BRIDGE OUT 2A SR OUT2B ENABLE PFD VBB2 PWM TIMER PWM LATCH BLANKING MIXED DECAY 4 RC 2 + - DAC SENSE2 Dwg. FP-050-2 Functional Block Diagram Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 A3977 Microstepping DMOS Driver with Translator Pinout Diagram and Terminal List Table LP Package, 28-Pin TSSOP Pinout Diagram Terminal List Table Terminal Name Terminal Number SENSE1 1 Sense Resistor for Bridge 1 HOME 2 Logic Output DIR 3 Logic Input OUT1A 4 DMOS H Bridge 1 Output A PFD 5 Mixed Decay Setting RC1 6 Analog Input for Fixed Offtime – Bridge 1 AGND 7* Analog Ground REF 8 Gm Reference Input RC2 9 Analog Input for Fixed Offtime – Bridge 2 LOGIC SUPPLYNC 10 VDD, the Logic Supply Voltage OUT2A 11 DMOS H Bridge 2 Output A MS2 12 Logic Input MS1 13 Logic Input SENSE2 14 Sense Resistor for Bridge 2 Terminal Description Terminal Name Terminal Number LOAD SUPPLY2 15 VBB2, the Load Supply for Bridge 2 Terminal Description SR 16 Logic Input RESET 17 Logic Input OUT2B 18 DMOS H Bridge 2 Output B STEP 19 Logic Input VREG 20 Regulator Decoupling PGND 21* Power Ground VCP 22 Reservoir Capacitor CP1 23 Charge Pump Capacitor CP2 24 Charge Pump Capacitor OUT1B 25 DMOS H Bridge 1 Output B ENABLE 26 Logic Input SLEEP 27 Logic Input LOAD SUPPLY1 28 VBB1, the Load Supply for Bridge 1 *AGND and PGND on the TSSOP package must be connected together externally. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 A3977 Microstepping DMOS Driver with Translator Maximum Power Dissipation, PD(max) 5.0 4.5 Power Dissipation, PD (W) 4.0 H (R igh- K = PCB 28 2La ºC ye /W rP ) C (R B w ith θJ A = 3 32 .8 in 2 ºC co /W pp er ) p 3.5 θJ 3.0 2.5 2.0 A er 1.5 sid e 1.0 0.5 0.0 20 40 60 80 100 120 Temperature (°C) 140 160 Table 1: Microstep Resolution Truth Table MS1 MS2 Resolution L L Full Step (2 Phase) H L Half Step L H Quarter Step H H Eighth Step Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 A3977 Microstepping DMOS Driver with Translator ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 to 5.5 V (unless otherwise noted) Characteristic Symbol Test Conditions Min. Typ. Max. Units 8.0 – 35 V OUTPUT DRIVERS Load Supply Voltage Range Output Leakage Current Output On Resistance VBB IDSS RDS(on) Body Diode Forward Voltage VF Motor Supply Current IBB Operating During sleep mode 0 – 35 V VOUT = VBB –