A3980
Automotive DMOS Microstepping Driver with Translator
Not for New Design
These parts are in production but have been determined to be
NOT FOR NEW DESIGN. This classification indicates that sale of
this device is currently restricted to existing customer applications.
The device should not be purchased for new design applications
because obsolescence in the near future is probable. Samples are no
longer available.
Date of status change: November 17, 2011
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, refer to the A3981.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A3980
Automotive DMOS Microstepping Driver with Translator
Features and Benefits
Description
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▪
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▪
▪
▪
▪
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The A3980 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full-, half-, eighth-, and sixteenthstep modes, at up to 35 V and ±1 A. The A3980 includes a
fixed off-time current regulator which has the ability to operate
in slow, fast, or mixed decay modes. This results in reduced
audible motor noise, increased step accuracy, and reduced
power dissipation.
Typical application up to ±1 A, 35 V output rating
Low RDS(ON) outputs, 0.67 Ω source, 0.54 Ω sink typical
Automatic current decay mode detection/selection
3.0 V to 5.5 V logic supply voltage range
Mixed, fast, and slow current decay modes
Synchronous rectification for low power dissipation
Internal OVLO, UVLO, and thermal shutdown circuitry
Crossover current protection
Short to supply/ground and short/low load current
diagnostics
Package: 28 pin TSSOP with exposed
thermal pad (suffix LP)
The translator is the key to the easy implementation of the
A3980. Simply inputting one pulse on the step input drives
the motor one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A3980 interface is an ideal fit for applications where a
complex μP is unavailable or overburdened.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Internal circuit protection includes: thermal shutdown with
hysteresis, overvoltage lockout (OVLO), undervoltage lockout
(UVLO), and crossover current protection. Special power-up
sequencing is not required. In addition, two diagnostic fault flags
provide indication of shorts or opens on the motor windings.
Approximate Size
The A3980 is supplied in a low-profile (1.1 mm) 28L TSSOP
with exposed thermal pad. This device is lead (Pb) free, with
100% matte tin leadframe plating.
Typical Application
26184.26H
Automotive DMOS Microstepping Driver
with Translator
A3980
Selection Guide
Part Number
Packing
A3980KLPTR-T
4000 pieces per reel
Absolute Maximum Ratings
Characteristic
Symbol
Load Supply Voltage
VBB
Logic Supply Voltage
VDD
Logic Input Voltage
VIN
Sense Voltage
Notes
Rating
Units
50
V
7.0
V
–0.3 to VDD + 0.3
V
500 ms
(tW < 30 ns)
–1.0 to VDD + 1
V
0.5
V
VSENSE
Reference Voltage
VREF
0 to VDD
V
–40 to 125
°C
TJ(max)
150
°C
Tstg
–55 to 150
°C
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
Range K
ESD Rating - Human Body Model
AEC-Q100-002, all pins
2.0
kV
ESD Rating - Charged Device Model
AEC-Q100-011, all pins
1.0
kV
Thermal Ratings
Characteristic
Symbol
Package Thermal Resistance
RθJA
Test Conditions*
Value Units
2
2-layer PCB with 3.8 in. of copper area each side
32
ºC/W
connected by thermal vias
4-layer PCB based on JEDEC standards
28
ºC/W
*Additional thermal information available on Allegro Web site.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Automotive DMOS Microstepping Driver
with Translator
A3980
Functional Block Diagram
C CP
VREG
CP2
CP1
5V
VDD
VCP
V REF
SENSE 1
Charge
Pump
C CS
DAC
Voltage
Regulator
VBATT
STEP
DMOS Full Bridge
DIR
MS1
VBB1
Translator
MS2
OUT1A
OUT1B
RC1
R T1
PWM Latch
Blanking
Mixed Decay
C T1
SENSE1
Gate
Drive
SR
SLEEP
DMOS Full Bridge
VBB2
Control
Logic
ENABLE
R S1
OUT2A
OUT2B
PFD
PWM Latch
Blanking
Mixed Decay
RC2
R T2
SENSE2
C T2
R S2
VDD
VCP
VBB
OUT1A/1B
OUT2A/2B
SENSE1
SENSE2
DAC
OVLO
UVLO
OVERTEMP
SHORT SENSE
OPEN SENSE
SENSE 2
V REF
AGND
REF
FF1
FF2
PGND
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Automotive DMOS Microstepping Driver
with Translator
A3980
ELECTRICAL CHARACTERISTICS at TJ = –40°C to +150ºC, VBB = 14 V, VDD = 3.0 to 5.5 V (unless otherwise noted)
Characteristics
Symbol
Test Conditions
Min.
Typ.1
Max.
Units
Output Drivers
Load Supply Voltage Range
VBB
Driving
Operating
Sleep mode
8
7
0
–
VOVB
50
35
V
Output Leakage Current2
IDSS
VOUT = VBB
VOUT = 0 V
–
< 1.0
< 1.0
20
–20
μA
Source driver, IOUT = –1 A, TA < 25ºC
Sink driver, IOUT = 1 A, TA < 25ºC
–
0.51
0.45
0.86
0.65
Source driver, IOUT = –1 A, TA < 125ºC
Sink driver, IOUT = 1 A, TA < 125ºC
–
0.87
0.72
1.06
0.83
Output-On Resistance
RDSON
Body Diode Forward Voltage
VF
Source diode, IF = –1 A
Sink diode, IF = 1 A
–
–
1.4
1.4
V
Motor Supply Current
IBB
fPWM < 50 kHz
Operating, outputs disabled
Sleep mode
–
–
8
6
20
mA
mA
μA
Logic Supply Current
IDD
fPWM < 50 kHz
Outputs off
Sleep mode
–
–
12
10
20
mA
mA
μA
Logic Supply Voltage Range
VDD
Operating
3.0
5.0
5.5
V
Input Low Voltage
VIL
–
V
VIH
–
–
0.3 VDD
Input High Voltage
–
–
–
–
–
V
200
300
500
mV
–20
< ±1
20
μA
–
–
–
–
–
–
–
–
0.4
V
–
–
–
–
–
V
Logic Interface
Input Hysteresis
Input Current2
VIHYS
IIN
Output Low Voltage
VOL
IO = 3 mA
Output High Voltage
VOH
IO = –200 μA
STEP Pin Low
tSTPL
STEP Pin High
tSTPH
–
–
0.7 VDD
2.8
1
1
Setup Time for Input Change to STEP
tSU
MS1, MS2, DIR
200
Hold Time for Input Change from STEP
tH
MS1, MS2, DIR
200
Wake-Up Time from SLEEP
tEN
–
–
1
μs
μs
ns
ns
ms
Continued on next page
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Automotive DMOS Microstepping Driver
with Translator
A3980
ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to +150ºC, VBB = 14 V, VDD = 3.0 to 5.5 V (unless otherwise noted)
Characteristics
Symbol
Test Conditions
Min.
Typ.1
Max.
Units
Current Control
Blank Time
Fixed Off Time
Mixed Decay Trip Points
Crossover Dead Time
Recommended Reference Input Voltage
Reference Input
Current2
Current Trip-Level Error3
tBLANK
RT = 56 K , CT = 680 pF
700
950
1200
ns
tOFF
RT = 56 K , CT = 680 pF
30
38
46
μs
PFDH
PFDL
–
–
0.60 VDD
0.21 VDD
–
V
tDT
–
–
–
100
475
800
ns
0.8
–
4
V
–3
0
3
μA
–
–
±15
±10
±5
%
160
170
180
ºC
–
15
–
ºC
1.5
V
35
–
–
–
–
VREF
IREF
errI
2 V < VREF < 4 V, %ITripMAX = 38%
2 V < VREF < 4 V, %ITripMAX = 70%
2 V < VREF < 4 V, %ITripMAX = 100%
Thermal Protection
Thermal Shutdown
TSD
Thermal Shutdown Hysteresis
TSDH
–
–
Max VDS on High-Side Bridge FETs
VDSHT
Sampled after tBLANK + tSCT
Max VDS on Low-Side Bridge FETs
VDSLT
Sampled after tBLANK + tSCT
Diagnostics
VDS Fault Measurement Delay
tSCT
–
Minimum Load Current
IOC
w.r.t. ITRIPMAX at Home position
–
–
–
–
1.5
700
V
ns
%
VBB Overvoltage Lockout
VOVB
VBB rising
32
34
36
V
VBB Overvoltage Lockout Hysteresis
VOVBH
–
2
–
4
V
VREG Undervoltage Lockout
VUVR
VREG falling
5.3
5.7
6.0
V
VDD Enable Threshold
VUVD
VDD rising
2.45
2.7
2.95
V
VDD Enable Threshold Hysteresis
VUVDH
–
50
100
–
mV
1Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary
for individual units, within the specified maximum and minimum limits.
2Negative current is defined as coming out of (sourcing from) the specified device pin.
3err
I
= (ITrip – IProg ) ⁄ IProg , where IProg = %ITripMAX
× ITripMAX.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Automotive DMOS Microstepping Driver
with Translator
A3980
Logic Interface Timing Diagram
tSTPH
tSTPL
STEP
tSU
tH
MS1, MS2,
or DIR
tEN
SLEEP
Table 1. Microstep Resolution Truth Table
MS1
MS2
Microstep Resolution
L
L
Full Step
H
L
Half Step
L
H
Eighth Step
H
H
Sixteenth Step
Table 2. Fault Report by Fault Flags
FF1
FF2
Fault
L
L
UVLO, OVLO, Overtemperature,
Low Load Current, or Shorted Load
H
L
Short to Ground
L
H
Short to Supply
H
H
None
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Automotive DMOS Microstepping Driver
with Translator
A3980
Table 3. Step Sequencing Settings
Home microstep position at Step Angle 45º; DIR = H
Full
Step
#
Half
Step
#
1
2
99.52
9.80
5.6
98.08
19.51
11.3
4
95.69
29.03
16.9
5
92.39
38.27
22.5
6
88.19
47.14
28.1
7
83.15
55.56
33.8
8
77.30
63.44
39.4
9
70.71
70.71
45.0
5
(%)
0.00
63.44
77.30
50.6
11
55.56
83.15
56.3
12
47.14
88.19
61.9
13
38.27
92.39
67.5
14
29.03
95.69
73.1
15
19.51
98.08
78.8
16
9.80
99.52
84.4
9
17
0.00
100.00
90.0
18
–9.80
99.52
95.6
10
19
–19.51
98.08
101.3
20
–29.03
95.69
106.9
21
–38.27
92.39
112.5
22
–47.14
88.19
118.1
23
–55.56
83.15
123.8
24
–63.44
77.30
129.4
13
25
–70.71
70.71
135.0
26
–77.30
63.44
140.6
14
27
–83.15
55.56
146.3
28
–88.19
47.14
151.9
29
–92.39
38.27
157.5
30
–95.69
29.03
163.1
31
–98.08
19.51
168.8
32
–99.52
9.80
174.4
8
11
12
4
(%)
100.00
Step
Angle
(º)
0.0
10
7
2
[% ItripMax]
3
6
3
[% ItripMax]
2
4
2
Phase 2
Current
1/16
Step
#
1
3
1
Phase 1
Current
1/8
Step
#
1
15
16
Full
Step
#
Half
Step
#
5
34
–99.52
–9.80
185.6
18
35
–98.08
–19.51
191.3
36
–95.69
–29.03
196.9
37
–92.39
–38.27
202.5
38
–88.19
–47.14
208.1
39
–83.15
–55.56
213.8
40
–77.30
–63.44
219.4
21
41
–70.71
–70.71
225.0
42
–63.44
–77.30
230.6
22
43
–55.56
–83.15
236.3
44
–47.14
–88.19
241.9
45
–38.27
–92.39
247.5
46
–29.03
–95.69
253.1
47
–19.51
–98.08
258.8
48
–9.80
–99.52
264.4
25
49
0.00
–100.00
270.0
50
9.80
–99.52
275.6
26
51
19.51
–98.08
281.3
52
29.03
–95.69
286.9
53
38.27
–92.39
292.5
54
47.14
–88.19
298.1
55
55.56
–83.15
303.8
56
63.44
–77.30
309.4
29
57
70.71
–70.71
315.0
58
77.30
–63.44
320.6
30
59
83.15
–55.56
326.3
60
88.19
–47.14
331.9
61
92.39
–38.27
337.5
62
95.69
–29.03
343.1
63
98.08
–19.51
348.8
64
99.52
–9.80
354.4
20
6
23
24
7
27
28
4
8
Phase 2
Current
1/16
Step
#
33
19
3
Phase 1
Current
1/8
Step
#
17
31
32
[% ItripMax]
(%)
–100.00
[% ItripMax]
(%)
0.00
Step
Angle
(º)
180.0
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
100.00
100.00
70.71
70.71
–70.71
–100.00
100.00
Phase 1
IOUT1B
Direction = H
(%)
Home Microstep Position
Phase 1
IOUT1B
Direction = H
(%)
–70.71
–100.00
100.00
Home Microstep Position
Automotive DMOS Microstepping Driver
with Translator
A3980
70.71
70.71
Phase 2
IOUT2B
Direction = H
(%)
Phase 2
IOUT2B
Direction = H
(%)
–70.71
–70.71
–100.00
–100.00
Figure 6. Half Step
Figure 5. Full Step
STEP
100.00
92.39
83.15
70.71
55.56
38.27
19.51
Slow
Mixed
Mixed
Slow
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–100.00
100.00
92.39
83.15
70.71
55.56
Phase 2
IOUT2B
Direction = H
(%)
Slow
Mixed
Mixed
Slow
0.00
Home Microstep Position
Phase 1
IOUT1B
Direction = H
(%)
38.27
19.51
0.00
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–100.00
Figure 7. Eighth Step
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Automotive DMOS Microstepping Driver
with Translator
A3980
STEP
100.00
95.69
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
Phase 1
IOUT1B
Direction = H
(%)
9.8
Slow
Mixed
Slow
Mixed
0.00
–9.8
–19.51
–29.03
–38.27
Home Microstep Position
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–95.69
–100.00
100.00
95.69
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
Phase 2
IOUT2B
Direction = H
(%)
9.8
Slow
Mixed
Slow
Mixed
Slow
0.00
–9.8
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–95.69
–100.00
Figure 8. Sixteenth Steps
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A3980
Automotive DMOS Microstepping Driver
with Translator
Functional Description
Device Operation. The A3980 is a complete microstepping motor driver with a built-in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full-, half-, eighth-, and sixteenth-step
modes. The currents in each of the two output full-bridges
and all of the N-channel DMOS FETs are regulated with
fixed off-time PMW (pulse width modulated) control circuitry. At each step, the current for each full-bridge is set by
the value of its external current-sense resistor (RS1 or RS2), a
reference voltage (VREF), and the output voltage of its DAC
(which in turn is controlled by the output of the translator).
At power-up, the translator resets to the Home state, in which
the motor is driven to the Home microstep position, where
both phase currents are set to +70%. Then the translator sets
the voltage regulator to mixed decay mode for both phases.
When a step command signal occurs on the STEP input, the
translator automatically sequences the DACs to the next
level and current polarity. (See table 3 for the current-level
sequence.) The microstep resolution is set by the combined
effect of inputs MS1 and MS2, as shown in table 1.
When stepping, if the new output levels of the DACs are
lower than their previous output levels, then the decay mode
(fast, slow, or mixed decay) for the active full-bridge is set
by the PFD input. If the new output levels of the DACs are
higher than or equal to their previous levels, then the decay
mode for the active full-bridge is set to slow decay. This
automatic current decay selection improves microstepping
performance by reducing the distortion of the current waveform that results from the back EMF of the motor.
Home Microstep Position. At power-up, or after
a UVLO (undervoltage lockout) condition caused by low
voltage on VDD, the translator in the A3980 resets the motor
to the Home microstep position. This corresponds to the 45°
position, which is the step where both phase currents are
+70%. Referring to table 3, for full-step mode this is step
1, for half-step this is step 2, for eighth-step this is step 5,
and for sixteenth-step this is step 9. In table 3 and figures 5
through 8, the Home microstep position is indicated.
Step Input (STEP). A low-to-high transition on the STEP
input sequences the translator and advances the motor one
increment. The translator controls the input to the DACs and
the direction of current flow in each winding. The size of
the increment is determined by the combined state of inputs
MS1 and MS2.
Microstep Select (MS1 and MS2). Selects the microstepping format, as shown in table 1. Any changes made to
these inputs do not take effect until the next STEP rising edge.
Direction Input (DIR). This determines the direction of
rotation of the motor. When low, the direction will be clockwise and when high, counterclockwise. Changes to this input
do not take effect until the next STEP rising edge.
Internal PWM Current Control. Each full-bridge is
controlled by a fixed off-time PWM current control circuit
that limits the load current to a desired value, ITRIP. Initially,
a diagonal pair of source and sink DMOS FETs are enabled
and current flows through the motor winding and the current
sense resistor, RS. When the voltage across RS equals the
DAC output voltage, the current sense comparator resets the
PWM latch. The latch then turns off either the source DMOS
(when in slow decay mode) or the sink and source DMOSs
(when in fast or mixed decay modes).
The transconductance function is approximated by the maximum value of current limiting, ITripMAX (A), which is set by
ITripMAX = VREF ⁄ (8
RS)
where RS is the resistance of the sense resistor (Ω) and VREF
is the input voltage on the REF pin (V).
The DAC output reduces the VREF output to the current
sense comparator in precise steps, such that
Itrip = (%ITripMAX ⁄ 100)
× ITripMAX
(See table 3 for %ITripMAX at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE
pin is not exceeded. For full-step mode, VREF can be applied
up to the maximum rating of VDD, because the peak sense
value is 70% of maximum:
VREF
× (0.707 ⁄ 8)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Automotive DMOS Microstepping Driver
with Translator
A3980
as shown in table 3. In all other modes, VREF should not be
allowed to exceed 4 V, because the peak sense value can
reach VREF ⁄ 8, or 100%.
Fixed Off-Time. The internal PWM current control
circuitry uses a one-shot circuit to control the duration of
time that the DMOS FETs remain off. The one shot off-time,
tOFF, is determined for each of the two phases by the combination of an external resistor (RT) and a capacitor (CT). One
combination is connected from the timing terminal RC1 to
ground, and the other similarly connected to RC2 . tOFF (ns)
is approximated by
tOFF = RT
× CT
over a range of values from CT= 470 pF to 1500 pF and from
RT = 12 kΩ to 100 kΩ.
RC Blanking. In addition to the fixed off-time of the
PWM control circuit, the CT component sets the comparator
blanking time. This function blanks the output of the current
sense comparators when the outputs are switched by the
internal current control circuitry. The comparator outputs are
blanked to prevent false overcurrent detection due to reverse
recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time,
tBLANK (ns), can be approximated by
tBLANK = 1400
× CT
where CT is the value of the capacitor CT (nF).
The blank time should be as short as possible, without causing a false fault detection, to ensure that power dissipation
during a fault condition is minimized. The blank time also
defines the minimum duration of time that the full-bridge
DMOS outputs cause the load current to rise. To ensure
correct detection of motor faults, the minimum on-time is
extended by an additional fault sampling time, tSCT. The
minimum on-time, tMINON is then
tMINON = tBLANK + tSCT
Charge Pump (CP1 and CP2). The charge pump is
used to generate a gate supply greater than that of VBB for
driving the source-side DMOS gates. A 100 nF ceramic
capacitor (CCP), capable of withstanding the battery voltage VBATT, should be connected between CP1 and CP2.
In addition, a 100 nF ceramic capacitor (CCS)is required
between VCP and VBB, to act as a reservoir for operating
the high-side DMOS devices. The voltage on CCS is limited to
the charge pump voltage, which is always less than 10 V.
VREG (VREG). This internally-generated voltage is used
to operate the sink-side DMOS FETs. The VREG terminal
must be decoupled with a 220 nF (10V) capacitor to ground.
VREG is internally monitored. In the case of a fault condition, the DMOS outputs of the A3980 are disabled.
Enable Input (ENABLE). This input simply turns off all
of the DMOS outputs. When set to a logic high, the outputs
are disabled. When set to a logic low, the internal control
enables the outputs as required. The translator inputs (STEP,
DIR, MS1, and MS2), as well as the internal sequencing
logic, all remain active, independent of the ENABLE input
state.
Sleep Mode (SLEEP). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output DMOS FETs, voltage
regulator, and charge pump. A logic low on the SLEEP terminal puts the A3980 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A3980
drives the motor to the Home microstep position). If the
A3980 comes out of Sleep mode when VBB is greater than
VOVB – VOVBH and less than VOVB , the A3980 will remain
in safety mode until VBB is reduced below VOVB - VOVBH.
Percent Fast Decay Input (PFD). When a STEP input
signal commands an output current level that is lower than
that of the previous step, it switches the output current decay
to slow, fast, or mixed decay mode, depending on the voltage
level at the PFD input, as shown in the following table.
Lower PFD Input
Voltage Level
× VDD )
(0.21 × VDD ) ≤ VPFD ≤ (0.6 × VDD )
VPFD < (0.21 × VDD)
VPFD > (0.6
Decay Mode
Slow
Mixed
Fast
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115 Northeast Cutoff
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11
Automotive DMOS Microstepping Driver
with Translator
A3980
Mixed Decay Operation. Depending on the step
sequence, if the voltage on the PFD pin is between
0.6 VDD and 0.21 VDD, the full-bridge can operate
in mixed decay mode, as shown in figures 5 through 8.
As the trip point is reached, the A3980 goes into fast
decay mode until the voltage on the RC pin decays to
the same level as the voltage applied to the PFD pin. The
duration of time that the bridge operates in fast decay
mode, tFD (ns), is estimated by
×
×
tFD = RT
× CT × ln[0.6 (VDD ⁄ VPFD)]
over a range of values from CT= 470 pF to 1500 pF and
from RT = 12 kΩ to 100 kΩ.
After this fast decay period, the A3980 switches to slow
decay mode for the remainder of the fixed off-time
period.
Synchronous Rectification. When a PWM-off
cycle is triggered by an internal fixed-off-time cycle,
load current recirculates according to the decay mode
selected by the control logic. The synchronous rectification feature turns on the appropriate FETs during current
decay, and effectively shorts out the body diodes with
the low DMOS RDSON. This reduces power dissipation significantly, and eliminates the need for external
Schottky diodes. Synchronous rectification has two
modes: Active mode and Disabled mode (described below).
Active Mode. When the input on the SR terminal
is set at logic low, Active mode is enabled. This mode
allows synchronous rectification to occur, but when a
zero current level is detected, it also prevents reversal of
the load current by turning off synchronous rectification.
This prevents the motor winding from conducting in the
reverse direction.
Disabled Mode. When the input on the SR terminal
is set at logic high, Disabled mode takes effect. This
mode disables synchronous rectification. This mode
is typically used when external diodes are required to
transfer power dissipation from the A3980 package to
the external diodes.
Shutdown. In the event of an overtemperature fault
or an undervoltage fault on VREG, the DMOS outputs
of the A3980 are disabled until the fault condition is
removed. In the case of an overvoltage fault, the sink
DMOS FETs are switched on, and the source FETs off.
At power-up, and in the event of low VDD, the UVLO
circuit disables the DMOS outputs until VDD reaches the
minimum level. Once VDD is above the minimum level,
the translator resets to the Home state and the DMOS
outputs are re-enabled.
Thermal Protection. All drivers are turned off
when the junction temperature reaches the thermal
shutdown value, typically 170C. This is intended only
to protect the A3980 from failures due to excessive junction temperatures. Thermal protection will not protect
the A3980 from continuous short circuits, and additional
fault diagnostics are integrated for this purpose. Thermal
shutdown has a hysteresis of approximately 15C.
Diagnostic Features. The A3980 includes monitor circuits that can detect shorts to VBB, shorts to
ground, and shorted or open circuit load. Short circuits
are detected by monitoring the voltage across the driving
DMOS FETs and the open load is detected by monitoring the phase current when the motor is in the Home
microstep position. All fault detection takes place following a delay after the blank time.
Short to VBB. A short from any of the motor connections to the battery or VBB connection is detected by
monitoring the voltage across the bottom FETs in each
full-bridge. When the FET is on, the voltage should be
no greater than the VDSLT value defined in the Electrical
Characteristics table.
Short to Ground. A short from any of the motor connections to ground is detected by monitoring the voltage
across the top FETs in each full-bridge. When the FET
is turned on, the voltage should be no greater than the
VDSHT value defined in the Electrical Characteristics
table.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A3980
Automotive DMOS Microstepping Driver
with Translator
Shorted Load. A short across the load is detected by monitoring the voltage across both the top and bottom FETs in each
full-bridge.
Short Fault Operation. Because motor capacitance may
cause the measured voltages to show a fault as the full-bridge
switches, voltages are not sampled until after the blank time plus
an internally-generated delay, tSCT. Once a short circuit has been
detected, all outputs for the faulty phase are disabled until the
next step command. At the next step command, the outputs are
re-enabled and the voltage across the FET is resampled.
While the fault persists, the A3980 continues this cycle at each
step command: enabling the outputs for a short period, and then
disabling the outputs. This allows the A3980 to handle a continuous short circuit without damage. If, while stepping rapidly, a
short circuit appears and no action is taken, the repeated short-circuit current pulses eventually cause the temperature of the A3980
to rise and an overtemperature fault occurs.
Low Load Current Fault Operation. A low load current is
detected by monitoring the measured phase current in each output
while driving the motor in the Home microstep position. At the
Home microstep position, each phase current should reach 70%
of ITripMax. If either phase current does not exceed half of this
expected value (more than 35% of ITripMax) while in the Home
microstep position, then a low load current condition is reported
on the next rising edge of the STEP input. If the measured current in both phases exceeds 35% of ITripMax) then no fault will be
generated on the next rising edge of the STEP input.
rate, after completing the number of steps required to pass the
home condition, then an open circuit condition is confirmed.
To allow immediate detection of an open load condition at power
up or after coming out of sleep mode, the A3980 translator is
reset to the Home microstep position and the low load current
fault flags are set. If no open load condition exists then the fault
flags will be reset on the next rising edge of the STEP input.
Supply Monitors. External and internal supplies are monitored to ensure that they are within the correct operating range.
If the main supply exceeds the overvoltage limit, VOVB, the fault
flags are set and the A3980 enters a safety mode in which all lowside DMOS FETs are enabled and all high-side DMOS FETs are
disabled. This allows the A3980 to survive a load dump transient
condition that has up to 50 V on VBATT and a duration of up
to 500 ms. If the internal regulator VREG or the logic supply VDD go
below their respective undervoltage limits (VUVR or VUVD), then: the
fault flags are set, the DMOS outputs are disabled, and the internal
logic is reset to the power-on state (the translator is set to the Home
state).
Diagnostic Fault Flags (FF1, FF2). Diagnostic fault conditions are reported using the two fault flag outputs (open drain).
These are active-low outputs which are coded as shown in table
2 to discriminate between the fault conditions. When both fault
flags are high, no fault exists.
If an open load condition appears while stepping, then it is
detected after the translator cycles through the Home state.
Although the A3980 continues to drive the DMOS outputs during
an open load condition, it does not clear the fault flags until the
next Home state occurs.
There are two conditions that can cause a low load current. The
first is an open circuit on either or both motor phase connections.
In this condition, current can never flow through the phase so a
low load current will always be flagged. The second condition is
where the back EMF of the motor limits the phase current to less
than the low load current trip level. This will happen when the
stepper motor is running close to its limiting speed. To confirm an
open load condition when a low load current is flagged, the step
rate should be reduced to a level below half the maximum step
rate. If the low load current flag remains active at the lower step
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
Automotive DMOS Microstepping Driver
with Translator
A3980
Application Information
The A3980 is a power circuit, therefore careful consideration must be given to power dissipation and the effects
of high currents on interconnect and supply wiring.
Power Dissipation. A first order approximation of
the power dissipation in the A3980 can be determined
by examining the power dissipation in each of the
two full-bridges during each of the operation modes.
When synchronous rectification is used, current flow
most of the time through the DMOS FETs that are
switched on. When synchronous rectification is not
used, the current flows through the body diode of
the DMOS FETs during the decay phase. The use of
fast or slow decay also affects the dissipation. All the
above combinations can be calculated from five basic
DMOS output states, shown in the following illustrations.
Synchronous Slow Decay
Both low-side DMOS output
transistors are on. Current circulates through both transistors and
the load.
Dissipation is I2R losses in the
DMOS transistors:
PSS = I2 (2
+
M
+
M
Diagonally opposite DMOS output
transistors are on. Current flows
from ground through load to positive supply.
Dissipation is I2R losses in the
DMOS transistors:
PSF = I2 (RDSONH + RDSONL)
Diagonally opposite DMOS
output transistors are on. Current flows from positive supply
through load to ground. Used in
all combinations.
Dissipation is I2R losses in the
DMOS transistors:
PD = I2 (RDSONH + RDSONL)
+
M
× RDSONL)
Synchronous Fast Decay
Drive Current Ramp
Non-Synchronous Slow Decay
One low-side DMOS output transistor and one body diode conducting. Current circulates through the
diode, the transistor, and the load.
Dissipation is I2R losses in the
DMOS transistors plus IV loss in
the diode:
PNS = (I2
+
M
+
M
× RDSONL) + (I × VF)
Non-Synchronous Fast Decay
Diagonally opposite body diodes
conducting. Current flows from
ground through load to positive
supply.
Dissipation is IV losses in the
diodes:
PNF = I (VFH + VFl)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
Automotive DMOS Microstepping Driver
with Translator
A3980
The total dissipation for each of the four decay modes is the
average power for the current ramp and the current decay
portions of the PWM cycle.
For slow decay, the current is rising for approximately 20%
of the cycle and decaying for approximately 80%. For fast
decay, the ratio is approximately 50% for each. Note that
these are approximate figures, and they vary slightly depending on the motor characteristics and the use of synchronous
rectification.
The power dissipation, PTOT, in each decay mode can be
calculated as shown in the following formulas.
Non-synchronous slow decay mode:
PTOT = (0.2
PTOT = [0.2
× I2(RDSONH+RDSONL)]+{0.8 × [I2RDSONL+(I × VF)]}
Synchronous fast decay mode:
PTOT = (0.5
PTOT = [0.2
×
×
PD ) + (0.8
×
I2 (RDSONH + RDSONL)] + [0.8
Non-synchronous fast decay mode:
PTOT = (0.5
PSS )
×
I2 (2
× RDSONL)]
5
Power Dissipation (W)
× PD ) + (0.5 × PNF )
× I2 (RDSONH + RDSONL)] + (0.5 × I2 × RDSONL)
An approximation of the total dissipation can be calculated
by summing the total power dissipated in both full-bridges
and adding the control circuit power due to VBB IBB and
VDD IDD. The total power at the required ambient temperature can then be compared to the allowable power dissipation,
shown in the Allowable Package Power Dissipation chart.
×
For critical applications, where the first order power estimate
is close to the allowable dissipation, the power calculation
should take several other parameters into account including:
motor parameters, dead time, and switching losses in the
controller.
4
3
1R
θJA
Layout. The printed circuit board should use a heavy
ground plane. For optimum electrical and thermal performance, the A3980 should be soldered directly onto the board.
The load supply terminal, VBB, should be decoupled with
an electrolytic capacitor (> 47 μF is recommended), placed
as close to the A3980 as possible. To avoid problems due to
capacitive coupling of the high dv/dt switching transients,
route the full-bridge output traces away from the sensitive
logic input traces. Always drive the logic inputs with a low
source impedance to increase noise immunity.
= 28ºC/W
2
2R
θJA
= 38ºC/W
1
0
PTOT = [0.5
×
Allowable Package Power Dissipation
× PD ) + (0.5 × PSF )
PTOT = I2 (RDSONH + RDSONL)
Synchronous slow decay mode:
PTOT = (0.2
× PD ) + (0.8 × PNS )
25
1R
50
75
100
125
Ambient Temperature (°C)
θJA at 28ºC/ W measured on a JEDEC-standard
“High-K” 4-layer PCB.
2R
θJA at 38ºC/ W measured on a typical 2-sided PCB
with 3 in.2 (1935 mm2) copper ground area.
150
Grounding. A star ground system located close to the
A3980 is recommended. On the 28-lead TSSOP package, the
analog ground (lead 7) and the power ground (lead 21) must
be connected together externally. The copper ground plane
located under the exposed thermal pad is typically used as
the star ground point.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
Automotive DMOS Microstepping Driver
with Translator
A3980
Current Sensing. To minimize inaccuracies caused by
ground-trace IR drops in sensing the output current level,
the current-sense resistors (RS1 and RS2) should have an
independent ground return to the star ground point. This path
should be as short as possible. For low-value sense resistors,
the IR drops in the printed circuit board sense resistor traces
can be significant and should be taken into account. The use
of sockets should be avoided as they can introduce variation
in RS due to their contact resistance.
The recommended value of the sense resistor, RS (Ω), is
given by
RS = 0.5 / ITripMAX
up to a maximum of 1 Ω for ITripMAX of 0.5 A. Below 0.5 A,
RS should be 1 Ω, and VREF reduced accordingly, as shown
in the following table.
IMAX (A)
Recommended
RS(Ω)
VREF (V)
0.1
1.00
0.8
0.2
1.00
1.6
0.3
1.00
2.4
0.4
1.00
3.2
0.5
1.00
4.0
0.6
0.83
4.0
0.7
0.71
4.0
0.8
0.63
4.0
0.9
0.56
4.0
1.0
0.50
4.0
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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16
Automotive DMOS Microstepping Driver
with Translator
A3980
Terminal List Table
Name
SENSE1
VBB1 28 VBB1
Number
Sense resistor for full-bridge 1
1
SR
Enable synchronous rectification
2
DIR
Logic input
3
Output A for for full-bridge 1
4
PFD
Mixed decay setting
5
RC1
Analog input for fixed off-time for full-bridge 1
6
Analog ground
7
OUT1A
Pin-out Diagram
Description
AGND
1
SR
2
27 SLEEP
REF
Current trip reference voltage input
8
DIR
3
26 ENABLE
RC2
Analog input for fixed off-time for full-bridge 2
9
OUT1A
4
25 OUT1B
PFD
5
VDD
Logic supply voltage
10
RC1
6
Output A for for full-bridge 2
11
AGND
7
REF
8
RC2
9
÷8
VDD 10 VDD
OUT2A 11
Charge
Pump
24 CP2
Translator
& Control Logic
PWM
Timer
SENSE1
23 CP1
OUT2A
22 VCP
MS2
Logic input
12
MS1
Logic input
13
Sense resistor for full-bridge 2
14
Load supply 2
15
FF1
Fault flag 1
16
FF2
Fault flag 2
17
Output B for for full-bridge 2
18
STEP
Logic input
19
VREG
Regulator decoupling
20
PGND
Power ground
21
VCP
Reservoir capacitor
22
CP1
Charge pump capacitor 1
23
CP2
Charge pump capacitor 2
24
Output B for for full-bridge 1
25
ENABLE
Logic input
26
SLEEP
Logic input
27
Load supply 1
28
21 PGND
Reg
20 VREG
19 STEP
18 OUT2B
MS2 12
17 FF2
MS1 13
16 FF1
SENSE2 14
VBB2 15 VBB2
SENSE2
VBB2
OUT2B
OUT1B
VBB1
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
Automotive DMOS Microstepping Driver
with Translator
A3980
Pacakge LP, 28-Pin TSSOP with Exposed Thermal Pad
0.45
9.70 ±0.10
28
+0.05
0.15 –0.06
0.65
28
4° ±4
1.65
B
3.00
4.40 ±0.10
6.40 ±0.20
3.00
6.10
0.60 ±0.15
A
1
(1.00)
2
5.1
0.25
28X
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
0.65
C
1 2
SEATING PLANE
GAUGE PLANE
5.1
C
PCB Layout Reference View
1.20 MAX
0.10 MAX
For reference only
(reference JEDEC MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Copyright ©2003-2010, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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115 Northeast Cutoff
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