A3983
DMOS Microstepping Driver with Translator
Features and Benefits
Description
▪
▪
▪
▪
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The A3983 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full-, half-, quarter-, and eighth-step
modes, with an output drive capacity of up to 35 V and ±2 A.
The A3983 includes a fixed off-time current regulator which
has the ability to operate in Slow or Mixed decay modes.
Low RDS(ON) outputs
Automatic current decay mode detection/selection
Mixed and Slow current decay modes
Synchronous rectification for low power dissipation
Internal UVLO and thermal shutdown circuitry
Crossover-current protection
Package: 24-pin TSSOP with exposed thermal pad
(suffix LP)
Not to scale
The translator is the key to the easy implementation of the
A3983. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A3983 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
The chopping control in the A3983 automatically selects the
current decay mode (Slow or Mixed). When a signal occurs at
the STEP input pin, the A3983 determines if that step results
in a higher or lower current in each of the motor phases. If
the change is to a higher current, then the decay mode is set to
Slow decay. If the change is to a lower current, then the current
decay is set to Mixed (set initially to a fast decay for a period
amounting to 31.25% of the fixed off-time, then to a slow
decay for the remainder of the off-time). This current decay
Continued on the next page…
Functional Block Diagram
0.1 μF
0.22 μF
VREG
VDD
Current
Regulator
ROSC
CP1
CP2
Charge
Pump
OSC
VCP
0.1 μF
DMOS Full Bridge
REF
DAC
VBB1
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
STEP
DIR
RESET
Translator
MS1
Control
Logic
MS2
DMOS Full Bridge
RS1
VBB2
OUT2A
OUT2B
PWM Latch
Blanking
Mixed Decay
ENABLE
SLEEP
SENSE2
RS2
DAC
VREF
26184.29D
SENSE1
Gate
Drive
A3983
DMOS Microstepping Driver with Translator
Description (continued)
control scheme results in reduced audible motor noise, increased
step accuracy, and reduced power dissipation.
lockout (UVLO), and crossover-current protection. Special poweron sequencing is not required.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation. Internal circuit
protection includes: thermal shutdown with hysteresis, undervoltage
The A3983 is supplied in a low-profile (1.2 mm maximum height),
24-pin TSSOP with exposed thermal pad (suffix LP). It is lead (Pb)
free, with 100% matte tin leadframe plating.
Selection Guide
Part Number
A3983SLPTR-T
Package
Packing
24-pin TSSOP with exposed thermal pad
4000 pieces per 13-in. reel
Absolute Maximum Ratings
Characteristic
Symbol
Load Supply Voltage
Notes
VBB
Output Current
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions,
do not exceed the specified current rating or a junction temperature of 150°C.
IOUT
Logic Input Voltage
Sense Voltage
Units
35
V
±2
A
VIN
–0.3 to 7
V
VSENSE
0.5
V
Reference Voltage
VREF
Operating Ambient Temperature
TA
Maximum Junction
Rating
Range S
4
V
–20 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
THERMAL CHARACTERISTICS
Characteristic
Symbol
Package Thermal Resistance
RθJA
Test Conditions*
Value Units
4-layer PCB, based on JEDEC standard)
28
ºC/W
*In still air. Additional thermal information available on Allegro Web site.
Maximum Power Dissipation, PD(max)
5.5
Power Dissipation, PD (W)
5.0
4.5
4.0
(R
3.5
θJ
3.0
2.5
A
=
28
ºC
/W
)
2.0
1.5
1.0
0.5
0.0
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A3983
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
Characteristics
Output Drivers
Min.
Typ.2
Max.
Units
8
0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
0.350
0.300
–
–
–
–
–
–
–
–
35
35
5.5
0.450
0.370
1.2
1.2
4
2
10
8
5
10
V
V
V
Ω
Ω
V
V
mA
mA
μA
mA
mA
μA
VIN(1)
VDD0.7
–
–
V
VIN(0)
–
–
V
μA
Symbol
Load Supply Voltage Range
VBB
Logic Supply Voltage Range
VDD
Output On Resistance
RDSON
Body Diode Forward Voltage
VF
Motor Supply Current
IBB
Logic Supply Current
IDD
Test Conditions
Operating
During Sleep Mode
Operating
Source Driver, IOUT = –1.5 A
Sink Driver, IOUT = 1.5 A
Source Diode, IF = –1.5 A
Sink Diode, IF = 1.5 A
fPWM < 50 kHz
Operating, outputs disabled
Sleep Mode
fPWM < 50 kHz
Outputs off
Sleep Mode
Control Logic
Logic Input Voltage
Logic Input Current
Microstep Select 2
Input Hysteresis
Blank Time
IIN(1)
IIN(0)
VIN = VDD0.7
VIN = VDD0.3
MS2
–20
3 V, then tOFF defaults to
30 μs. The ROSC pin can be safely connected to the VDD
pin for this purpose. The value of tOFF (μs) is approximately
tOFF ≈ ROSC ⁄ 825
Blanking. This function blanks the output of the current
sense comparators when the outputs are switched by the
internal current control circuitry. The comparator outputs are
blanked to prevent false overcurrent detection due to reverse
recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time,
tBLANK (μs), is approximately
tBLANK ≈ 1 μs
Charge Pump (CP1 and CP2). The charge pump is
used to generate a gate supply greater than that of VBB
for driving the source-side DMOS gates. A 0.1 μF ceramic
capacitor, should be connected between CP1 and CP2. In
addition, a 0.1 μF ceramic capacitor is required between
VCP and VBB, to act as a reservoir for operating the
high-side DMOS gates.
VREG (VREG). This internally-generated voltage is used
to operate the sink-side DMOS outputs. The VREG pin must
be decoupled with a 0.22 μF ceramic capacitor to ground.
VREG is internally monitored. In the case of a fault condition, the DMOS outputs of the A3983 are disabled.
Enable Input (ENABLE). This input turns on or off all of
the DMOS outputs. When set to a logic high, the outputs are
disabled. When set to a logic low, the internal control enables
the outputs as required. The translator inputs STEP, DIR,
MS1, and MS2, as well as the internal sequencing logic, all
remain active, independent of the ENABLE input state.
Shutdown. In the event of a fault, overtemperature
(excess TJ) or an undervoltage (on VCP), the DMOS outputs of the A3983 are disabled until the fault condition is
removed. At power-on, the UVLO (undervoltage lockout)
circuit disables the DMOS outputs and resets the translator to
the Home state.
Sleep Mode (SLEEP). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output DMOS FETs, current
regulator, and charge pump. A logic low on the SLEEP pin
puts the A3983 into Sleep mode. A logic high allows normal
operation, as well as start-up (at which time the A3983 drives
the motor to the Home microstep position). When emerging
from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command.
Mixed Decay Operation. The bridge can operate in
Mixed Decay mode, depending on the step sequence, as
shown in figures 3 thru 5. As the trip point is reached, the
A3983 initially goes into a fast decay mode for 31.25% of
the off-time. tOFF. After that, it switches to Slow Decay mode
for the remainder of tOFF.
Synchronous Rectification. When a PWM-off cycle
is triggered by an internal fixed–off-time cycle, load current
recirculates according to the decay mode selected by the
control logic. This synchronous rectification feature turns on
the appropriate FETs during current decay, and effectively
shorts out the body diodes with the low DMOS RDS(ON). This
reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications.
Turning off synchronous rectification prevents the reversal of
the load current when a zero-current level is detected.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
A3983
DMOS Microstepping Driver with Translator
Application Layout
be created using the exposed thermal pad under the device, to
serve both as a low impedance ground point and thermal path.
Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the
A3983 must be soldered directly onto the board. On the underside of the A3983 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
The two input capacitors should be placed in parallel, and as
close to the device supply pins as possible. The ceramic capacitor (CIN1) should be closer to the pins than the bulk capacitor
(CIN2). This is necessary because the ceramic capacitor will be
responsible for delivering the high frequency current components.
The sense resistors, RSx , should have a very low impedance
path to ground, because they must carry a large current while
supporting very accurate voltage measurements by the current
sense comparators. Long ground traces will cause additional
voltage drops, adversely affecting the ability of the comparators
to accurately measure the current in the windings. The SENSEx
pins have very short traces to the RSx resistors and very thick,
low impedance traces directly to the star ground underneath the
device. If possible, there should be no other components on the
sense circuits.
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance single-point
ground, known as a star ground, located very close to the device.
By making the connection between the pad and the ground plane
directly under the A3983, that area becomes an ideal location for
a star ground point. A low impedance ground will prevent ground
bounce during high current operation and ensure that the supply
voltage remains stable at the input terminal. The star ground can
Solder
A3983
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
Thermal Vias
OUT2B
C3
U1
GND
C6
GND
C4
GND
C3
OUT2A
C5
R4
ROSC
R5
C4
C5
OUT1A
C1
RESET
OUT1B
GND
BULK
GND
CAPACITANCE
C2
VDD
VCP
VREG
ROSC
SLEEP
VDD
STEP
C1
REF
GND
VDD
GND
ENABLE
OUT2B
CP2
MS1
MS2
GND
ROSC
GND
A3983
CP1
VBB2
PAD
C6
SENSE2
OUT2A
R4
OUT1A
SENSE1
VBB1
R5
OUT1B
DIR
C2
GND
VBB
VBB
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
A3983
DMOS Microstepping Driver with Translator
STEP
STEP
100.00
100.00
70.71
70.71
Slow
Phase 1
IOUT1A
Direction = H
(%)
–100.00
100.00
Phase 2
IOUT2A
Direction = H
(%)
–100.00
100.00
70.71
Phase 2
IOUT2B
Direction = H
(%)
0.00
Slow
Slow Slow
Mixed
Mixed
Slow
Slow
Mixed
0.00
–70.71
–70.71
–100.00
–100.00
Figure 2. Decay Mode for Full-Step Increments
Mixed
0.00
–70.71
70.71
Slow
Mixed
Home Microstep Position
–70.71
Home Microstep Position
0.00
Slow
Mixed
Home Microstep Position
Slow
Home Microstep Position
Phase 1
IOUT1A
Direction = H
(%)
Figure 3. Decay Modes for Half-Step Increments
STEP
100.00
92.39
70.71
38.27
Slow
Mixed
Slow
Mixed
Slow
0.00
Home Microstep Position
Phase 1
IOUT1A
Direction = H
(%)
–38.27
–70.71
–92.39
–100.00
100.00
92.39
70.71
Phase 2
IOUT2B
Direction = H
(%)
38.27
Slow
Mixed
Slow
Mixed
Slow
Mixed
0.00
–38.27
–70.71
–92.39
–100.00
Figure 4. Decay Modes for Quarter-Step Increments
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
A3983
DMOS Microstepping Driver with Translator
STEP
100.00
92.39
83.15
70.71
55.56
38.27
19.51
0.00
Slow
Mixed
Mixed
Slow
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–100.00
100.00
92.39
83.15
70.71
55.56
Phase 2
IOUT2B
Direction = H
(%)
Slow
Mixed
Mixed
Slow
Home Microstep Position
Phase 1
IOUT1A
Direction = H
(%)
38.27
19.51
0.00
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–100.00
Figure 5. Decay Modes for Eighth-Step Increments
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
A3983
DMOS Microstepping Driver with Translator
Table 2. Step Sequencing Settings
Home microstep position at Step Angle 45º; DIR = H
Full
Step
#
1
Half
Step
#
1
2
4
3
6
4
8
(%)
100.00
(%)
0.00
2
98.08
19.51
11.3
92.39
38.27
22.5
4
83.15
55.56
33.8
3
5
Step
Angle
(º)
0.0
5
70.71
70.71
45.0
6
55.56
83.15
56.3
7
38.27
92.39
67.5
8
19.51
98.08
78.8
9
0.00
100.00
90.0
101.3
10
–19.51
98.08
11
–38.27
92.39
112.5
12
–55.56
83.15
123.8
13
–70.71
70.71
135.0
14
–83.15
55.56
146.3
15
–92.39
38.27
157.5
16
–98.08
19.51
168.8
9
17
–100.00
0.00
180.0
18
–98.08
–19.51
191.3
10
19
–92.39
–38.27
202.5
20
–83.15
–55.56
213.8
21
–70.71
–70.71
225.0
22
–55.56
–83.15
236.3
23
–38.27
–92.39
247.5
24
–19.51
–98.08
258.8
13
25
0.00
–100.00
270.0
26
19.51
–98.08
281.3
14
27
38.27
–92.39
292.5
28
55.56
–83.15
303.8
29
70.71
–70.71
315.0
30
83.15
–55.56
326.3
31
92.39
–38.27
337.5
32
98.08
–19.51
348.8
7
11
12
7
[% ItripMax]
3
8
5
[% ItripMax]
2
6
2
Phase 2
Current
1/8
Step
#
1
4
3
Phase 1
Current
1/4
Step
#
1
15
16
10
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A3983
DMOS Microstepping Driver with Translator
Package LP
CP1
1
24 GND
CP2
2
23 ENABLE
VCP
3
22 OUT2B
VREG
4
21 VBB2
MS1
5
MS2
6
RESET
7
18 OUT1A
ROSC
8
17 SENSE1
SLEEP
9
16 VBB1
20 SENSE2
PAD
VDD 10
19 OUT2A
15 OUT1B
STEP 11
14 DIR
REF 12
13 GND
Terminal List Table
Number
Name
Description
Package LP
CP1
1
Charge pump capacitor terminal
CP2
2
Charge pump capacitor terminal
VCP
3
Reservoir capacitor terminal
VREG
4
Regulator decoupling terminal
MS1
5
Logic input
MS2
6
Logic input
RESET
7
Logic input
ROSC
8
Timing set
SLEEP
9
Logic input
VDD
10
Logic supply
STEP
11
Logic input
REF
12
Gm reference voltage input
GND
13, 24
Ground*
DIR
14
Logic input
OUT1B
15
DMOS Full Bridge 1 Output B
VBB1
16
Load supply
SENSE1
17
Sense resistor terminal for Bridge 1
OUT1A
18
DMOS Full Bridge 1 Output A
OUT2A
19
DMOS Full Bridge 2 Output A
SENSE2
20
Sense resistor terminal for Bridge 2
VBB2
21
Load supply
OUT2B
22
DMOS Full Bridge 2 Output B
ENABLE
23
Logic input
NC
–
No connection
PAD
–
Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane
under the device.
11
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A3983
DMOS Microstepping Driver with Translator
LP Package, 24-Pin TSSOP with Exposed Thermal Pad
7.80 ±0.10
24
0.65
0.45
4° ±4
+0.05
0.15 –0.06
B
3.00
4.40 ±0.10
6.40 ±0.20
A
1
6.10
(1.00)
2
4.32
0.25
24X
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
3.00
0.60 ±0.15
0.65
1.20 MAX
0.15 MAX
C
SEATING PLANE
GAUGE PLANE
1.65
4.32
C
PCB Layout Reference View
For reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
12
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A3983
DMOS Microstepping Driver with Translator
Copyright ©2005-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
13
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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