A3984SLPTR-T

A3984 DMOS Microstepping Driver with Translator Package LP CP1 CP2 VCP VREG MS1 MS2 RESET ROSC SLEEP 1 24 GND 2 3 23 ENABLE 22 OUT2B 21 VBB2 20 SENSE2 4 5 6 7 19 OUT2A 18 OUT1A 17 SENSE1 16 VBB1 15 OUT1B 14 DIR 13 GND 8 9 VDD 10 STEP 11 REF 12 Approximate Scale 1:1 ABSOLUTE MAXIMUM RATINGS Load Supply Voltage,VBB ...................................35 V Output Current, IOUT ......................................... ±2 A* Logic Input Voltage, VIN ..................... –0.3 V to 7 V Sense Voltage, VSENSE .......................................0.5 V Reference Voltage, VREF ……….. ........................ 4 V Operating Temperature Range Ambient, TA ................................. –20°C to 85°C Junction Temperature, TJ(MAX)..................... 150°C Storage Temperature, TS .................... –55°C to 150°C The A3984 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes, with an output drive capacity of up to 35 V and ±2 A. The A3984 includes a fixed offtime current regulator which has the ability to operate in Slow or Mixed decay modes. The translator is the key to the easy implementation of the A3984. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A3984 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. The chopping control in the A3984 automatically selects the current decay mode (Slow or Mixed). When a signal occurs at the STEP input pin, the A3984 determines if that step results in a higher or lower current in each of the motor phases. If the change is to a higher current, then the decay mode is set to Slow decay. If the change is to a lower current, then the current decay is set to Mixed (set initially to a fast decay for a period amounting to 31.25% of the fixed off-time, then to a slow decay for the remainder of the off-time). This current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-on sequencing is not required. The A3984 is supplied in a low-profile (1.2 mm maximum), 24-pin TSSOP with exposed thermal pad (package LP). It is also available in a lead (Pb) free version (suffix –T), with 100% matte tin plated leadframes. Reg Charge Pump Translator & Control Logic OSC FEATURES *Output current rating may be limited by duty cycle, Selection Guide Part Number Low RDS(ON) outputs Automatic current decay mode detection/selection Mixed and Slow current decay modes Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection Pb-free* Package Packing ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. A3984SLP-T Yes 24-pin TSSOP 62 per tube A3984SLPTR-T Yes 24-pin TSSOP 4000 per reel *Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production but have been determined to be LAST TIME BUY. This classification indicates that sale of this device is currently restricted to existing customer applications. The variants should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: October 31, 2006. Deadline for receipt of LAST TIME BUY orders: April 27, 2007. These variants include: A3984SLP and A3984SLPTR. 26184.30Bpb A3984 DMOS Microstepping Driver with Translator Functional Block Diagram 0.1 uF 0.22 uF VREG ROSC CP1 CP2 VDD Current Regulator OSC Charge Pump VCP REF DMOS Full Bridge 0.1 uF VBB1 DAC OUT1A OUT1B PWM Latch Blanking Mixed Decay SENSE1 Gate Drive RS1 VBB2 STEP DIR RESET MS1 MS2 Translator Control Logic DMOS Full Bridge OUT2A OUT2B ENABLE SLEEP PWM Latch Blanking Mixed Decay SENSE2 RS2 DAC VREF 26184.30A Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A3984 DMOS Microstepping Driver with Translator ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted) Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage Symbol Test Conditions Operating During Sleep Mode Operating Source Driver, IOUT = –1.5 A Sink Driver, IOUT = 1.5 A Source Diode, IF = –1.5 A Sink Diode, IF = 1.5 A fPWM < 50 kHz Operating, outputs disabled Sleep Mode fPWM < 50 kHz Outputs off Sleep Mode Min. 8 0 3.0 – – – – – – – – – – VDD×0.7 VIN = VDD×0.7 – –20 –20 – 150 0.7 20 23 0 –3 – – – 100 – – 2.35 0.05 Typ.2 – – – 0.350 0.300 – – – – – – – – – – 3 V, then tOFF defaults to 30 μ s. The ROSC pin can be safely connected to the VDD pin for this purpose. The value of tOFF (μ s) is approximately tOFF ≈ (ROSC ⁄ 880) + 1.6 Shutdown. In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the DMOS outputs of the A3984 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the DMOS outputs and resets the translator to the Home state. Blanking. This function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK (μ s), is approximately tBLANK ≈ 1 μ s Sleep Mode (SLEEP). To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output DMOS FETs, current regulator, and charge pump. A logic low on the SLEEP pin puts the A3984 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A3984 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command. Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side DMOS gates. A 0.1 μ F ceramic capacitor, should be connected between CP1 and CP2. In addition, a 0.1 μ F ceramic capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side DMOS gates. Mixed Decay Operation. The bridge can operate in Mixed Decay mode, depending on the step sequence, as shown in figures 3 thru 5. As the trip point is reached, the A3984 initially goes into a fast decay mode for 31.25% of the off-time. tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. VREG (VREG). This internally-generated voltage is used to operate the sink-side DMOS outputs. The VREG pin must be decoupled with a 0.22 μ F capacitor to ground. VREG is internally monitored. In the case of a fault condition, the DMOS outputs of the A3984 are disabled. Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed–off-time cycle, load current recirculates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low DMOS RDSON. This reduces power dissipation significantly, and can eliminate the need for external Schottky diodes in many applications. Turning off synchronous rectification prevents the reversal of the load current when a zero-current level is detected. Enable Input (ENABLE). This input turns on or off all of the DMOS outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs STEP, DIR, MS1, and MS2, as well as the internal sequencing logic, all remain active, independent of the ENABLE input state. 26184.30A Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A3984 DMOS Microstepping Driver with Translator STEP 100.00 70.71 STEP 100.00 70.71 Slow Slow Mixed Slow Mixed Home Microstep Position Home Microstep Position –70.71 –100.00 100.00 70.71 Home Microstep Position –70.71 –100.00 100.00 70.71 Slow Slow Mixed Mixed Slow Mixed Phase 2 IOUT2A Direction = H (%) 0.00 Slow –70.71 Phase 2 IOUT2B Direction = H (%) 0.00 –70.71 –100.00 –100.00 Figure 2. Decay Mode for Full-Step Increments STEP 100.00 92.39 70.71 Figure 3. Decay Modes for Half-Step Increments –38.27 –70.71 –92.39 –100.00 100.00 92.39 70.71 Phase 2 IOUT2B Direction = H (%) 38.27 Slow Mixed Slow Mixed Slow Mixed 0.00 –38.27 –70.71 –92.39 –100.00 Figure 4. Decay Modes for Quarter-Step Increments Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Home Microstep Position Phase 1 IOUT1A Direction = H (%) 38.27 Slow 0.00 Mixed Slow Mixed Slow Home Microstep Position Phase 1 IOUT1A Direction = H (%) Slow 0.00 Phase 1 IOUT1A Direction = H (%) Mixed 0.00 Slow 8 26184.30A A3984 DMOS Microstepping Driver with Translator STEP 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 Phase 1 IOUT1A Direction = H (%) 9.8 0.00 –9.8 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –95.69 –100.00 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 Slow Mixed Slow Mixed Phase 2 IOUT2B Direction = H (%) 9.8 0.00 –9.8 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –95.69 –100.00 Slow Mixed Slow Mixed Slow Figure 5. Decay Modes for Sixteenth-Step Increments 26184.30A Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Home Microstep Position 9 A3984 DMOS Microstepping Driver with Translator Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Full Step # Half Step # 1 1/4 Step # 1 1/16 Step # 1 2 3 4 2 5 6 7 8 1 2 3 9 10 11 12 4 13 14 15 16 3 5 17 18 19 20 6 21 22 23 24 2 4 7 25 26 27 28 8 29 30 31 32 Phase 1 Current [% ItripMax] Phase 2 Current [% ItripMax] (%) 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 0.00 –9.80 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –92.39 –95.69 –98.08 –99.52 (%) 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 Step Angle (º) 0.0 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45.0 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90.0 95.6 101.3 106.9 112.5 118.1 123.8 129.4 135.0 140.6 146.3 151.9 157.5 163.1 168.8 174.4 Full Step # Half Step # 5 1/4 Step # 9 1/16 Step # 33 34 35 36 Phase 1 Current [% ItripMax] Phase 2 Current [% ItripMax] Step Angle (º) (%) –100.00 –99.52 –98.08 –95.69 –92.39 –88.19 –83.15 –77.30 –70.71 –63.44 –55.56 –47.14 –38.27 –29.03 –19.51 –9.80 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 (%) 0.00 –9.80 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –92.39 –95.69 –98.08 –99.52 –100.00 –99.52 –98.08 –95.69 –92.39 –88.19 –83.15 –77.30 –70.71 –63.44 –55.56 –47.14 –38.27 –29.03 –19.51 –9.80 180.0 185.6 191.3 196.9 202.5 208.1 213.8 219.4 225.0 230.6 236.3 241.9 247.5 253.1 258.8 264.4 270.0 275.6 281.3 286.9 292.5 298.1 303.8 309.4 315.0 320.6 326.3 331.9 337.5 343.1 348.8 354.4 10 37 38 39 40 3 6 11 41 42 43 44 12 45 46 47 48 7 13 49 50 51 52 14 53 54 55 56 4 8 15 57 58 59 60 16 61 62 63 64 26184.30A Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 10 A3984 DMOS Microstepping Driver with Translator Pin List Table Name CP1 CP2 VCP VREG MS1 MS2 RESET ROSC SLEEP VDD STEP REF GND DIR OUT1B VBB1 SENSE1 OUT1A OUT2A SENSE2 VBB2 OUT2B ENABLE GND Description Charge pump capacitor 1 Charge pump capacitor 2 Reservoir capacitor Regulator decoupling Logic input Logic input Logic input Timing set Logic input Logic supply Logic input Current trip reference voltage input Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Ground* Logic input DMOS Full Bridge 1 Output B Load supply Sense resistor for Bridge 1 DMOS Full Bridge 1 Output A DMOS Full Bridge 2 Output A Sense resistor for Bridge 2 Load supply DMOS Full Bridge 2 Output B Logic input Ground* *The two GND pins must be tied together externally by connecting to the exposed pad ground plane under the device. 26184.30A Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 11 A3984 DMOS Microstepping Driver with Translator LP Package, 24-Pin TSSOP with Exposed Thermal Pad 26184.30A Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 12 A3984 DMOS Microstepping Driver with Translator The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2005 AllegroMicrosystems, Inc. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 13 26184.30A