A3984
DMOS Microstepping Driver with Translator
FEATURES AND BENEFITS
DESCRIPTION
▪ Low RDS(ON) outputs
▪ Automatic current decay mode detection/selection
▪ Mixed and Slow current decay modes
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO and thermal shutdown circuitry
▪ Crossover-current protection
The A3984 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to
operate bipolar stepper motors in full-, half-, quarter-, and
sixteenth-step modes, with an output drive capacity of up to
35 V and ±2 A. The A3984 includes a fixed off-time current
regulator which has the ability to operate in Slow or Mixed
decay modes.
The translator is the key to the easy implementation of the
A3984. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence
tables, high frequency control lines, or complex interfaces to
program. The A3984 interface is an ideal fit for applications
where a complex microprocessor is unavailable or is
overburdened.
The chopping control in the A3984 automatically selects
the current decay mode (Slow or Mixed). When a signal
occurs at the STEP input pin, the A3984 determines if
that step results in a higher or lower current in each of the
motor phases. If the change is to a higher current, then the
decay mode is set to Slow decay. If the change is to a lower
current, then the current decay is set to Mixed (set initially
to a fast decay for a period amounting to 31.25% of the
fixed off-time, then to a slow decay for the remainder of the
PACKAGE: 24-pin TSSOP with exposed
thermal pad (suffix LP)
Not to scale
Continued on the next page…
Pinout Diagram
3
VREG
4
MS1
5
MS2
6
RESET
7
ROSC
8
SLEEP
9
VDD 10
STEP 11
REF 12
26184.30, Rev. 7
MCO-0000917
23 ENABLE
22 OUT2B
21 VBB2
20 SENSE2
Translator
& Control Logic
2
Charge
Pump
CP2
VCP
24 GND
Reg
1
OSC
CP1
19 OUT2A
18 OUT1A
17 SENSE1
16 VBB1
15 OUT1B
14 DIR
13 GND
July 6, 2022
A3984
DMOS Microstepping Driver with Translator
DESCRIPTION (continued)
off-time). This current decay control scheme results in reduced
audible motor noise, increased step accuracy, and reduced power
dissipation.
hysteresis, undervoltage lockout (UVLO), and crossover-current
protection. Special power-on sequencing is not required.
The A3984 is supplied in a low-profile (1.2 mm maximum),
24-pin TSSOP with exposed thermal pad (package LP). It is lead
(Pb) free, with 100% matte tin leadframe plating.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Internal circuit protection includes: thermal shutdown with
SELECTION GUIDE
Part Number
A3984SLPTR-T
Packing
4000 pieces per 13-in. reel
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Rating
Units
35
V
±2
A
VIN
–0.3 to 7
V
VSENSE
0.5
V
VREF
4
V
Load Supply Voltage
VBB
Output Current
IOUT
Logic Input Voltage
Sense Voltage
Reference Voltage
Operating Ambient Temperature
Maximum Junction
Storage Temperature
Notes
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions,
do not exceed the specified current rating or a junction temperature of 150°C.
–20 to 85
°C
TJ(max)
TA
Range S
150
°C
Tstg
–55 to 150
°C
THERMAL CHARACTERISTICS
Characteristic
Package Thermal Resistance
Symbol
Test Conditions*
RθJA
Value
Units
28
°C/W
4-layer PCB, based on JEDEC standard
*Additional thermal information available on Allegro website.
Maximum Power Dissipation, PD(max)
5.5
Power Dissipation, PD (W)
5.0
4.5
4.0
(R
3.5
θJ
3.0
2.5
A
=
28
ºC
/W
)
2.0
1.5
1.0
0.5
0.0
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems
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A3984
DMOS Microstepping Driver with Translator
FUNCTIONAL BLOCK DIAGRAM
0.1 uF
0.22 uF
VREG
VDD
Current
Regulator
ROSC
CP1
CP2
Charge
Pump
OSC
VCP
0.1 uF
REF
DMOS Full Bridge
DAC
VBB1
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
STEP
Gate
Drive
DIR
RESET
SENSE1
Translator
MS1
Control
Logic
MS2
DMOS Full Bridge
RS1
VBB2
OUT2A
OUT2B
PWM Latch
Blanking
Mixed Decay
ENABLE
SLEEP
SENSE2
RS2
DAC
VREF
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A3984
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS [1]: Valid at TA = 25°C, VBB = 35 V (unless otherwise noted)
Characteristics
Symbol
Test Conditions
Min.
Typ. [2]
Max.
Units
8
–
35
V
OUTPUT DRIVERS
Load Supply Voltage Range
VBB
Logic Supply Voltage Range
VDD
Output On Resistance
Body Diode Forward Voltage
Motor Supply Current
Logic Supply Current
Operating
0
–
35
V
3.0
–
5.5
V
Source Driver, IOUT = –1.5 A
–
0.350
0.450
Ω
Sink Driver, IOUT = 1.5 A
–
0.300
0.370
Ω
Source Diode, IF = –1.5 A
–
–
1.2
V
Sink Diode, IF = 1.5 A
–
–
1.2
V
fPWM < 50 kHz
–
–
4
mA
Operating, outputs disabled
–
–
2
mA
Sleep Mode
–
–
10
μA
fPWM < 50 kHz
–
–
8
mA
Outputs off
–
–
5
mA
Sleep Mode
–
–
10
μA
VIN(1)
VDD × 0.7
–
–
V
VIN(0)
–
–
VDD × 0.3
V
µA
RDSON
VF
IBB
IDD
During Sleep Mode
Operating
CONTROL LOGIC
Logic Input Voltage
Logic Input Current
Microstep Select 2
Input Hysteresis
Blank Time
IIN(1)
VIN = VDD×0.7
–20
3 V, then tOFF defaults to 30 µs. The ROSC pin can
be safely connected to the VDD pin for this purpose. The value
of tOFF (µs) is approximately
tOFF = ROSC ⁄ 825
Blanking. This function blanks the output of the current sense
comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to
prevent false overcurrent detection due to reverse recovery cur-
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A3984
DMOS Microstepping Driver with Translator
rents of the clamp diodes, and switching transients related to the
capacitance of the load. The blank time, tBLANK (µs), is approximately
tBLANK ≈ 1 µs
Charge Pump (CP1 and CP2). The charge pump is used to
generate a gate supply greater than that of VBB for driving the
source-side DMOS gates. A 0.1 µF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 µF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high‑side DMOS gates.
VREG (VREG). This internally generated voltage is used to
operate the sink-side DMOS outputs. The VREG pin must be
decoupled with a 0.22 µF capacitor to ground. VREG is internally monitored. In the case of a fault condition, the DMOS
outputs of the A3984 are disabled.
Enable Input (ENABLE). This input turns on or off all of
the DMOS outputs. When set to a logic high, the outputs are
disabled. When set to a logic low, the internal control enables the
outputs as required. The translator inputs STEP, DIR, MS1, and
MS2, as well as the internal sequencing logic, all remain active,
independent of the ENABLE input state.
Shutdown. In the event of a fault, overtemperature (excess TJ)
or an undervoltage (on VCP), the DMOS outputs of the A3984
are disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the DMOS outputs
and resets the translator to the Home state.
Sleep Mode (SLEEP). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output DMOS FETs, current regulator, and charge pump. A logic low on the SLEEP pin puts the
A3984 into Sleep mode. A logic high allows normal operation, as
well as start-up (at which time the A3984 drives the motor to the
Home microstep position). When emerging from Sleep mode, in
order to allow the charge pump to stabilize, provide a delay of 1
ms before issuing a Step command.
Mixed Decay Operation. The bridge can operate in Mixed
Decay mode, depending on the step sequence, as shown in figures 3 through 5. As the trip point is reached, the A3984 initially
goes into a fast decay mode for 31.25% of the off-time. tOFF.
After that, it switches to Slow Decay mode for the remainder of
tOFF.
Synchronous Rectification. When a PWM-off cycle is
triggered by an internal fixed–off-time cycle, load current recirculates according to the decay mode selected by the control logic.
This synchronous rectification feature turns on the appropriate
FETs during current decay, and effectively shorts out the body
diodes with the low DMOS RDSON. This reduces power dissipation significantly and can eliminate the need for external Schottky
diodes in many applications. Turning off synchronous rectification
prevents the reversal of the load current when a zero-current level is
detected.
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A3984
DMOS Microstepping Driver with Translator
STEP
STEP
100.00
100.00
70.71
70.71
Slow
100.00
Phase 2
IOUT2A
Direction = H
(%)
–100.00
100.00
70.71
Phase 2
IOUT2B
Direction = H
(%)
0.00
Slow
Slow Slow
Mixed
Mixed
Slow
Slow
Mixed
0.00
–70.71
–70.71
–100.00
–100.00
Figure 2. Decay Mode for Full-Step Increments
Mixed
0.00
–70.71
70.71
Slow
Mixed
Home Microstep Position
–100.00
Home Microstep Position
–70.71
Slow
Mixed
Home Microstep Position
Phase 1
IOUT1A
Direction = H
(%)
0.00
Home Microstep Position
Phase 1
IOUT1A
Direction = H
(%)
Slow
Figure 3. Decay Modes for Half-Step Increments
STEP
100.00
92.39
70.71
38.27
Slow
Mixed
Slow
Mixed
Slow
0.00
Home Microstep Position
Phase 1
IOUT1A
Direction = H
(%)
–38.27
–70.71
–92.39
–100.00
100.00
92.39
70.71
Phase 2
IOUT2B
Direction = H
(%)
38.27
Slow
Mixed
Slow
Mixed
Slow
Mixed
0.00
–38.27
–70.71
–92.39
–100.00
Figure 4. Decay Modes for Quarter-Step Increments
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A3984
DMOS Microstepping Driver with Translator
STEP
100.00
95.69
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
Phase 1
IOUT1A
Direction = H
(%)
9.8
Slow
0.00
Mixed
Slow
Mixed
–9.8
–19.51
–29.03
Home Microstep Position
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–95.69
–100.00
100.00
95.69
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
Phase 2
IOUT2B
Direction = H
(%)
9.8
0.00
Slow
Mixed
Slow
Mixed
Slow
–9.8
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–95.69
–100.00
Figure 5. Decay Modes for Sixteenth-Step Increments
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A3984
DMOS Microstepping Driver with Translator
Table 2. Step Sequencing Settings
Home microstep position at Step Angle 45°; DIR = H
Full
Step
#
Half
Step
#
1
1/4
Step
#
1
2
1
2
3
4
3
5
6
2
4
7
8
1/16
Step
#
1
Phase 1
Current
[% ItripMax]
(%)
100.00
Phase 2
Current
[% ItripMax]
(%)
0.00
Step
Angle
(°)
0.0
Full
Step
#
Half
Step
#
5
1/4
Step
#
9
Phase 1
Current
1/16
Step
#
33
[% ItripMax]
(%)
–100.00
Phase 2
Current
[% ItripMax]
(%)
0.00
Step
Angle
(°)
180.0
2
99.52
9.80
5.6
34
–99.52
–9.80
185.6
3
98.08
19.51
11.3
35
–98.08
–19.51
191.3
4
95.69
29.03
16.9
36
–95.69
–29.03
196.9
5
92.39
38.27
22.5
37
–92.39
–38.27
202.5
6
88.19
47.14
28.1
38
–88.19
–47.14
208.1
7
83.15
55.56
33.8
39
–83.15
–55.56
213.8
8
77.30
63.44
39.4
40
–77.30
–63.44
219.4
9
70.71
70.71
45.0
41
–70.71
–70.71
225.0
10
63.44
77.30
50.6
42
–63.44
–77.30
230.6
11
55.56
83.15
56.3
43
–55.56
–83.15
236.3
12
47.14
88.19
61.9
44
–47.14
–88.19
241.9
13
38.27
92.39
67.5
45
–38.27
–92.39
247.5
14
29.03
95.69
73.1
46
–29.03
–95.69
253.1
15
19.51
98.08
78.8
47
–19.51
–98.08
258.8
16
9.80
99.52
84.4
48
–9.80
–99.52
264.4
17
0.00
100.00
90.0
49
0.00
–100.00
270.0
18
–9.80
99.52
95.6
50
9.80
–99.52
275.6
19
–19.51
98.08
101.3
51
19.51
–98.08
281.3
20
–29.03
95.69
106.9
52
29.03
–95.69
286.9
21
–38.27
92.39
112.5
53
38.27
–92.39
292.5
22
–47.14
88.19
118.1
54
47.14
–88.19
298.1
23
–55.56
83.15
123.8
55
55.56
–83.15
303.8
24
–63.44
77.30
129.4
56
63.44
–77.30
309.4
25
–70.71
70.71
135.0
57
70.71
–70.71
315.0
26
–77.30
63.44
140.6
58
77.30
–63.44
320.6
27
–83.15
55.56
146.3
59
83.15
–55.56
326.3
28
–88.19
47.14
151.9
60
88.19
–47.14
331.9
29
–92.39
38.27
157.5
61
92.39
–38.27
337.5
30
–95.69
29.03
163.1
62
95.69
–29.03
343.1
31
–98.08
19.51
168.8
63
98.08
–19.51
348.8
32
–99.52
9.80
174.4
64
99.52
–9.80
354.4
10
3
6
11
12
7
13
14
4
8
15
16
Allegro MicroSystems
955 Perimeter Road
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A3984
DMOS Microstepping Driver with Translator
Pin List Table
Name
Description
Number
CP1
Charge pump capacitor 1
1
CP2
Charge pump capacitor 2
2
VCP
Reservoir capacitor
3
Regulator decoupling
4
MS1
Logic input
5
VREG
MS2
Logic input
6
RESET
Logic input
7
ROSC
Timing set
8
SLEEP
Logic input
9
VDD
Logic supply
10
STEP
Logic input
11
REF
Current trip reference voltage input
12
GND
Ground*
13
DIR
Logic input
14
DMOS Full Bridge 1 Output B
15
Load supply
16
OUT1B
VBB1
SENSE1
Sense resistor for Bridge 1
17
OUT1A
DMOS Full Bridge 1 Output A
18
OUT2A
DMOS Full Bridge 2 Output A
19
Sense resistor for Bridge 2
20
Load supply
21
DMOS Full Bridge 2 Output B
22
Logic input
23
Ground*
24
SENSE2
VBB2
OUT2B
ENABLE
GND
*The two GND pins must be tied together externally by connecting to the exposed
pad ground plane under the device.
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A3984
DMOS Microstepping Driver with Translator
LP Package, 24-Pin TSSOP with Exposed Thermal Pad
For Reference Only – Not for Tooling Use
(Reference Allegro DWG-0000379, Rev. 3 and JEDEC MO-153ADT)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
7.80 ±0.10
4.32 NOM
8º
0º
24
0.20
0.09
B
3 NOM
4.40 ±0.10 6.40 ±0.20
A
0.60 ±0.15 1.00 REF
1
2
0.25 BSC
24×
1.20 MAX
0.10 C
0.30
0.19
0.65 BSC
0.45
SEATING PLANE
C
GAUGE PLANE
SEATING
PLANE
0.15
0.025
XXXXXXXXX
Date Code
Lot Number
0.65
1
D
Standard Branding Reference View
Line 1: Part number
Line 2: Logo A, 4-digit date code
Line 3: Characters 5, 6, 7, 8 of
Assembly Lot Number
1.65
3.00
4.32
C
6.10
A
Terminal #1 mark area.
B
Exposed thermal pad (bottom surface); dimensions may vary with device.
C
Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias can improve thermal dissipation
(reference EIA/JEDEC Standard JESD51-5).
D
Branding scale and appearance at supplier discretion.
PCB Layout Reference View
Allegro MicroSystems
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A3984
DMOS Microstepping Driver with Translator
Revision History
Number
Date
Description
6
July 10, 2020
Minor editorial updates
7
July 6, 2022
Updated package drawing (page 12) and minor editorial updates
Copyright 2022, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
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