A4412KLVTR-T

A4412 Buck or Buck/Boost Pre-Regulator with a Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI FEATURES AND BENEFITS • A2-SIL™ product—device features for safety critical systems • Automotive AEC-Q100 qualified • Wide input voltage range, 3.8 to 40 VIN operating range, 50 VIN maximum • Buck or buck/boost pre-regulator (VREG) • Adjustable 1.3 to 3.3 V, 400 mA synchronous buck. • Four internal linear regulators with foldback short-circuit protection, 3.3 V (3V3) and three 5 V (V5CAN, V5A, and V5B) • One internal 5 V linear regulator (V5P) with foldback short-circuit and short-to-battery protection • Power-on reset signal indicating a fault on the synchronous buck, 3V3 or V5A regulator outputs (NPOR) • Window watchdog timer with fail-safe features • Dual bandgaps for increased safety coverage and fault detection, BGVREF, BGFAULT • Control and diagnostic reporting through a serial peripheral interface (SPI) • Logic enable input (ENB) for microprocessor control • Ignition enable input (ENBAT) with status indicator output • Frequency dithering and controlled slew rate helps reduce EMI/EMC • OV and UV protection for all output rails • Pin-to-pin and pin-to-ground tolerant at every pin APPLICATIONS • Automotive Control Modules for: □ EPS modules □ Automotive power trains □ CAN power supplies □ High-temperature applications - Enable inputs to the A4412 include a logic level (ENB) and a high-voltage (ENBAT). The A4412 also provides flexibility with disable function of the individual 5 V rails through a serial peripheral interface (SPI). Diagnostic outputs from the A4412 include a power-on-reset output (NPOR), an ENBAT status output, and a fault flag output to alert the microprocessor that a fault has occurred. The microprocessor can read fault status through SPI. Dual bandgaps, one for regulation and one for fault checking, improve safety coverage and fault detection of the A4412. The A4412 contains a Window Watchdog timer with a detect period of 2 ms. The watchdog timer is activated once it receives valid 2 ms pulses from the processor. The watchdog can be put into flash mode or be reset via secure SPI commands. The A4412 is supplied in a low-profile (1.2 mm maximum height) 38-lead eTSSOP package (suffix “LV”) with exposed power pad. Not to scale Dual Bandgaps The A4412 is a power management IC that uses a buck or buck/ boost pre-regulator to efficiently convert automotive battery voltages into a tightly regulated intermediate voltage complete with control, diagnostics and protections. The output of the preregulator supplies a 5 V / 100 mA protected linear regulator, a 3.3 V / 90 mA linear regulator, a 5 V / 200 mA linear regulator, a 5 V / 55 mA linear regulator, a 5 V / 30 mA linear regulator and an adjustable 400 mA synchronous buck regulator. Designed to supply CAN transceiver, sensor, and microprocessor power supplies in high-temperature environments, the A4412 is ideal for under-hood applications. Protection features include undervoltage and overvoltage on all output rails. In case of a shorted output, all linear regulators feature foldback overcurrent protection. In addition, the V5P output is protected from a short-to-battery event. Both switching regulators include pulse-by-pulse current limit, hiccup mode short-circuit protection, LX short-circuit protection, missing asynchronous diode protection (VREG only) and thermal shutdown. 2 PACKAGE: 38-Pin eTSSOP (suffix LV) Enable and Startup Timing DESCRIPTION Charge Pump Thermal Shutdown (TSD) 5.35 V (VREG) Buck-Boost Pre-Regulator Serial Interface (SPI) Adjustable 1.305 to 3.3 V Sync. Buck Regulator OV/UV Detect with BIST and NPOR 3.3 V Linear Regulator with Foldback Protection Clock Edge Window Watchdog 5 V Linear Regulator with Foldback Protection 5 V Linear Regulator with Foldback Protection 5 V Linear Regulator with Foldback Protection 5 V Protected Linear Regulator with Foldback and Short-to-VBAT Protection A4412 Simplified Block Diagram A4412-DS, Rev. 9 MCO-0000172 April 15, 2022 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 SELECTION GUIDE [1] Part Number Temperature Range Package Packing [1] Lead Frame A4412KLVTR-T –40 to 150°C 38-pin eTSSOP w/ thermal pad 4000 pieces per 7-in reel 100% matte tin Contact Allegro for additional packing options. SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS [2] Characteristic Symbol VIN Notes VVIN With current limiting resistor VENBAT ENBAT [3] IENBAT LX1 VLX1 V5P VV5P Unit V −13 to 50 V −0.3 to 8 V ±75 mA −0.3 to VVIN + 0.3 V t < 250 ns −1.5 V t < 50 ns VVIN + 3 V V −0.3 to 60 V −1 to 50 V VVCP, VCP1, VCP2 VCP, CP1, CP2 Rating −0.3 to 50 Independent of VVIN All other pins −0.3 to 7 V Junction Temperature Range TJ −40 to 165 °C Storage Temperature Range Tstg −40 to 150 °C Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [3] The higher ENBAT ratings (–13 V and 50 V) are measured at node “A” in the following circuit configuration: [2] Node “A” ≥450 Ω ENBAT VENBAT + - A4412 GND THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Junction to Ambient Thermal Resistance [4] Additional Symbol RθJA Test Conditions [4] Value Unit 30 °C/W eTSSOP-38 (LV) package thermal information available on the Allegro website. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI Table of Contents Features and Benefits................................................. 1 Description.................................................................. 1 Applications................................................................ 1 Package...................................................................... 1 Simplified Block Diagram............................................ 1 Selection Guide.......................................................... 2 Absolute Maximum Ratings........................................ 2 Thermal Characteristics.............................................. 2 Functional Block Diagram........................................... 4 Typical Schematics..................................................... 5 Pinout Diagram and Terminal List Table..................... 7 Electrical Characteristics............................................ 8 General Specifications................................................. 8 Buck and Buck-Boost Pre-Regulator Specifications......... 9 Adjustable Sync Buck Regulator Specifications............. 11 Linear Regulator Specifications................................... 13 Control Inputs Specifications...................................... 14 Diagnostic Outputs Specifications............................... 15 Window Watchdog Timer Specifications....................... 17 Communications Interface Specifications..................... 18 Startup and Shutdown Logic..................................... 19 Summary of Fault Mode Operation........................... 22 Timing Diagrams....................................................... 25 Functional Description.............................................. 26 Overview.................................................................. 26 Pre-Regulator........................................................... 26 Bias Supply.............................................................. 26 Charge Pump........................................................... 26 Bandgap.................................................................. 26 Enable..................................................................... 26 Synchronous Buck.................................................... 26 Linear Regulators...................................................... 27 Fault Detection and Reporting.................................... 27 Startup Self-Test....................................................... 27 Undervoltage Detect Self-Test.................................... 27 Overvoltage Detect Self-Test...................................... 27 Overtemperature Shutdown Self-Test.......................... 27 Power-On Enable Self-Test........................................ 28 Watchdog................................................................. 28 Serial Communication Interface................................ 31 Register Mapping...................................................... 32 Design and Component Selection............................ 41 Setting Up the Pre-Regulator...................................... 41 Charge Pump Capacitors........................................... 41 PWM Switching Frequency......................................... 41 Pre-Regulator Output Inductor (L1).............................. 41 Pre-Regulator Output Capacitors................................ 42 Ceramic Input Capacitors........................................... 42 Buck-Boost Asynchronous Diode (D1)......................... 43 Boost MOSFET (Q1)................................................. 43 Boost Diode (D2)...................................................... 43 Pre-Regulator Soft Start and Hiccup Mode (CSS1)......... 43 Pre-Regulator Compensation (RZ, CZ, CP).................... 44 Synchronous Buck Component Selection..................... 44 Setting the Output Voltage, RFB1 and RFB2................ 45 Synchronous Buck Output Inductor (L2)....................... 45 Synchronous Buck Output Capacitors.......................... 45 Synchronous Buck Compensation Components............ 46 Synchronous Buck Soft-Start & Hiccup Mode Timing..... 46 Linear Regulators...................................................... 47 Internal Bias (VCC)................................................... 47 Signal Pins (NPOR, ENBATs, FFn, POE, DIAG)............ 47 PCB Layout Recommendations................................ 48 Input/Output Structures............................................. 51 Package Outline Drawing......................................... 52 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 SU/SD VCP VIN VINOK BGVREF VINOK LDO VDD Oscillator CLK @ fosc DITH_DIS VDD BGVREF CLK1MHz BGFAULT BG2 DEGLITCH tdFILT 650 kΩ SS1 VREG VREG ↑ 3.3 VTYP ↓ 2.6 VTYP ENBATS BUCK REGULATOR VREG FALLING DELAY tdLDO ,OFF SU/SD LX2 VSS2RST ON/OFF CLK @ fosc BGVREF SYNC. BUCK Controller (w/ Hiccup Mode) MPOR COMP2 & SS2 Reset BUCK_ON ENB_EN MPOR ENB SU/SD 60 kΩ BUCK_ON 3V3_ON LDOs_ON Regulator Sequencer OV/UV DETECT & DELAYS MPOR TSD DEGLITCH tdFILT DEGLITCH tdFILT POE STRn SDI SDO SCK VCC VCP VREG V5B V5CAN V5P V5PDISC *D1MISSING *ILIM,LX1 WD_F WINDOW WATCHDOG nERROR 3V3 FB V5A ON/OFF CLK1MHz BGFAULT RST DIAG WD_IN FB COMP2 V5P Regulator TSD V5PDISC VCORE_OK REF FFn OV SS2 TSD OV/UV Detect NPOR LG COMP1 COMP1 VSS1RST BG2_UV ENABLE and STARTUP TIMING ENBAT LX1 STOP PWM CLK @ fosc BG1_UV BG1 WDOSC VCP UV WD Monitor MPOR MASTER IC POR (MPOR) MASTER IC POR (MPOR) SS OK FOLDBACK VCP VREG 5 V Linear BGVREF V5P BG1_UV Regulator V5P_DIS BG2_UV VCC_UV LDOs_ON VCP_UV *VREG_OV V5A Regulator *VCP_OV FOLDBACK VCP *D1MISSING *FB_OV VREG *ILIM,LX2 BGVREF 5 V Linear VSS1RST V5A Regulator V5A_DIS VSS2RST BUCK_ON TSD V5B Regulator * indicates a latched fault V5A_DIS V5B_DIS V5P_DIS V5CAN_DIS VDD DITH_DIS WD_STATE MAX_TIMER MAX_TIMER MIN_TIMER MIN_TIMER VALID_COUNT VALID_COUNT WD_FLASH WD_FLASH WD_RESTART WD_RESTART WD_F V5CAN_DIS VCC_UV WDOSC VCP_UV ENB_EN *VCP_OV WD_F *D1MISSING VCORE_OK *ILIM,LX1 *ILIM,LX2 VDD SPI Short-toVBAT Protection FOLDBACK VCP VREG_UV V5A_UV V5B_UV V5P_UV V5CAN_UV 3V3_UV FB_UV VREG_OV V5A_OV V5B_OV V5P_OV V5CAN_OV 3V3_OV FB_OV VREG_OCP V5A_OCP V5B_OCP V5P_OCP V5CAN_OCP 3V3_OCP FB_OCP TSD ENBATS VREG BGVREF 5 V Linear Regulator V5B_DIS LDOs_ON V5B V5CAN Regulator FOLDBACK VCP VREG BGVREF V5CAN_DIS LDOs_ON 5 V Linear Regulator V5CAN 3V3 Regulator FOLDBACK VCP VREG BGVREF 3V3_ON 3.3 V Linear Regulator 3V3 PGND Oscillator and Clocks LX1 COMP1 & SS1 Reset MPOR AGND VDD VREG ON VCP UV Charge Pump BUCK-BOOST Control BGVREF VCP OV DGND VCC VCP VCP OV/UV Detect BGFAULT BUCK-BOOST PRE-REGULATOR ISLEW Charge Pump VREG CLK1MHz BGFAULT VIN SS1 VCC FB LDO VIN CP2 Bias LDO CP1 VCP FUNCTIONAL BLOCK DIAGRAM Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 TYPICAL SCHEMATICS 1 μF 0.22 μF VIN A4412 D2 SS3P4 10 μH D1 SS3P4 LX1 0.1 μF 0603 10 μF Q1 FDS8449 or Si4446DY LG 2 kΩ VCC COMP1 CVCC 1 μF 10 pF 2.2 nF 10 μF VREG SS1 8.25 kΩ 5.35 VTYP LX1 VIN 2 × 4.7 μF 50 V 1210 100 μF 50 V / 250 mΩ CP2 DIN SS3P4 VCP CP1 VBAT 0.47 μF CSS1 10 μH KEY_SW 3V3 NPOR 10 μF OV FB 10 kΩ COMP2 NPOR SS2 3V3 FAULT 1.3 V 400 mA LX2 10 pF 2.74 kΩ CSS2 4.7 nF 10 kΩ FFn 3V3 90 mA 5V PROTECTED 100 mA 2.2 μF V5P D3 MSS1P5 3V3 2.2 μF V5A 55 mA V5A 3.3 kΩ V_IGN 2.2 μF ENBAT V5B 30 mA V5B DIAG 2.2 μF ENB V5CAN 200 mA V5CAN STRn 2.2 μF VCC SCK 10 kΩ SDI ENBAT STATUS ENBATS SDO POE WD_IN Buck setup for 3.3 V output A4412 nERROR AGND DGND PGND µP ENABLE 22 μH 3.3 V 100 mA 10 μF LX2 15.4 kΩ OV 15.4 kΩ FB COMP2 SS2 CSS2 5.11 kΩ 10 pF 10 kΩ 10 kΩ 4.7 nF Buck-Boost Mode Using a Series Diode for Reverse-Battery Protection (DIN) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 1 μF 0.22 μF 100 μF 50 V / 250 mΩ 2 × 4.7 μF 50 V 1210 VIN 0.1 μF 0603 CP2 VIN CP1 Din SS3P4 VCP VBAT A4412 5.35 VTYP LX1 D1 SS3P4 LX1 LG VCC COMP1 CVCC 1 μF CP1 VREG SS1 RZ1 0.47 μF CSS1 CZ1 Functional Block Diagram Modifications for Buck Only Mode Protected Circuits Functional Block Diagram Using a PMOS FET for Reverse-Battery Protection Instead of a Series Schottky Diode (DIN) Protected Circuits Functional Block Diagram Using an NMOS FET for Reverse-Battery Protection Instead of a Series Schottky Diode (DIN) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 Terminal List Table Number Name Function VCP Charge pump reservoir capacitor VCP 1 38 CP2 1 VIN 2 37 CP1 2,3 VIN Input voltage pins VIN 3 36 LX1 4 AGND Analog ground pin AGND 4 35 LX1 5 ENBAT Ignition enable input from the key/switch via a series resistor ENBAT 5 34 PGND 6 VCC VCC 6 33 LG 7 ENBATS ENBATS 7 32 LX2 8 SS1 SS1 8 31 VREG 9 COMP1 30 V5CAN 10 DIAG COMP1 9 DIAG 10 SDI 11 PAD 29 3V3 Internal voltage regulator bypass capacitor pin Open-drain ignition status output of ENBAT Soft-start programming pin for the buck/boost pre-regulator Error amplifier compensation network pin for the buck/boost pre-regulator Diagnostic pin to aid debug. A pulse train whose frequency depends on the fault that occurred is sent to this pin. See fault table. 28 V5B 11 SDI SPI data input from the microcontroller 12 27 V5A 12 SDO SPI data output to the microcontroller STRn 13 26 V5P 13 STRn Chip select input from the microcontroller 25 COMP2 14 SCK Clock input from the microcontroller 24 OV 15 NPOR Active LOW, open-drain regulator fault detection output 23 FB 16 WD_IN Watchdog pulse train input from a microcontroller or DSP ENB 17 22 SS2 17 ENB DGND 18 21 FFn 18 DGND 20 nERROR 19 POE 20 nERROR 21 FFn Active-low fault flag, alerts the microprocessor of a fault within the regulator 22 SS2 Soft-start programming pin for the adjustable synchronous buck regulator 23 FB Feedback pin with 1.305 V reference for synchronous buck regulator 24 OV Input to synchronous overvoltage sense circuit 25 COMP2 26 V5P 5 V / 100 mA protected regulator output 27 V5A 5 V / 55 mA regulator output 28 V5B 5 V / 30 mA regulator output 29 3V3 3.3 V / 180 mA regulator output 30 5VCAN 5 V / 200 mA regulator output for communications 31 VREG Output of the pre-regulator and input to the linear regulators and synchronous buck 32 LX2 Switching node for the adjustable synchronous buck regulator 33 LG Boost gate drive output for the buck/boost pre-regulator 34 PGND SDO SCK 14 NPOR 15 WD_IN 16 POE 19 Package LV, 38-Pin eTSSOP Pinout Diagram Logic enable input from a microcontroller or DSP Digital ground pin Gate drive enable signal, goes low if a watchdog fault is detected or nERROR is low System fault input. This fault is ANDed with the watchdog fault to create the POE signal Error amplifier compensation network pin for the adjustable synchronous buck regulator Power ground for the adjustable synchronous regulator / gate driver 35,36 LX1 Switching node for the buck/boost pre-regulator 37 CP1 Charge pump capacitor connection 38 CP2 Charge pump capacitor connection – PAD Connect to ground Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI ELECTRICAL CHARACTERISTICS – GENERAL SPECIFICATIONS [1]: Valid at 3.8 V [4] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit After VVIN > VINSTART, and VENB > 2 V or VENBAT > 3.5 V, buck-boost mode 3.8 13.5 40 V After VVIN > VINSTART, and VENB > 2 V or VENBAT > 3.5 V, buck mode 5.5 13.5 40 V GENERAL SPECIFICATIONS Operating Input Voltage VVIN VIN UVLO START Voltage VINSTART VVIN rising 4.55 4.8 5.05 V VIN UVLO STOP Voltage VINSTOP VVIN falling, VENBAT ≥ 3.8 V or VENB ≥ 2 V, VVREG = 5.2 V 3.25 3.5 3.75 V VIN UVLO Hysteresis VINHYS VINSTART ‒ VINSTOP – 1.3 – V VVIN = 13.5 V, VENBAT ≥ 3.8 V or VENB ≥ 2.0 V, VVREG = 5.6 V (no PWM) – 13 – mA VVIN = 13.5 V, VENBAT ≤ 2.2 V and VENB ≤ 0.8 V – – 10 µA 2 2.2 2.4 MHz IQ Supply Quiescent Current [1] IQ,SLEEP PWM SWITCHING FREQUENCY AND DITHERING Switching Frequency fOSC Frequency Dithering ΔfOSC Dither/Slew START Threshold VINDS,ON Dither/Slew STOP Threshold VINDS,OFF Dithering disabled 3.8 V [4] ≤ VVIN ≤ 18 V As a percent of fOSC – ±10 – % VVIN rising 8.5 9 9.5 V VVIN falling – 17 – V VVIN falling 7.8 8.3 8.8 V VVIN rising – 18 – V – 700 – mV VVCP – VVIN, VVIN ≥ 5.5 V, buck mode 4.1 6.6 – V VVCP – VVIN, VVIN = 3.8 V, VREG = 5.35 V, buckboost mode 3.1 3.8 – V – 65 – kHz – 4.65 – V VIN Dithering/Slew Hysteresis CHARGE PUMP (VCP) Output Voltage VVCP Switching Frequency fSW,CP VCC PIN VOLTAGE Output Voltage VVCC VVREG = 5.35 V SYSTEM CLOCK Internal Clock Frequency fSYS – 1 – MHz Internal Clock Tolerance fSYS,TOL –4 – 4 % 165 – – °C – 15 – °C THERMAL PROTECTION Thermal Shutdown Threshold [2] TTSD Thermal Shutdown Hysteresis THYS [2] TJ rising For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VVIN is reduced. [1] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI ELECTRICAL CHARACTERISTICS – BUCK AND BUCK-BOOST PRE-REGULATOR SPECIFICATIONS [1]: Valid at 3.8 V [4] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit VVREG VVIN = 13.5 V, ENB = 1, 0.1 A < IVREG < 1.2 A 5.25 5.35 5.45 V OUTPUT VOLTAGE SPECIFICATIONS Buck Output Voltage – Regulating PULSE-WIDTH MODULATION (PWM) PWM Ramp Offset VCOMP1 for 0% duty cycle – 400 – mV LX1RISE VVIN = 13.5 V, 10% to 90%, IVREG = 1 A – 1.4 – V/ns LX1 Falling Slew Rate [2] LX1FALL VVIN = 13.5 V, 90% to 10%, IVREG = 1 A – 1.5 – V/ns Buck Minimum ON-Time tON,MIN,BUCK – 85 160 ns VVIN < 7.8 V – 100 – % After VVIN > VINSTART, VVIN = 3.8 V – 65 – % LX1 Rising Slew Rate Control [2] PWM1OFFS Buck Maximum Duty Cycle DMAX,BUCK Boost Maximum Duty Cycle DMAX,BST COMP1 to LX1 Current Gain gmPOWER1 – 4.57 – A/V SE1 1.1 1.62 2.15 A/µs VVIN = 13.5 V, TJ = ‒40°C [2], IDS = 0.1 A – 60 75 mΩ VVIN = 13.5 V, TJ = 25°C [3], IDS = 0.1 A – 95 110 mΩ VVIN = 13.5 V, TJ = 150°C, IDS = 0.1 A – 160 190 mΩ VENBAT ≤ 2.2 V, VENB ≤ 0.8 V, VLX1 = 0 V, VVIN = 16 V, −40°C < TJ < 85°C [3] – – 10 µA VENBAT ≤ 2.2 V, VENB ≤ 0.8 V, VLX1 = 0 V, VVIN = 16 V, −40°C < TJ < 150°C – 50 150 µA Slope Compensation [2] INTERNAL MOSFET MOSFET On-Resistance MOSFET Leakage RDSon IFET,LKG ERROR AMPLIFIER Open Loop Voltage Gain Transconductance Output Current AVOL1 gmEA1 60 – dB 520 720 920 µA/V VSS1 = 500 mV 260 360 460 µA/V – ±75 – µA VVIN < 8.5 V 1.2 1.52 2.1 V VVIN > 9.5 V 0.9 1.22 1.7 V – – 300 mV – 1 – kΩ IEA1 Maximum Output Voltage EA1VO(max) Minimum Output Voltage EA1VO(min) COMP1 Pull Down Resistance – VSS1 = 750 mV RCOMP1 HICCUP1 = 1 or FAULT1 = 1 or VENBAT ≤ 2.2 V and VENB ≤ 0.8 V, latched until VSS1 < VSS1RST For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VVIN is reduced. [1] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI ELECTRICAL CHARACTERISTICS – BUCK AND BUCK-BOOST PRE-REGULATOR SPECIFICATIONS (continued) [1]: Valid at 3.8 V [1] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit 4.6 – 5.5 V BOOST MOSFET (LG) GATE DRIVER LG High Output Voltage VLG,ON VVIN = 6 V, VVREG = 5.35 V LG Low Output Voltage VLG,OFF VVIN = 13.5 V, VVREG = 5.35 V – 0.2 0.4 V LG Source Current [1] ILG,ON VVIN = 6 V, VVREG = 5.35 V, VLG = 1 V – −300 – mA LG Sink Current [1] ILG,OFF VVIN =13.5 V, VVREG = 5.35 V, VLG = 1 V – 150 – mA – 400 – mV SOFT-START SS1 Offset Voltage VSS1OFFS VSS1 rising due to ISS1SU SS1 Fault/Hiccup Reset Voltage VSS1RST VSS1 falling due to HICCUP1 = 1 or FAULT1 = 1 or VENBAT ≤ 2.2 V and VENB ≤ 0.8 V 140 200 275 mV SS1 Startup (Source) Current ISS1SU VSS1 = 1 V, HICCUP1 = FAULT1 = 0 −15 −20 −25 µA SS1 Hiccup (Sink) Current ISS1HIC VSS1 = 0.5 V, HICCUP1 = 1 7.5 10 12.5 µA SS1 Delay Time tSS1,DLY CSS1 = 22 nF – 440 – µs SS1 Ramp Time tSS1 CSS1 = 22 nF – 880 – µs FAULT1 = 1 or VENBAT ≤ 2.2 V and VENB ≤ 0.8 V, latched until VSS1 < VSS1RST – 3 – kΩ 0 V ≤ VVREG < 1.34 V typical and VCOMP1 = EA1VO(max) – fOSC/8 – – 0 V ≤ VVREG < 1.34 V typical and VCOMP1 < EA1VO(max) – fOSC/4 – – 1.34 V ≤ VVREG < 2.68 V typical and VCOMP1 < EA1VO(max) – fOSC/2 – – VVREG ≥ 2.68 V typical and VCOMP1 < EA1VO(max) – fOSC – – VSS1 rising – 2.3 – V VSS1 > VHIC1,EN, VVREG < 1.95 VTYP, VCOMP = EA1VO(max) – 30 – PWM cycles VSS1 > VHIC1,EN, VVREG > 1.95 VTYP, VCOMP = EA1VO(max) – 120 – PWM cycles VVIN < 8.5 V 3.83 4.2 4.77 A VVIN > 9.5 V 2.49 2.8 3.2 A 5.3 7.1 – A SS1 Pull-Down Resistance SS1 PWM Frequency Foldback RPDSS1 fSW1,SS HICCUP MODE Hiccup1 OCP Enable Threshold Hiccup1 OCP PWM Counts VHIC1,EN tHIC1,OCP CURRENT PROTECTIONS Pulse-by-Pulse Current Limit LX1 Short-Circuit Current Limit ILIM1,ton(min) ILIM,LX1 Latched fault after 2nd detection For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VVIN is reduced. [1] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 ELECTRICAL CHARACTERISTICS – ADJUSTABLE SYNCHRONOUS BUCK REGULATOR [1]: Valid at 3.8 V [4] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit –40°C ≤ TJ ≤ 85°C −1.72 −1.4 −1.0 V –40°C ≤ TJ ≤ 150°C MISSING ASYNCHRONOUS DIODE (D1) PROTECTION Detection Level VD,OPEN −1.72 −1.4 −0.85 V Time Filtering [2] tD,OPEN 50 – 250 ns VFB 1.27 1.305 1.33 V − 440 − mV − 65 105 ns − 100 200 ns FEEDBACK REFERENCE VOLTAGE Reference Voltage PULSE-WIDTH MODULATION (PWM) PWM Ramp Offset PWM2OFFS High-Side MOSFET Minimum ON-Time tON(MIN) High-Side MOSFET Minimum OFF-Time tOFF(MIN) Gate Driver Non-Overlap Time [2] COMP2 to LX2 Current Gain Slope Compensation [2] VCOMP2 for 0% duty cycle Does not include total gate driver non-overlap time, tNO tNO − 15 − ns gmPOWER2 − 1 − A/V SE2 0.19 0.26 0.33 A/μs TJ = 25°C [3], IDS = 100 mA − 225 300 mΩ IDS = 100 mA − − 500 mΩ VVREG = 5.5 V − 12 − ns VENBAT ≤ 2.2 V, VENB ≤ 0.8 V, VLX2 = 0 V, VVREG = 5.5 V, ‒40˚C < TJ < 85˚C [3] − − 2 μA VENBAT ≤ 2.2 V, VENB ≤ 0.8 V, VLX2 = 0 V, VVREG = 5.5 V, −40°C < TJ < 150°C − 3 15 μA TJ = 25°C [3], IDS = 100 mA − 165 195 mΩ IDS = 100 mA − − 280 mΩ VENBAT ≤ 2.2 V, VENB ≤ 0.8 V, VLX2 = 5.5 V, ‒40˚C < TJ < 85˚C [3] − − 1 μA VENBAT ≤ 2.2 V, VENB ≤ 0.8 V, VLX2 = 5.5 V, −40°C < TJ < 150°C − 4 10 μA 840 1020 mA INTERNAL MOSFETS High-Side MOSFET On-Resistance LX2 Node Rise/Fall Time t R/F,LX2 [2] High-Side MOSFET Leakage [1] Low-Side MOSFET On-Resistance Low-Side MOSFET Leakage Pulse-by-Pulse Current Limit LX2 Short-Circuit Protection RDSON (HS) [1] IDSS (HS) RDSON (LS) IDSS (LS) ILIM2,5% Duty cycle = 5% 720 ILIM2,90% Duty cycle = 90% 480 640 800 mA VLIM,LX2 VLX2 stuck low for more than 60 ns, hiccup mode after 2× detection – VVREG – 1.2 V – V For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VVIN is reduced. [1] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI ELECTRICAL CHARACTERISTICS – ADJUSTABLE SYNCHRONOUS BUCK REGULATOR (continued) [1]: Valid at 3.8 V [4] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit – –150 –350 nA ERROR AMPLIFIER Feedback Input Bias Current [1] IFB,ADJ Open Loop Voltage Gain [2] AVOL2 Transconductance gmEA2 VCOMP2 = 0.8 V, VFB,ADJ regulated so that ICOMP2 = 0 A − 60 − dB 520 720 920 μA/V 0 V < VSS2 < 500 mV – 250 – μA/V VCOMP2 = 0.8 V − ±50 − μA ICOMP2 = 0 A, VSS2 > 500 mV Source and Sink Current IEA2 Maximum Output Voltage EA2VO(max) 1.04 1.3 1.56 V Minimum Output Voltage EA2VO(min) – – 150 mV − 1.3 − kΩ 120 200 270 mV VSS2 falling due to HICCUP2 = 1 or FAULT2 = 1 or VENBAT ≤ 2.2 V and VENB ≤ 0.8 V − 100 120 mV COMP2 Pull-Down Resistance RCOMP2 HICCUP2 = 1 or FAULT2 = 1 or VENBAT ≤ 2.2 V and VENB ≤ 0.8 V, latched until VSS2 < VSS2RST SOFT-START SS2 Offset Voltage SS2 Fault/Hiccup Reset Voltage VSS2OFFS VSS2RST VSS2 rising due to ISS2SU SS2 Startup (Source) Current ISS2SU VSS2 = 1 V, HICCUP2 = FAULT2 = 0 −15 –20 −25 μA SS2 Hiccup (Sink) Current ISS2HIC VSS2 = 0.5 V, HICCUP2 = 1 5 10 15 μA SS2 to Synchronous Buck Output Delay Time tSS2,DLY CSS2 = 10 nF − 100 − μs tSS2 CSS2 = 10 nF − 400 − μs FAULT2 = 1 or VENBAT ≤ 2.2 V and VENB ≤ 0.8 V, latched until VSS2 < VSS2RST − 2 − kΩ VFB < 450 mV typical − fOSC/4 − − 450 mV < VFB < 780 mV typical − fOSC/2 − − VFB > 780 mV typical − fOSC − − VSS2 rising – 1.8 – V VSS2 > VHIC2,EN, VFB < 450 mVTYP – 30 – PWM cycles VSS2 > VHIC2,EN, VFB > 450 mVTYP – 120 – PWM cycles Synchronous Buck Soft-Start Ramp Time SS2 Pull-Down Resistance SS2 PWM Frequency Foldback RPDSS2 fSW2,SS HICCUP MODE Hiccup2 OCP Enable Threshold Hiccup2 OCP Counts VHIC2,EN tHIC2,OCP For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VVIN is reduced. [1] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 ELECTRICAL CHARACTERISTICS – LINEAR REGULATOR SPECIFICATIONS [1]: Valid at 3.8 V [4] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit 10 mA < IV5CAN < 200 mA, VVREG = 5.25 V 4.9 5 5.1 V 1 – 15 µF 5 mA < IV5A < 55 mA, VVREG = 5.25 V 4.9 5 5.1 V 1 – 15 µF 4.9 5 5.1 V 1 – 15 µF 4.9 5 5.1 V 1 – 15 µF V5CAN, V5A, V5B AND V5P LINEAR REGULATORS V5CAN Accuracy and Load Regulation V5CAN Output Capacitance Range [2] VV5CAN COUT,V5CAN V5A Accuracy and Load Regulation VV5A V5A Output Capacitance Range [2] COUT,V5A V5B Accuracy and Load Regulation VV5B V5B Output Capacitance Range [2] COUT,V5B V5P Accuracy and Load Regulation VV5P V5P Output Capacitance Range [2] COUT,V5P 5 mA < IV5B < 30 mA, VVREG = 5.25 V 5 mA < IV5P < 100 mA, VVREG = 5.25 V V5CAN OVERCURRENT PROTECTION V5CAN Current Limit [1] V5CAN Foldback Current [1] V5CANILIM VV5CAN = 5 V –220 −310 – mA V5CANIFBK VV5CAN = 0 V −40 −80 −140 mA V5A OVERCURRENT PROTECTION V5A Current Limit [1] V5AILIM VV5A = 5 V −60 −100 – mA V5A Foldback Current [1] V5AIFBK VV5A = 0 V −15 −30 −45 mA V5B Current Limit [1] V5BILIM VV5B = 5 V −40 −90 – mA V5B Foldback Current [1] V5BIFBK VV5B = 0 V −5 −20 −35 mA V5PILIM VV5P = 5 V −110 −155 – mA V5PIFBK VV5P = 0 V −20 −40 −60 mA V5B OVERCURRENT PROTECTION V5P OVERCURRENT PROTECTION V5P Current Limit [1] V5P Foldback Current [1] V5CAN, V5A, V5B, AND V5P STARTUP TIMING V5CAN Startup Time [2] CV5CAN ≤ 2.9 µF, Load = 200 Ω ±5% (25 mA) – 0.4 1 ms tV5A,START CV5A ≤ 2.9 µF, Load = 200 Ω ±5% (25 mA) – 0.6 1 ms [2] tV5B,START CV5B ≤ 2.9 µF, Load = 333 Ω ±5% (15 mA) – 0.8 1 ms V5P Startup Time [2] tV5C,START CV5P ≤ 2.9 µF, Load = 100 Ω ±5% (50 mA) – 0.5 1 ms 3.23 3.30 3.37 V 1.0 – 15 µF V5A Startup Time [2] V5B Startup Time tV5CAN,START 3V3 LINEAR REGULATOR 3V3 Accuracy and Load Regulation V3V3 3V3 Output Capacitance Range [2] COUT,3V3 5 mA < I3V3 < 90 mA, VVREG = 5.25 V 3V3 OVERCURRENT PROTECTION 3V3 Current Limit [1] 3V3 Foldback Current [1] 3V3ILIM V3V3 = 3.3 V −110 −155 – mA 3V3IFBK V3V3 = 0 V −20 −50 −80 mA 3V3 STARTUP TIMING 3V3 Startup Time [2] 3V3 to Synchronous Buck Startup t3V3,START C3V3 ≤ 2.9 µF, Load = 66 Ω ±5% (50 mA) – 0.5 0.8 ms t3V3,BUCK Time from when 3V3 = V3V3,UV,H to when VFB = VFB,UV,H – – 1 ms For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VVIN is reduced. [1] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI ELECTRICAL CHARACTERISTICS – CONTROL INPUTS [1]: Valid at 3.8 V [4] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit IGNITION ENABLE (ENBAT) INPUT ENBAT Thresholds ENBAT Hysteresis ENBAT Bias Current [1] ENBAT Pull-Down Resistance VENBAT,H VENBAT rising 2.9 3.1 3.5 V VENBAT,L VENBAT falling 2.2 2.6 2.9 V VENBAT,H – VENBAT,L – 500 – mV VENBAT = 5.5 V via a 1 kΩ series resistor – 50 100 µA VENBAT = 0.8 V via a 1 kΩ series resistor VENBAT,HYS IENBAT,BIAS 0.5 – 5 µA RENBAT VENBAT < 1.2 V – 600 – kΩ VENB,H VENB rising – – 2 V LOGIC ENABLE (ENB) INPUT ENB Thresholds VENB,L VENB falling 0.8 – – V ENB Bias Current [1] IENB,IN VENB = 3.3 V – – 175 µA ENB Resistance RENB – 60 – kΩ EN td,FILT 10 15 20 µs ENB/ENBAT FILTER/DEGLITCH Enable Filter/Deglitch Time nERROR INPUT nERROR Thresholds VnERROR,H VnERROR rising – – 2 V VnERROR,L VnERROR falling 0.8 – – V For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VVIN is reduced. [1] [2] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS [1]: Valid at 3.8 V [4] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit 3V3 AND SYNCHRONOUS BUCK OV/UV PROTECTION THRESHOLDS 3V3 OV Thresholds 3V3 OV Hysteresis 3V3 UV Thresholds 3V3 UV Hysteresis Synchronous Buck FB OV Thresholds Synchronous Buck FB UV Thresholds Synchronous Buck FB UV Hysteresis V3V3,OV,H V3V3 rising 3.41 3.51 3.6 V V3V3,OV,L V3V3 falling – 3.49 – V V3V3,OV,HYS V3V3,OV,H – V3V3,OV,L 10 20 40 mV V3V3,UV,H V3V3 rising – 3.12 – V V3V3,UV,L V3V3 falling 3 3.1 3.19 V V3V3,UV,H – V3V3,UV,L 10 20 40 mV V3V3,UV,HYS VFB,OV,H VFB rising 1.35 1.385 1.42 V VFB,UV,H VFB rising 1.210 1.245 1.27 V VFB,UV,L VFB falling 1.205 1.235 1.26 V 5 15 25 mV VFBUV,HYS VFB,UV,H – VFB,UV,L V5CAN, V5A, V5B AND V5P OV/UV PROTECTION THRESHOLDS V5CAN, V5A, V5B and V5P OV Thresholds V5CAN, V5A, V5B and V5P OV Hysteresis V5CAN, V5A, V5B and V5P UV Thresholds VV5,OV,H VV5 rising 5.15 5.33 5.5 V VV5,OV,L VV5 falling – 5.30 – V VV5,OV,H – VV5,OV,L 15 30 50 mV VV5,OV,HYS VV5,UV,H VV5 rising – 4.71 – V VV5,UV,L VV5 falling 4.5 4.68 4.85 V V5CAN, V5A, V5B and V5P UV Hysteresis VV5,UV,HYS VV5,UV,H – VV5,UV,L 15 30 50 mV V5P Output Disconnect Threshold VV5P,DISC VV5P rising – 7.2 – V V VREG, VCP, AND BG THRESHOLDS VREG Non-Latching OV Threshold VREG Non-Latching OV Hysteresis VREG Latching OV Threshold VREG UV Thresholds VREGOV1,H VVREG rising, LX1 PWM disabled 5.5 5.62 5.75 VREGOV1,L VVREG falling, LX1 PWM enabled – 5.53 – V VREGOV1,H – VREGOV1,L – 100 – mV VREGOV2,H VVREG rising, all regulators latched off – 6.55 – V VREGUV,H VVREG rising, triggers rise of 3V3 linear regulator 4.14 4.38 4.62 V VREGUV,L VVREG falling – 4.28 – V VREGOV1,HYS VREG UV Hysteresis VREGUV,HYS VREGUV,H – VREGUV,L – 100 – mV VCP OV Thresholds VCPOV,H VVCP rising, latches all regulators off 11 12.5 14 V VCPUV,H VVCP rising, PWM enabled 3 3.2 3.4 V VCPUV,L VVCP falling, PWM disabled – 2.8 – V VCPUV,H – VCPUV,L – 400 – mV BGVREF or BGFAULT rising 1 1.05 1.1 V VCP UV Thresholds VCP UV Hysteresis BGREF and BGFAULT UV Thresholds [2] VCPUV,HYS BGxUV For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VVIN is reduced. [1] [2] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS (continued) [1]: Valid at 3.8 V [4] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit Time from when 3V3, synchronous buck output, and V5A are all in regulation to NPOR being asserted high 15 20 25 ms ENB or ENBAT high, VIN ≥ 2.5 V, INPOR = 2 mA – 150 400 mV VNPOR = 3.3 V – – 2 µA ENB = 1 or ENBAT = 1 and FFn is tripped, VVIN ≥ 2.5 V, IFF = 2 mA – 150 400 mV VFF= 3.3 V – – 2 µA IENBATS = 2 mA, VENBAT < VENBAT,L – – 400 mV IENBATS VENBATS = 3.3 V – – 2 µA OVtd,FILT Overvoltage detection delay time 10 15 20 µs UVtd,FILT Undervoltage detection delay time 10 15 20 µs NPOR TURN-ON AND TURN-OFF DELAYS NPOR Turn-On Delay tdNPOR,ON NPOR OUTPUT VOLTAGES NPOR Output Low Voltage VNPOR,L NPOR Leakage Current [1] INPOR,LKG FAULT FLAG OUTPUT VOLTAGES (FFn) FFn Output Voltage VFF,L FFn Leakage Current IFF,LKG IGNITION STATUS (ENBATS) ENBATS Output Voltage ENBATS Leakage Current VOENBATS,LO [1] OV FILTERING/DEGLITCH TIME Overvoltage Detection Delay UV FILTERING/DEGLITCH TIME UV Filter/Deglitch Times For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VVIN is reduced. [1] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 16 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI ELECTRICAL CHARACTERISTICS – WINDOW WATCHDOG TIMER (WWDT) [1]: Valid at 3.8 V [4] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit WD_IN VOLTAGE THRESHOLDS AND CURRENT WDIN Input Voltage Thresholds WDIN Pull-Down Resistance [2] WDIN,LO VWD_IN falling 0.8 – – V WDIN,HI VWD_IN rising – – 2 V − 50 – kΩ RWD_IN WD_IN TIMING SPECIFICATIONS WDIN Frequency fWDIN – 500 – Hz WDIN Pulse High Time tWDIN,HI 50 – – µs WDIN Pulse Low Time tWDIN,LO 50 – – µs GATE DRIVE ENABLE (POE) POE Output Voltage VPOE,L IPOE = 4 mA POE Output Voltage VPOE,H IPOE = –3.5 mA Power Supply Disable Delay Anti-Latchup Timeout tPS_DISABLE tANTI_ LATCHUP – 150 400 mV 2.85 – – V Time from POE going low due to watchdog fault to V5CAN starts to decay – 250 – ms Time from POE going low due to watchdog fault to when enable control is removed from the ENB pin – 10 – s For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VIN is reduced. [1] [2] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 17 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 ELECTRICAL CHARACTERISTICS – COMMUNICATIONS INTERFACE [1]: Valid at 3.8 V [4] ≤ VVIN ≤ 40 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit V SERIAL INTERFACE (STRn, SDI, SDO, SCK) Input Low Voltage VIL – – 0.8 Input High Voltage VIH All logic inputs 2 – – V Input Hysteresis VIhys All logic inputs 250 550 – mV Input Pull-Down SDI, SCK RPDS 0 V < VIN < 5 V – 50 – kΩ STRn – 50 – kΩ Input Pull-Up To VCC IPU Output Low Voltage VOL IOL = – 0.2 0.4 V Output High Voltage VOH IOL = –1 mA [1] 2.8 VDD – 0.2 – V Output Leakage ILK,SDO 1 mA [1] 0 V < VSDO < 5.5 V, STRn = 1 –1 – 1 µA Clock High Time tSCKH A in figure 4 50 – – ns Clock Low Time tSCKL B in figure 4 50 – – ns Strobe Lead Time tSTLD C in figure 4 30 – – ns Strobe Lag Time tSTLG D in figure 4 30 – – ns Strobe High Time tSTRH E in figure 4 300 – – ns Data Out Enable Time tSDOE F in figure 4 – – 40 ns Data Out Disable Time tSDOD G in figure 4 – – 30 ns Data Out Valid Time From Clock Falling tSDOV H in figure 4 – – 40 ns Data Out Hold Time From Clock Falling tSDOH J in figure 4 5 – – ns Data In Setup Time To Clock Rising tSDIS K in figure 4 15 – – ns Data In Hold Time From Clock Rising tSDIH L in figure 4 10 – – ns – – 2 ms [1] Wake Up From Sleep tEN For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. [3] Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. [4] The lowest operating voltage is only valid if the conditions V VIN > VVIN,START and VVCP – VVIN > VCPUV,H and VVREG > VREGUV,H are satisfied before VVIN is reduced. [1] [2] STRn C A B D E SCK K X SDI D15 F SDO Z L X D14 X X D0 G J D15' X D14' D0' Z H Figure 1: Serial Interface Timing X = don’t care; Z = high-impedance (tri-state) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 18 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 Table 1: Startup and Shutdown Logic (signal names consistent with Functional Block Diagram) Regulator Control Bits (0=OFF, 1=ON) A4412 Status Signals VREG ON 3V3 ON SYNC BUCK and V5A ON V5B, V5P, and V5CAN ON EN MPOR VREG UV RESET 0 0 0 0 0 1 OFF 0 0 0 0 0 0 STARTUP 1 0 0 0 1 ↓ 1 1 0 0 1 ↓ 1 1 1 0 A4412 MODE ↓ 3V3 UV SYNC BUCK and V5A UV V5B, V5P, and V5CAN UV NPOR 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 SHUTTING DOWN 1 1 1 1 0 0 0 0 0 0 0 ↓ 1 1 0 0 0 0 0 0 1 1 0 ↓ 1 0 0 0 0 0 0 1 1 1 0 OFF 0 0 0 0 0 0 1 1 1 1 0 TIME RUN 15 µs DEGLITCH X = DON’T CARE EN = ENBAT + ENB MPOR = VCC_UV + VCP_UV + BG1_UV + BG2_UV + TSD + VCP_OV (latched) + D1MISSING (latched) + ILIM,LX1 (latched) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 19 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI STARTUP TIMING DIAGRAM 13.5 V VIN EN ENB OR ENBAT = HIGH SS VSSOF FS COMP fOSC/4 fOSC/2 fOSC LX1 tSS1 VREG VVREG,UV,H tSS1,DLY V3V3,UV,H 3V3 1.3 V fOSC/4 fOSC/2 fOSC LX2 tSS2 Buck Output VFB,UV,H VV5A,UV,H V5A 3V3 OK* Buck OK* t3V3,BUCK V5A OK* t3V3,V5A NPOR ON* td NPOR,ON NPOR Figure 2: Startup Timing Diagram Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 20 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 SHUTDOWN TIMING DIAGRAM VIN EN td,FILT ENB AND ENBAT tOUT,FALL 3V3, Sync Buck or V5A UV All Outputs UV td,FILT NPOR All outputs start to decay ENtd,FILT seconds after ENB and ENBAT are low. Time for outputs to drop to zero, tOUT,FALL, various for each output and depends on load current and capacitance. NPOR falls when 3V3, Sync Buck or V5A reaches its UV point. Figure 3: Shutdown Timing Diagram Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 21 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI Table 2: Summary of Fault Mode Operation FAULT TYPE and CONDITION A4412 LATCHED RESPONSE FAULT? TO FAULT VCC VCP VREG SYNC BUCK O/P 3V3 V5CAN V5A V5B V5P NPOR FFn POE DIAG SPI WD RESET METHOD Latching Faults CPUMP OV Results in an MPOR after 1 detection, so all regulators are shut off Yes No effect ? off off off off off off off Low Low Low 102 kHz On On None VREG overvoltage VREGOV2,H < VVREG Results in an MPOR after 1 detection, so all regulators are shut off Yes No effect No effect off off off off off off off Low Low Low 204 kHz On On Check the short/ Cycle EN or Vin / replace 4412 Results in an MPOR after 1 VREG asynchronous detection, so all diode (D1) missing regulators are shut off Yes No effect No effect off off off off off off off Low Low Low 315 kHz xx xx Place D1 then cycle EN or VIN Asynchronous diode (D1) short circuited or LX1 shorted to ground Results in an MPOR after the high side MOSFET current exceeds ILIM,LX1 so all regulators are shut off Yes No effect No effect off off off off off off off Low Low Low 409 kHz xx xx Remove the short then cycle EN or VIN 1V25 overvoltage If OV condition persists for more than tdOV then set NPOR Low and shut off all regulators Yes No effect No effect off off off off off off off Low Low Low 512 kHz xx xx Check for short circuits then cycle EN or VIN FB pin is open FB pin will be pulled high, LX2 will stop switching Yes No effect No effect No effect Low off off off off off Low Low Low 512 kHz xx xx Connect the FB pin Non-Latching Faults Vin UVLO 4412 is in reset state No Ramping Vin off off off off off off off Low Low Low Low xx xx None BG1 UVLO 4412 is in reset state No Ramping Vin off off off off off off off Low Low Low Low xx xx None BG2 UVLO 4412 is in reset state No Ramping Vin off off off off off off off Low Low Low Low xx xx None VCC UVLO 4412 is in reset state No ON Vin off off off off off off off Low Low Low Low xx xx None VCC short Ilimit 4412 is in reset state No UVLO Vin off off off off off off off Low Low Low Low xx xx None CPUMP UVLO 4412 is in reset state No ON Ramping off off off off off off off Low Low Low Low xx xx None Low if V5 or V5P are too Low Low Low No effect No effect None VREG over voltage VREGOV1,H < VVREG Stop PWM switching of LX1 No No effect No effect No effect No effect No effect No effect No effect No effect No effect Low if 3V3, 1V25 or V5A are too Low VREG pin open circuit VREG will decay to 0 V, LX1 will switch at maximum duty cycle so the voltage on the output capacitors will be very close to VBAT No No effect No effect off off off off off off off Low Low Low Low No effect No effect Connect the VREG pin VREG shorted to ground VSS1 < VHIC1,EN, VREG < 1.95 V, VCOMP1 ≠ EA1VO(MAX) Continue to PWM but turn off LX1 when the high side MOSFET current exceeds ILIM1 No No effect No effect Shorted off if Vreg off if Vreg off if Vreg off if Vreg off if Vreg off if Vreg 180 -45 -40 -90 Total Gain C to O Gain E/A Phase -60 -80 Phase - ° For the synchronous buck, we select a crossover frequency, fC, in the region of 50 kHz. The RZ selection is based on the gain required at the crossover frequency, and can be calculated by the following simplified equation: 80 0.1 E/A Gain Total Phase C to O Phase 1 -135 10 100 -180 1000 Frequency - kHz Figure 16: Bode Plot of the Complete System (red curve) RZ = 2.74 kΩ, CZ = 4.7 nF, CP = 10 pF LO = 10 µH, CO = 10 µF Ceramic Synchronous Buck Soft-Start and Hiccup Mode Timing The soft-start time of the synchronous buck is determined by the value of the capacitance at the soft-start pin, CSS2. If the A4412 is starting into a very heavy load, a very fast softstart time may cause the regulator to exceed the pulse-by-pulse overcurrent threshold. To avoid prematurely triggering hiccup mode, the soft-start time, tSS2, should be calculated according to equation 29, tSS2 = VSYNC_BUCK × CO ICO (29) Where VSYNC_BUCK is the output voltage, CO is the output capacitance, ICO is the amount of current allowed to charge the output capacitance during soft-start (recommend 20 mA < ICO < 30 mA). Higher values of ICO result in faster soft-start time and lower values of ICO ensure that hiccup mode is not falsely triggered. We recommend starting the design with an ICO of 20 mA and increasing it only if the soft-start time is too slow. Then CSS2 can be selected based on equation 30, CSS2 > ISS2SU × t SS1 0.8 (30) If a non-standard capacitor value for CSS2 is calculated, the next larger value should be used. The voltage at the soft-start pin will start from 0 V and will be Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 46 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 charged by the soft-start current, ISS2SU. However, PWM switching will not begin instantly because the voltage at the soft-start pin must rise above the soft-start offset voltage (VSS2OFFS). The soft start delay (tSS2,DELAY) can be calculated using equation 31, tSS2,DELAY = CSS2 × VSS2OFFS ISS2SU (31) When the A4412 is in hiccup mode, the soft-start capacitor sets the hiccup period. During a startup attempt, the soft-start pin charges the soft-start capacitor with ISS2SU and discharges the same capacitor with ISS2HIC between startup attempts. In applications where the A4412 will be enabled with VREG > VREG UV threshold (VREGUV,H), the above guidance for CSS2 will not be optimal and could result in output overshoot on VSYNC_BUCK. For further information on properly sizing both CSS1 and CSS2 in this event, see the Pre-Regulator Soft Start and Hiccup Mode Timing (CSS1) section of this datasheet. Linear Regulators The five linear regulators only require an ceramic capacitor to ensure stable operation. The capacitor can be any value between 1 and 15 μF. A 2.2 μF capacitor per regulator is recommended. Also, since the V5P is used to power remote circuitry, its load can include long cables. The inductance of these cables may cause negative spikes on the V5P pin if a short occurs. It is recommended to use a small diode to clamp this negative spike. A MSS1P5 is recommended. Internal Bias (VCC) The internal bias voltage should be decoupled at the VCC pin using a 1 μF ceramic capacitor. It is not recommended to use this pin as a source. Signal Pins (NPOR, ENBATs, FFn, POE, DIAG) The A4412 has many signal level pins. The NPOR, FFn, and ENBATS are open-drain outputs and require external pull-up resistors. The DIAG and POE signals are push-pull outputs and do not require external pull-up resistors. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 47 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI PCB LAYOUT RECOMMENDATIONS The input ceramic capacitors must be located as close as possible to the VIN pins. In general, the smaller capacitors (0402, 0603) must be placed very close to the VIN pin. The larger capacitors should be placed within 0.5 inches of the VIN pin. There must not be any vias between the input capacitors and the VIN pins. The pre-regulator input ceramic capacitors, A4412 VIN and LX1, and asynchronous diode (D1), must be routed on one layer. This loop should be as small as possible, see below. The snubber (RN1 and CN1) should be placed close to D1. A single star point ground connected to the ground plane using multiple vias is recommended. The synchronous buck output inductor should be located near the LX2 pins. The trace from the LX2 pins to the output inductor (L2) should be relatively wide and preferably on the same layer as the IC. The two synchronous buck feedback resistors (RFB1, RFB2) must be located near the FB pin. The output capacitors should be located near the load. The output voltage sense trace (to RFB1) must connect at the load for the best regulation, trace A in figure below goes to load. The pre-regulator output inductor (L1) should be located close to the LX1 pins. The LX1 trace widths (to L1, D1) should be relatively wide and preferably on the same layer as the IC. The pre-regulators output ceramic capacitors should be located near the VREG pin. There must be 1 or 2 smaller ceramic capacitors as close as possible to the VREG pin. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 48 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI The two charge pump capacitors must be placed as close as possible to VCP and CP1/CP2. The ceramic capacitors for the LDOs (3V3, V5A, V5B, V5P, and V5CAN) must be placed near their output pins. The V5P output must have a 1 A / 40 V Schottky diode (D3) located very close to its pin to limit negative voltages. The thermal pad under the A4412 must connect to the ground plane(s) with multiple vias. The VCC bypass capacitor must be placed very close to the VCC pin. The COMP network for both buck regulators (CZx, RZx, CPx) must be located very close to the COMPx pin. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 49 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI The boost MOSFET (Q1) and the boost diode (D2) must be placed very close to each other. Q1 should have thermal vias to a polygon on the bottom layer. Also, there should be “local” bypass capacitors from D2 anode to Q1 source. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 50 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI INPUT/OUTPUT STRUCTURES FFn, DIAG, NPOR, 3V3, V5A, V5B, V5CAN, VREG, ENB, ENBAT, ENBATS, FB, OV, COMP1, COMP2, SS1, SS2, WD_IN, nERROR, VCC, LG, POE VCP, CP1, CP2 CP1 CP2 PIN VCP 9V 7V 52V LX2 LX1 VREG SDO LX1 SDI, SCK VDD VDD 50 Ω SDO 2 kΩ PIN 9V 9V STRn Input VDD 50 kΩ V5P 9V AGND, PGND VDD 50 kΩ 9V 52 V LX2 9V PIN VIN V5P 2 kΩ 9V 52 V AGND PGND Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 51 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI A4412 PACKAGE OUTLINE DRAWING For Reference Only – Not for Tooling Use (Reference Allegro DWG-0000379, Rev. 3 and JEDEC MO-153 BDT-1) Dimensions in millimeters NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 9.70 ±0.10 8º 0º 6.50 ±0.10 38 0.20 0.09 B 3.00 ±0.10 4.40 ±0.10 6.40 ±0.20 A 0.60 ±0.15 1.00 REF 1 2 0.25 BSC SEATING PLANE GAUGE PLANE Branded Face 38X 0.90 ±0.05 1.20 MAX 0.10 C 0.27 0.17 C SEATING PLANE 0.150 0.025 0.50 BSC 0.50 0.30 38 XXXXXXXXX Date Code Lot Number 1.70 1 2 3.00 D 6.00 Standard Branding Reference View Line 1, 2, 3 = 13 Characters Line 1: Part Number Line 2: Logo A, 4 digit Date Code Line 3: Assembly Lot Number A 1 2 6.5 C Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOP50P640X120-39M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Branding scale and appearance at supplier discretion PCB Layout Reference View Figure 30: Package LV, 38-Pin eTSSOP Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 52 A4412 Buck or Buck/Boost Pre-Regulator with Synchronous Buck, 5 Internal Linear Regulators, Pulse-Width Watchdog Timer, and SPI Revision History Number Date Description – March 22, 2017 Initial release 1 June 28, 2017 2 July 5, 2018 3 April 23, 2019 4 August 13, 2019 Added Table of Contents (page 3); updated Synchronous Buck FB UV Thresholds (page 14) and Input/Output Structures (page 51) Minor editorial updates Updated Functional Block Diagrams (page 6), Figure 13 (page 44), and Figure 16 (page 46). Updated Synchronous Buck FB UV Thresholds minimum values (page 15), Equation 2 (page 41), Equation 6 and 10 (page 42). 5 May 20, 2020 6 August 27, 2020 Corrected V5B Overvoltage fault type (page 24). Updated Functional Block Diagram (page 4) and Equation 22 (page 45). 7 February 9, 2021 Added guidance on soft-start capacitor selection (pages 44, 47). 8 February 8, 2022 Updated package drawing (page 52) 9 April 15, 2022 Updated Pulse-by-Pulse Current Limit maximum value (pages 10-11), Reference Voltage minimum value, and High-Side MOSFET Minimum Off-Time maximum value (page 11) Copyright 2022, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 53