A4926
Automotive Half-Bridge MOSFET Driver
FEATURES AND BENEFITS
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The A4926 is an N-channel power MOSFET driver capable of
controlling MOSFETs connected in a half-bridge arrangement
and is specifically designed for automotive applications with
high-power inductive loads, such as brush DC motors solenoids
and actuators.
Half-bridge MOSFET driver
Bootstrap gate drive for N-channel MOSFET bridge
Cross-conduction protection with adjustable dead time
Charge pump regulator for low supply voltage operation
5.5 to 50 V supply voltage operating range
SPI-compatible serial interface
Bridge control by direct logic inputs or serial interface
Programmable gate drive
Programmable diagnostics
2
A2SIL product—device features for
safety-critical systems
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APPLICATIONS
•
•
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Anti-lock braking systems (ABS)
HVAC (blower fan)
DC pumps (fuel, oil, water)
Solenoids and actuators
Similar industrial applications
The A4926 is intended for automotive systems that must meet
ASIL requirements. In common with other Allegro A2SIL™
products, this device incorporates features to complement
proper system design, allowing users to achieve the required
ASIL level.
A unique charge pump regulator provides full gate drive for
battery voltages down to 5.5 V for most applications. A bootstrap
capacitor is used to provide the above-battery supply voltage
required for N-channel MOSFETs.
The half bridge can be controlled by independent logic-level
inputs or through the SPI-compatible serial interface. The
external power MOSFETs are protected from shoot-through
by a programmable dead time.
Integrated diagnostics provide indication of multiple internal
faults, system faults, and power bridge faults, and can be
configured to protect the power MOSFETs under most shortcircuit conditions.
PACKAGE:
20-lead TSSOP with
exposed pad (suffix LP)
In addition to providing full access to the bridge control, the
serial interface is also used to alter programmable settings such
as dead time, VDS threshold, and fault blank time. Detailed
diagnostic information can be read through the serial interface.
The A4926 is supplied in a 20-lead eTSSOP (suffix LP). This
package is lead (Pb) free, with 100% matte-tin leadframe
plating (suffix –T).
Not to scale
VBAT
ECU
A4926
Load
SPI
GND
Figure 1: Typical Application
A4926-DS, Rev. 4
MCO-0000155
February 28, 2020
A4926
Automotive Half-Bridge MOSFET Driver
SPECIFICATIONS
SELECTION GUIDE
Part Number
A4926KLPTR-T
Packing
Package
4000 pieces per reel
6.5 mm × 4.4 mm, 1.2 mm maximum height
20-lead TSSOP with exposed thermal pad
ABSOLUTE MAXIMUM RATINGS [1]
Characteristic
Load Supply Voltage
Symbol
Notes
VBB
Rating
Unit
–0.3 to 50
V
–0.3 to 16
V
Regulator Output
VREG
VREG
Charge Pump Capacitor Terminal
VCP1
CP1
–0.3 to 16
V
CP2
VCP1 – 0.3 to
VREG + 0.3
V
Charge Pump Capacitor Terminal
VCP2
Battery-Compliant Logic Input Terminals
VIB
HS, LSn, RESETn, ENABLE
–0.3 to 50
V
Logic Input Terminals
VI
STRn, SCK, SDI
–0.3 to 6
V
Logic Output Terminal
VO
SDO
–0.3 to 6
V
Diagnostics Output
VDIAG
DIAG
–0.3 to 50
V
Bridge Drain Monitor Terminal
VBRG
VBRG
Bootstrap Supply Terminal
VC
High-Side Gate Drive Output Terminal
VGH
High-Side Source (Load) Terminal
VS
Low-Side Gate Drive Output Terminal
VGL
Bridge Low-Side Source Terminal
Ambient Operating Temperature Range
Maximum Continuous Junction Temperature
VLSS
TA
GH
GH (transient)
S
TJt
Storage Temperature Range
Tstg
–5 to 55
V
–0.3 to VREG + 50
V
VC – 16 to VC + 0.3
V
–18 to VC + 0.3
V
VC – 16 to VC + 0.3
V
S (transient)
–18 to VC + 0.3
V
GL
VREG – 16 to 18
V
–8 to 18
V
VREG – 16 to 18
V
GL (transient)
LSS
LSS (transient)
Limited by power dissipation
TJ(max)
Transient Junction Temperature
1
C
Overtemperature event not exceeding 10 seconds,
lifetime duration not exceeding 10 hours,
guaranteed by design characterization.
–8 to 18
V
–40 to 150
°C
165
°C
180
°C
–55 to 150
°C
Value
Unit
28
°C/W
38
°C/W
2
°C/W
With respect to GND. Ratings apply when no other circuit operating constraints are present.
THERMAL CHARACTERISTICS: May require derating at maximum conditions
Characteristic
Package Thermal Resistance
Symbol
RθJA
RθJP
2 Additional
Test Conditions [2]
4-layer PCB based on JEDEC standard
2-layer PCB with
3.8 in.2
copper each side
thermal information available on the Allegro website.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
A4926
Automotive Half-Bridge MOSFET Driver
Table of Contents
Features and Benefits 1
Description 1
Package 1
Typical Application 1
Selection Guide 2
Absolute Maximum Ratings 2
Thermal Characteristics 2
Pinout Diagram and Terminal List Table 4
Functional Block Diagram 5
Electrical Characteristics 6
Supply and Reference 6
Gate Output Drive 7
Logic Inputs and Outputs 8
Logic I/O – Dynamic Parameters 8
Diagnostics and Protection 9
Timing Diagrams 10
Logic Truth Tables 11
Functional Description 12
Input and Output Terminal Functions 12
Power Supplies 13
Pump Regulator 13
Gate Drives 13
Bootstrap Supply 13
Bootstrap Charge Management 13
Top-Off Charge Pump 14
High-Side Gate Drive 14
Low-Side Gate Drive 14
Gate Drive Passive Pull-Down 15
Dead Time 15
Gate Drive Control 15
Logic Control Inputs 16
Output Disable 16
Sleep Mode 17
Diagnostic Monitors 17
Status and Diagnostic Registers 17
Chip-Level Protection 17
Operational Monitors 18
Power Bridge and Load Faults 19
Fault Action 21
Fault Masks 21
Serial Interface 22
Configuration Registers 24
Diagnostic Registers 24
Control Register 24
Status Register 25
Serial Register Reference 26
Application Information 31
Dead-Time Selection 31
Bootstrap Capacitor Selection 31
Bootstrap Charging 31
VREG Capacitor Selection 32
Input/Output Structures 33
Layout Recommendations 34
Package Outline Drawing 35
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
A4926
Automotive Half-Bridge MOSFET Driver
PINOUT DIAGRAM AND TERMINAL LIST TABLE
GND 1
20 VBRG
DIAG 2
19 VBB
ENABLE 3
18 CP1
RESETn 4
HS 5
LSn 6
SDI 7
17 CP2
PAD
16 VREG
15 C
14 S
SCK 8
13 GH
SDO 9
12 GL
STRn 10
11 LSS
20-Lead eTSSOP (suffix LP)
Pinout Diagram
Terminal List Table
Name
Number
Function
C
15
Bootstrap capacitor
CP1
18
Pump capacitor CCP connection
CP2
17
Pump capacitor CCP connection
DIAG
2
Diagnostic output
ENABLE
3
Gate drive output control input
GH
13
High-side gate drive output
GL
12
Low-side gate drive output
GND
1
Power ground
HS
5
HS control input
LSn
6
LS control input
LSS
11
Low-side source
RESETn
4
Standby mode control input
S
14
Load connection
SCK
8
Serial clock input
SDI
7
Serial data input
SDO
9
Serial data output
STRn
10
Serial strobe (chip select) input
VBB
19
Main power supply
VBRG
20
High-side drain voltage sense
VREG
16
Regulated gate drive supply
PAD
–
Thermal pad; connect to GND
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
A4926
Automotive Half-Bridge MOSFET Driver
VBB
Logic
Supply
Regulator
Bootstrap
Monitor
Control
Logic
C
HS
Drive
GH
VDS
Monitor
S
VDS
Monitor
LS
Drive
STRn
DIAG
VBRG
Timers
RESETn
VBAT
CREG
Charge
Pump
HS
SCK
SDI
SDO
VREG
Charge
Pump
Regulator
ENABLE
LSn
CP2
CP1
CCP
Serial
Interface
GL
LSS
Diagnostics &
Protection
PAD
GND
Figure 2: Functional Block Diagram
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
A4926
Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS: Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY AND REFERENCE
Operating; outputs active
VBB Functional Operating Range
VBB Quiescent Current
Internal Logic Supply Regulator
Voltage [3][4]
VREG Output Voltage, VRG = 0
VREG Output Voltage, VRG = 1
Bootstrap Diode Forward Voltage
5.5
–
50
V
VBB
Operating; outputs disabled
5
–
50
V
No unsafe states
0
–
50
V
IBBQ
RESETn = high, VBB = 12 V,
All gate drive outputs low
–
6
20
mA
IBBS
RESETn ≤ 300 mV, sleep mode, VBB < 35 V
–
–
20
µA
3.1
3.3
3.5
V
VBB > 7.5 V, IVREG = 0 to 30 mA
7.5
8
8.5
V
6 V < VBB ≤ 7.5 V, IVREG = 0 to 13 mA
7.5
8
8.5
V
5.5 V < VBB ≤ 6 V, IVREG < 8 mA
7.5
8
8.5
V
VBB > 9 V, IVREG = 0 to 30 mA
9
11
11.7
V
7.5 V < VBB ≤ 9 V, IVREG = 0 to 20 mA
9
11
11.7
V
VDL
VREG
VREG
VfBOOT
6 V < VBB ≤ 7.5V, IVREG ≤ 0 to 13mA
7.9
–
–
V
5.5 V < VBB ≤ 6 V, IVREG < 8 mA
7.9
9.5
–
V
ID = 10 mA
0.4
0.7
1.0
V
ID = 100 mA
1.2
1.9
2.5
V
Bootstrap Diode Current Limit
IDBOOT
250
500
750
mA
Top-Off Charge Pump Current Limit
ITOCPM
50
100
–
µA
High-Side Gate Drive Static Load
Resistance
RGSH
250
–
–
kΩ
System Clock Period
tOSC
42.5
50
57.5
ns
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
A4926
Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
GATE OUTPUT DRIVE
Turn-On Time
tr
CLOAD = 10 nF, 20% to 80%
–
190
–
ns
Turn-Off Time
tf
CLOAD = 10 nF, 80% to 20%
–
120
–
ns
–
400
–
mA
4
6
10.5
Ω
9.5
12
19
Ω
–
800
–
mA
1.5
2.4
3.1
Ω
Pull-Up Peak Source Current
Pull-Up On Resistance
Pull-Down Peak Sink Current
Pull-Down On Resistance
IPUPK
RDS(on)UP
RDS(on)DN
VGHH
GH Output Voltage Low
VGHL
Gl Output Voltage High
VGLH
Gl Output Voltage Low
VGLL
GH Passive Pull-Down
RGHPD
Turn-On Propagation Delay
IR1 = IR2 = 0, TJ = 150°C, IGH =
–150 mA [1]
IPDPK
GH Output Voltage High
Turn-Off Propagation Delay
IR1 = IR2 = 0, TJ = 25°C, IGH = –150 mA [1]
tP(off)
tP(on)
IF1 = IF2 = 0, TJ = 25°C, IGL = 150 mA
IF1 = IF2 = 0, TJ = 150°C, IGL = 150 mA
–10 µA < IGH < 10 µA
2.9
4
5.5
Ω
VC – 0.2
–
–
V
–
–
VS + 0.3
V
VREG –
0.2
–
–
V
–10 µA < IGL < 10 µA
–
–
VLSS +
0.3
V
VBB = 0 V, VGH – VS < 0.3 V
–
950
–
kΩ
VBB = 0 V, VGL – VLSS < 0.3 V
–
950
–
kΩ
Input Change to unloaded Gate output change,
(Figure 4) DT[5:0] = 0
60
90
140
ns
Input Change to unloaded Gate output change,
(Figure 4) DT[5:0] > 0
135
165
215
ns
Input Change to unloaded Gate output change,
(Figure 4) DT[5:0] = 0
50
80
130
ns
Input Change to unloaded Gate output change,
(Figure 4) DT[5:0] > 0
125
155
205
ns
Propagation Delay Matching
(On-to-Off)
ΔtOO
DT[5:0]=0
–
15
30
ns
Propagation Delay Matching
(GH-to-GL)
ΔtHL
Same state change, DT[5:0] = 0
–
–
20
ns
Dead Time (Turn-Off To Turn-On Delay)
tDEAD
Default power-up state (Figure 4)
1.36
1.6
1.84
µs
Programmable range DT[5:0], nominal
0.1
–
3.15
µs
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
7
A4926
Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
LOGIC INPUT AND OUTPUTS
Input Low Voltage
VIL
–
–
0.8
V
Input High Voltage
VIH
All logic inputs
2.0
–
–
V
Input Hysteresis
VIhys
RESETn inputs
200
400
–
mV
Input Hysteresis
VIhys
All other logic inputs
250
550
–
mV
Input Pull-Down HS, ENABLE,
RESETn
RPD
0 < VIN < 3 V
–
50
–
kΩ
IPD
3 V < VIN < 50 V
–
70
–
µA
Input Pull-Down SDI, SCK
RPDS
0 < VIN < 3 V
–
50
–
kΩ
Input Pull-Up Current to VDL
IPU
STRn
–
70
–
µA
Input Pull-Up to VDL
RPU
LSn
–
170
–
kΩ
Output Low Voltage SDO, DIAG
VOL
IOL = 1 mA
Output High Voltage SDO
Output Leakage SDO [1]
Output Current Limit (DIAG)
Output Leakage [1] (DIAG)
VOHS
IOS
IOLDLIM
IOD
–
0.1
0.4
V
IOS = –200 µA [1]
VDL – 0.1
–
–
V
IOS =
–1 mA [1]
VDL – 0.4
–
–
V
0 V < VOS < VDL, STRn = 1
–1
–
1
µA
0 V < VOD < 12 V, DIAG active
–
10
17
mA
18 V ≤ VOD < 50 V, DIAG active
–
–
2.5
mA
0 V < VOD < 12 V, DIAG inactive
–1
–
1
µA
18 V ≤ VOD < 50 V, DIAG inactive
–
–
2.5
mA
LOGIC I/O – DYNAMIC PARAMETERS
Reset Pulse Width
tRST
0.5
–
4.5
µs
Reset Shutdown Time
tRSD
30
–
–
µs
Input Pulse Filter Time
tPIN
HS, LSn
–
35
–
ns
Clock High Time
tSCKH
A in Figure 3
50
–
–
ns
Clock Low Time
tSCKL
B in Figure 3
50
–
–
ns
Strobe Lead Time
tSTLD
C in Figure 3
30
–
–
ns
Strobe Lag Time
tSTLG
D in Figure 3
30
–
–
ns
Strobe High Time
tSTRH
E in Figure 3
300
–
–
ns
Data Out Enable Time
tSDOE
F in Figure 3
–
–
40
ns
Data Out Disable Time
tSDOD
G in Figure 3
–
–
30
ns
Data Out Valid Time From Clock
Falling
tSDOV
H in Figure 3
–
–
40
ns
Data Out Hold Time From Clock
Falling
tSDOH
I in Figure 3
5
–
–
ns
Data In Set-Up Time To Clock Rising
tSDIS
J in Figure 3
15
–
–
ns
Data In Hold Time From Clock Rising
tSDIH
K in Figure 3
10
–
–
ns
–
–
2
ms
Wake Up From Sleep
tEN
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
8
A4926
Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
DIAGNOSTICS AND PROTECTION
VREG Undervoltage VRG = 0
VREG Undervoltage VRG = 1
VREG Overvoltage Warning
VREG Overvoltage Hysteresis
VBB Overvoltage Warning
VBB Overvoltage Hysteresis
VBB POR Voltage
Bootstrap Undervoltage
Bootstrap Undervoltage Hysteresis
VRON
VREG rising
6.4
6.6
6.7
V
VROFF
VREG falling
5.5
5.7
5.9
V
VRON
VREG rising
7.6
7.95
8.2
V
VROFF
VREG falling
6.9
7.15
7.4
V
VROV
VREG rising
15.5
15.9
16.5
V
1200
1500
–
mV
VBB rising
32
–
36
V
1
–
–
V
VBBR
VBB
–
3.5
–
V
VBCUV
VBOOT falling, VBOOT = VC – VS
56
–
64
%VREG
–
13
–
%VREG
VROVHys
VBBOV
VBBOVHys
VBCUVHys
Gate Drive Undervoltage Warning HS
VGSHUV
VGSH
VBOOT
– 1.25
VBOOT
–1
VBOOT
– 0.8
V
Gate Drive Undervoltage Warning LS
VGSLUV
VGSL
VREG
– 1.25
VREG
–1
VREG
– 0.8
V
VBRG Input Voltage
VBRG Input Current
VDS Threshold – High Side
High-Side VDS Threshold Offset [2]
VDS Threshold – Low Side
Low-Side VDS Threshold Offset [2]
VBRG
When VDS monitor is active
5.5
VBB
50
V
IVBRG
VDSTH = default, VBB = 12 V
0 V < VBRG < VBB
–
–
500
µA
IVBRGQ
Sleep mode VBB < 35 V
–
–
5
µA
Default power-up value
1.1
1.2
1.3
V
Programmable range VT[5:0], nominal
VBRG ≥ 7 V
0
–
3.15
V
Programmable range VT[5:0]
5.5 V ≤ VBRG < 7 V [5]
0
–
1.5
V
High-side on, VDSTH ≥1 V, VBRG > 7 V
–200
±100
200
mV
High-side on, VDSTH < 1 V
–150
±50
150
mV
1.1
1.2
1.3
V
VDSTH
VDSTHO
VDSTL
VDSTLO
VDS Qualify Time
tVDQ
Temperature Warning Threshold
TJWH
Temperature Warning Hysteresis
TJWHhys
Default power-up value
Programmable range, VBB ≥
5.5 V [5]
0
–
3.15
V
Low-side on, VDSTL ≥ 1 V, VBRG > 7 V
–200
±100
200
mV
Low-side on, VDSTL < 1 V
–150
±50
150
mV
Default power-up value (Figure 5)
1.36
1.6
1.84
µs
Programmable range TVD[5:0], nominal
Temperature increasing
Recovery = TJWH – TJWHhys
0
–
6.3
µs
125
135
145
°C
–
15
–
°C
Overtemperature Threshold
TJF
Temperature increasing
170
175
180
°C
Overtemperature Hysteresis
TJHys
Recovery = TJF – TJHys
–
15
–
°C
1 For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device terminal.
offset is the difference between the programmed threshold, VDSTH or VDSTL and the actual trip voltage.
3 VDL derived from VBB for internal use only. Not accessible on any device terminal.
4 Verified by design and characterization.
5 Maximum value of VDS threshold that should be set in the configuration registers for correct operation when VBRG is within the stated range.
2 VDS
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
9
A4926
Automotive Half-Bridge MOSFET Driver
STRn
C
A
B
D
E
SCK
J
SDI
X
K
D15
F
SDO
X
D14
X
X
D0
X
I
Z
G
D15’
D14’
D0’
Z
H
Figure 3: Serial Interface Timing (X = don’t care, Z = high impedance (tri-state))
HS
LSn
tDEAD
GH
tP(off)
tP(on)
tP(off)
GL
tP(off)
tDEAD
Synchronous Rectification
tP(on)
tP(off)
Low-side pwm
High-side pwm
Figure 4: Gate Drive Timing – Control Inputs
MOSFET turn on
No fault present
MOSFET turn on
Fault present
MOSFET on
Transient disturbance
No fault present
MOSFET on
Fault occurs
MOSFET on
Transient disturbance
No fault present
MOSFET on
Fault occurs
Gx
VDS
tVDQ
tVDQ
Fault Bit
Figure 5a: VDS Fault Monitor – Blank Mode Timing (VDQ = 1)
MOSFET turn on
No fault present
MOSFET turn on
Fault present
Gx
VDS
tVDQ
tVDQ
tVDQ
tVDQ
Fault Bit
Figure 5b: VDS Fault Monitor – Debounce Mode Timing (VDQ = 0)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
10
A4926
Automotive Half-Bridge MOSFET Driver
LOGIC TRUTH TABLES
Table 1: Control Logic (Control by Logic Inputs)
HS
LSn
GH
GL
S
0
1
LO
LO
Z
0
0
LO
HI
LO
1
1
HI
LO
HI
1
0
LO
LO
Z
HI = high-side FET active, LO = low-side FET active
Z = high impedance, both FETs off
All control register bits set to 0, RESETn = 1, ENABLE = 1
Table 2: Control Logic (Control by Serial Register)
HSR
LSR
GH
GL
S
0
0
LO
LO
Z
0
1
LO
HI
LO
1
0
HI
LO
HI
1
1
LO
LO
Z
HI = high-side FET active, LO = low-side FET active
Z = high impedance, both FETs off
HS = 0, LSN = 1, RESETn = 1, ENABLE = 1
Table 3: Control combination logic table – Logic Inputs and Serial Register
Terminal
Register
Internal
Terminal
Register
Internal
HS
HSR
HI
LSn
LSR
LO
0
0
0
0
0
1
0
1
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
1
Internal control signals (HI, LO) are derived by combining
the logic states applied to the control input terminals (HS,
LS) with the bit patterns held in the Control register (HSR,
LSR).
Normally the input terminals or the Control register method
is used for control with the other being held inactive (all
termials or bits at logic 0).
ENABLE
HI
LO
GH
GL
S
Comment
1
0
0
L
L
Z
Bridge disabled
1
0
1
L
H
LO
Bridge sinking
1
1
0
H
L
HI
Bridge sourcing
1
1
1
L
L
Z
Bridge disabled
0
X
X
L
L
Z
Bridge disabled
X = don’t care
Allegro MicroSystems
955 Perimeter Road
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11
A4926
Automotive Half-Bridge MOSFET Driver
FUNCTIONAL DESCRIPTION
The A4926 is a half-bridge (H-bridge) MOSFET driver (predriver) requiring a single unregulated supply of 5.5 to 50 V. It
includes an integrated linear regulator to supply the internal logic.
All logic inputs are TTL compatible and can be driven by 3.3 or
5 V logic.
The two high-current gate drives are capable of driving a wide
range of N-channel power MOSFETs, and are configured as a
half-bridge driver with one high-side drive and one low-side
drive. The A4926 provides all necessary circuits to ensure that the
gate-source voltage of both high-side and low-side external FETs
are above 10 V, at supply voltages down to 7 V. For extreme
battery voltage drop conditions, correct functional operation is
guaranteed at supply voltages down to 5.5 V, but with a reduced
gate drive voltage.
Gate drives can be controlled directly through the logic input terminals or through an SPI-compatible serial interface. The sense
of the logic inputs are arranged to allow the bridge to be driven
by a single PWM input if required. The bridge can also be driven
by direct logic inputs or by two PWM signals depending on the
required complexity. The logic inputs are battery voltage compliant, meaning they can be shorted to ground or supply without
damage, up to the maximum battery voltage of 50 V.
Bridge efficiency can be enhanced by using the synchronous
rectification ability of the drives. When synchronous rectification
is used, cross-conduction (shoot through) in the external bridge
is avoided by an adjustable dead time. A hardwired logic lockout
ensures that the high-side and the low-side cannot be permanently
active at the same time.
A low-power sleep mode allows the A4926, the power bridge,
and the load to remain connected to a vehicle battery supply without the need for an additional supply switch.
The A4926 includes a number of diagnostic features to provide
indication and/or protection against undervoltage, overtemperature, and power bridge faults. A single diagnostic output provides
basic fault indication and detailed diagnostic information is
available through the serial interface. The serial interface also
provides access to programmable dead time, fault blanking time
and programmable VDS threshold for short detection.
Input and Output Terminal Functions
VBB: Main power supply for internal regulators and charge
pump. The main power supply should be connected to VBB
through a reverse voltage protection circuit and should be
decoupled with ceramic capacitors connected close to the supply
and ground terminals.
VBRG: Sense input to the top of the external MOSFET bridge.
Allows accurate measurement of the voltage at the drain of the
high-side MOSFET in the bridge.
CP1, CP2: Pump capacitor connection for charge pump. Connect a minimum 220 nF, typically 470 nF, ceramic capacitor
between CP1 and CP2.
VREG: programmable regulated voltage, 8 or 11 V, used to supply the low-side gate drivers and to provide current for the above
supply charge pump. A sufficiently large storage capacitor must
be connected to this terminal to provide the required transient
charging current.
GND: Analog, digital, and power ground. Connect to supply
ground–see Layout Recommendations.
C: High-side connection for the bootstrap capacitor and positive
supply for the high-side gate driver.
GH: High-side, gate-drive output for an external N-channel
MOSFET.
S: Source connection for high-side MOSFET providing the negative supply connections for the floating high-side driver.
GL: Low-side gate-drive output for an external N-channel MOSFET.
LSS: Low-side return path for discharge of the capacitance on
the low-side MOSFET gate, connected to the source of the lowside external MOSFET independently through a low-impedance
track.
HS: Logic inputs with pull-down to control the high-side gate
drive. Battery voltage compliant terminal.
LSn: Logic input with pull-up to control the low-side gate drive.
This is an active-low input. Battery voltage compliant terminal.
ENABLE: Logic input to enable the gate drive outputs. Battery
voltage compliant terminal.
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955 Perimeter Road
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A4926
Automotive Half-Bridge MOSFET Driver
RESETn: Clears latched faults that may have disabled the outputs when taken low for the reset pulse width, tRST. Forces lowpower shutdown (sleep) when held low for more than the RESET
shutdown time, tRSD. Battery voltage compliant terminal.
SDI: Serial data logic input with pull-down. 16-bit serial word
input msb first.
SDO: Serial data output. High impedance when STRn is high.
Outputs bit 15 of the diagnostic register, the fault flag, as soon as
STRn goes low.
is set to 11 V; when VRG = 0 the voltage is set to 8 V. A sufficiently large storage capacitor (see Application Information
section) must be connected to this terminal to provide the transient charging current to the low-side drivers and the bootstrap
capacitors.
Gate Drives
DIAG: Diagnostic output. Provides general fault flag output.
The A4926 is designed to drive external, low on-resistance,
power N-channel MOSFETs. It will supply the large transient
currents necessary to quickly charge and discharge the external
MOSFET gate capacitance in order to reduce dissipation in the
external MOSFET during switching. The charge current for the
low-side drive is provided by the capacitor on the VREG terminal. The charge current for the high-side drives is provided by
the bootstrap capacitor connected between the C and S terminals.
MOSFET gate charge and discharge rates may be controlled by
setting a group of parameters via the serial interface or by using
an external gate resistor between the gate drive output and the
gate terminal of the MOSFET.
Power Supplies
Bootstrap Supply
SCK: Serial clock logic input with pull-down. Data is latched
in from SDI on the rising edge of SCK. There must be 16 rising
edges per write and SCK must be held high when STRn changes.
STRn: Serial data strobe and serial access enable logic input
with pull-up. When STRn is high, any activity on SCK or SDI
is ignored and SDO is high impedance, allowing multiple SDI
slaves to have common SDI, SCK, and SDO connections.
A single power supply voltage is required. The main power supply, VBB, should be connected to VBB through a reverse voltage
protection circuit. A 100 nF ceramic decoupling capacitor must
be connected close to the supply and ground terminals.
An internal regulator provides the supply to the internal logic.
All logic is guaranteed to operate correctly to below the regulator undervoltage levels ensuring that the A4926 will continue to
operate safely until all logic is reset when a power-on-reset state
is present.
The A4926 will operate within specified parameters with VBB
from 7 to 50 V and will function correctly with a supply down to
5.5 V. This provides a rugged solution for use in the harsh automotive environment.
When the high-side drivers are active, the reference voltage for
the driver will rise to close to the bridge supply voltage. The
supply to the driver will then have to be above the bridge supply
voltage to ensure that the driver remains active. This temporary
high-side supply is provided by a bootstrap capacitor connected
between the bootstrap supply terminal, C, and the high-side reference terminal, S.
The bootstrap capacitor is independently charged to approximately VREG when the associated reference S terminal is low.
When the output swings high, the voltage on the bootstrap supply
terminal rises with the output to provide the boosted gate voltage
needed for the high-side N-channel power MOSFETs.
Bootstrap Charge Management
The gate drivers are powered by a programmable voltage internal
regulator which limits the supply to the drivers and therefore
the maximum gate voltage. At low supply voltage, the regulated
supply is maintained by a charge pump boost converter which
requires a pump capacitor, typically 470 nF, connected between
the CP1 and CP2 terminals.
The A4926 monitors the bootstrap capacitor charge voltage to
ensure sufficient high-side drive. It also includes an optional
bootstrap capacitor charge management system (bootstrap manager) to ensure that the bootstrap capacitor remains sufficiently
charged under all conditions. The bootstrap manager is enabled
by default but may be disabled by setting the DBM bit to 1. This
may be required in systems where the output MOSFET switching
must only be allowed by the controlling processor.
The regulated voltage, VREG, can be programmed to 8 or 11 V
and is available on the VREG terminal. The voltage level is
selected by the value of the VRG bit. When VRG = 1, the voltage
Before a high-side drive can be turned on, the bootstrap capacitor
voltage must be higher than the turn-on voltage threshold, VBCUV
+ VBCUVHys. If this is not the case, then the A4926 will attempt
Pump Regulator
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13
A4926
Automotive Half-Bridge MOSFET Driver
to charge the bootstrap capacitor by activating the low-side drive.
Under normal circumstances this will charge the capacitor above
the turn-on voltage in a few microseconds and the high-side drive
will then be enabled. The bootstrap voltage monitor remains
active while the high-side drive is active and if the voltage drops
below the turn-off voltage threshold, VBCUV, a charge cycle is
also initiated.
The bootstrap charge management circuit may actively charge the
bootstrap capacitor regularly when the PWM duty cycle is very
high, particularly when the PWM off-time is too short to permit
the bootstrap capacitor to become sufficiently charged.
In some systems, it may not be desirable to permit this feature.
In this case the bootstrap manager may be disabled by setting
the DBM bit to 1. If the bootstrap manager is disabled, then the
user must ensure that the bootstrap capacitor does not become
discharged below the bootstrap undervoltage threshold, VBCUV,
or a bootstrap fault will be indicated and the outputs disabled.
This can happen with very high PWM duty cycles when the
charge time for the bootstrap capacitor is insufficient to ensure
a sufficient recharge to match the MOSFET gate charge transfer
during turn on.
If, for any reason, the bootstrap capacitor cannot be sufficiently
charged a bootstrap fault will occur—see diagnostics section for
further details.
Top-Off Charge Pump
An additional “top-off” charge pump is provided, which will
allow the high-side drive to maintain the gate voltage on the
external MOSFET indefinitely, ensuring so-called 100% PWM
if required. This is a low-current trickle charge pump and is only
operated after a high side has been signaled to turn on. There is a
small amount of bias current drawn from the C terminal to operate the floating high side circuit (> QGATE
A factor of 20 is a reasonable value, so
QBOOT = CBOOT × VBOOT = QGATE × 20
or
CBOOT = QGATE × 20
VBOOT
where VBOOT is the voltage across the bootstrap capacitor.
VGLA
VGSL
in the bootstrap capacitor, QBOOT, should be much larger than
QGATE, the charge required by the gate:
tDEAD
The voltage drop, ∆V, across the bootstrap capacitor as the MOSFET is being turned on, can be approximated by:
∆V =
Vt0
VGSH
QGATE
CBOOT
so for a factor of 20, ∆V will be 5% of VBOOT.
Figure 7: Minimum Dead Time
Figure 7 shows the typical switching characteristics of a pair of
complementary MOSFETs. Ideally, one MOSFET should start to
turn on just after the other has completely turned off. The point at
which a MOSFET starts to conduct is the threshold voltage Vt0.
The dead time should be long enough to ensure that the gatesource voltage of the MOSFET that is switching off is just below
Vt0 before the gate-source voltage of the MOSFET that is switching on rises to Vt0. This will be the minimum theoretical dead
time, but in practice the dead time will have to be longer than this
to accommodate variations in MOSFET and driver parameters for
process variations and overtemperature.
Bootstrap Capacitor Selection
The A4926 requires a bootstrap capacitor C. To simplify this
description of the bootstrap capacitor selection criteria, generic
naming is used here. So, for example, CBOOT, QBOOT, and VBOOT
refer to the bootstrap capacitor, and QGATE refers to any of the
two associated MOSFETs. CBOOT must be correctly selected to
ensure proper operation of the device—too large and time will be
wasted charging the capacitor, resulting in a limit on the maximum duty cycle and PWM frequency; too small and there can
be a large voltage drop at the time the charge is transferred from
CBOOT to the MOSFET gate.
To keep the voltage drop due to charge sharing small, the charge
The maximum voltage across the bootstrap capacitor under
normal operating conditions is VREG (max). However in some
circumstances the voltage may transiently reach a maximum of
18 V, which is the clamp voltage of the Zener diode between the
C terminal and the S terminal. In most applications with a good
ceramic capacitor, the working voltage can be limited to 16 V.
Bootstrap Charging
It is good practice to ensure the high-side bootstrap capacitor is
completely charged before a high-side PWM cycle is requested.
The time required to charge the capacitor, tCHARGE , in µs, is
approximated by:
tCHARGE =
CBOOT × ∆V
100
where CBOOT is the value of the bootstrap capacitor in nF and ∆V
is the required voltage of the bootstrap capacitor. At power up and
when the drivers have been disabled for a long time, the bootstrap
capacitor can be completely discharged. In this case, ∆V can be
considered to be the full high-side drive voltage, 12 V. Otherwise,
∆V is the amount of voltage dropped during the charge transfer,
which should be 400 mV or less. The capacitor is charged whenever the S terminal is pulled low and current flows from the capacitor connected to the VREG terminal through the internal bootstrap
diode circuit to CBOOT.
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A4926
Automotive Half-Bridge MOSFET Driver
VREG Capacitor Selection
The internal reference, VREG, supplies current for the low-side
gate-drive circuits and the charging current for the bootstrap
capacitors. When a low-side MOSFET is turned on, the gatedrive circuit will provide the high transient current to the gate that
is necessary to turn the MOSFET on quickly. This current, which
can be several hundred milliamperes, cannot be provided directly
by the limited output of the VREG regulator but must be supplied
by an external capacitor, CREG, connected between the VREG
terminal and GND
The turn-on current for the high-side MOSFET is similar in value
but is mainly supplied by the bootstrap capacitor. However, the
bootstrap capacitor must then be recharged from CREG through
the VREG terminal. Unfortunately, the bootstrap recharge can
occur a very short time after the low-side turn on occurs. This
means that the value of CREG between VREG and GND should
be high enough to minimize the transient voltage drop on
VREG for the combination of a low-side MOSFET turn on and
a bootstrap capacitor recharge. For block commutation control
(trapezoidal drive), where only one high side and one low side
are switching during each PWM period, a minimum value of 20 ×
CBOOT is reasonable. For sinusoidal control schemes, a minimum
value of 40 × CBOOT is recommended. As the maximum working voltage of CREG will never exceed VREG, the part’s voltage
rating can be as low as 15 V. However, it is recommended that
a capacitor rated to at least twice the maximum working voltage should be used to reduce any impact operating voltage may
have on capacitance value. For best performance, CREG should be
ceramic rather than electrolytic. CREG should be mounted as close
to the VREG terminal as possible.
Allegro MicroSystems
955 Perimeter Road
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32
A4926
Automotive Half-Bridge MOSFET Driver
INPUT/OUTPUT STRUCTURES
C
16 V
GH
56 V
VBRG
VBB
S
CP1
CP2
DL
VREG
6V
VREG
7.5 V
16 V
GL
56 V
16 V
16 V
20 V
56 V
6V
LSS
Figure 8a: Gate Drive Outputs
Figure 8b: Supplies
VDL
VDL
VDL
BIAS
50 kΩ
2 kΩ
SDI
SCK
RESETn
ENABLE
HS
2 kΩ
STRn
2 kΩ
50 kΩ
50 kΩ
7.5 V
6V
7.5 V
Figure 8c: SDI, SCK Inputs
6V
56 V
Figure 8d: STRn Inputs
Figure 8e: RESETn, ENABLE, HS Inputs
VDL
VDL
BIAS
50 Ω
SDO
7.5 V
Figure 8f: SDO Output
LSn
25 Ω
2 kΩ
170 kΩ
DIAG
56 V
Figure 8g: DIAG Output
56 V
Figure 8h: LSn Input
Allegro MicroSystems
955 Perimeter Road
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33
A4926
Automotive Half-Bridge MOSFET Driver
LAYOUT RECOMMENDATIONS
Careful consideration must be given to PCB layout when designing high-frequency, fast-switching, high-current circuits:
• The exposed thermal pad should be connected to the GND
terminal.
• Minimize stray inductance by using short, wide copper tracks
at the drain and source terminals of all power MOSFETs. This
includes load lead connections, the input power bus.This will
minimize voltages induced by fast switching of large load
currents.
• Consider the addition of small (100 nF) ceramic decoupling
capacitor across the source and drain of the power MOSFETs
to limit fast transient voltage spikes caused by track
inductance.
• Keep the gate discharge return connections S and LSS as short
as possible. Any inductance on these tracks will cause negative
transitions on the corresponding A4926 terminals, which may
exceed the absolute maximum ratings. If this is likely, consider
the use of clamping diodes to limit the negative excursion on
these terminals with respect to the GND terminal.
• Supply decoupling, typically a 100 nF ceramic capacitor,
should be connected between VBB and GND as close to the
A4926 terminals as possible.
• Supply decoupling should be connected between VREG and
GND as close to the A4926 terminals as possible.
• Check the peak voltage excursion of the transients on the
LSS terminals with reference to the GND terminal using a
close-grounded (“tip & barrel”) probe. If the voltage at any
LSS terminal exceeds the absolute maximum in the datasheet,
add additional clamping and/or capacitance between the LSS
terminal and the GND terminal.
• Gate charge drive paths and gate discharge return paths may
carry a large transient current pulse. Therefore, the traces from
GH, GL, S, and LSS should be as short as possible to reduce
the trace inductance.
• Provide an independent connection between the LSS terminal
to the source of the low-side MOSFET in the power bridge.
Connection of the LSS terminal directly to the GND terminal
is not recommended as this may inject noise into sensitive
functions such as the various voltage monitors.
• A low-cost diode can be placed in the connection to VBB
to provide reverse battery protection. In reverse battery
conditions, it is possible to use the body diodes of the power
MOSFETs to clamp the reverse voltage to approximately
4 V. In this case, the additional diode in the VBB connection
will prevent damage to the A4926 and the VBRG input will
survive the reverse voltage.
Optional reverse
battery protection
VBB
+ Supply
VBRG
VREG
GH
Load
S
A4926
GL
LSS
Supply
Common
GND PAD
Controller Supply Ground
Power Ground
Figure 9: Supply Routing Suggestions
Allegro MicroSystems
955 Perimeter Road
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34
A4926
Automotive Half-Bridge MOSFET Driver
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MO-153 ACT)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
6.50 NOM
0.45
4.20
8º MAX
0º MIN
20
0.65
20
0.20 MAX
0.09 MIN
1.70
C
3.00
4.40 ±0.10
3.00
6.40 ±0.20
6.10
A
0.60 ±0.15
1
1.00 REF
2
1
0.25 BSC
20X
0.10
1.20 MAX
C
0.30
0.19
C
2
4.20
SEATING PLANE
GAUGE PLANE
B
SEATING
PLANE
PCB Layout Reference View
0.15 MAX
0.00 MIN
0.65 BSC
NNNNNNN
YYWW
LLLLLLL
A
Terminal #1 mark area
B
Reference land pattern layout (reference IPC7351 SOP65P640X110-21M); all pads a minimum of 0.20 mm from all adjacent pads;
adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB,
thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
C
Exposed thermal pad (bottom surface)
1
B
Standard Branding Reference View
N = Device part number
= Supplier emblem
Y = Last two digits of year of manufacture
W = Week of manufacture
L = Lot number
Figure 10: Package LP, 20-Lead TSSOP with Exposed Pad
Allegro MicroSystems
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35
A4926
Automotive Half-Bridge MOSFET Driver
Revision History
Number
Date
–
March 21, 2017
Description
Initial release
1
April 11, 2017
Corrected Serial Register Reference, Config 7 and 8 (page 27).
2
April 24, 2017
Added DIAG Output section and updated Status and Diagnostic Registers section (page 17).
3
February 11, 2019
Minor editorial updates
4
February 28, 2020
Minor editorial updates
Copyright 2020, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
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