A4928
Automotive Half-Bridge MOSFET Driver
FEATURES AND BENEFITS
DESCRIPTION
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The A4928 is an N-channel power MOSFET driver capable of
controlling MOSFETs connected in a half-bridge arrangement
and is specifically designed for automotive applications with
high-power inductive loads, such as brush DC motors solenoids
and actuators.
Half-bridge MOSFET driver
Bootstrap gate drive for N-channel MOSFET bridge
Cross-conduction protection with adjustable dead time
Charge pump regulator for low supply voltage operation
5.5 to 50 V supply voltage operating range
5 V CMOS Logic I/O
SPI-compatible serial interface
Bridge control by direct logic inputs or serial interface
Programmable gate drive
Current sense amplifier
Programmable diagnostics
2
Automotive AEC-Q100 qualified
A2SIL™ product—device features for
safety-critical systems
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APPLICATIONS
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The A4928 is intended for automotive systems that must meet
ASIL requirements. In common with other Allegro A2SIL™
products, this device incorporates features to complement
proper system design, allowing users to achieve the required
ASIL level.
A unique charge pump regulator provides full gate drive for
battery voltages down to 5.5 V for most applications. A bootstrap
capacitor is used to provide the above-battery supply voltage
required for N-channel MOSFETs.
The half bridge can be controlled by independent logic-level
inputs or through the SPI-compatible serial interface. The
external power MOSFETs are protected from shoot-through
by a programmable dead time.
Anti-lock braking systems (ABS)
HVAC (blower fan)
DC pumps (fuel, oil, water)
Solenoids and actuators
Similar industrial applications
Integrated diagnostics provide indication of multiple internal
faults, system faults, and power bridge faults, and can be
configured to protect the power MOSFETs under most shortcircuit conditions.
PACKAGE:
24-lead TSSOP with
exposed pad (suffix LP)
In addition to providing full access to the bridge control, the
serial interface is also used to alter programmable settings such
as dead time, VDS threshold, and fault blank time. Detailed
diagnostic information can be read through the serial interface.
The A4928 is supplied in a 24-lead eTSSOP (suffix LP). This
package is lead (Pb) free, with 100% matte-tin leadframe
plating (suffix –T).
Not to scale
VBAT
ECU
A4928
Load
SPI
GND
Figure 1: Typical Application
A4928-DS, Rev. 2
MCO-0000332
February 21, 2020
A4928
Automotive Half-Bridge MOSFET Driver
SELECTION GUIDE
Part Number
Packing
Package
A4928KLPTR-T
4000 pieces per reel
7.8 mm × 4.4 mm, 1.2 mm max height
24-lead TSSOP with exposed thermal pad
ABSOLUTE MAXIMUM RATINGS [1]
Characteristic
Load Supply Voltage
Symbol
Notes
VBB
Rating
Unit
–0.3 to 50
V
Regulator Output
VREG
VREG
–0.3 to 16
V
Charge Pump Capacitor Terminal
VCP1
CP1
–0.3 to 16
V
Charge Pump Capacitor Terminal
VCP2
CP2
VCP1 – 0.3 to
VREG + 0.3
V
Battery-Compliant Logic Input Terminals
VIB
HS, LSn, RESETn, ENABLE
–0.3 to 50
V
Logic Input Terminals
VI
STRn, SCK, SDI
–0.3 to 6
V
Logic Output Terminal
VO
SDO
–0.3 to 6
V
Diagnostics Output
VDIAG
DIAG
–0.3 to 50
V
Sense Amplifier Inputs
VCSI
CSP, CSM
–4 to 6.5
V
Sense Amplifier Output
VCSO
CSO, OOS
–0.3 to 6
V
Bridge Drain Monitor Terminal
VBRG
VBRG
–5 to 55
V
Bootstrap Supply Terminal
High-Side Gate Drive Output Terminal
VC
VGH
High-Side Source (Load) Terminal
VS
Low-Side Gate Drive Output Terminal
VGL
Bridge Low-Side Source Terminal
VLSS
Ambient Operating Temperature Range
Maximum Continuous Junction Temperature
TA
GH
GH (transient)
S
TJt
Storage Temperature Range
Tstg
–0.3 to VREG + 50
V
VC – 16 to VC + 0.3
V
–18 to VC + 0.3
V
VC – 16 to VC + 0.3
V
S (transient)
–18 to VC + 0.3
V
GL
VREG – 16 to 18
V
–8 to 18
V
VREG – 16 to 18
V
–8 to 18
V
GL (transient)
LSS
LSS (transient)
Limited by power dissipation
–40 to 150
°C
165
°C
180
°C
–55 to 150
°C
Value
Unit
4-layer PCB based on JEDEC standard
28
°C/W
2-layer PCB with 3.8 in.2 copper each side
38
°C/W
2
°C/W
TJ(max)
Transient Junction Temperature
[1]
C
Overtemperature event not exceeding 10 seconds,
lifetime duration not exceeding 10 hours,
guaranteed by design characterization.
With respect to GND. Ratings apply when no other circuit operating constraints are present.
THERMAL CHARACTERISTICS: May require derating at maximum conditions
Characteristic
Package Thermal Resistance
Symbol
RθJA
RθJP
[2] Additional
Test Conditions [2]
thermal information available on the Allegro website.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
A4928
Automotive Half-Bridge MOSFET Driver
Table of Contents
Features and Benefits........................................................ 1
Description......................................................................... 1
Package............................................................................. 1
Typical Application............................................................. 1
Selection Guide................................................................. 2
Absolute Maximum Ratings............................................... 2
Thermal Characteristics..................................................... 2
Pinout Diagram and Terminal List Table............................ 4
Functional Block Diagram.................................................. 5
Electrical Characteristics................................................... 6
Supply and Reference........................................................ 6
Gate Output Drive.............................................................. 7
Logic Inputs and Outputs.................................................... 8
Logic I/O – Dynamic Parameters......................................... 8
Current Sense Amplifier...................................................... 9
Diagnostics and Protection................................................ 10
Timing Diagrams...............................................................11
Logic Truth Tables............................................................ 13
Functional Description..................................................... 14
Input and Output Terminal Functions.................................. 14
Power Supplies............................................................... 15
Pump Regulator............................................................... 15
Gate Drives..................................................................... 15
Bootstrap Supply............................................................. 15
Bootstrap Charge Management......................................... 15
Top-Off Charge Pump....................................................... 16
High-Side Gate Drive....................................................... 16
Low-Side Gate Drive........................................................ 16
Gate Drive Passive Pull-Down........................................... 17
Dead Time...................................................................... 17
Gate Drive Control........................................................... 17
Logic Control Inputs......................................................... 18
Output Disable................................................................. 18
Sleep Mode..................................................................... 19
Current Sense Amplifier.................................................... 19
Diagnostic Monitors.......................................................... 19
Status and Diagnostic Registers........................................ 20
Chip-Level Protection....................................................... 20
Operational Monitors........................................................ 21
Power Bridge and Load Faults........................................... 21
Fault Action..................................................................... 24
Fault Masks.................................................................... 25
Serial Interface................................................................. 26
Configuration Registers.................................................... 28
Diagnostic Registers........................................................ 28
Control Register............................................................... 28
Status Register................................................................ 29
Serial Register Reference................................................ 30
Application Information.................................................... 36
Dead-Time Selection........................................................ 36
Bootstrap Capacitor Selection........................................... 36
Bootstrap Charging.......................................................... 36
VREG Capacitor Selection................................................ 37
Current Sense Amplifier Configuration................................ 37
Current Sense Amplifier Output Signals.............................. 37
Input/Output Structures.................................................... 38
Layout Recommendations............................................... 39
Package Outline Drawing................................................ 40
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
A4928
Automotive Half-Bridge MOSFET Driver
PINOUT DIAGRAM AND TERMINAL LIST TABLE
GND 1
24 VBRG
DIAG 2
23 VBB
ENABLE 3
22 CP1
RESETn 4
21 CP2
20 VREG
HS 5
LSn 6
PAD
SDI 7
19 C
18 S
SCK 8
17 GH
SDO 9
16 GL
STRn 10
15 LSS
OOS 11
14 CSP
CSO 12
13 CMS
24-Lead eTSSOP (suffix LP)
Pinout Diagram
Terminal List Table
Name
Number
Function
C
19
Bootstrap capacitor
CP1
22
Pump capacitor CCP connection
CP2
21
Pump capacitor CCP connection
CSM
13
Current sense amplifier (–) input
CSO
12
Current sense amplifier output
CSP
14
Current sense amplifier (+) input
DIAG
2
Diagnostic output
ENABLE
3
Gate drive output control input
GH
17
High-side gate drive output
GL
16
Low-side gate drive output
GND
1
Power ground
HS
5
HS control input
LSn
6
LS control input
LSS
15
Low-side source
OOS
11
Sense amplifier offset output
RESETn
4
Standby mode control input
S
18
Load connection
SCK
8
Serial clock input
SDI
7
Serial data input
SDO
9
Serial data output
STRn
10
Serial strobe (chip select) input
VBB
23
Main power supply
VBRG
24
High-side drain voltage sense
VREG
20
Regulated gate drive supply
PAD
–
Thermal pad; connect to GND
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
A4928
Automotive Half-Bridge MOSFET Driver
VBB
Logic
I/O
Regulator
CP2
CP1
CCP
VREG
Charge
Pump
Regulator
Logic
Supply
Regulator
CREG
VBRG
Charge
Pump
ENABLE
C
GH
HS
Drive
VDS
Monitor
HS
LSn
Bootstrap
Monitor
Control
Logic
VDS
Monitor
LS
Drive
RESETn
Timers
DIAG
Serial
Interface
DAC
V OOS
DAC
GL
CSP
CSM
CSO
Diagnostics &
Protection
PAD
S
LSS
OOS
STRn
SCK
SDI
SDO
VBAT
GND
Figure 2: Functional Block Diagram
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
A4928
Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS: Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY AND REFERENCE
Operating; outputs active
VBB Functional Operating Range
VBB Quiescent Current
5.5
–
50
V
VBB
Operating; outputs disabled
5
–
50
V
No unsafe states
0
–
50
V
IBBQ
RESETn = high, VBB = 12 V,
All gate drive outputs low
–
8
20
mA
IBBS
RESETn ≤ 300 mV, sleep mode, VBB < 35 V
–
–
20
µA
3.1
3.3
3.5
V
VBB > 6 V
4.8
5
5.2
V
VBB > 7.5 V, IVREG = 0 to 30 mA
7.5
8
8.5
V
6 V < VBB ≤ 7.5 V, IVREG = 0 to 13 mA
7.5
8
8.5
V
5.5 V < VBB ≤ 6 V, IVREG < 8 mA
7.5
8
8.5
V
9
11
11.7
V
7.5 V < VBB ≤ 9 V, IVREG = 0 to 20 mA
9
11
11.7
V
6 V < VBB ≤ 7.5V, IVREG ≤ 0 to 13mA
7.9
–
–
V
5.5 V < VBB ≤ 6 V, IVREG < 8 mA
7.9
9.5
–
V
ID = 10 mA
0.4
0.7
1.0
V
Internal Logic Supply Regulator
Voltage [3][4]
VDL
Logic I/O Regulator Voltage [3][4]
VIO
VREG Output Voltage, VRG = 0
VREG
VBB > 9 V, IVREG = 0 to 30 mA
VREG Output Voltage, VRG = 1
VREG
Bootstrap Diode Forward Voltage
VfBOOT
1.2
1.9
2.5
V
Bootstrap Diode Current Limit
IDBOOT
250
500
750
mA
Top-Off Charge Pump Current Limit
ITOCPM
50
100
–
µA
High-Side Gate Drive Static Load
Resistance
RGSH
250
–
–
kΩ
System Clock Period
tOSC
42.5
50
57.5
ns
ID = 100 mA
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
A4928
Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
GATE OUTPUT DRIVE
Turn-On Time
tr
CLOAD = 10 nF, 20% to 80%
–
190
–
ns
Turn-Off Time
tf
CLOAD = 10 nF, 80% to 20%
–
120
–
ns
–
400
–
mA
4
6
10.5
Ω
9.5
12
19
Ω
–
800
–
mA
1.5
2.4
3.1
Ω
Pull-Up Peak Source Current
Pull-Up On Resistance
Pull-Down Peak Sink Current
Pull-Down On Resistance
GH Output Voltage High
IPUPK
RDS(on)UP
RDS(on)DN
VGHL
VGLH
GL Output Voltage Low
VGLL
Turn-On Propagation Delay
TJ = 25°C, IGL = 150 mA
TJ = 150°C, IGL = 150 mA
VGHH
GH Output Voltage Low
Turn-Off Propagation Delay
TJ = 150°C, IGH =
–150 mA [1]
IPDPK
GL Output Voltage High
GH Passive Pull-Down
TJ = 25°C, IGH = –150 mA [1]
RGHPD
tP(off)
tP(on)
–10 µA < IGH < 10 µA
2.9
4
5.5
Ω
VC – 0.2
–
–
V
–
–
VS + 0.3
V
VREG – 0.2
–
–
V
–10 µA < IGL < 10 µA
–
–
VLSS + 0.3
V
VGH – VS < 0.3 V
–
950
–
kΩ
VGL – VLSS < 0.3 V
–
950
–
kΩ
Input Change to unloaded Gate output change,
(Figure 5) DT[9:0] = 0
60
90
140
ns
Input Change to unloaded Gate output change,
(Figure 5) DT[9:0] > 0
135
165
215
ns
Input Change to unloaded Gate output change,
(Figure 5) DT[9:0] = 0
50
80
130
ns
Input Change to unloaded Gate output change,
(Figure 5) DT[9:0] > 0
125
155
205
ns
Propagation Delay Matching
(On-to-Off)
ΔtOO
DT[9:0] = 0
–
15
30
ns
Propagation Delay Matching
(GH-to-GL)
ΔtHL
Same state change, DT[9:0] = 0
–
–
20
ns
Dead Time (Turn-Off To Turn-On Delay)
tDEAD
Default power-up state (Figure 5)
40
51.15
62.35
µs
Programmable range DT[9:0], nominal
0.1
–
51.15
µs
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
7
A4928
Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
–
–
1.5
V
3.5
–
–
V
LOGIC INPUT AND OUTPUTS
Input Low Voltage
VIL
Input High Voltage
VIH
All logic inputs
RESETn inputs
200
400
–
mV
All other logic inputs
250
550
–
mV
–
50
–
kΩ
–
100
–
µA
0 < VIN < 5 V
–
50
–
kΩ
Input Hysteresis
VIhys
Input Pull-Down HS, ENABLE,
RESETn
RPD
0 < VIN < 5 V
IPD
5 V < VIN < 50 V
Input Pull-Down SDI, SCK
RPDS
Input Pull-Up Current to VDL
IPU
STRn
–
100
–
µA
Input Pull-Up to VDL
RPU
LSn
–
170
–
kΩ
Output Low Voltage SDO, DIAG
VOL
IOL = 1 mA
Output High Voltage SDO
Output Leakage SDO [1]
Output Current Limit (DIAG)
Output Leakage [1] (DIAG)
VOHS
IOS
IOLDLIM
IOD
–
0.1
0.4
V
IOS = –200 µA [1]
VIO – 0.1
–
–
V
IOS =
–1 mA [1]
VIO – 0.4
–
–
V
0 V < VOS < VIO, STRn = 1
–1
–
1
µA
0 V < VOD < 12 V, DIAG active
–
10
17
mA
18 V ≤ VOD < 50 V, DIAG active
–
–
2.5
mA
0 V < VOD < 12 V, DIAG inactive
–1
–
1
µA
18 V ≤ VOD < 50 V, DIAG inactive
–
–
2.5
mA
LOGIC I/O – DYNAMIC PARAMETERS
Reset Pulse Width
tRST
0.5
–
4.5
µs
Reset Shutdown Time
tRSD
30
–
–
µs
Input Pulse Filter Time
tPIN
HS, LSn
–
35
–
ns
Clock High Time
tSCKH
A in Figure 4
50
–
–
ns
Clock Low Time
tSCKL
B in Figure 4
50
–
–
ns
Strobe Lead Time
tSTLD
C in Figure 4
30
–
–
ns
Strobe Lag Time
tSTLG
D in Figure 4
30
–
–
ns
Strobe High Time
tSTRH
E in Figure 4
300
–
–
ns
Data Out Enable Time
tSDOE
F in Figure 4
–
–
40
ns
Data Out Disable Time
tSDOD
G in Figure 4
–
–
30
ns
Data Out Valid Time From Clock Falling
tSDOV
H in Figure 4
–
–
40
ns
Data Out Hold Time From Clock Falling
tSDOH
I in Figure 4
5
–
–
ns
Data In Set-Up Time To Clock Rising
tSDIS
J in Figure 4
15
–
–
ns
Data In Hold Time From Clock Rising
tSDIH
K in Figure 4
10
–
–
ns
–
–
2
ms
Wake Up From Sleep
tEN
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
8
A4928
Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
CURRENT SENSE AMPLIFIER
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current [1]
VIOS
–4
–
+4
mV
ΔVIOS
–
±4
–
µV/°C
0 V < VCSP < VDL, 0 V < VCSM < VDL
–16
–
31
µA
Input Offset Current [1]
IBIAS
IOS
VID = 0 V, VCM in range
–10
–
+10
µA
Input Common-Mode Range (DC)
VCM
VID = 0 V
Gain
AV
Gain Error
EA
–1.8
–
+2
V
Default power-up value
–
35
–
V/V
Programmable range, SAG[2:0], nominal
10
–
50
V/V
VCM in range
–5
±2
+5
%
Default power-up value
–
2.5
–
V
Output Offset
VOOS
0
–
2.5
V
Output Offset Error
EVO
VCM in range, VOOS > 0 V
–10
±2
+10
%
Small Signal –3 dB Bandwidth
at Gain = 25
BW
VIN = 10 mVpp
500
–
–
kHz
Output Settling Time (to within 40 mV)
tSET
VCSO = 1 Vpp square wave
Gain = 25, COUT = 200 pF
–
1
1.8
µs
–100 µA < ICSO < 100 µA
0.3
–
4.8
V
Output Dynamic Range
VCSOUT
Programmable range, SAO[3:0], nominal
Output Voltage Clamp
VCSC
ICSO = –2 mA
4.85
5.2
5.6
V
Output Current Sink [1]
ICSsink
VID = 0 V, VCSO = 1.5 V, Gain = 25
0.275
–
–
mA
Output Current Sink (Boosted) [1][5]
ICSsinkb
VOOS = 0 V, VID = –50 mV, VCSO = 1.5 V,
Gain = 25
1
–
–
mA
Output Current Source [1]
ICSsource
VID = 200 mV, VCSO = 1.5 V
Gain = 25, Offset = 0 V
–
–
–1
mA
VID = 0 V, 100 kHz, Gain = 25
–
75
–
dB
VBB Supply Ripple Rejection Ratio
DC Common-Mode Rejection Ratio
AC Common-Mode Rejection Ratio
PSRR
CMRR
CMRR
VCSP = VCSM = 0 V, DC, Gain = 25
75
–
–
dB
VCM step from 0 to 200 mV
Gain = 25
55
–
–
dB
VCM = 200 mVpp, 100 kHz, Gain = 25
–
62
–
dB
VCM = 200 mVpp, 1 MHz, Gain = 25
–
43
–
dB
VCM = 200 mVpp, 10 MHz, Gain = 25
–
25
–
dB
Common Mode Recovery Time
(to within 100 mV)
tCMrec
VCM step from –4 V to +1 V
Gain = 25, COUT = 200 pF
–
1
–
µs
Output Slew Rate 10% to 90%
SR
VID step from 0 to 175 mV
Gain = 25, COUT = 200 pF
–
10
–
V/µs
VID step from 250 mV to 0 V
Gain = 25, COUT = 200 pF
–
1
–
µs
Input Overload Recovery
(to within 100 mV)
tIDrec
Continued on the next page…
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
9
A4928
Automotive Half-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued): Valid for TJ = –40 to 150°C, VBB = 5.5 to 50 V, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
DIAGNOSTICS AND PROTECTION
VREG Undervoltage VRG = 0
VREG Undervoltage VRG = 1
VREG Overvoltage Warning
VREG Overvoltage Hysteresis
VBB Overvoltage Warning
VBB Overvoltage Hysteresis
VRON
VREG rising
6.4
6.6
6.7
V
VROFF
VREG falling
5.5
5.7
5.9
V
VRON
VREG rising
7.6
7.95
8.2
V
VROFF
VREG falling
6.9
7.15
7.4
V
VROV
VREG rising
VROVHys
VBBOV
VBB rising
VBBOVHys
15.5
15.9
16.5
V
1200
1500
–
mV
32
–
36
V
1
–
–
V
VBB POR Voltage
VBBR
VBB
–
3.5
–
V
Bootstrap Undervoltage
VBCUV
VBOOT falling, VBOOT = VC – VS
56
–
64
%VREG
–
13
–
%VREG
Bootstrap Undervoltage Hysteresis
VBCUVHys
Gate Drive Undervoltage Warning HS
VGSHUV
VGSH
VBOOT
– 1.25
VBOOT
–1
VBOOT
– 0.8
V
Gate Drive Undervoltage Warning LS
VGSLUV
VGSL
VREG
– 1.25
VREG
–1
VREG
– 0.8
V
VBRG Input Voltage
VBRG Input Current
VDS Threshold – High Side
High-Side VDS Threshold Offset [2]
VDS Threshold – Low Side
Low-Side VDS Threshold Offset [2]
VBRG
When VDS monitor is active
5.5
VBB
50
V
IVBRG
VDSTH = default, VBB = 12 V
0 V < VBRG < VBB
–
–
500
µA
IVBRGQ
Sleep mode VBB < 35 V
–
–
5
µA
Default power-up value
1.1
1.2
1.3
V
Programmable range VT[5:0], nominal
0
–
3.15
V
Programmable range VT[5:0]
5.5 V ≤ VBRG < 7 V [6]
0
–
1.5
V
High-side on, VDSTH ≥1 V, VBRG > 7 V
–200
±100
200
mV
High-side on, VDSTH < 1 V
–150
±50
150
mV
1.1
1.2
1.3
V
VDSTH
VDSTHO
VDSTL
VDSTLO
VDS and VGS Qualify Time
tVDQ
Overcurrent Voltage
VOCT
Overcurrent Qualify Time
tOCQ
Temperature Warning Threshold
TJWH
Temperature Warning Hysteresis
TJWHhys
Default power-up value
Programmable range, VBB ≥
5.5 V [6]
0
–
3.15
V
Low-side on, VDSTL ≥ 1 V, VBRG > 7 V
–200
±100
200
mV
Low-side on, VDSTL < 1 V
–150
±50
150
mV
Default power-up value (Figure 6)
86.96
102.3
117.65
µs
0
–
102.3
µs
Default power-up value
2.7
3.0
3.3
V
Programmable range, OCT[3:0], nominal
0.3
–
4.8
V
6.75
7.5
8.25
µs
125
135
145
°C
Programmable range TVD[9:0], nominal
Temperature increasing
–
15
–
°C
Overtemperature Threshold
TJF
Recovery = TJWH – TJWHhys
Temperature increasing
170
175
180
°C
Overtemperature Hysteresis
TJHys
Recovery = TJF – TJHys
–
15
–
°C
[1] For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device terminal.
[2] VDS offset is the difference between the programmed threshold, V
DSTH or VDSTL and the actual trip voltage.
[3] VIO, VDL derived from VBB for internal use only. Not accessible on any device terminal.
[4] Verified by design and characterization.
[5] If the amplifier output voltage (V
CSO) is more positive than the value demanded by the applied differential input (VID) and output offset (VOOS)
conditions, then output current sink capability is boosted to enhance negative-going transient response.
[6] Maximum value of VDS threshold that should be set in the configuration registers for correct operation when V
BRG is within the stated range.
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10
A4928
Automotive Half-Bridge MOSFET Driver
VCSO = [(VCSP + VCSM) × AV] + VOOS
CSP
CSO
AV
VID
RS
VCM = (VCSP + VCSM) / 2
VCSD
OOS
CSM
AV set by
SAG[2:0]
VCSP
VCSM
IPH
VOOS set by
SAO[3:0]
VOOS
VCSO
A4928
GND
Figure 3: Sense Amplifier Voltage Definitions
STRn
C
A
B
D
E
SCK
J
SDI
X
K
D15
F
SDO
X
D14
X
X
D0
X
I
Z
G
D15’
D14’
D0’
Z
H
Figure 4: Serial Interface Timing (X = don’t care, Z = high impedance (tri-state))
HS
LSn
tDEAD
GH
tP(off)
tP(on)
tP(off)
GL
tP(off)
Synchronous Rectification
tDEAD
High-Side PWM
tP(on)
tP(off)
Low-Side PWM
Figure 5: Gate Drive Timing – Control Inputs
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A4928
Automotive Half-Bridge MOSFET Driver
MOSFET turn on
No fault present
MOSFET turn on
Fault present
MOSFET on
Transient disturbance
No fault present
MOSFET on
Fault occurs
MOSFET on
Transient disturbance
No fault present
MOSFET on
Fault occurs
Gx
VDS
tVDQ
tVDQ
Fault Bit
Figure 6a: VDS Fault Monitor – Blank Mode Timing (VDQ = 1)
MOSFET turn on
No fault present
MOSFET turn on
Fault present
Gx
VDS
tVDQ
tVDQ
tVDQ
tVDQ
Fault Bit
Figure 6b: VDS Fault Monitor – Debounce Mode Timing (VDQ = 0)
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A4928
Automotive Half-Bridge MOSFET Driver
LOGIC TRUTH TABLES
Table 1: Control Logic (Control by Logic Inputs)
HS
LSn
GH
GL
S
0
1
LO
LO
Z
0
0
LO
HI
LO
1
1
HI
LO
HI
1
0
LO
LO
Z
HI = high-side FET active, LO = low-side FET active
Z = high impedance, both FETs off
All control register bits set to 0, RESETn = 1, ENABLE = 1
Table 2: Control Logic (Control by Serial Register)
HSR
LSR
GH
GL
S
0
0
LO
LO
Z
0
1
LO
HI
LO
1
0
HI
LO
HI
1
1
LO
LO
Z
HI = high-side FET active, LO = low-side FET active
Z = high impedance, both FETs off
HS = 0, LSN = 1, RESETn = 1, ENABLE = 1
Table 3: Control combination logic table – Logic Inputs and Serial Register
Terminal
Register
Internal
Terminal
Register
Internal
HS
HSR
HI
LSn
LSR
LO
0
0
0
0
0
1
Internal control signals (HI, LO) are derived by combining
the logic states applied to the control input terminals (HS,
LS) with the bit patterns held in the Control register (HSR,
LSR).
0
1
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
1
GL
S
Comment
ENABLE
HI
LO
GH
Normally the input terminals or the Control register method
is used for control with the other being held inactive (all
termials or bits at logic 0).
1
0
0
L
L
Z
Bridge disabled
1
0
1
L
H
LO
Bridge sinking
1
1
0
H
L
HI
Bridge sourcing
1
1
1
L
L
Z
Bridge disabled
0
X
X
L
L
Z
Bridge disabled
X = don’t care
Allegro MicroSystems
955 Perimeter Road
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13
A4928
Automotive Half-Bridge MOSFET Driver
FUNCTIONAL DESCRIPTION
The A4928 is a half-bridge (H-bridge) MOSFET driver (predriver) requiring a single unregulated supply of 5.5 to 50 V. It
includes an integrated linear regulator to supply the internal logic.
All logic inputs are TTL compatible and can be driven by 3.3 or
5 V logic.
The two high-current gate drives are capable of driving a wide
range of N-channel power MOSFETs, and are configured as a
half-bridge driver with one high-side drive and one low-side
drive. The A4928 provides all necessary circuits to ensure that the
gate-source voltage of both high-side and low-side external FETs
are above 10 V, at supply voltages down to 7 V. For extreme
battery voltage drop conditions, correct functional operation is
guaranteed at supply voltages down to 5.5 V, but with a reduced
gate drive voltage.
Gate drives can be controlled directly through the logic input terminals or through an SPI-compatible serial interface. The sense
of the logic inputs are arranged to allow the bridge to be driven
by a single PWM input if required. The bridge can also be driven
by direct logic inputs or by two PWM signals depending on the
required complexity. The logic inputs are battery voltage compliant, meaning they can be shorted to ground or supply without
damage, up to the maximum battery voltage of 50 V.
Bridge efficiency can be enhanced by using the synchronous
rectification ability of the drives. When synchronous rectification
is used, cross-conduction (shoot through) in the external bridge
is avoided by an adjustable dead time. A hardwired logic lockout
ensures that the high-side and the low-side cannot be permanently
active at the same time.
A low-power sleep mode allows the A4928, the power bridge,
and the load to remain connected to a vehicle battery supply without the need for an additional supply switch.
The A4928 includes a number of diagnostic features to provide
indication and/or protection against undervoltage, overtemperature, and power bridge faults. A single diagnostic output provides
basic fault indication and detailed diagnostic information is
available through the serial interface. The serial interface also
provides access to programmable dead time, fault blanking time
and programmable VDS threshold for short detection.
The A4928 includes a low-side current sense amplifier with programmable gain and offset. The amplifier is specifically designed
for current sensing in the presence of high voltage and current
transients.
Input and Output Terminal Functions
VBB: Main power supply for internal regulators and charge
pump. The main power supply should be connected to VBB
through a reverse voltage protection circuit and should be
decoupled with ceramic capacitors connected close to the supply
and ground terminals.
VBRG: Sense input to the top of the external MOSFET bridge.
Allows accurate measurement of the voltage at the drain of the
high-side MOSFET in the bridge.
CP1, CP2: Pump capacitor connection for charge pump. Connect a minimum 220 nF, typically 470 nF, ceramic capacitor
between CP1 and CP2.
VREG: Programmable regulated voltage, 8 or 11 V, used to supply the low-side gate drivers and to provide current for the above
supply charge pump. A sufficiently large storage capacitor must
be connected to this terminal to provide the required transient
charging current.
GND: Analog, digital, and power ground. Connect to supply
ground–see Layout Recommendations.
C: High-side connection for the bootstrap capacitor and positive
supply for the high-side gate driver.
GH: High-side, gate-drive output for an external N-channel
MOSFET.
S: Source connection for high-side MOSFET providing the negative supply connections for the floating high-side driver.
GL: Low-side gate-drive output for an external N-channel MOSFET.
LSS: Low-side return path for discharge of the capacitance on
the low-side MOSFET gate, connected to the source of the lowside external MOSFET independently through a low-impedance
track.
HS: Logic inputs with pull-down to control the high-side gate
drive. Battery voltage compliant terminal.
LSn: Logic input with pull-up to control the low-side gate drive.
This is an active-low input. Battery voltage compliant terminal.
ENABLE: Logic input to enable the gate drive outputs. Battery
voltage compliant terminal.
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A4928
Automotive Half-Bridge MOSFET Driver
RESETn: Clears latched fault states that may have disabled the
outputs when taken low for the reset pulse width, tRST. Forces
low-power shutdown (sleep) when held low for more than the
RESET shutdown time, tRSD. Battery voltage compliant terminal.
SDI: Serial data logic input with pull-down. 16-bit serial word
input msb first.
SDO: Serial data output. High impedance when STRn is high.
Outputs bit 15 of the diagnostic register, the fault flag, as soon as
STRn goes low.
SCK: Serial clock logic input with pull-down. Data is latched
in from SDI on the rising edge of SCK. There must be 16 rising
edges per write and SCK must be held high when STRn changes.
STRn: Serial data strobe and serial access enable logic input
with pull-up. When STRn is high, any activity on SCK or SDI
is ignored and SDO is high impedance, allowing multiple SDI
slaves to have common SDI, SCK, and SDO connections.
CSP, CSM: Current sense amplifier inputs.
CSO: Current sense amplifier output.
OOS: Monitor point for programmable analogue output offset
voltage applied to current sense amplifiers.
DIAG: Diagnostic output. Provides general fault flag output.
Power Supplies
A single power supply voltage is required. The main power supply, VBB, should be connected to VBB through a reverse voltage
protection circuit. A 100 nF ceramic decoupling capacitor must
be connected close to the supply and ground terminals.
A low power independent internal regulator provides the supply
voltage, VDL, to the internal logic. A second integrated linear
regulator provides the supply voltage, VIO, to all logic inputs and
push-pull outputs.
An internal regulator provides the supply to the internal logic.
All logic is guaranteed to operate correctly to below the regulator undervoltage levels ensuring that the A4928 will continue to
operate safely until all logic is reset when a power-on-reset state
is present.
The A4928 will operate within specified parameters with VBB
from 7 to 50 V and will function correctly with a supply down to
5.5 V. This provides a rugged solution for use in the harsh automotive environment.
Pump Regulator
The gate drivers are powered by a programmable voltage internal
regulator which limits the supply to the drivers and therefore
the maximum gate voltage. At low supply voltage, the regulated
supply is maintained by a charge pump boost converter which
requires a pump capacitor, typically 470 nF, connected between
the CP1 and CP2 terminals.
The regulated voltage, VREG, can be programmed to 8 or 11 V
and is available on the VREG terminal. The voltage level is
selected by the value of the VRG bit. When VRG = 1, the voltage
is set to 11 V; when VRG = 0 the voltage is set to 8 V. A sufficiently large storage capacitor (see Application Information
section) must be connected to this terminal to provide the transient charging current to the low-side drivers and the bootstrap
capacitors.
Gate Drives
The A4928 is designed to drive external, low on-resistance,
power N-channel MOSFETs. It will supply the large transient
currents necessary to quickly charge and discharge the external
MOSFET gate capacitance in order to reduce dissipation in the
external MOSFET during switching. The charge current for the
low-side drive is provided by the capacitor on the VREG terminal. The charge current for the high-side drives is provided by
the bootstrap capacitor connected between the C and S terminals.
MOSFET gate charge and discharge rates may be controlled by
setting a group of parameters via the serial interface or by using
an external gate resistor between the gate drive output and the
gate terminal of the MOSFET.
Bootstrap Supply
When the high-side drivers are active, the reference voltage for
the driver will rise to close to the bridge supply voltage. The
supply to the driver will then have to be above the bridge supply
voltage to ensure that the driver remains active. This temporary
high-side supply is provided by a bootstrap capacitor connected
between the bootstrap supply terminal, C, and the high-side reference terminal, S.
The bootstrap capacitor is independently charged to approximately VREG when the associated reference S terminal is low.
When the output swings high, the voltage on the bootstrap supply
terminal rises with the output to provide the boosted gate voltage
needed for the high-side N-channel power MOSFETs.
Allegro MicroSystems
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15
A4928
Automotive Half-Bridge MOSFET Driver
Bootstrap Charge Management
The A4928 monitors the bootstrap capacitor charge voltage to
ensure sufficient high-side drive. It also includes an optional
bootstrap capacitor charge management system (bootstrap manager) to ensure that the bootstrap capacitor remains sufficiently
charged under all conditions. The bootstrap manager is enabled
by default but may be disabled by setting the DBM bit to 1. This
may be required in systems where the output MOSFET switching
must only be allowed by the controlling processor.
Before a high-side drive can be turned on, the bootstrap capacitor
voltage must be higher than the turn-on voltage threshold, VBCUV
+ VBCUVHys. If this is not the case, then the A4928 will attempt
to charge the bootstrap capacitor by activating the low-side drive.
Under normal circumstances this will charge the capacitor above
the turn-on voltage in a few microseconds and the high-side drive
will then be enabled. The bootstrap voltage monitor remains
active while the high-side drive is active and if the voltage drops
below the turn-off voltage threshold, VBCUV, a charge cycle is
also initiated.
The bootstrap charge management circuit may actively charge the
bootstrap capacitor regularly when the PWM duty cycle is very
high, particularly when the PWM off-time is too short to permit
the bootstrap capacitor to become sufficiently charged.
In some systems, it may not be desirable to permit this feature.
In this case the bootstrap manager may be disabled by setting
the DBM bit to 1. If the bootstrap manager is disabled, then the
user must ensure that the bootstrap capacitor does not become
discharged below the bootstrap undervoltage threshold, VBCUV,
or a bootstrap fault will be indicated and the outputs disabled.
This can happen with very high PWM duty cycles when the
charge time for the bootstrap capacitor is insufficient to ensure
a sufficient recharge to match the MOSFET gate charge transfer
during turn on.
If, for any reason, the bootstrap capacitor cannot be sufficiently
charged a bootstrap fault will occur—see diagnostics section for
further details.
Top-Off Charge Pump
An additional “top-off” charge pump is provided, which will
allow the high-side drive to maintain the gate voltage on the
external MOSFET indefinitely, ensuring so-called 100% PWM
if required. This is a low-current trickle charge pump and is only
operated after a high side has been signaled to turn on. There is a
small amount of bias current drawn from the C terminal to oper-
ate the floating high side circuit (> QGATE
A factor of 20 is a reasonable value, so
QBOOT = CBOOT × VBOOT = QGATE × 20
or
CBOOT = QGATE × 20
VBOOT
where VBOOT is the voltage across the bootstrap capacitor.
VGLA
VGSL
in the bootstrap capacitor, QBOOT, should be much larger than
QGATE, the charge required by the gate:
tDEAD
The voltage drop, ∆V, across the bootstrap capacitor as the MOSFET is being turned on, can be approximated by:
∆V =
Vt0
VGSH
QGATE
CBOOT
so for a factor of 20, ∆V will be 5% of VBOOT.
Figure 8: Minimum Dead Time
Figure 8 shows the typical switching characteristics of a pair of
complementary MOSFETs. Ideally, one MOSFET should start to
turn on just after the other has completely turned off. The point at
which a MOSFET starts to conduct is the threshold voltage Vt0.
The dead time should be long enough to ensure that the gatesource voltage of the MOSFET that is switching off is just below
Vt0 before the gate-source voltage of the MOSFET that is switching on rises to Vt0. This will be the minimum theoretical dead
time, but in practice the dead time will have to be longer than this
to accommodate variations in MOSFET and driver parameters for
process variations and overtemperature.
Bootstrap Capacitor Selection
The A4928 requires a bootstrap capacitor C. To simplify this
description of the bootstrap capacitor selection criteria, generic
naming is used here. So, for example, CBOOT, QBOOT, and VBOOT
refer to the bootstrap capacitor, and QGATE refers to any of the
two associated MOSFETs. CBOOT must be correctly selected to
ensure proper operation of the device—too large and time will be
wasted charging the capacitor, resulting in a limit on the maximum duty cycle and PWM frequency; too small and there can
be a large voltage drop at the time the charge is transferred from
CBOOT to the MOSFET gate.
To keep the voltage drop due to charge sharing small, the charge
The maximum voltage across the bootstrap capacitor under
normal operating conditions is VREG (max). However in some
circumstances the voltage may transiently reach a maximum of
18 V, which is the clamp voltage of the Zener diode between the
C terminal and the S terminal. In most applications with a good
ceramic capacitor, the working voltage can be limited to 16 V.
Bootstrap Charging
It is good practice to ensure the high-side bootstrap capacitor is
completely charged before a high-side PWM cycle is requested.
The time required to charge the capacitor, tCHARGE , in µs, is
approximated by:
tCHARGE =
CBOOT × ∆V
100
where CBOOT is the value of the bootstrap capacitor in nF and ∆V
is the required voltage of the bootstrap capacitor. At power up and
when the drivers have been disabled for a long time, the bootstrap
capacitor can be completely discharged. In this case, ∆V can be
considered to be the full high-side drive voltage, 12 V. Otherwise,
∆V is the amount of voltage dropped during the charge transfer,
which should be 400 mV or less. The capacitor is charged whenever the S terminal is pulled low and current flows from the capacitor connected to the VREG terminal through the internal bootstrap
diode circuit to CBOOT.
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36
A4928
Automotive Half-Bridge MOSFET Driver
VREG Capacitor Selection
The internal reference, VREG, supplies current for the low-side
gate-drive circuits and the charging current for the bootstrap
capacitors. When a low-side MOSFET is turned on, the gatedrive circuit will provide the high transient current to the gate that
is necessary to turn the MOSFET on quickly. This current, which
can be several hundred milliamperes, cannot be provided directly
by the limited output of the VREG regulator but must be supplied
by an external capacitor, CREG, connected between the VREG
terminal and GND
The turn-on current for the high-side MOSFET is similar in value
but is mainly supplied by the bootstrap capacitor. However, the
bootstrap capacitor must then be recharged from CREG through
the VREG terminal. Unfortunately, the bootstrap recharge can
occur a very short time after the low-side turn on occurs. This
means that the value of CREG between VREG and GND should
be high enough to minimize the transient voltage drop on
VREG for the combination of a low-side MOSFET turn on and
a bootstrap capacitor recharge. For block commutation control
(trapezoidal drive), where only one high side and one low side
are switching during each PWM period, a minimum value of 20 ×
CBOOT is reasonable. For sinusoidal control schemes, a minimum
value of 40 × CBOOT is recommended. As the maximum working voltage of CREG will never exceed VREG, the part’s voltage
rating can be as low as 15 V. However, it is recommended that
a capacitor rated to at least twice the maximum working voltage should be used to reduce any impact operating voltage may
have on capacitance value. For best performance, CREG should be
ceramic rather than electrolytic. CREG should be mounted as close
to the VREG terminal as possible.
Current Sense Amplifier Configuration
Amplifier gain, AV, and output offset zero point voltage, VOOS,
may be set to a range of values by the SAG[2:0] and SAO[3:0]
variables respectively as defined in the Current Sense Amplifiers section above. It is important that both values are selected
to ensure the absolute voltage at the CSO output, VCSO, remains
within the amplifier’s dynamic range, VCSOUT, and the dynamic
range of any downstream signal processing circuitry. Allowance
must be made for both positive and negative current flows within
the sense resistor.
With reference to Figure 3, the relationship between phase current IPH, sense resistor value, RS, and differential amplifier input
voltage, VID is given by:
VID = VCSP – VCSM = IPH × RS
The current sense amplifier’s output voltage on CSxO with
respect to the programmed value of output offset on OOS is:
VCSD = (VCSP – VCSM) × AV
The absolute voltage on CSxO with respect to ground is therefore:
VCSO = [(VCSP – VCSM) × AV] + VOOS
If, for example, the following parameter values are assumed:
• RS = 1 mΩ
• IPH = –20A to +40A
• AV = 20 (SAG[2:0] = 0b010)
• VOOS = 1 V (SAO[3:0] = 0b1001)
VID ranges between –20 mV and +40 mV and VCSO between
0.6 V and 1.8 V. VCSO remains within the amplifier dynamic
range, VCSOUT, of 0.3 V to 4.8 V. However, if AV is increased
to 50, VCSO attempts to drive to 0 V and 3.0 V, the amplifier
dynamic range limits are not complied with, and the amplifier
output saturates at its negative limit. This situation could be remedied by reducing AV to 30 (0.4 V < VCSO < 2.2 V) or increasing
VOOS to 1.5 V (0.5 V < VCSO < 3.5 V).
Current Sense Amplifier Output Signals
As defined in Figure 3, the current sense amplifier output signals
on the CSO pins are internally referenced to the voltage on the
OOS pin. Consequently, the signal voltages on CSO should be
measured differentially with respect to OOS (VCSD). Alternatively, the voltages on both CSO (VCSO) and OOS (VOOS) may
be measured consecutively with respect to ground and the values
subtracted to give the required output signal voltages as VCSD =
VCSO – VOOS.
The Input Offset Voltage, VIOS, and the associated drift, ΔVIOS,
multiplied by the selected amplifier gain, AV, represent the offset
and offset drift limits that apply to VCSD. The Output Offset Error,
EVO, and Output Offset Drift, VOOSD, limits apply directly to
VOOS. EVO and VOOSD do not affect current sense output accuracy.
Allegro MicroSystems
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37
A4928
Automotive Half-Bridge MOSFET Driver
INPUT/OUTPUT STRUCTURES
C
16 V
GH
56 V
VBRG
VBB
CP1
CP2
DL
VREG
S
6V
VREG
7.5 V
16 V
56 V
GL
16 V
20 V
56 V
6V
16 V
LSS
Figure 9a: Gate Drive Outputs
Figure 9b: Supplies
VIO
VIO
VIO
BIAS
50 kΩ
2 kΩ
SDI
SCK
RESETn
ENABLE
HS
2 kΩ
STRn
2 kΩ
50 kΩ
50 kΩ
7.5 V
6V
7.5 V
Figure 9c: SDI, SCK Inputs
6V
56 V
Figure 9d: STRn Inputs
Figure 9e: RESETn, ENABLE, HS Inputs
VIO
VIO
BIAS
50 Ω
25 Ω
SDO
7.5 V
Figure 9f: SDO Output
56 V
Figure 9g: DIAG Output
LSn
2 kΩ
170 kΩ
DIAG
56 V
Figure 9h: LSn Input
6V
CSM
CSO
OOS
CSP
6V
7.5 V
Figure 9i: CSM, CSP Inputs
7.5 V
Figure 9j: CSO, OOS Outputs
Allegro MicroSystems
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38
A4928
Automotive Half-Bridge MOSFET Driver
LAYOUT RECOMMENDATIONS
Careful consideration must be given to PCB layout when designing high-frequency, fast-switching, high-current circuits:
• The exposed thermal pad should be connected to the GND
terminal.
• Minimize stray inductance by using short, wide copper tracks
at the drain and source terminals of all power MOSFETs. This
includes load lead connections, the input power bus.This will
minimize voltages induced by fast switching of large load
currents.
• Consider the addition of small (100 nF) ceramic decoupling
capacitor across the source and drain of the power MOSFETs to
limit fast transient voltage spikes caused by track inductance.
• Keep the gate discharge return connections S and LSS as short
as possible. Any inductance on these tracks will cause negative
transitions on the corresponding A4928 terminals, which may
exceed the absolute maximum ratings. If this is likely, consider
the use of clamping diodes to limit the negative excursion on
these terminals with respect to the GND terminal.
• Supply decoupling, typically a 100 nF ceramic capacitor,
should be connected between VBB and GND as close to the
A4928 terminals as possible.
• Check the peak voltage excursion of the transients on the
LSS terminals with reference to the GND terminal using a
close-grounded (“tip & barrel”) probe. If the voltage at any
LSS terminal exceeds the absolute maximum in the datasheet,
add additional clamping and/or capacitance between the LSS
terminal and the GND terminal.
• Gate charge drive paths and gate discharge return paths may
carry a large transient current pulse. Therefore, the traces from
GH, GL, S, and LSS should be as short as possible to reduce
the trace inductance.
• Provide an independent connection between the LSS terminal
to the source of the low-side MOSFET in the power bridge.
Connection of the LSS terminal directly to the GND terminal
is not recommended as this may inject noise into sensitive
functions such as the various voltage monitors.
• A low-cost diode can be placed in the connection to VBB
to provide reverse battery protection. In reverse battery
conditions, it is possible to use the body diodes of the power
MOSFETs to clamp the reverse voltage to approximately
4 V. In this case, the additional diode in the VBB connection
will prevent damage to the A4928 and the VBRG input will
survive the reverse voltage.
• Supply decoupling should be connected between VREG and
GND as close to the A4928 terminals as possible.
Optional reverse
battery protection
VBB
+ Supply
VBRG
VREG
GH
Load
S
A4928
GL
LSS
GND PAD
Controller Supply Ground
RS
Supply
Common
Power Ground
Figure 10: Supply Routing Suggestions
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
39
A4928
Automotive Half-Bridge MOSFET Driver
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MO-153 ADT)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
7.80 ±0.10
4.32 NOM
8º
0º
24
0.20
0.09
B
3 NOM
4.40±0.10
6.40±0.20
A
0.60 ±0.15 1.00 REF
1
2
0.25 BSC
24X
1.20 MAX
0.10 C
0.30
0.19
0.65 BSC
0.45
SEATING PLANE
C
GAUGE PLANE
SEATING
PLANE
0.15
0.00
0.65
1.65
3.00
6.10
A
Terminal #1 mark area
B
Exposed thermal pad (bottom surface); dimensions may vary with device
C
Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
4.32
C
PCB Layout Reference View
Figure 11: Package LP, 24-Lead TSSOP with Exposed Pad
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
40
A4928
Automotive Half-Bridge MOSFET Driver
Revision History
Number
Date
–
January 4, 2018
Initial release
Description
1
January 31, 2019
Minor editorial updates
2
February 21, 2020
Minor editorial updates
Copyright 2020, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
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