A4945GLJTR-T

A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver DESCRIPTION FEATURES AND BENEFITS • 180° sinusoidal drive for low audible noise • High efficiency control algorithm • Sensorless operation • Analog Speed input (A4945) • PWM Speed input (A4949) • Wide supply voltage range • FG speed output • Lock detection • Overcurrent protection • Soft start • Short circuit protection The A4945 and A4949 three phase motor drivers incorporate sinusoidal drive to minimize audible noise and vibration for medium power fans. A Speed input is provided to control motor speed. This allows system cost savings by eliminating an external variable power supply. Alternatively, power supply modulation down to 4 V can be used to adjust motor speed. The A4945 and A4949 are supplied in an 8-pin SOICN with exposed power pad (suffix LJ), and an 8-pin SOICN (suffix L) for wave solder applications. Both packages are lead (Pb) free with 100% matte-tin leadframe plating. PACKAGES: 8-pin SOICN with exposed thermal pad (LJ package) Not to scale 8-pin SOICN (L package) Functional Block Diagram VSUPPLY IDC Protection VBB VREG TSD VREF VBB 50 kΩ PWM Speed Demand Input Duty Measure 100 kΩ Speed Demand IDC Sinusoidal Drive Wave Shape 6 Gate Drive CVREF 0.1 µF X5R 10 V CVBB 10 µF OUTA OUTB M OUTC Startup Logic 30 kHz PWM OSC Duty Cycle FG GND OUTA Position Detect OUTB OUTC A4949 device shown A4945-DS, Rev. 5 MCO-0000480 PAD LJ package only August 1, 2019 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver SELECTION GUIDE Part Number Operating Ambient Temperature Range TA, (°C) Speed Input A4945GLJTR-T [1] A4945GLTR-T [1] –40 to 105 Analog –40 to 125 A4945KLJTR-T [1][2] A4949GLJTR-T [1] A4949GLJTR-6-T [3][4] A4949GLTR-T [1] –40 to 105 PWM A4949KLJTR-T [1][2] –40 to 125 A4949KLJTR-6-T [2][3][4] Package 8-pin SOICN Packing Exposed thermal pad 8-pin SOICN – 8-pin SOICN Exposed thermal pad 8-pin SOICN Exposed thermal pad 8-pin SOICN – 8-pin SOICN Exposed thermal pad 3000 pieces per 13-in. reel [1] Startup Current Ramp: Slow ramp – device takes a 50 mA current step every 128 ms. BEMF Hysteresis at Startup: 100 mV. See Figure 4. The A4945KLJTR-T, A4949KLJTR-T, and A4949KLJTR-6-T part variants are in production but have been determined to be LAST TIME BUY. This classification indicates that the product is obsolete and notice has been given. Sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Date of status change: July 1, 2019. Deadline for receipt of LAST TIME BUY orders: December 27, 2019. For existing customer transition, and for new customers or new applications, refer to A5947KLPTR-T. [3] Contact Allegro sales for availability of this package option. [4] Startup Current Ramp: Fast ramp – device takes a 50 mA current step every 31 ms. BEMF Hysteresis at Startup: 40 mV. See Figure 4. [2] ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Notes Rating Unit Supply Voltage VBB Input Logic Voltage Range VIN PWM and VSP pins Logic Output VFG FG pin 14 V Logic Output Current IFG FG pin 10 mA Load Output Current IOUT Internally limited IOCL(max) A G temperature range –40 to 105 °C K temperature range 18 V –0.3 to 6 V Operating Ambient Temperature TA –40 to 125 °C Maximum Junction Temperature TJ(max) 150 °C Tstg –55 to 150 °C Storage Temperature THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Package Thermal Resistance Symbol RθJA Test Conditions Value Unit L package, single-sided PCB with copper limited to mounting lands 140 °C/W LJ package, 2-sided PCB with 0.8 in2 copper each side 62 °C/W Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver Pinout Diagrams L and LJ packages GND 1 OUTA 2 VBB 3 A4945 PAD (LJ package) VSP 4 8 OUTB 7 OUTC 6 FG 5 VREF Terminal List Table Number GND 1 OUTA 2 VBB 3 PWM 4 PAD (LJ package) Function 1 GND Ground 2 OUTA Motor terminal 3 VBB Input supply VSP Speed (analog) logic input (A4945) PWM Speed (PWM) logic input (A4949) VREF Analog output 4 5 A4949 Name 6 FG 7 OUTC 7 OUTC Motor terminal 6 FG 8 OUTB Motor terminal – PAD 8 OUTB 5 VREF Speed output signal Exposed thermal pad (LJ package) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver ELECTRICAL CHARACTERISTICS: Unless otherwise specified, G version*: Valid at TA = 25°C, VBB = 4 to 18 V K version*: Valid at TA = –40°C to 125°C, VBB = 4 to 18 V Characteristic Symbol Test Conditions Min. Typ. Max. Unit GENERAL VBB Supply Current Total Driver RDS(on) (Sink + Source) Reference Voltage (VREF pin) IBB RDS(on) VIN = 3 V – 10 15 mA IOUT = 1 A, TJ = 25°C, VBB = 12 V – 1.1 1.4 Ω – 1.5 1.8 Ω 3.2 3.3 3.4 V IOUT = 1 A, TJ = 25°C, VBB = 4 V VREF IFG = 5 mA Output Saturation Voltage (FG Pin) VFG(sat) IFG = 5 mA – – 0.3 V FG Output Leakage IFG(LKG) VFG = 14 V – – 1 µA Motor PWM Frequency fOUTPWM 28 30 32 kHz 21 33 45 µA INPUT LOGIC (A4945 VSP Pin or A4949 PWM Pin) Input Current IIN VIN = 3 V (RIN = 100 kΩ pulldown) Logic Input (Low Level) VIL 0 – 0.8 V Logic Input (High Level) VIH 2 – 5.5 V VIHYS 200 300 600 mV RIN – 100 – kΩ VON 0.45 0.9 1.2 V Logic Input Hysteresis Input Pulldown Resistance A4945 SPEED INPUT (VSP Pin) VSP On-Threshold Level VSP On-Time VSP Disable Threshold tON CVREF = 1 µF VTHOFF 100 – – µs 194 228 264 mV VSP Accuracy ERRVSP – ±6 – LSB VSP Maximum Level VSP(MAX) 2.95 3 3.05 V PWM On Threshold DON 9.5 10 10.5 % PWM Off Threshold DOFF 7 7.5 8 % PWM Input Frequency Range fPWM 0.1 – 100 kHz – 3.85 3.98 V 150 300 450 mV A4949 SPEED INPUT (PWM Pin) PROTECTION VBB Undervoltage Lockout (UVLO) VBBUVLO VBB UVLO Hysteresis VBBUVHYS VBB rising Lock Protection tOFF 7 8 9 s Overcurrent Limiting (OCL) IOCL 1.4 1.6 1.8 A 150 165 180 °C – 20 – °C Thermal Shutdown Temperature (TSD) Thermal Shutdown Hysteresis TJTSD TJTSDHYS Temperature rising Recovery = TJTSD – TJTSDHYS *Specified limits are tested at a single temperature and assured across the operating temperature range by design and characterization. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver FUNCTIONAL DESCRIPTION The A4945/A4949 targets fan applications, meeting application design objectives of low audible noise, minimal vibration, and high efficiency. The Allegro proprietary control algorithm results in a sinusoidal current waveform that adapts to a variety of motor characteristics, in order to dynamically optimize efficiency across a wide range of speeds. The A4945/A4949 trapezoidal startup method does not require any external components and automatically switches to sinusoidal operation as the motor is accelerating up to operating speed. Speed Control The speed of the fan can be controlled by: voltage mode (control of power supply amplitude), variable duty cycle PWM input (A4949 only), or via an adjustable analog input (A4945 only). Use of the PWM or analog input allows overall system cost savings by eliminating the requirement for an external variable power supply. Voltage mode operation allows the IC to fit into legacy systems, achieving operation down to 4 V. The Speed input, analog voltage for the A4945 or PWM duty cycle for the A4949, is measured and converted to a 9-bit number. This 9-bit speed demand value is applied to an internal PWM generator function to create the modulation profile. The modulation profile is applied to the three motor outputs, with a 120-degree phase relationship, to create the sinusoidal current waveform as shown in Figure 1. A BEMF detection window is opened on the phase A modulation profile in order to measure the rotor position, so as to define the modulation timing. The control system maintains the window at a small level in order to minimize the disturbance and to approximate the ideal sinusoidal current waveform as much as possible. A4945 – VSP Pin Analog Input. An internal A-to-D convertor translates the input voltage to a demand value to control speed of the fan (Figure 2). The motor drive will be disabled if the VSP pin voltage is lower than VTHOFF . Upon startup, VIN must exceed VTHON for tON . The tON delay is required to allow internal reference supply and analog circuits to properly power-up. After this short delay, VSP can be adjusted below VTHOFF to allow full scale operation (7.5% to 100%). 100.0 FG Speed Demand (%) Motor Detection Output OUTA Sinusoidal Drive Modulation Profile OUTB OUTC 25.0 Motor Terminal PWM OUTA iC Ideal Sinusoidal Current Waveforms iB iA Figure 1: Sinusoidal PWM Output Generation 7.5 Disabled VTHOFF VTHON 1.5 3.0 VSP (V) Figure 2: A4945 Analog Speed Input Characteristic Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver A4949 – PWM Pin Duty Cycle Input. A duty cycle measurement There is an internal pulldown resistor (100 kΩ) on the PWM pin that turns the motor off if the input signal is disconnected. If 100% speed demand is required, such as for an open PWM condition, connect a 50 kΩ pullup resistor to the VBB pin. Power Supply Modulation. Speed can be controlled simply by varying the power supply voltage. To allow this function, insert a 50 kΩ pullup resistor from the VSP pin (A4945) or the PWM pin (A4949) to the VBB pin. Motor driving will be enabled and disabled at the VBB undervoltage lockout rising and falling thresholds. 100.0[511] Speed Demand (%[bit]) circuit converts the applied duty cycle to a demand value (9-bit resolution) to control speed of the fan. The motor drive will be enabled if the duty cycle is greater than DON (10% (typ)) (Figure 3). The PWM input is filtered to prevent spurious noise from turning the IC on or off unexpectedly. 25.0[127] 10.0[51] 7.5[39] Disabled DOFF DON 50 100 Duty Cycle (%) Figure 3: A4949 PWM Speed Input Characteristic Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver Soft Start A soft start feature is integrated, both to minimize demand on the power supply at startup, and to smoothly initiate motor rotation and ramp up to speed. Soft start ramps both the speed demand (duty cycle) and current limit as shown in Figure 4. Protection Protection features include: lock detection with restart, overcurrent limit, motor output short circuit detection, supply undervoltage monitor, and thermal shutdown. Lock Detect Speed is monitored to determine if the rotor is locked. If a lock condition is detected, the IC will be disabled for tOFF before an auto-restart is attempted. FG Open drain output provides speed information to the system. FG changes state one period per electrical revolution of the motor (as shown in Figure 1). Current Limit Load current is monitored on the high-side MOS- FET. If the current has reached IOCL , the source drivers will turn off for the remaining time of the PWM cycle. Fast Ramp 1600 1600 1200 1200 IOCL (mA) 800 Typical peak motor current 400 800 Typical peak motor current 400 Speed Demand (%) Time (ms) 1024 768 512 64 128 4096 3072 2048 1024 512 200 100 256 200 100 256 IOCL (mA) Slow Ramp Time (ms) Trapezoidal Drive Sinusoidal Drive 100 Target B 50 Target A Time Figure 4: A4945 and A4949 Startup 1. Target A represents situation where the external duty cycle applied is less than 50% at startup. A minimum level of 50% demand is applied internally to ensure the motor will accelerate in reasonable time. 500 ms after the IC has switched from trapezoidal mode to sinusoidal mode, demand ramps down at a rate of 410 ms for every 10% demand. 2. Target B represents the external duty cycle applied at greater than 50% at startup. In this case, the internally applied duty cycle stays constant. 3. Drive mode switches from trapezoidal mode to sinusoidal mode after the motor approaches startup target speed (50% or greater). The time required to switch-over depends on motor characteristics and the demand applied at startup. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver APPLICATION INFORMATION A4949 LJ Package Motor Terminal GND OUTB Motor Terminal OUTA OUTC Motor Terminal VBB FG PWM VREF D1 12 V ZD1 100 Hz to 100 kHz PWM In 10% to 100% duty cycle CVBB RPU RFG FG Output Signal CVREF RPWM Typical Application Circuit Name Suggested Value CVREF 0.1 µF/X5R/10 V Comment CVBB 4.7 to 47 µF RFG 20 kΩ D1 Not installed May be required to isolate motor from system or for reverse polarity protection ZD1 Not Installed Optional – TVS to limit maximum VBB due to transients resulting from motor generation or power line. Suggested to clamp below 18 V (example: Fairchild SMBJ14A). Typically required if blocking diode D1 is used. RPWM 1 kΩ Optional – If the PWM or VSP pin is wired to a connector, RPWM will isolate the IC pin from noise or overvoltage transients. RPU 50 kΩ Optional – If the application requires maximum speed when a PWM pin open circuit occurs, then this pullup resistor to VBB is required. Do not pullup to VREF . Required – ceramic capacitor Power supply stabilization; electrolytic or ceramic can be used Optional – Pullup resistor for speed feedback Layout Notes: 1. Add thermal vias to exposed pad area. Connect to ground planes on top and bottom of PCB. 2. Place CVREF and CVBB as close as possible to the IC. L Package Board LJ Package Board Via Layout for Thermal Dissipation Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver INPUT/OUTPUT PIN STRUCTURES VBB VBB VBB OUTA/B/C 21V GND VBB 7. 5 kΩ PWM 21V 100 kΩ VREF 6. 5V VSP FG 21V 60 kΩ 40 kΩ 16V 6.5V Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver Package L, 8-Pin SOICN 4.90 ±0.10 0.65 8° 0° 8 3.90 ±0.10 1 6.00 ±0.20 2 0.25 BSC 8X SEATING PLANE 0.10 C 0.51 0.31 1.27 BSC 5.60 1.04 REF 1.27 0.40 SEATING PLANE GAUGE PLANE Branded Face 1.27 1.75 0.25 0.17 A 8 1 2 B PCB Layout Reference View C 1.75 MAX 0.25 0.10 For Reference Only; not for tooling use (reference MS-012AA) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver Package LJ, 8-Pin SOICN with Exposed Thermal Pad 4.90 ±0.10 0.65 8° 0° 8 B A 1 3.90 ±0.10 6.00 ±0.20 0.25 BSC SEATING PLANE GAUGE PLANE Branded Face SEATING PLANE 0.10 C 1.27 BSC 1 1.27 0.40 3.30 NOM 0.51 0.31 2.41 1.04 REF 2 8X C 5.60 2 3.30 C PCB Layout Reference View For Reference Only; not for tooling use (reference MS-012BA) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 1.70 MAX 0.15 0.00 1.27 1.75 0.25 0.17 2.41 NOM 8 A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A4945 and A4949 Three Phase Sensorless Sinusoidal Fan Driver Revision History Number Date Description 1 May 6, 2014 2 January 30, 2015 Added -6 variant Added KLJ-6-T variant 3 July 25, 2018 Minor editorial updates 4 February 1, 2019 Updated K temperature variant product status to Pre-End-of-Life 5 August 1, 2019 Updated K temperature variant product status to Last Time Buy Copyright 2019, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12