A4954ELPTR-T

A4954 Dual Full-Bridge DMOS PWM Motor Driver FEATURES AND BENEFITS DESCRIPTION Designed for pulse width modulated (PWM) control of two DC motors, the A4954 is capable of peak output currents to ±2 A and operating voltages to 40 V. • Low RDS(on) outputs • Overcurrent protection (OCP) □□ Motor short protection □□ Motor lead short to ground protection □□ Motor lead short to battery protection • Low Power Standby mode • Adjustable PWM current limit • Synchronous rectification • Internal undervoltage lockout (UVLO) • Crossover-current protection Input terminals are provided for use in controlling the speed and direction of a DC motor with externally applied PWM control signals. Internal synchronous rectification control circuitry is provided to lower power dissipation during PWM operation. Internal circuit protection includes overcurrent protection, motor lead short to ground or supply, thermal shutdown with hysteresis, undervoltage monitoring of VBB, and crossovercurrent protection. Package: 16-pin TSSOP with exposed thermal pad (suffix LP) The A4954 is provided in a low-profile 16-pin TSSOP package with exposed thermal pad (suffix LP) that is lead (Pb) free, with 100% matte tin leadframe plating. Not to scale Load Supply OSC IN1 Charge Pump VBB Control Logic Disable TSD UVLO IN2 OUT1 OUT2 7V GND LSS12 VREF12 ÷ 10 (Optional) OSC IN3 Charge Pump VBB Control Logic Disable IN4 TSD UVLO OUT3 OUT4 7V GND LSS34 VREF34 ÷ 10 (Optional) Figure 1: Functional Block Diagram A4954-DS, Rev. 7 MCO-0000811 March 27, 2020 A4954 Dual Full-Bridge DMOS PWM Motor Driver SPECIFICATIONS Table 1: Selection Guide Part Number A4954ELPTR-T Packing 4000 pieces per 13-in. reel Ambient Operating Temperature –40ºC to 85ºC Table 2: Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit Load Supply Voltage VBB 40 V Logic Input Voltage Range VIN –0.3 to 6 V VREF Input Voltage Range VREF –0.3 to 6 V Sense Voltage (LSSx pin) VS –0.5 to 0.5 V Motor Outputs Voltage VOUT –2 to 42 V Output Current IOUT Duty cycle = 100% 2 A Transient Output Current iOUT TW < 500 ns 5 A Operating Temperature Range Maximum Junction Temperature Storage Temperature Range TA –40 to 85 °C TJ(max) 150 °C Tstg –55 to 150 °C Table 3: Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Package Thermal Resistance RθJA Test Conditions* Value Unit On 2-layer PCB with 3.8 in2. exposed 2-oz. copper each side 43 ºC/W On 4-layer PCB based on JEDEC standard 34 ºC/W *Additional thermal information available on the Allegro website. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A4954 Dual Full-Bridge DMOS PWM Motor Driver 16 VBB GND 1 15 OUT4 VREF34 2 14 LSS34 IN3 3 IN4 4 IN2 5 PAD IN1 6 VREF12 7 GND 8 13 OUT3 12 OUT2 11 LSS12 10 OUT1 9 VBB Figure 2: Package LJ, 8-Pin SOIC Pin-outs Table 4: Terminal List Table Number Name 1 GND Function 2 VREF34 3 IN3 Logic input 3 4 IN4 Logic input 4 5 IN2 Logic input 2 6 IN1 Logic input 1 7 VREF12 8 GND Ground 9 VBB Load supply voltage 10 OUT1 DMOS full bridge output 1 11 LSS12 Power return – sense resistor connection for bridge 1-2 12 OUT2 DMOS full bridge output 2 13 OUT3 DMOS full bridge output 3 14 LSS34 Power return – sense resistor connection for bridge 3-4 15 OUT4 DMOS full bridge output 4 16 VBB Load supply voltage – PAD Exposed pad for enhanced thermal dissipation Ground Analog input for bridge 3-4 Analog input for bridge 1-2 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 A4954 Dual Full-Bridge DMOS PWM Motor Driver Table 5: ELECTRICAL CHARACTERISTICS; Valid at TJ = 25°C, VBB = 8 to 40 V, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit 8 – 40 V General Load Supply Voltage Range VBB RDS(on) Sink + Source Total RDS(on) Load Supply Current IBB Body Diode Forward Voltage Vf IOUT = |1.5 A|, TJ = 25°C – 0.8 1.12 Ω IOUT = |1.5 A|, TJ = 150°C – 1.28 1.8 Ω fPWM < 30 kHz – 10 – mA Low Power Standby mode – – 10 µA Source diode, If = –1.5 A – – 1.5 V Sink diode, If = 1.5 A – – 1.5 V Logic Inputs Logic Input Voltage Range VIN(1) 2.0 – – V VIN(0) – – 0.8 V VIN(STANDBY) Low Power Standby mode – – 0.4 V IIN(1) VIN = 2.0 V – 40 100 µA IIN(0) VIN = 0.8 V – 16 40 µA – 50 – kΩ VHYS – 250 550 mV Crossover Delay tCOD 50 – 500 ns VREF Input Voltage Range VREF Logic Input Current Logic Input Pull-Down Resistance Input Hysteresis RLOGIC(PD) VIN = 0 V = IN1 = IN2 = IN3 = IN4 RR Timing Current Gain Blank Time Constant Off-time A V 0 – 5 V VREF / ISS , VREF = 5 V 9.5 – 10.5 V/V VREF / ISS , VREF = 2.5 V 9.0 – 10.0 V/V VREF / ISS , VREF = 1 V 8.0 – 10.0 V/V tBLANK 2 3 4 µs toff 16 25 34 µs – 1 1.5 ms – – 30 µs 7 7.5 7.95 V mV Standby Timer tst Power-Up Delay tpu IN1 = IN2 = IN3 = IN4 < VIN(STANDBY) Protection Circuits UVLO Enable Threshold UVLO Hysteresis Thermal Shutdown Temperature Thermal Shutdown Hysteresis VBBUVLO VBB increasing VBBUVLOhys TJTSD TTSDhys – 500 – Temperature increasing – 160 – °C Recovery = TJTSD – TTSDhys – 15 – °C Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 A4954 Dual Full-Bridge DMOS PWM Motor Driver CHARACTERISTIC PERFORMANCE VIN(1) IN1, IN3 GND VIN(1) IN2, IN4 GND +IREG IOUTx 0A -IREG Forward/ Fast Decay Reverse/ Fast Decay Forward/ Slow Decay Reverse/ Slow Decay Figure 3: PWM Control Timing Diagram Table 6: PWM Control Truth Table IN1, IN3 IN2, IN4 10×VS > VREF OUT1, OUT3 OUT2, OUT4 0 1 1 0 Function False L H Reverse False H L Forward 0 1 True H/L L Chop (mixed decay), reverse 1 0 True L H/L Chop (mixed decay), forward 1 1 False L L Brake (slow decay) 0 0 False Z Z Coast, enters Low Power Standby mode after 1 ms Note: Z indicates high impedance. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 A4954 Dual Full-Bridge DMOS PWM Motor Driver FUNCTIONAL DESCRIPTION Device Operation The A4954 is designed to operate two DC motors. The output drivers are all low-RDS(on) , N-channel DMOS drivers that feature internal synchronous rectification to reduce power dissipation. The current in each of the two output full bridges is regulated with fixed off-time pulse width modulated (PWM) control circuitry. The IN1-IN2 and IN3-IN4 inputs allow two-wire control for each bridge. Protection circuitry includes internal thermal shutdown, and protection against shorted loads, or against output shorts to ground or supply. Undervoltage lockout prevents damage by keeping the outputs off until the driver has enough voltage to operate normally. Standby Mode Low Power Standby mode is activated when all four input (INx) pins are low for longer than 1 ms. Low Power Standby mode disables most of the internal circuitry, including the charge pump and the regulator. When the A4954 is coming out of standby mode, the charge pump should be allowed to reach its regulated voltage (a maximum delay of 30 µs) before any PWM commands are issued to the device. Internal PWM Current Control Initially, a diagonal pair of source and sink FET outputs are enabled and current flows through the motor winding and the optional external current sense resistor, RSx . When the voltage across RSx equals the comparator trip value, then the current sense comparator resets the PWM latch. The latch then turns off the sink and source FETs (Mixed Decay mode). VREF The maximum value of current limiting is set by the selection of RSx and the voltage at the VREFx pin in each channel. The transconductance function is approximated by the maximum value of current limiting, ITripMAX (A), which is set by: ITripMAX = VREF AV RS where VREF is the input voltage on the VREFx pin (V) and RS is the resistance of the sense resistor (Ω) on the corresponding LSSx terminal. Overcurrent Protection A current monitor will protect the IC from damage due to output shorts. If a short is detected, the IC will latch the fault and disable the outputs. Each channel has independent OCP protection. The fault latch can only be cleared by coming out of Low Power Standby mode or by cycling the power to VBB. During OCP events, Absolute Maximum Ratings may be exceeded for a short period of time before the device latches. Shutdown If the die temperature increases to approximately 160°C, the full bridge outputs will be disabled until the internal temperature falls below a hysteresis, TTSDhys , of 15°C. Internal UVLO is present on VBB to prevent the output drivers from turning-on below the UVLO threshold. Braking The braking function is implemented by driving the device in Slow Decay mode, which is done by applying a logic high to both inputs of both channels, after a bridge-enable Chop command (see PWM Control Truth Table). Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts-out the motor-generated BEMF, as long as the Chop command is asserted. The maximum current can be approximated by VBEMF / RL . Care should be taken to ensure that the maximum ratings of the device are not exceeded in worse case braking situations: high speed and high-inertia loads. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 A4954 Dual Full-Bridge DMOS PWM Motor Driver Synchronous Rectification Mixed Decay Operation When a PWM off-cycle is triggered by an internal fixed off-time cycle, load current will recirculate. The A4954 synchronous rectification feature turns-on the appropriate DMOSFETs during the current decay, and effectively shorts out the body diodes with the low RDS(on) driver. This significantly lowers power dissipation. When a zero current level is detected, synchronous rectification is turned off to prevent reversal of the load current. The bridges operate in Mixed Decay mode. Referring to the lower panel of the figure below, as the trip point is reached, the device goes into fast decay mode for 50% of the fixed off-time period. After this fast decay portion the device switches to slow decay mode for the remainder of the off-time. During transitions from fast decay to slow decay, the drivers are forced off for the Crossover Delay, tCOD . This feature is added to prevent shootthrough in the bridge. During this “dead time” portion, synchronous rectification is not active, and the device operates in fast decay and slow decay only. VPHASE + IOUT See Enlargement A 0 – Enlargement A Fixed Off-Time, toff = 25 µs 0.50 × toff 0.50 × toff ITrip IOUT Fast Decay tCOD tCOD Slow Decay tCOD Figure 4: Mixed Decay Mode Operation Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A4954 Dual Full-Bridge DMOS PWM Motor Driver APPLICATION INFORMATION Sense Pins (LSSx) In order to use PWM current control, a low-value resistor is placed between the LSSx pin and ground for current sensing purposes. To minimize ground-trace IR drops in sensing the output current level, the current sensing resistor should have an independent ground return to the star ground point. This trace should be as short as possible. For low-value sense resistors, the IR drops in the PCB can be significant, and should be taken into account. When selecting a value for the sense resistor be sure not to exceed the maximum voltage on the LSSx pin of ±500 mV at maximum load. During overcurrent events, this rating may be exceeded for short durations. Ground A star ground should be located as close to the A4954 as possible. GND The copper ground plane directly under the exposed thermal pad of the device makes a good location for the star ground point. The exposed pad can be connected to ground for this purpose. Layout The PCB should have a thick ground plane. For optimum electrical and thermal performance, the A4954 must be soldered directly onto the board. On the underside of the A4954 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad must be soldered directly to an exposed surface on the PCB in order to achieve optimal thermal conduction. Thermal vias are used to transfer heat to other layers of the PCB. The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 μF) in parallel with a lower valued ceramic capacitor placed as close as practicable to the device. GND OUT4 RS12 OUT3 Figure 6: Thermal Vias OUT2 A4954 RS34 C1 1 GND OUT1 VBB OUT4 VREF34 C2 IN4 BULK CAPACITANCE GND LSS34 IN3 VBB GND PAD OUT3 IN2 OUT2 IN1 LSS12 VREF12 OUT1 GND RS34 RS12 VBB VBB C1 Figure 5: PCB Layout C2 Figure 7: Typical Application Table 7: Bill of Materials Item Reference Value Units Description 1 RS12, RS34 0.25 (for VREF = 5 V, IOUT = 2 A) Ω 2512, 1 W, 1% or better, carbon film chip resistor 2 C1 0.22 µF X5R minimum, 50 V or greater 3 C2 100 µF Electrolytic, 50 V or greater Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A4954 Dual Full-Bridge DMOS PWM Motor Driver Package Outline Drawing For Reference Only – Not for Tooling Use (Reference MO-153 ABT) Dimensions in millimeters. NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 0.65 0.45 8º 0º 5.00 ±0.10 16 16 0.20 0.09 1.70 B 3 NOM 4.40 ±0.10 3.00 6.40 ±0.20 A 6.10 0.60 ±0.15 1.00 REF 1 2 3 NOM 1 0.25 BSC 2 Branded Face 3.00 SEATING PLANE C 16X 0.10 SEATING PLANE C 0.30 0.19 GAUGE PLANE C PCB Layout Reference View 1.20 MAX 0.65 BSC NNNNNNN YYWW LLLL 0.15 0.00 A Terminal #1 mark area B Exposed thermal pad (bottom surface); dimensions may vary with device C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D 1 D Standard Branding Reference View N = Device part number = Supplier emblem Y = Last two digits of year of manufacture W = Week of manufacture L = Characters 5-8 of lot number Branding scale and appearance at supplier discretion Figure 8: Package LP, 16-Pin TSSOP with exposed thermal pad Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A4954 Dual Full-Bridge DMOS PWM Motor Driver Revision History Number Date Description 5 July 17, 2013 Update standby mode description 6 June 4, 2014 Added K Variant 7 March 27, 2020 Removed K variant; minor editorial updates Copyright 2020, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10