A4964KJPTR-T

A4964 2 Sensorless Sinusoidal Drive BLDC Controller - FEATURES AND BENEFITS DESCRIPTION • • • • • • • • • • • • • • • • The A4964 is a three-phase, sensorless, brushless DC (BLDC) motor controller for use with external N-channel power MOSFETs and is specifically designed for automotive applications. It is designed to provide the motor control functions in a system where a small microcontroller provides the communication interface to a central ECU and intelligent fault and status handling. The A4964 provides the supply and watchdog for the microcontroller and the high-voltage interfaces between the microcontroller and the central ECU and ignition switch. The A4964 can also operate as an independent singlechip remote motor controller. Three-phase sensorless BLDC motor control FET driver Three-phase sinusoidal drive with soft start Sensorless start-up and commutation Windmill detection and synchronization Bootstrap gate drive for N-channel MOSFET bridge 5.5 to 50 V supply range SPI-compatible interface Programmable control modes: speed, voltage, current Peak current limiting Control via SPI or PWM Programmable gate drive for slew rate control LIN / PWM physical interface with wake Logic supply regulator with current limit MCU watchdog and reset Ignition switch interface Diagnostics, status, current, and speed feedback APPLICATIONS • Automotive fuel, oil, and urea pumps • Automotive fans and blowers The motor is driven using 3-phase sinusoidal current drive where phase commutation is determined, without the need for independent position sensors, by monitoring the motor back-EMF (bemf). The sensorless start-up scheme includes forward and reverse pre-rotation (windmill) detection and synchronization, and allows the A4964 to operate over a wide range of motor and load combinations. The A4964 can operate with duty cycle (voltage) control, current (torque limit) control, and closed-loop speed control. Control mode, operating mode, and control parameters are programmed through an SPI-compatible serial interface. PACKAGES 36-terminal eQFN (suffix EV) A single current sense amplifier provides peak current limiting and average current measurement through the serial interface. Integrated diagnostics provide indication of undervoltage, overtemperature, and power bridge faults and can protect the power switches under most short-circuit conditions. 32-lead eQFP (suffix JP) The A4964 is provided in a 36-terminal QFN and a 32-lead QFP, both with exposed thermal pad. Not to scale VBAT VBAT IG IG LIN DIAG VLR VLR LIN MCU PWM DIAG A4964 3-Phase Motor A4964 3-Phase Motor WDOG MRSTn SPI Figure 1: Typical Applications A4964-DS, Rev. 2 MCO-0000214 December 4, 2017 A4964 Sensorless Sinusoidal Drive BLDC Controller SELECTION GUIDE Part Number Packing Package A4964KEVTR-J 1500 pieces per 13 in. reel 6 mm × 6 mm, 1.0 mm max. height, wettable flank 36-lead QFN with exposed thermal pad A4964KJPTR-T 1500 pieces per 13 in. reel 7 mm × 7 mm, 1.6 mm max. height 32-lead QFP with exposed thermal pad ABSOLUTE MAXIMUM RATINGS [1] Characteristic Supply Voltage Symbol VBB Notes Rating Unit VBB –0.3 to 50 V VREG VREG –0.3 to 16 V Charge Pump Capacitor Low Terminals VCP CP1 –0.3 to 16 V Charge Pump Capacitor High Terminal VCP2 CP2 VCP1 – 0.3 to VREG + 0.3 V Logic Regulator Reference VLR VLR –0.3 to 6 V Battery Compliant Inputs VIG IG –0.3 to 50 V LIN Bus Interface VLIN LIN –40 to 50 V Pumped Regulator Terminal Logic Inputs STRn, SCK, SDI, WDOG, LTX –0.3 to 6 V Logic Outputs SDO, MRSTn, LRX –0.3 to 6 V Logic Output DIAG –0.3 to 50 V VBRG VBRG –5 to 55 V Bootstrap Supply Terminals VCX CA, CB, CC –0.3 to VREG + 50 V High-Side Gate Drive Output Terminals VGHX GHA, GHB, GHC VCX – 16 to VCX + 0.3 V VCX – 16 to VCX + 0.3 V VREG – 16 to 18 V Bridge Drain Monitor Terminals Motor Phase Terminals VSX SA, SB, SC Low-Side Gate Drive Output Terminals VGLX GLA, GLB, GLC Sense Amplifier Inputs VCSI CSP, CSM Ambient Operating Temperature Range Maximum Continuous Junction Temperature Storage Temperature Range [1] –4 to 6 V TA –40 to 150 °C TJ(max) 165 °C Tstg –55 to 150 °C With respect to GND. THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Package Thermal Resistance [2] Additional Symbol RθJA Test Conditions [2] Value Unit EV package, 4-layer PCB based on JEDEC standard 27 °C/W JP package, 4-layer PCB based on JEDEC standard 23 °C/W JP package, 2-layer PCB with 3 in.2 copper each side 44 °C/W thermal information available on the Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4964 Sensorless Sinusoidal Drive BLDC Controller Table of Contents Features and Benefits 1 Applications 1 Packages 1 Description 1 Typical Applications 1 Selection Guide 2 Absolute Maximum Ratings 2 Thermal Characteristics 2 Pinout Diagrams and Terminal List Tables 4 Functional Block Diagram 6 Electrical Characteristics 7 Supply and Reference 7 Gate Output Drive 8 Logic Inputs and Outputs 9 Serial Interface – Timing Parameters 10 LIN/PWM Interface Parameters 11 Current Limiting 13 Data Acquisition System 13 Motor Startup Parameters 14 Motor Run Parameters 14 Watchdog – Timing Parameters 14 NVM – Programming Parameters 15 Diagnostics and Protection 15 VDS Fault Timing Diagrams 16 Phase Signal Diagrams 17 Modulation and Overmodulation Examples 20 PWM Mode Diagrams 21 Functional Description 22 Input and Output Terminal Functions 22 Supplies and Regulators 23 Main Power Supply 23 VLR Regulator 23 Pump Regulator 24 Operating Modes 24 SPI Mode 24 Stand-Alone Mode 24 Low-Power Sleep State 24 Microcontroller Reset and Watchdog 26 Microcontroller Reset 26 Microcontroller Watchdog 26 LIN Physical Interface 27 Motor Drive 28 Gate Drive 28 Gate Drive Voltage Regulation 28 Low-Side Gate Drive 28 High-Side Gate Drive 29 Bootstrap Supply 29 Bootstrap Charge Management 29 Gate Drive Passive Pull-Down 29 Gate Drive Control 29 Dead Time 32 PWM Frequency 32 ∆PWM Frequency Dither 33 Current Limit 33 Current Comparator Blanking 34 Motor Commutation Control 34 PWM Generator 34 Overmodulation 35 Rotor Position Sensing Using Motor BEMF 35 36 Phase Advance Commutation Controller Tuning 36 Motor Startup 37 Alignment 37 Ramp 37 Coast 38 39 Start with Pre-Rotation (Windmilling) Motor Control Modes 39 PWM Control Input 40 Open-Loop Speed (Voltage) Control 41 Closed-Loop Torque (Current) Control 42 Closed-Loop Speed Control 42 Speed Control Dynamic Response 43 Supply Voltage Compensation 44 Diagnostics 46 Serial Status Register 46 Diagnostic Register 46 46 DIAG Output DIAG Fault Waveforms 47 Fault Action 47 49 Fault Masks Chip-Level Diagnostics 49 49 Chip Fault State: Power-On Reset Chip Fault State: Overtemperature 49 Chip Fault State: VBB Undervoltage 50 50 Chip Fault State: VREG Undervoltage Chip Fault State: VLR Undervoltage 50 50 Chip Fault State: VPP Undervoltage Chip Fault State: Serial Error 50 Chip Fault State: System Error 51 51 Motor Fault: Loss of Synchronization MOSFET Fault Detection 52 52 MOSFET Fault Qualification Bootstrap Undervoltage Fault 53 System Clock Verification 53 Serial Interface 54 Serial Registers Definition 54 Configuration and Control Registers Status and Diagnostic Registers Readback Register 56 59 60 Non-Volatile Memory 61 Serial Register Reference 62 Applications Information 79 Dead Time Selection 79 Bootstrap Capacitor Selection 79 Bootstrap Charging 79 VREF Capacitor Selection 80 Braking 80 Current Sense Amplifier 80 Single-Wire PWM Diagnostic Feedback 81 Systems with Negative Voltage Requirements 81 Systems with Low-Level Input Requirements 81 Layout Recommendations 82 Input / Output Structures 83 Package Outline Drawings 84 Appendix A: Fault Response Actions 86 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4964 Sensorless Sinusoidal Drive BLDC Controller VBRG IG VBB CP1 CP2 VREG CA SA 32 31 30 29 28 27 26 25 PINOUT DIAGRAMS AND TERMINAL LIST TABLES DIAG 1 24 GHA VLR 2 23 GLA STRn 3 22 CB SCK 4 21 SB SDI 5 20 GHB WDOG 6 19 GLB SDO 7 18 CC MRSTn 8 17 SC 14 15 16 GND GLC GHC LIN 13 12 LTX 11 LRX 10 CSP CSM 9 PAD 32-lead eQFP (suffix JP) Terminal List Table Name Number Name Number CA 26 Phase A Bootstrap Capacitor Function LIN 13 LIN Bus Connection Function CB 22 Phase B Bootstrap Capacitor LTX 12 LIN Transmit Data Logic Input CC 18 Phase C Bootstrap Capacitor LRX 11 LIN Receive Data Logic Output CP1 29 Pump Capacitor MRSTn 8 MCU Reset Logic Output CP2 28 Pump Capacitor SA 25 Phase A Motor Phase CSM 9 Sense Amp Negative Input SB 21 Phase B Motor Phase CSP 10 Sense Amp Positive Input SC 17 Phase C Motor Phase DIAG 1 Programmable Diagnostic Output SCK 4 Serial Clock Logic Input GHA 24 Phase A HS FET Gate Drive SDI 5 Serial Data Logic Input GHB 20 Phase B HS FET Gate Drive SDO 7 Serial Data Logic Output GHC 16 Phase C HS FET Gate Drive STRn 3 Serial Strobe (Chip Select) Logic Input GLA 23 Phase A LS FET Gate Drive VBB 30 Main Supply GLB 19 Phase B LS FET Gate Drive VBRG 32 High-Side Drain Voltage Sense GLC 15 Phase C LS FET Gate Drive VLR 2 VLR Logic Regulator Output GND 14 Ground VREG 27 Gate Drive Supply Capacitor IG 31 Ignition Switch Input WDOG 6 MCU Watchdog Logic Input PAD – Thermal Pad; Connect to GND Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4964 DIAG VBRG IG VBB CP1 CP2 VREG CA SA 36 35 34 33 32 31 30 29 28 Sensorless Sinusoidal Drive BLDC Controller NC 1 27 GHA VLR 2 26 GLA NC 3 25 CB STRn 4 24 SB SCK 5 23 GHB SDI 6 22 GLB WDOG 7 21 CC SDO 8 20 SC MRSTn 9 19 GHC LIN GLC 15 LTX 18 14 LRX 17 13 CSP GND 12 CSM 16 11 GND 10 NC PAD 36-terminal eQFN (suffix EV) Terminal List Table Name Number Name Number CA 29 Phase A Bootstrap Capacitor Function LIN 15 LIN Bus Connection Function CB 25 Phase B Bootstrap Capacitor LTX 14 LIN Transmit Data Logic Input CC 21 Phase C Bootstrap Capacitor LRX 13 LIN Receive Data Logic Output CP1 32 Pump Capacitor MRSTn 9 MCU Reset Logic Output CP2 31 Pump Capacitor NC 3 No Connect CSM 11 Sense Amp Negative Input SA 28 Phase A Motor Phase CSP 12 Sense Amp Positive Input SB 24 Phase B Motor Phase DIAG 36 Programmable Diagnostic Output GHA 27 Phase A HS FET Gate Drive GHB 23 GHC 19 SC 20 Phase C Motor Phase SCK 5 Serial Clock Logic Input Phase B HS FET Gate Drive SDI 6 Serial Data Logic Input Phase C HS FET Gate Drive SDO 8 Serial Data Logic Output GLA 26 Phase A LS FET Gate Drive STRn 4 Serial Strobe (Chip Select) Logic Input GLB 22 Phase B LS FET Gate Drive VBB 33 Main Supply GLC 18 Phase C LS FET Gate Drive VBRG 35 High-Side Drain Voltage Sense GND 16 Ground; Connect GND Terminals Together VLR 2 VLR Logic Regulator Output GND 17 Ground; Connect GND Terminals Together VREG 30 Gate Drive Supply Capacitor IG 34 Ignition Switch Input WDOG 7 MCU Watchdog Logic Input PAD – Thermal Pad; Connect to GND Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4964 Sensorless Sinusoidal Drive BLDC Controller FUNCTIONAL BLOCK DIAGRAM Logic Supply Battery + IG WDOG MRSTn STRn SDI SDO SCK Sleep & Standby Control Ignition Interface VLR Regulator CP2 CP1 VLR VBB CP Charge Pump Regulator VREG Window Watchdog Logic Supply Regulator Ref Diagnostics & Protection VREF VBRG Serial Interface Phase A shown (repeatedfor B & C) DIAG CA Cboot Monitor Phase Angle Countr Run Control Speed Control LIN LTX LRX PWM/ LIN Phy GHA Phase B SA VREG Bridge Control Low-Side Drive GLA Phase C GND Position Estimator bemf & Zero-x Detect CBOOTA High-Side Drive 3-ph Sine PWM Gate Drive Control Motor Phase Control CREG CSP SA SB SC Blanking CSM VILIM Data Acquisition GND Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4964 Sensorless Sinusoidal Drive BLDC Controller ELECTRICAL CHARACTERISTICS: Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit 5.5 – 50 V 0 – 50 V SUPPLY AND REFERENCE VBB Functional Operating Range VBB Operating; outputs active No unsafe states VBB Quiescent Current IBBQ RUN = 0, VBB = 12 V – 13 20 mA VBB Sleep Current IBBS RUN = 0, VLIN = VBB = 12 V, in sleep state – 10 20 µA VBB ≥ 7.5 V, IVREG = 0 to 30 mA 7.5 8 8.5 V VREG Output Voltage VRG = 0 VREG 6 V ≤ VBB < 7.5 V, IVREG = 0 to 15 mA 7.5 8 8.5 V 5.5 V ≤ VBB < 6 V, IVREG ≤ 10 mA 7.5 8 8.5 V 9 11 11.7 V 7.5 V ≤ VBB < 9 V, IVREG = 0 to 20 mA 9 11 11.7 V 6 V ≤ VBB < 7.5 V, IVREG = 0 to 15 mA 7.9 – – V 5.5 V ≤ VBB < 6 V, IVREG ≤ 10 mA 7.9 9.5 – V VLR = 0; IVLR < 70 mA, VBB > 6 V 3.1 3.3 3.5 V VLR = 1; IVLR < 70 mA, VBB > 6 V 4.8 5.0 5.2 V 130 – 260 mA VBB ≥ 9 V, IVREG = 0 to 30 mA VREG Output Voltage VRG = 1 VLR Output Voltage VLR Regulator Current Limit VREG VLR ILROC VLR Regulator Shutdown Voltage Threshold VLROSD VLR falling 1.2 – – V VLR Regulator Enable Voltage Threshold VLROE VLR rising – – 1.5 V VLR Regulator Shutdown Lockout Period tLRLO – 2 – ms VLR Regulator Pilot Current ILROP Bootstrap Diode Forward Voltage Bootstrap Diode Resistance Bootstrap Diode Current Limit System Clock Period – 2 – mA ID = 10 mA 0.6 0.8 1.0 V ID = 100 mA 1.5 2.2 2.8 V 6 11 22 Ω IDBOOT 250 500 750 mA tOSC 47.5 50 52.5 ns VfBOOT rD rD(100mA) = (VfBOOT(150mA) – VfBOOT(50mA)) / 100 mA Continued on next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4964 Sensorless Sinusoidal Drive BLDC Controller ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit GATE OUTPUT DRIVE Turn-On Time tr Switched mode, CLOAD = 10 nF, 20% to 80% – 190 – ns Turn-Off Time tf Switched mode, CLOAD = 10 nF, 80% to 20% – 120 – ns TJ = 25°C, IG = -150 mA [1] 4 7 11 Ω Pull-Up On Resistance Pull-Up Peak Source Current [1][8] Pull-Down On Resistance Pull-Down Peak Sink Current [8] Turn-On Current 1 Turn-On Current 2 RDS(on)UP IPUPK RDS(on)DN IPDPK IR1 IR2 Turn-Off Current 1 IF1 Turn-Off Current 2 IF2 TJ = 150°C, IG = –150 mA [1] VGS = 0 V 9 12 20 Ω –500 –600 – mA TJ = 25°C, IG = 150 mA 1.5 3 4.5 Ω TJ = 150°C, IG = 150 mA 2.9 4 6 Ω VGS > 9 V 600 750 – mA VGS = 0 V, VRG = 1, IR1 = 15 – –75 – mA Programmable range –5 – –75 mA VGS = 0 V, VRG = 1, IR2 = 15 – –75 – mA Programmable range –5 – –75 mA VGS = 9 V, VRG = 1, IF1 = 15 – 75 – mA Programmable range 5 – 75 mA VGS = 9 V, VRG = 1, IF2 = 15 – 75 – mA Programmable range 5 – 75 mA VCX – 0.2 – – V – – VSX + 0.3 V GHx Output Voltage High VGHH Bootstrap capacitor fully charged GHx Output Voltage Low VGHL –10 µA < IGH < 10 µA GLx Output Voltage High VGLH GLx Output Voltage Low VGLL GHx Passive Pull-Down RGHPD VBB = 0 V, IGH = 500 µA – 5 – kΩ GLx Passive Pull-Down RGLPD VBB = 0 V, IGL = 500 µA – 5 – kΩ Bridge PWM Period tPW Bridge PWM Dither Step Period ΔtPW Bridge PWM Dither Dwell Time tDIT Dead Time (Turn-Off to Turn-On Delay) [2][5] tDEAD –10 µA < IGL < 10 µA VREG – 0.2 – – V – – 0.3 V Default power-up value, DS = 0, PMD = 0 47.9 50.5 53.0 µs Programmable range, DS = 0, PMD = 0 20.1 – 70.5 µs Default power-up value –0.21 –0.2 –0.19 µs Programmable range –0.2 – –1.6 µs Default power-up value 0.95 1 1.05 ms Programmable range 1 – 10 ms Default power-up value 1.52 1.6 1.68 µs Programmable range 0.1 – 3.15 µs Continued on next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4964 Sensorless Sinusoidal Drive BLDC Controller ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit LOGIC INPUTS AND OUTPUTS Input Low Voltage (STRn, SCK, SDI, WDOG) VIL – – 0.3 × VLR V Input High Voltage(STRn, SCK, SDI, WDOG) VIH 0.7 × VLR – – V Input Hysteresis (STRn, SCK, SDI, WDOG) VIhys 150 440 – mV Input Pull-Down Resistor (SCK, SDI, WDOG) RPD 30 50 70 kΩ Input Pull-Up Resistor (STRn) RPU 30 50 70 kΩ Input Low Voltage (IG) VIL – – 0.6 V Input High Voltage (IG) Input Hysteresis (IG) Input Current (IG) VIH 3.0 – – V VIhys 300 – – mV IG Input Pull-Down Resistor (IG) VIG ≥ 1 V RPD 0 V < VIG < 1 V Output Low Voltage (SDO, MRSTn) VOL IOL = 1 mA Output High Voltage (SDO, MRSTn) VOH IOL = –1 mA [1] Output Leakage [1] (SDO) – – 20 µA 120 240 480 kΩ – – 0.4 V VLR – 0.4 – – V IO 0 V < VO < VIO, STRn = 1 –1 – 1 µA Output Low Voltage (DIAG) VOLD IOD = 4 mA, DIAG active – 0.2 0.4 V Output Current Limit (DIAG) IODLIM 0 V < VOD < 18 V, DIAG active – 10 17 mA 18 V ≤ VOD < 50 V, DIAG active – – 2.5 mA 0 V < VOD < 6 V, DIAG inactive –1 – 1 µA 6 V ≤ VOD < 50 V, DIAG inactive – – 2.5 mA Output Leakage [1] (DIAG) IOD Continued on next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4964 Sensorless Sinusoidal Drive BLDC Controller ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit SERIAL INTERFACE – TIMING PARAMETERS Clock High Time tSCKH A in Figure 2 50 – – ns Clock Low Time tSCKL B in Figure 2 50 – – ns Strobe Lead Time tSTLD C in Figure 2 30 – – ns Strobe Lag Time tSTLG D in Figure 2 30 – – ns Strobe High Time tSTRH E in Figure 2 300 – – ns Data Out Enable Time tSDOE F in Figure 2 – – 40 ns Data Out Disable Time tSDOD G in Figure 2 – – 30 ns Data Out Valid Time From Clock Falling tSDOV H in Figure 2 – – 40 ns Data Out Hold Time From Clock Falling tSDOH I in Figure 2 5 – – ns Data In Set-Up Time To Clock Rising tSDIS J in Figure 2 15 – – ns Data In Hold Time From Clock Rising tSDIH K in Figure 2 10 – – ns VBB > VBBR to STRn low 500 – – µs Strn Delay From POR tEN Continued on next page... STRn C A B D E SCK J SDI X K D15 F SDO X D14 X X D0 I Z X G D15’ D14’ D0’ Z H Figure 2: Serial Interface Timing X = don’t care, Z = high impedance (tri-state) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4964 Sensorless Sinusoidal Drive BLDC Controller ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit V LIN/PWM INTERFACE LOGIC I/O [10] Transmitter Input Low Voltage (LTX) VIL – – 0.3 × VLR Transmitter Input High Voltage (LTX) VIH 0.7 × VLR – – V Transmitter Input Hysteresis (LTX) VIhys – 400 – mV 30 50 70 kΩ – – 0.4 V VLR – 0.4 – – V 0.8 × VBB – – V – – 1.4 V Transmitter Input Pull-Up Resistor (LTX) RPU Receiver Output Low Voltage (LRX) VOL Receiver Output High Voltage (LRX) VOH IOL = 1 mA, VBUS = 0 V IOL = –1 mA [1], VBUS = VBB LIN/PWM INTERFACE BUS TRANSMITTER [10] Bus Recessive Output Voltage VBUSRO Bus Dominant Output Voltage VBUSDO Bus Short Circuit Current IBUSLIM LTX High, Bus open load LTX Low, RLIN = 500 Ω, VBB = 7 V LTX Low, RLIN = 500 Ω, VBB = 18 V – – 2.0 V VBUS = 13.5 V 40 – 100 mA IBUS_PAS_dom VBB = 12 V, VBUS = 0 V –1 – – mA Leakage Current – Recessive IBUS_PAS_ rec 7 V < VBB < 18 V, 7 V < VBUS < 18 V VBUS ≥ VBB – – 20 µA Leakage Current – Ground Disconnect IBUS_NO_ GND VBB = 12 V, 0 V < VBUS < 18 V –1 – 1 mA Leakage Current – Supply Disconnect IBUS_NO_ BAT VBB = 0 V, 0 V < VBUS < 18 V – – 100 µA Normal operation 20 30 60 kΩ – 2 – MΩ 0.4 0.7 1 V Leakage Current – Dominant Bus Pull-Up Resistance RSLAVE Termination Diode Forward Voltage LIN/PWM INTERFACE BUS Sleep state VSerDiode RECEIVER [10] Receiver Center Voltage VBUSCNT Receiver Dominant State VBUSdom Receiver Recessive State Receiver Hysteresis Receiver Wake-Up Threshold Voltage 0.475 × VBB 0.5 × VBB 0.525 × VBB 0.4 × VBB V – – V VBUSrec 0.6 × VBB – – V VHYS 0.05 × VBB – 0.175 × VBB V VBUSwk 0.4 × VBB 0.5 × VBB 0.6 × VBB V LIN/PWM INTERFACE – TIMING PARAMETERS [10] Receiver Propagation Delay H → L trx_pdf Bus dominant to LRX low – – 6 µs Receiver Propagation Delay L → H trx_pdr Bus recessive to LRX high – – 6 µs Receiver Delay Symmetry trx_sym trx_pdf – trx_pdr –2 – 2 µs Bus Dominant Time For Wake tBUSWK 22 – 150 µs Wake Up Delay tWL PWM Input Timeout tPTO Transmit Dominant Time-Out tTXTO LIN Wake up to VREG 90% LWK = 1, OPM = 0, LEN = 1 – 3 – ms 209 220 231 ms – 15 – ms Continued on next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A4964 Sensorless Sinusoidal Drive BLDC Controller ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit LIN/PWM INTERFACE – TIMING PARAMETERS (continued) D1 7 V < VBB < 18 V, tBIT = 50 µs THRec(max) = 0.744 × VBB THDom(max) = 0.581 × VBB D1 = tBUS_rec(min) / (2 × tBIT) 0.396 – – – Duty Cycle D2 (worst case at 20 kb/s) [7][9] D2 7 V < VBB < 18 V, tBIT = 50 µs THRec(min) = 0.422 × VBB THDom(min) = 0.284 × VBB D2 = tBUS_rec(max) / (2 × tBIT) – – 0.581 – Duty Cycle D3 (worst case at 10.4 kb/s) [7][9] D3 7 V < VBB < 18 V, tBIT = 96 µs THRec(max) = 0.778 × VBB THDom(max) = 0.616 × VBB D3 = tBUS_rec(min) / (2 × tBIT) 0.417 – – – Duty Cycle D4 (worst case at 10.4 kb/s) [7][9] D4 7 V < VBB < 18 V, tBIT = 96 µs THRec(min) = 0.389 × VBB THDom(min) = 0.251 × VBB D4 = tBUS_rec(max) / (2 × tBIT) – – 0.590 – Duty Cycle D1 (worst case at 20 kb/s) [7][9] Continued on next page... tBIT tBIT tBIT LTX (Input to transmitting node) tBus_dom(max) tBus_rec(min) THRec(max) VSUP (Tranceiver supply of transmitting node) Thresholds of receiving node 1 THDom(max) THRec(min) Thresholds of receiving node 2 THDom(min) tBus_dom(min) tBus_rec(max) LRX (Output of receiving node 1) trx_pdf(1) trx_pdr(1) LRX (Output of receiving node 2) trx_pdr(2) trx_pdf(2) Figure 3: LIN Bus Timing Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A4964 Sensorless Sinusoidal Drive BLDC Controller ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit Default power-up value; VMIT = VCSP – VCSM – 200 – mV Programmable range; VMIT = VCSP – VCSM 25 – 200 mV VIL = 15, MIT = 0 –5% – +5% %FS Default power-up value, OBT = 7 1.71 1.80 1.89 µs 1 – 6.6 µs 0 – 50.4 V – ±0.5 – V CURRENT LIMITING Sense Amplifier Maximum Current Limit Threshold VMIT Current Limit Threshold Error [6] EILIM Current Limit Blank Time tOCB Programmable range DATA ACQUISITION SYSTEM Supply Voltage (VBRG): Measurement Range VVM Supply Voltage (VBRG): Measurement Accuracy EVM Average Supply Current Measurement: Sense Voltage Range VVS 0 – 200 mV Average Supply Current Measurement: Sense Voltage Accuracy EVS – ±1 – % Temperature Measurement Range TJ –50 – 190 °C Temperature Measurement Accuracy ETJ – ±5 – °C VBRG ≤ 30 V Continued on next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A4964 Sensorless Sinusoidal Drive BLDC Controller ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit ms MOTOR STARTUP PARAMETERS Hold Time Hold Duty Cycle Start Speed 1 Start Speed 2 Start Duty Cycle 1 Start Duty Cycle 2 tHOLD DH fS1 fS2 DS1 DS2 Start Time Step tSS Start Speed Step fSS Brake Duty Cycle DWB Min. Windmill Frequency fWM Default power-up value 190 200 210 Programmable range 0 – 3 s Default power-up value – 18.75 – % 3.125 – 100 % 3.8 4 4.2 Hz Programmable range Default power-up value Programmable range Default power-up value 0.5 – 8 Hz 26.12 27.5 28.88 Hz Programmable range 10 – 47.5 Hz Default power-up value – 50 – % 6.25 – 100 % – 50 – % Programmable range Default power-up value Programmable range 6.25 – 100 % Default power-up value 76 80 84 ms Programmable range 10 – 300 ms Default power-up value Programmable range Default power-up value 0.95 1 1.05 Hz 0.0125 – 15 Hz – 50 – % Programmable range 6.25 – 100 % Default power-up value 6.46 6.8 7.14 Hz Programmable range 0.4 – 22.8 Hz – 7 – °(elec.) MOTOR RUN PARAMETERS BEMF Window Windmill BEMF Filter Time Speed Control Resolution Phase Advance (in electrical degrees) Speed Error θBW tBF fSR θADV Default power-up value Programmable range 1.4 – 60 °(elec.) Default power-up value 0.19 0.20 0.21 ms Programmable range 0 – 20 ms 0.095 0.1 0.105 Hz 0.1 – 3.2 Hz Default power-up value – 0 – °(elec.) Programmable range 0 – 60 °(elec.) –5 – +5 % 0.95 1 1.05 ms 1 – 63 ms Default power-up value 9.5 10.0 10.5 ms Programmable range 10 – 320 ms Default power-up value Programmable range EfE WATCHDOG –TIMING PARAMETERS Minimum Watchdog Time tWM Watchdog Window Time tWW Default power-up value Programmable range Watchdog Detect To MRSTn Low tWDET 100 – 200 ns MRSTn Low tMRST 9.5 10.0 10.5 ms Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A4964 Sensorless Sinusoidal Drive BLDC Controller ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit NVM – PROGRAMMING PARAMETERS Programming Voltage VPP Applied to VBB when programming 27 – – V Programming Supply Setup Time tPRS VPP > VPPMIN to start of NVM write 10 – – ms VBBON VBB rising 4.0 4.3 4.5 V VBBOFF VBB falling DIAGNOSTICS AND PROTECTION VBB Undervoltage Lockout VBB Undervoltage Lockout Hysteresis VBBHys VBB POR Voltage VBBR VPP Undervoltage VPPUV VLR Undervoltage Reset 3.3 V VLR Undervoltage Reset 5 V VREG Undervoltage VRG = 0 VREG Undervoltage VRG = 1 Bootstrap Undervoltage Bootstrap Undervoltage Hysteresis VBRG Input Voltage VBRG Input Current VDS Threshold VBB falling VDS Qualifier Time [5] SDO Output: Clock Division Ratio 4.0 4.2 V 280 – mV – 3.2 3.5 V 21.6 – 26.6 V VLRON VLR rising, VLR = 0 – – 3.1 V VLROFF VLR falling, VLR = 0 2.4 – – V VLRON VLR rising, VLR = 1 – – 4.8 V VLROFF VLR falling, VLR = 1 4.2 – – V VRON VREG rising 6.2 6.5 6.8 V VROFF VREG falling 5.4 5.6 5.8 V VRON VREG rising 7.6 7.9 8.2 V VROFF VREG falling 6.9 7.15 7.4 V VBCUV VBOOT falling, VBOOT = VCx – VSx 60 – 71 %VREG VBCUVHys – 5 – %VREG VBRG –1 VBB +1 V – – 500 µA IVBRG VDST = default, VBB = 12 V 0 V < VBRG < VBB IVBRGQ Sleep mode VBB < 35 V – – 5 µA Default power-up level 1400 1550 1700 mV – – 3150 mV VDST VBRG ≥ 8 V [11] VBRG < VDS Threshold Offset [3][4] 3.8 150 VDSTO tVDQ ND Temperature Warning Threshold TJWH Temperature Warning Hysteresis TJWHhys 8 V [11] – – 1550 mV VDST > 1 V –200 ±100 +200 mV VDST ≤ 1 V –150 ±50 +150 mV Default power-up value 2.99 3.15 3.31 µs Programmable range 0.6 – 3.15 µs CKS = 1 Temperature increasing 280000 – 125 135 145 ºC – 15 – ºC Overtemperature Threshold TJF Temperature increasing 170 175 180 ºC Overtemperature Hysteresis TJHyst Recovery = TJF – TJHyst – 15 – °C [1] For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device terminal. Figure 4 for gate drive output timing. [3] As V SX decreases, high-side fault occurs if (VBAT – VSX) > (VDST + VDSTO). [4] As V SX increases, low-side fault occurs if VSX > (VDST + VDSTO). [5] See Figure 4 and Figure 5 for V DS monitor timing. [6] Current limit threshold voltage error is the difference between the target threshold voltage and the actual threshold voltage, referred to maximum full scale (100%) current: EILIM = 100 × (VILIMActual – VILIM) / 200%. (VILIM in mV). [7] Slew rate is controlled during both transitions and will not exceed specified limits at any point between test limits. [8] Ensured by design and characterization. [9] LIN bus load conditions (C BUS, RBUS): 1 nF; 1 kΩ / 6.8 nF; 660 Ω / 10 nF; 500 Ω. [10] Parameters are not guaranteed above or below the LIN 2.2 A operating limits V BB = 7 to 18 V. [11] Maximum value of VDS threshold that should be set in the configuration registers for correct operation when V BB is within the stated range. [2] See Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A4964 Sensorless Sinusoidal Drive BLDC Controller tDEAD GHx tVDQ HS monitor disabled High-side VDS monitor active High-side VDS monitor disabled tDEAD GLx tVDQ Low-side VDS monitor disabled Low-side VDS monitor active disabled Figure 4: VDS Fault Monitor Activation – Blank Mode Timing (VDQ = 1) MOSFET turn on No fault present MOSFET turn on Fault present Gate Active MOSFET on Transient disturbance No fault present MOSFET on Fault occurs VDS tVDQ tVDQ Fault Bit Figure 5a: VDS Fault Detection - Blank Mode Timing (VDQ = 1) MOSFET turn on No fault present MOSFET turn on Fault present Gate Active MOSFET on Transient disturbance No fault present MOSFET on Fault occurs VDS tVDQ tVDQ tVDQ tVDQ Fault Bit Figure 5b: VDS Fault Detection - Debounce Mode Timing (VDQ = 0) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A4964 Sensorless Sinusoidal Drive BLDC Controller Electrical Period Electrical Phase Angle 360 300 240 180 120 60 0 SA Phase PWM Duty SB SC Forward IA Phase Current IB IC SA Phase PWM Duty SB SC Reverse IA Phase Current IB IC Figure 6: Phase Current Commutation Sequence for Sinusoidal Drive with 3-Phase Modulation Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 A4964 Sensorless Sinusoidal Drive BLDC Controller Electrical Period Electrical Phase Angle 360 300 240 180 120 60 0 SA Phase PWM Duty SB SC Forward IA Phase Current IB IC SA Phase PWM Duty SB SC Reverse IA Phase Current IB IC Figure 7: Phase Current Commutation Sequence for Sinusoidal Drive with 2-Phase Modulation Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 A4964 Sensorless Sinusoidal Drive BLDC Controller Electrical Period Electrical Phase Angle 360 300 240 180 120 60 0 SA Phase PWM Duty SB SC Forward IA Phase Current IB IC SA Phase PWM Duty SB SC Reverse IA Phase Current IB IC Figure 8: Phase Current Commutation Sequence for Trapezoidal Drive with 2-Phase Modulation Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 A4964 Sensorless Sinusoidal Drive BLDC Controller Sin Drive, 3-Phase Modulation Sin Drive, 2-Phase Modulation 100% DPK= 100% 50% OVM= 0 0% 0° 60° 120° 180° 240° 300° 360° 0° 60° 120° 180° 240° 300° 360° 0° 60° 120° 180° 240° 300° 360° 0° 60° 120° 180° 240° 300° 360° 0° 60° 120° 180° 240° 300° 360° 100% DPK= 75% OVM= 0 or 50% DPK= 50% OVM= 3 0% 0° 60° 120° 180° 240° 300° 360° 100% DPK= 85% 50% OVM= 2 0% 0° 60° 120° 180° 240° 300° 360° 100% DPK= 92% 50% OVM= 3 0% 0° 60° 120° 180° 240° 300° 360° Figure 9: Modulation and Overmodulation Examples Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 A4964 Sensorless Sinusoidal Drive BLDC Controller tPW tPW Phase A Phase B Phase C Figure 10a: Center-Aligned Bridge PWM Mode PMD = 0 tPW tPW Phase A Phase B Phase C Figure 10b: Edge Aligned Bridge PWM Mode PMD = 1 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 A4964 Sensorless Sinusoidal Drive BLDC Controller FUNCTIONAL DESCRIPTION The A4964 is a three-phase, sensorless, brushless DC (BLDC) motor controller for use with external N-channel power MOSFETs and is specifically designed for automotive applications. The motor is driven using 3-phase sinusoidal current drive, where phase commutation is determined by a proprietary, motor back-emf (bemf) sensing technique. The motor bemf is sensed to determine the rotor position without the need for independent position sensors. An integrated sensorless startup scheme includes forwards and reverse pre-rotation (windmill) detection and syncronization and allows a wide range of motor and load combinations. to protect the power FETs under most short-circuit conditions. Detailed diagnostics are available through the serial interface. Motor current is provided by six external power N-channel MOSFETs arranged as a three phase bridge. The A4964 provides six high current gate drives, three high-side and three low-side, capable of driving a wide range of MOSFETs. The maximum MOSFET drive voltage is internally limited under all supply conditions to protect the MOSFET from excessive gate-source voltage without the need for an external clamp circuit. The A4964 provides all the necessary circuits to ensure that the gate-source voltage of both high-side and low-side external MOSFETs are sufficiently high to achieve full correct conduction at low supply levels. A low-power sleep state allows the A4964, the power bridge, and the load to remain connected to a vehicle battery supply without the need for an additional supply switch. VBRG. Sense input to the top of the external MOSFET bridge. Allows accurate measurement of the voltage at the drain of the high-side MOSFETs in the bridge. Three motor control modes are available: closed-loop speed control, open-loop speed (voltage) control, and current (torque) control. The motor control mode and the control and configuration parameters can be altered through an SPI-compatible serial interface and the user-defined power-up parameters can be stored in non-volatile memory. The A4964 can also operate in a standalone mode, without the need for an external microcontroller, where the duty cycle of a PWM signal applied to the LIN terminal is used to control the output of the motor. Specific functions are described more fully in following sections. Input and Output Terminal Functions VBB. Main power supply for internal regulators and charge pump. The main power supply should be connected to VBB through a reverse voltage protection circuit and should be decoupled with ceramic capacitors connected close to the supply and ground terminals. CP1, CP2. Pump capacitor connections for charge pump. Connect a 470 nF ceramic capacitor between CP1 and CP2. VREG. Regulated voltage, nominally 11 V, used to supply the low-side gate drivers and to charge the bootstrap capacitors. A sufficiently large storage capacitor must be connected to this terminal to provide the transient charging current. VLR. VLR regulator output. External logic can be powered by this node. The voltage can be selected as 3.3 or 5 V. A ceramic capacitor of at least 1 µF with an ESR of no more than 250 mΩ should be fitted between the VLR output and GND to ensure stability. GND. Analog reference, digital and power ground. Connect to supply ground—see layout recommendations. CA, CB, CC. High-side connections for the bootstrap capacitors and positive supply for high-side gate drivers. GHA, GHB, GHC. High-side gate-drive outputs for external N-channel MOSFETs. Startup (inrush) current, and peak motor current is limited by an integrated fixed frequency PWM current limiter. The maximum current limit is set by a single external sense resistor and the active current limit can be modified through the serial interface. SA, SB, SC. Motor phase connections. These terminals sense the voltages switched across the load. They are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drivers. An integrated data acquisition system provides measurement of the motor voltage, the chip temperature, the motor speed, and an estimate of the average supply current. GLA, GLB, GLC. Low-side gate-drive outputs for external N-channel MOSFETs. Integrated diagnostics provide indication of undervoltage, overtemperature, and power bridge faults, and can be configured CSP, CSM. Differential current sense amplifier inputs. Connect directly to each end of the sense resistor using separate PCB traces. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22 A4964 Sensorless Sinusoidal Drive BLDC Controller LIN. LIN bus connection compliant with LIN 2.2 A. This input can also be used as a PWM that can be passed to the LRX output or used directly as the demand input when operating in standalone mode. LTX. LIN or FAULT transmit logic level input. LRX. LIN or PWM receive logic level output. IG. Ignition switch input, with resistor pull-down, to disable or wake-up the A4964 and enable the logic regulator for the microcontroller. When not used, IG should be tied to ground to minimize the effect on the supply current in the sleep state. DIAG. Programmable diagnostic output. Can be shorted to ground or VBB without damage. WDOG. Microcontroller watchdog logic input with resistor pull-down. Window watchdog with programmable minimum and maximum clock period. MRSTn. Microcontroller reset control output. Holds the microcontroller in reset until supplies are available. Resets the microcontroller in case of watchdog failure. SDI. Serial data input with resistor pull-down. 16-bit serial word input msb first. SDO. Serial data output. High impedance when STRn is high. Outputs bit 15 of the Diagnostic register, the fault flag, as soon as STRn goes low. SCK. Serial clock input with resistor pull-down. Data is latched in from SDI on the rising edge of CLK. There must be 16 rising edges per write and SCK must be held high when STRn changes. STRn. Serial data strobe and serial access enable input with resistor pull-up. When STRn is high, any activity on SCK or SDI is ignored and SDO is high impedance, allowing multiple SDI slaves to have common SDI, SCK, and SDO connections. Supplies and Regulators MAIN POWER SUPPLY A single power supply voltage is required. The main power supply, VBB, should be connected to VBB through a reverse voltage protection circuit. A 100 nF ceramic decoupling capacitor must be connected close to the supply and ground terminals of the A4964. An internal regulator provides the supply to the internal logic. All logic is guaranteed to operate correctly to below the VBB POR level, ensuring that the A4964 will continue to operate safely until all logic is reset when a power-on-reset state is present. The A4964 will operate within specified parameters with VBB from 5.5 to 50 V. Below 5.5 V, the gate drive outputs may be inactive, but the A4964 will continue to respond through the serial interface with a supply down to 3.5 V. It will remain in a safe state between 0 and 50 V under all supply switching conditions. This provides a very rugged solution for use in the harsh automotive environment. At power-up, the logic inputs and outputs will remain disabled until VLR rises above the rising undervoltage threshold, VLRON. If the WD mask bit is saved as 0 in non-volatile EEPROM (NWM), the MRSTn output will remain low for 10 ms. If the WD mask bit is saved as 1 in NWM, the MRSTn output will remain low for 10 ms or until the first valid serial transfer (whichever occurs first). After the MRSTn output goes high, the gate drive outputs will be re-enabled as described in the Fault Action section. VLR REGULATOR An integrated, programmable, linear regulator is provided to supply the logic I/O and external logic-level circuits, such as a microcontroller or interface circuit. The output of the regulator on the VLR terminal is derived from VBB and can be selected as 3.3 or 5 V using the VLR bit. The logic I/O threshold levels are also determined by the VLR bit, allowing the A4964 to match the logic I/O levels of external logic. The regulator includes current limit, undervoltage, and short protection. The current limiting circuit will reduce the output voltage to ensure that the output current does not exceed the current limit, ILROC. If the output voltage drops below the falling undervoltage threshold, VLROFF, the MRSTn output will go low and can be used to reset an external microcontroller. If the output voltage falls below the regulator shutdown threshold, VLROSD, for a period exceeding the shutdown lockout period, tLRLO, the regulator is turned off and all logic inputs and outputs are disabled. In this state a small pilot current, ILROP, is driven through the regulator output to detect load resistance. If the resultant voltage rises above the regulator enable threshold, VLROE, the regulator immediately attempts to restart. At power-up, or when the regulator restarts, full output current is delivered for a period equal to the shutdown lockout period. During this time, the output voltage is not monitored for short-circuit conditions in order to ensure reliable regulator startup. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 23 A4964 Sensorless Sinusoidal Drive BLDC Controller only be set through the serial interface in the SPI mode. If ESF = 1 and the A4964 internal junction temperature, TJ, rises above the overtemperature threshold, TJF, the regulator is immediately shut down and MRSTn will go low. All A4964 functions other than the regulator remain active. When TJ drops by more than the overtemperature hysteresis below the overtemperature threshold (TJ < TJF – TJHyst), the regulator will remain shut down and MRSTn will remain low for 10 ms. After this timeout, MRSTn goes high and the regulator is re-enabled and attempts to restart. If an undervoltage shutdown and an overtemperature warning occur simultaneously, both must be cleared to allow the regulator to restart. SPI MODE Internal A4964 logic circuitry is not powered from the VLR regulator and remains fully operational regardless of whether the VLR regulator is running normally or shut down. When operating in stand-alone mode (OPM = 1), the demand input is only determined by the duty cycle of a PWM signal applied to the LIN terminal. The 10-bit demand input through the serial interface is not available in this mode. However, all configuration settings and basic control functions, except for the demand input, can still be programmed through the serial interface. In this mode, the LIN input will also wake the A4964 when it is in the sleep state. A ceramic capacitor of at least 1 µF with an ESR of no more than 250 mΩ should be fitted between the VLR terminal and GND to guarantee stability and oscillation and voltage excursions beyond the specified output voltage range. In some applications, the use of redundant output capacitors may be advisable to avoid such a condition in the event of a single-point capacitor high-impedance failure. PUMP REGULATOR The gate drivers are powered by a programmable voltage internal regulator which limits the supply to the drivers and therefore the maximum gate voltage. At low input supply voltage, the regulated supply is maintained by a charge pump boost converter which requires a pump capacitor, typically 470 nF, connected between the CP1 and CP2 terminals. The regulated voltage, VREG, can be programmed to 8 or 11 V and is available on the VREG terminal. The voltage level is selected by the value of the VRG bit. When VRG = 1, the voltage is set to 11 V; when VRG = 0, the voltage is set to 8 V. A sufficiently large storage capacitor (see applications section) must be connected to this terminal to provide the transient charging current to the low side drivers and the bootstrap capacitors. Operating Modes The A4964 has two operating modes: SPI mode and stand-alone mode. In SPI mode, it can be fully controlled by a small low-cost external microcontroller through the serial interface. In standalone mode, the LIN terminal becomes a PWM input that is used to set the input demand. All configuration settings and basic control functions, except for the demand input, can be programmed through the serial interface in both modes. The demand input can When operating in SPI mode (OPM = 0) the demand input is determined by a 10-bit value, input from the external microcontroller. The LIN terminal is a simple LIN physical interface where the data on the LIN bus is interpreted and the responses are provided by the external microcontroller. The only other function that the LIN input provides is to wake the A4964 when it is in the sleep state. STAND-ALONE MODE LOW-POWER SLEEP STATE The A4964 provides a low-power sleep state where the consumption from the supply is reduced to a minimum by disabling all normal operation including the charge pump regulator, the internal logic regulator, the external regulator, and the internal clock. In the sleep state, the LIN terminal must be at the same voltage as the supply terminal, VBB, and the IG terminal should be tied to ground to achieve the minimum supply current. There are two sleep states: the normal commanded sleep state and the permanent sleep state. The permanent sleep state is only entered following a watchdog cycle count failure. The state of the A4964 is the same in both cases, but it will only exit the permanent sleep state after a power off-on cycle as described in the Microcontroller Watchdog section. When operating in SPI mode (OPM = 0), the A4964 can only be commanded to go into the normal sleep state using the serial interface to change the GTS bit from 0 to 1 when the LIN input is high (recessive). If the LIN input is low (dominant), any sleep command through the serial interface will be ignored, and the GTS bit must be changed to 0 followed by 1 to issue another goto-sleep command when the LIN input is high (recessive).When operating in stand-alone mode (OPM = 1), the A4964 will go into the normal sleep state using the serial interface to change the GTS bit from 0 to 1, irrespective of the level on the LIN terminal. In stand-alone mode, it will also go to sleep when the IG input Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 24 A4964 Sensorless Sinusoidal Drive BLDC Controller transitions from high to low. conditions. The sequence to wake the A4964 is determined by the LWK bit and is independent from the operating mode. When the LIN wake mode is selected (LWK = 1), the A4964 will wake up according to the LIN protocol. When the PWM wake mode is selected (LWK = 0), the A4964 will wake up on any valid transition of the signal at the LIN terminal. These sequences are fully described and defined in the LIN interface section below. Table 1: Operating and Wake Mode Features In either wake mode, the A4964 will also wake up on a low-tohigh transition of the signal on the IG terminal. In the sleep state, the MRSTn output is held low, latched faults are cleared, and the Diagnostic and Status registers are reset to zero. When coming out of the sleep state, all registers are reset to the user-defined values held in the non-volatile memory, and the A4964 follows the same procedure as for a full power-on reset. MRSTn is held low until 10 ms after the external regulator output exceeds its undervoltage threshold. In addition, the charge pump output monitor ensures that the gate drive outputs are off until the charge pump reaches its correct operating condition. The charge pump will stabilize in approximately 2 ms under nominal Operating Mode SPI Standalone OPM 0 1 Demand SPI 10-bit (DI[9:0]) No Demand LIN No LIN(PWM) Duty Sleep (SPI) Command SPI (GTS 0→1) [Only when LIN is high] SPI (GTS 0→1) Sleep (IG) Command No IG high to low Wake Mode PWM LIN LWK 0 1 Wake (IG) IG L→H IG L→H Wake (LIN) Any transition on LIN terminal present for > tBUSWK First L→H transition on LIN terminal after LIN terminal low for > tBUSWK Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 25 A4964 Sensorless Sinusoidal Drive BLDC Controller Microcontroller Reset and Watchdog MICROCONTROLLER RESET The microcontroller reset output, MRSTn, can be used to reset and re-initialize an external microcontroller if an undervoltage, watchdog fault, or power-on-reset (POR) occurs. The MRSTn output will be active low when the external regulator undervoltage or POR fault state is present and will remain low for 10 ms after all faults are removed. It will also go low for 10 ms when a watchdog fault is detected. MICROCONTROLLER WATCHDOG The A4964 includes a programmable window watchdog that can be used to determine if the external microcontroller is operating in an adverse state. After any transition (high-to-low or low-tohigh) on the WDOG input, the WDOG input must be held at a DC level for the duration of the minimum watchdog time, tWM, set by the WM variable. Following the end of the minimum watchdog time, a transition on the WDOG input must then be detected before the end of the watchdog window time, tWW, set by the WW variable in order to reset the watchdog timer. This means that the time between each transition on the WDOG input must be longer than tWM and shorter than tWM + tWW. If a subsequent transition is detected before tWM or if a transition is not detected within tWM + tWW, then the WD bit will be set in the Status register and the MRSTn output will go active low for 10 ms in order to reset the microcontroller. In all fault cases (POR, undervoltage or watchdog) when MRSTn goes high after the 10 ms low period, the watchdog timer will be reset and remain reset for 100 ms. During this time, the WDOG input is ignored. The first transition must then be detected within tWM + tWW or the micro-reset cycle will repeat. There is no minimum watchdog time, tWM, following a micro-reset.The microreset and watchdog timing is shown in Figure 11. The WD bit will remain set in the Status register until cleared. When a watchdog failure is detected, the motor drive is disabled and the motor will coast. The motor drive remains disabled until a valid watchdog transition is detected. Once a valid watchdog has been detected, the A4964 will attempt to restart the motor if the RUN and RSC bits are set to 1, and the demand input is at a level where starting the motor is permitted. If the watchdog function is not required, it is possible to disable the function by setting the WD bit in the mask register to 1. This will completely disable the watchdog monitor and any possible actions that it may take. tWM tWW WDOG Figure 11a: Watchdog Timing Requirements > tWM < tWM + tWW > tWW < tWM + tWW WDOG Figure 11b: Suitable Watchdog Signal tWM + tWW 10 ms MRSTn WDOG Figure 11c: Reset After Missing Watchdog Edge > tWM < tWM + tWW > tWM 10 ms MRSTn WDOG Figure 11d: Reset After Early Watchdog Edge 100 ms tWM + tWW MRSTn WDOG Watchdog input ignored Must change once in this period Figure 11e: Timing After Reset tWM + tWW tWDC tWDC tWDC Go to sleep MRSTn WDOG tWDC = 10 ms + 100 ms + tWM + tWW WC[3:0] = 3 Figure 11f: Sleep After Fail Cycle Count Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 26 A4964 Sensorless Sinusoidal Drive BLDC Controller If the microcontroller has completely stopped working it is possible to put the A4964 into the permanent sleep state, after a number of reset cycles using the watchdog fail cycle count variable, WC[3:0]. The value in WC[3:0] sets the number of watchdog fail-reset cycles that can occur before the A4964 goes into the permanent sleep state. A value of 1 will allow one fail-reset cycle and will go to sleep on the next watchdog failure if no valid transitions are detected on the WDOG input. A value of 8 will allow 8 fail-reset cycle and will go to sleep on the 9th watchdog failure if no transitions are detected on the WDOG input. The counter is reset if any valid transition is detected on the WDOG input. A valid transition is one that occurs after the initial 100 ms following a microcontroller reset and before the end of the initial watchdog window time, tWM + tWW. Figure 11f shows the fail-cycle operation when WC[3:0] is set to 3. A value of zero in WC[3:0] will disable this feature and permit unlimited fail-reset cycles. Once the A4964 goes into the permanent sleep state due to exceeding the fail-reset cycle limit, it will remain in this state until a power cycle occurs. LIN Physical Interface The A4964 includes a physical interface to drive and monitor a single wire LIN bus as a slave node that complies with the LIN 2.2 standard. The LIN terminal can withstand voltages from –14 V to +50 V with respect to the ground pin without adversely affecting LIN bus communications between other devices. LIN protocol handling is not included. LIN LRX LTX Figure 12: LIN Physical Interface The LIN terminal meets all the voltage, timing, and slew limitation requirements of LIN 2.2 when actively transmitting and when receiving. When operating in SPI mode, a timer is included to ensure that the LIN output does not remain dominant when a fault occurs. If the LIN terminal is driven in the dominant state for longer than the transmit dominant timeout period, tTXTO, then the output is disabled and allowed to return to the recessive state in order to avoid locking the LIN Bus for other messages. The dominant timeout function is disabled in standalone operating mode (OPM = 1), in PWM wake mode (LWK = 0), or when the LIN interface is in the standby state (LEN = 0). The data to be transmitted is input to the LTX terminal and converted to LIN bus signals. A logic high on the LTX input produces a recessive bus (high) state while a logic low produces a dominant bus (low) state. The LTX input has an internal pull-up resistor to ensure a recessive state if the pin is not connected or becomes disconnected. The logic state of the LIN Bus is determined by the receiver and output as a logic level on the LRX terminal. LRX will be low when the LIN Bus is in the dominant (low) state and high when the LIN Bus is in the recessive (high) state. In the sleep state, LRX is not active and will be low. In SPI mode, the LIN interface can also be used as a PWM interface to the external microcontroller. The level of the PWM signal applied to the LIN terminal will be output as a logic level on the LRX terminal. When used as a PWM input in SPI mode (OPM = 0), the LTX input can be used to pull the PWM signal low in order to indicate a fault to the external ECU. In standalone mode, the DIAG output can be connected directly to the LIN terminal to indicate a fault to the external ECU. See Diagnostics section for additional detail. When the A4964 is in the sleep state, the LIN terminal changes to a passive input and the resistance of the pull-up resistor on the LIN terminal increases to approximately 2 MΩ. This ensures that the LIN terminal is unable to affect the LIN bus signal. The LIN terminal continues to be monitored in the normal sleep state in order to detect a wake request. Two wake sequence modes are possible, selected by the LWK bit. The selected wake sequence mode is independent of the operating mode. When LWK = 1, the A4964 will wake up according to the LIN protocol. In this mode, the wake request is valid on the first lowto-high transition on the LIN terminal after the LIN terminal is in a dominant (low) state for longer than the wake time, tBUSWK, as shown in Figure 13a. If the LIN terminal changes to recessive (high) within tBUSWK then the A4964 returns to the sleep state. When LWK = 0, the A4964 will wake up on any valid transition of the signal at the LIN terminal. In this mode, the wake signal is valid when the signal on the LIN terminal changes state, high-tolow or low-to high, and remains in the changed state for longer than the wake time, tBUSWK, as shown in Figure 13b. This mode Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 27 A4964 Sensorless Sinusoidal Drive BLDC Controller is usually used when the LIN terminal is used as a PWM input, either in SPI mode or in standalone mode. If the LIN terminal does not remain in the changed state for longer than the wake time, tBUSWK, then the A4964 returns to the sleep state. When a valid wake request is detected on the LIN terminal or the IG terminal transitions from low to high, the A4964 will exit normal the sleep state, turn on all regulators and control circuits, and commence operation. At this time, if the LEN bit is 0, the LIN interface will remain in the standby state where the LIN terminal is a passive input. The LRX output will indicate the state of the LIN terminal but the signal on the LTX terminal is ignored. The LIN interface becomes fully active when LEN is set to 1. If the default value of LEN is 1, then the standby state is bypassed and the LIN interface is fully active as soon as the internal regulators are fully active. tHRec LIN tHDom tBUSWK State Sleep LEN Standby 0 Active 1 Figure 13a: LIN Wake Sequence and Timing LIN (PWM) LEN The motor drive consists of three half-bridge gate drive outputs, each driving one leg of an external three-phase MOSFET power bridge. The state of the gate drive outputs is determined by a three-phase PWM generator that determines the necessary PWM duty cycle required at each of the three-phase connections to the motor. GATE DRIVE The A4964 is designed to drive external, low on-resistance, power n-channel MOSFETs. It will supply the large transient currents necessary to quickly charge and discharge the external MOSFET gate capacitance in order to reduce dissipation in the external MOSFET during switching. The charge current for the low-side drives and the recharge current for the bootstrap capacitors is provided by the capacitor on the VREG terminal. The charge current for the high-side drives is provided by the bootstrap capacitors connected between the Cx and Sx terminal, one for each phase. The MOSFET gate charge and discharge rate can be controlled using an external resistor in series with the connection to the gate of the MOSFET or by selecting the gate drive current and timing using a group of parameters set via the serial interface. GATE DRIVE VOLTAGE REGULATION The gate drivers are powered by a programmable voltage internal regulator which limits the supply to the drivers and therefore the maximum gate voltage. At low supply voltage, the regulated supply is maintained by a charge pump boost converter which requires a pump capacitor, typically 470 nF, connected between the CP1 and CP2 terminals. The regulated voltage, VREG, can be programmed to 8 or 11 V and is available on the VREG terminal. The voltage level is selected by the value of the VRG bit. When VRG = 1, the voltage is set to 11 V; when VRG = 0, the voltage is set to 8 V. A sufficiently large storage capacitor (see applications section) must be connected to this terminal to provide the transient charging current to the low side drivers and the bootstrap capacitors. tHRec tHDom tBUSWK State Motor Drive Sleep Standby 0 Active 1 Figure 13b: PWM Wake Sequence and Timing LOW-SIDE GATE DRIVE The low-side, gate-drive outputs on GLA, GLB, and GLC are referenced to the GND terminal. These outputs are designed to drive external N-channel power MOSFETs. GLx = ON (or “high”) means that the upper half of the driver is turned on and it will source current to the gate of the low-side external MOSFET, turning it on. GLx = OFF (or “low”) means that the lower half of Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 28 A4964 Sensorless Sinusoidal Drive BLDC Controller the driver is turned on and it will sink current from the gate of the external MOSFET, turning it off. MOSFET gate charge and discharge rates may be controlled by external resistors between the gate drive output and the gate connection to the MOSFET (as close as possible to the MOSFET) or by programming the gate drive via the serial interface as detailed in the Gate Drive Control section below. HIGH-SIDE GATE DRIVE The high-side gate-drive outputs on GHA, GHB, and GHC are referenced to the SA, SB, and SC respectively. These outputs are designed to drive external N-channel power MOSFETs. GHx = ON (or “high”) means that the upper half of the driver is turned on and its drain will source current to the gate of the high-side MOSFET in the external motor-driving bridge, turning it on. GHx = OFF (or “low”) means that the lower half of the driver is turned on and its drain will sink current from the external MOSFET’s gate circuit to the respective Sx terminal, turning it off. The SA, SB, and SC terminals are connected directly to the motor phase connections. These terminals sense the voltages switched across the load. They are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drives. These inputs are referred to elsewhere as the Sx inputs where x is replaced by A, B, or C depending on the phase. The discharge current from the highside MOSFET gate capacitance flows through these connections which should have low-impedance traces to the MOSFET bridge. These terminals also provide the phase voltage feedback used to determine the rotor position. The CA, CB, and CC terminals are the positive supply for the floating high-side gate drives. These inputs are referred to elsewhere as the Cx inputs where x is replaced by A, B, or C, depending on the phase. The bootstrap capacitors are connected between corresponding Cx and Sx terminals. The bootstrap capacitors are charged to approximately VREG when the associated output Sx terminal is low. When the Sx output swings high, the charge on the bootstrap capacitor causes the voltage at the corresponding Cx terminal to rise with the output to provide the boosted gate voltage needed for the high-side FETs. BOOTSTRAP SUPPLY When a high-side driver is active, the reference voltage, Sx, will rise to close to the bridge supply voltage. The supply to the driver will then have to be above the bridge supply voltage to ensure that the driver remains active. This temporary high-side supply is provided by bootstrap capacitors, one for each high-side driver. These three bootstrap capacitors are connected between the bootstrap supply terminals, CA,CB, and CC, and the corresponding high-side reference terminal, SA, SB, and SC. The bootstrap capacitors are independently charged to approximately VREG when the associated reference terminal, Sx, is low. When the output swings high, the voltage on the bootstrap supply terminal, Cx, rises with the output to provide the boosted gate voltage needed for the high-side N-channel power MOSFETs. BOOTSTRAP CHARGE MANAGEMENT The A4964 monitors the individual bootstrap capacitor charge voltages to ensure sufficient high-side drive. Before a high-side drive can be turned on, the bootstrap capacitor voltage must be higher than the turn-on voltage limit. If this is not the case, then the A4964 will attempt to charge the bootstrap capacitor by activating the complementary low-side drive. Under normal circumstances, this will charge the capacitor above the turn-on voltage in a few microseconds and the high-side drive will then be enabled. The bootstrap voltage monitor remains active while the high-side drive is active, and if the voltage drops below the turn-off voltage, a charge cycle is also initiated. The bootstrap charge management circuit may actively charge the bootstrap capacitor regularly when the PWM duty cycle is very high, particularly when the PWM off-time is too short to permit the bootstrap capacitor to become sufficiently charged. If, for any reason, the bootstrap capacitor cannot be sufficiently charged, a bootstrap fault will occur—see Diagnostics section for further details. GATE DRIVE PASSIVE PULL-DOWN Each gate drive output includes a discharge circuit to ensure that any external MOSFET connected to the gate drive output is held off when the power is removed. This discharge circuit appears as 950 kΩ between the gate drive and the source connections for each MOSFET. It is only active when the A4964 is not driving the output to ensure that any charge accumulated on the MOSFET gate has a discharge path even when the power is not connected. GATE DRIVE CONTROL In some applications, it may be necessary to limit the rate of change of the voltage at the motor phase connections to help comply with EMC emission requirements. This is usually achieved by controlling the MOSFET gate charge and discharge rates. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 29 A4964 Sensorless Sinusoidal Drive BLDC Controller The conventional approach is to add an external resistor between the gate drive output and the gate connection to each MOSFET, and possibly an additional small value capacitor between the gate and source of the external MOSFET. In addition to operating in this basic switch mode drive, the A4964 gate drive output can be programmed to provide control of the slew rate of the drain-source voltage of the external power MOSFET. This is achieved by controlling the gate sink or source current during the time when the drain-source voltage is changing. This occurs during the Miller region when the gatedrain capacitance of the external MOSFET is being charged or discharged. This capacitance is referred to as the Miller capacitor and the period of time as the Miller time. MOSFET gate drives are controlled according to the values set in the slew control variables IR1, IR2, IF1, IF2, TRS, and TFS. The off-to-on transition is controlled by IR1, IR2, and TRS. The on-to-off transition is controlled by IF1, IF2, and TFS. There are two gate drive control modes, switched and slew control. All gate drives operate in the same mode. In switched mode, the gates are driven at the full capability of the pull-up or pull-down switches in the gate drive, as shown in Figure 14b. If both IR1 and IR2 are set to zero the gate drive operates in full switched mode for the off-to-on transition. If both IF1 and IF2 are set to zero, the gate drive operates in full switched mode for the on-to-off transition. In slew-control mode, the gates are driven using programmable currents to provide some control over the slew rate of the motor phase connection as shown in Figure 14a. To operate in slewcontrol mode for the off-to-on transition, both IR1 and IR2 must be non-zero. To operate in slew-control mode for the on-to-off transition, both IF1 and IF2 must be non-zero. If any of the drive currents are set to zero, then the output will operate in switched mode for the period of time when that current is active. The basic principle of the slew rate mode is to drive the gate with a controlled current for a fixed time to quickly get the MOSFET to the Miller region where the drain-source voltage, VDS, starts to change, then to follow this with a second usually lower current to control the VDS slew rate. Finally, the gate drive changes to switch mode once VDS has completed its transition. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 30 A4964 Sensorless Sinusoidal Drive BLDC Controller In slew control mode, when a gate drive is commanded to turn on, a current, IR1 (defined by IR1[3:0]), is sourced from the relevant gate drive output for a duration, tR (defined by TR[3:0]). These parameters should typically be set to quickly charge the MOSFET input capacitance such that the gate-source voltage rises close to the Miller voltage of the MOSFET. The drainsource voltage of the MOSFET will not start to change until the gate-source voltage reaches this level. After this time, the current sourced on the gate drive output is set to a value of IR2 (as defined by IR2[3:0]) and remains at this value while the MOSFET transitions through the Miller region. IR2 should be selected to achieve the required slew rate of the drain-source voltage by setting the charge time of the drain-gate (Miller) capacitor. Gate Drive Command Gate Drive OFF Source IR1 Source IR2 Sink IF1 ON tRS Sink IF2 OFF tFS VGS Miller Region Miller Region VDS Figure 14a: Off-to-On and On-to-Off Transitions with Gate Drive Control Enabled Gate Drive Command Gate Drive ON OFF OFF VGS Miller Region Miller Region VDS Figure 14b: Off-to-On and On-to-Off Transitions with Gate Drive Control Disabled Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 31 A4964 Sensorless Sinusoidal Drive BLDC Controller When the MOSFET reaches the fully on state, the gate drive output changes from current drive to voltage drive to hold the MOSFET in the on state. A high-side MOSFET is considered to be in the fully on state when the drain-source voltage, VDS (= VBB – VSx), drops below the programmed VDS threshold voltage, VDST. A low-side MOSFET is considered to be in the fully on state when the drain-source voltage, VDS (= VSx – VGND), drops below the programmed VDS threshold voltage, VDST. When a gate drive is commanded to turn off in slew control mode, a current, IF1 (defined by IF1[3:0]) is sinked to the relevant gate drive output for a duration, tFS (defined by TFS[3:0]). These parameters should typically be set to quickly discharge the MOSFET input capacitance such that the gate-source voltage drops to close to the Miller voltage of the MOSFET. The drainsource voltage of the MOSFET will not start to change until the gate-source voltage reaches this level. After this time, the current sourced on the gate drive output is set to a value of IF2 (as defined by IF2[3:0]) and remains at this value while the MOSFET transitions through the Miller region. IF2 should be selected to achieve the required slew rate of the drain-source voltage by setting the discharge time of the drain-gate (Miller) capacitor. When the MOSFET reaches the fully off state the gate drive output changes from current drive to voltage drive to hold the MOSFET in the off state. A high-side MOSFET is considered to be in the fully off state when the drain-source voltage of its complementary low-side MOSFET, VDS (= VSx – VGND), drops below the programmed VDS threshold voltage, VDST. VGS High-Side Min tDEAD VTO VGS Low-Side Min tDEAD VTO Figure 15: Minimum Dead Time A low-side MOSFET is considered to be in the fully off state when the drain-source voltage of its complementary high-side MOSFET, VDS (= VBB – VSx), drops below the programmed VDS threshold voltage, VDST. DEAD TIME To prevent shoot-through (transient cross-conduction) in any phase of the power MOSFET bridge, it is necessary to have a dead-time delay between a high- or low-side turn off and the next complementary turn-on event. The potential for cross-conduction occurs when any complementary high-side and low-side pair of MOSFETs is switched at the same time, for example, at the PWM switch point. In the A4964, the dead time for all three phases is set by the contents of the DT[5:0] bits. These six bits contain a positive integer that determines the dead time by division from the system clock. The dead time is defined as: tDEAD = n × 50 ns where n is a positive integer defined by DT[5:0] and tDEAD has a minimum value of 100 ns. For example, when DT[5:0] contains [01 1000] (= 24 in decimal), then tDEAD = 1.2 µs, typically. The accuracy of tDEAD is determined by the accuracy of the system clock as defined in the electrical characteristics table. A value of 0, 1, or 2 in DT[5:0] will set the minimum dead time of 100 ns. The value of the dead time should be selected such that the gatesource voltage of any pair of complementary MOSFETs is never above the threshold voltage for both MOSFET at the same time as shown in Figure 15. This applies in either the slew control mode or the switch mode. In the slew control mode, the dead time must be increased to accommodate the extended switching times. PWM FREQUENCY In all control modes, the base frequency of the bridge PWM signal is fixed by the value of the base PWM period, tPW. This base frequency can be altered by the frequency dither function described below. The PWM waveforms applied to each phase of the bridge can be aligned in two ways selected by the PMD bit. When PMD is set to 0, the bridge is in center-aligned mode and the three-phase PWM waveforms are centered about a common point in time, as shown in Figure 10a. When PMD is set to 1, the bridge is in edge-aligned mode and the three-phase PWM waveforms all change from low to high at the same time as shown in Figure 10b. In both modes, the period of the PWM frequency is set by the PW[5:0] variable. The six bits of PW contain a positive integer that determines the PWM period derived by division from the system clock. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 32 A4964 Sensorless Sinusoidal Drive BLDC Controller the resulting base frequency, fPW. The PWM period is defined as: tPW = 20.10 μs + (n × 0.8) μs (when PMD = 0) tPW = 20.05 μs + (n × 0.8) μs (when PMD = 1) where n is a positive integer defined by PW[5:0]. For example, when PW[5:0] = [10 0110] and PMD = 0, then tPW = 50.5 µs and the PWM frequency is 19.8 kHz. PWM FREQUENCY DITHER The A4964 includes an optional PWM frequency dither scheme that can be used to reduce the peak radiated and conducted electromagnetic (EM) emissions. This is accomplished by stepping the PWM period in a triangular pattern in order to spread the EM energy created by the PWM switching. There are three programmable variables that can be used to adjust the frequency spreading for different applications: dither step period, tΔPW, dwell time, tDD, and the number of steps in the pattern, NDS. These are identified in Figure 16. PWM Period where n is a positive integer defined by DP[2:0]. Following each change, the PWM period will remain at the new value for the duration of the dither dwell time, selected as 1 ms, 2 ms, 5 ms, or 10 ms by the contents of the DD[1:0] variable. The number of dither steps, NDS, is the value in the DS[3:0] variable. Starting at the base PWM period, the PWM period will decrease by the dither step period NDS times, then increase by the same amount and number of steps before restarting the cycle. NDS can have a value between 0 and 15. A value of 0 will disable PWM frequency dither. The minimum PWM period in any case is 18 µs. If the frequency dither settings attempt to reduce the PWM period below 18 µs, then it will be held at 18 µs until the dither sequence brings the required value above 18 µs again. Current Limit tΔPW NDS tDD time PWM Frequency t∆PW = –0.2 – (n × 0.2) µs As the frequency shift is defined by a fixed period change, the change in frequency will be slightly different for each step, but the frequency spreading effect will still be effective. tPW fPW The dither step period, tΔPW, is the incremental change in PWM period at each dither step and is defined by: tDD ΔfPW NDS time Figure 16: PWM Frequency Dither Figure 16 shows the dithered period on top and the corresponding frequency below. The PWM frequency at any time is defined by the PWM period. The base PWM period, tPW, is indicated as is An integrated fixed-frequency PWM current control circuit is provided to limit the motor current during periods where the torque demand exceeds the normal operating range, and to provide a variable current limit in the closed-loop current control mode. The frequency of the current control circuit is set to be the same as the programmed bridge PWM defined by the value of PW[5:0]. The current limit can be disabled in either of the speed control modes by setting the disable current limit bit, DIL, to 1. When the closed-loop current control mode is selected, DIL must be set to 0. The state of the current control circuit is reported by the current limit bit, CLI, in the Status register. In either of the speed control modes, the CLI bit is set to 1 when the motor current exceeds the current limit and reset to 0 when the motor current falls below the current limit. In the closed-loop current control mode, the CLI bit is set to 1 when the motor current does not reach the variable current limit and reset to 0 when the motor current reaches the variable current limit. The ground return current is measured as a voltage, VSENSE, across a sense resistor, RSENSE, placed between the supply ground and the common connection to the sources of the low-side MOSFETs in the three-phase power bridge. A sense amplifier with high common-mode rejection and a fast response time is provided Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 33 A4964 Sensorless Sinusoidal Drive BLDC Controller to convert the differential current sense voltage, directly across the sense resistor, to a ground-referenced voltage and remove any common-mode noise. The gain of the sense amplifier is programmable to provide four levels of threshold sensitivity. The maximum threshold voltage is set by the contents of the MIT[1:0] variable as follows: MIT1 MIT0 Maximum Threshold (mV) 0 0 200 0 1 100 1 0 50 1 1 25 The output of the sense amplifier is compared to a current limit threshold voltage, VILIM, to indicate to the PWM control circuit when the bridge current is greater than the current limit threshold. The value of VILIM can be set in two ways depending on the motor control method selected. When either of the speed control modes are selected, the value of VILIM is determined by: VILIM = VMIT × VISC and allow the phase currents to recirculate round the low-side MOSFETs. The MOSFETs in the bridge will remain in this state until the high-side MOSFETs are switched on again after the start of the next PWM period. CURRENT COMPARATOR BLANKING When the bridge is switching, the voltage across the sense resistor will be subject to various transient voltage spikes. To prevent these spikes from being detected as a current-limit trip, the output from the current comparator is qualified using a blanking timer to ensure that any current-limit trip that is detected is valid. The blank timer is started each time any gate drive output changes. At the end of the blank time, if the comparator is indicating that the current is higher than the trip level, then the current-limit trip is considered valid and the bridge MOSFETs will be switched as above. The length of the blank time, tOCB, is set by the contents of the OBT[4:0] variable. These four bits contain a positive integer that determines the time derived by division from the system clock. where VMIT is the maximum threshold of the sense amplifier as defined by the MIT variable, and VISC is the current limit scale as defined by the VIL variable. The blank time is defined as: When the closed-loop current control mode is selected, VILIM is determined by demand input. This sets the required value of VILIM as a ratio of the maximum threshold of VMIT. For example, when the demand input is 256 and VMIT is 200 mV then VILIM will be 50 mV. In this mode, only the 5 most significant bits of the 10-bit demand input are used to set the value of VILIM. For example if DI[9:0] = 0100000000, then the demand input is 287, and if DI[9:0] = 0100011111, then the demand input is also 287. For example, when OBT[4:0] contains [1 0110] (= 22 in decimal), then tOCB = 4.8 µs, typically. The relationship between the threshold voltage and the threshold current is defined as: ILIM = VILIM / RSENSE where RSENSE is the value of the sense resistor. At the start of a PWM cycle, the MOSFETs in the bridge are always turned on at the appropriate time to generate the required phase currents. During the PWM switching, the sum of the currents, in the phases where the low-side MOSFET for the phase is active, will pass through the sense resistor. If the current through the sense resistor increases such that the voltage across it, VSENSE, rises above VILIM, the bridge will switch off all high-side MOSFETs tOCB = (n + 2) × 200 ns where n is a positive integer defined by OBT[4:0]. Setting a value of OBT = 0, 1, 2, and 3 will set the blank time to 1 µs. The user must ensure that the blank time is long enough to mask any current transients seen by the internal sense amplifier. Motor Commutation Control The A4964 can drive a 3-phase BLDC motor using sinusoidal drive or trapezoidal drive (block commutation). Depending on the motor design, sinusoidal drive can be used to reduce audible motor noise by driving the motor with low output torque ripple. Trapezoidal drive provides the highest motor output but with an increased torque ripple at the commutation points. PWM GENERATOR A three-phase PWM generator is used to create the required waveform at each phase. When the drive mode bit, DRM, is set to 0, the PWM generator modulates (multiplies) the peak PWM duty cycle with an envelope that will create three sinusoidal Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 34 A4964 Sensorless Sinusoidal Drive BLDC Controller waveforms between the phases. When DRM is set to 1, the PWM generator drives each phase in sequence with the peak PWM duty cycle and ramps the duty cycle up and down at the beginning and end of the peak PWM duty cycle period to produce a trapezoidal drive waveform at each phase. In addition, the PWM generator can be set, using the PWM modulation bit, MOD, to drive the bridge with two-phase or three-phase modulation. When MOD is set to 0, the bridge will be driven with three-phase modulation, where all three phases will always be driven with a PWM signal. When MOD is set to 1, the bridge will be driven with two-phase modulation, where, at any instant, one phase will be held low and the other two phases driven with a PWM signal. Three-phase modulation must be enabled in order to use automatic phase advance. Two-phase modulation will reduce the switching losses in the bridge and the power dissipation in the A4964. Table 2: Trapezoidal Drive Phase Sequence Reverse Forward DIR = 1 DIR = 0 State Motor Phase SA SB SC 1 Z LO HI 2 HI LO Z 3 HI Z LO 4 Z HI LO 5 LO HI Z 6 LO Z HI HI ≡ high-side FET active, LO ≡ low-side FET active Z ≡ high impedance, both FETs off The modulation for each phase and each option is shown in Figure 6, Figure 7, and Figure 8. Figure 6 shows sinusoidal drive with three-phase modulation and Figure 7 with two-phase modulation. In both cases, although the resulting individual phase signals are not sinusoidal, they will produce sinusoidal signals between the three phases. In trapezoidal drive mode, the A4964 will ramp the phase duty cycle between the minimum and maximum duty cycles. This will produce a “soft switching” effect where the torque transitions smoothly between commutation points. If a classical trapezoidal drive is required as shown in Table 2, then set DRM to 1 for trapezoidal drive and set BW to 31 to set the bemf window to 60°. OVERMODULATION The A4964 also provides an overmodulation function, which may be used to increase the drive to the motor beyond the drive available using the pure sinusoidal drive. This function is enabled by setting a non-zero value in the overmodulation variable, OVM[1:0]. A value of 1, 2, or 3 in OVM will set the overmodulation factor to 112.5%, 125%, and 150% respectively. This overmodulation factor is applied to each setting of the PWM duty cycle sent to the bridge. For example, when OVM is set to 2, the overmodulation factor is set to 125%, and each modulation level is multiplied by 1.25, up to the 100% maximum duty cycle. The effect of this is to distort the sinusoidal waveform such that the 100% duty cycle is present for longer. This provides a similar effect to switching to trapezoidal drive, but maintains the sinusoidal waveform when the product of the overmodulation factor and the PWM level sent to the bridge is less than 100%. Overmodulation examples are shown in Figure 9. ROTOR POSITION SENSING USING MOTOR BEMF The phase sequences create a rotating magnetic field around the rotor against which the permanent magnets in the rotor can react to produce torque at the motor output shaft causing the motor to rotate. For the motor to run with low torque ripple the three phase drive has to be synchronized to the motor phase position. That is the position of the magnetic poles of the rotor in relation to the poles of the stator. This phase angle is determined by a closedloop commutation controller consisting of a position estimator and commutation timer. This controller uses the output of a complete self-contained bemf sensing scheme to determine the actual position of the motor, and adjusts the estimated position and commutation frequency to synchronize with the rotor poles in the motor. A key element of the controller is the back-emf (bemf) zerocrossing detector. This is a dedicated analog system that continuously monitors all three motor phases. It is capable of operating at high and low supply voltage with a very low bemf voltage in the presence of switching noise. This results in the ability to run a suitable motor from very low speeds to extremely high speeds. The internally generated center-tap (zero crossing reference) voltage follows the bridge drive voltage levels to allow bemf crossing detection during both PWM-on and PWM-off states. In trapezoidal drive mode, the rotor position is determined by comparing the voltage on the undriven (tri-state) motor phase (indicated by Z in Table 2) to the voltage at the center tap of the motor, approximated using an internally generated reference voltage. The voltage on the undriven phase with reference to the center tap voltage is the bemf of the motor. The bemf zero crossing, the point where the voltage of the undriven motor winding crosses the reference voltage, occurs when a pole of the rotor is in alignment with a pole of the stator and is used as a positional reference for the commutation controller. In this case, the bemf Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 35 A4964 Sensorless Sinusoidal Drive BLDC Controller for each phase is monitored for the complete commutation period where the phase is not driven. In sinusoidal drive, all three phases are being continuously driven. This does not allow for the bemf to be monitored independently of the drive signals, so the A4964 stops applying the driving signal for a brief duration close to the expected bemf crossing point. The size of this window and the number of times the window is opened per electrical cycle is programmable through the serial interface using the BW (bemf window) and BS (bemf samples) variables. The window can be programmed in 1.4° steps from 1.4° to 43.4° and to 60° when BW = 31. All angles are with respect to the electrical cycle. The window is opened just before the time at which the bemf is expected to be at the zero crossing point. In both cases the commutation controller compares the expected zero crossing point to the detected zero crossing point and adjusts the phase and frequency of the position estimator and commutation timer to minimize the difference between the expected and actual crossing points over a number of commutation periods. PHASE ADVANCE The controller also allows programmable phase advance, where the magnetic field of the stator can be driven ahead of the rotor. This can be used to produce an effect known as field weakening, which effectively reduces the bemf of the motor and allows the motor to run at a higher speed for the same applied voltage. It can also be used to optimize the efficiency of the drive by aligning the phase of the current with the phase of the applied voltage. There are two phase advance modes available: manual and automatic, selected by the phase advance mode bit, PAM. In manual phase advance mode, when PAM = 0, the angular position of the estimated bemf zero crossing point is simply adjusted to be later in the commutation period. The controller modifies the commutation timing to minimize the difference between the estimated and measured bemf zero-crossing points. This results in a phase advance of the stator field from the rotor position. In automatic phase advance mode, when PAM = 1, the angular position of the estimated bemf zero crossing point is adjusted based on the phase angle between the applied voltage waveform and the motor current. In this mode, when the programmed phase angle is set to zero, the A4964 will adjust the estimated bemf zero crossing point such that the angle between the motor phase current and applied phase voltage is zero. The programmed phase advance angle will then be the angle between the motor phase current and applied phase voltage. The automatic phase advance mode will adjust the estimated bemf zero crossing point to achieve the optimum performance across a wide range of speeds, loads and supply voltages and temperatures without having to update the phase angle as would be required in the manual mode. The gain of the control loop for the automatic phase advance can be adjusted by the KIP[1:0] variable to 1, 2, 4, or 8. A higher value will result in a faster change but less stability. A lower value will result in greater stability but a slower response to speed, voltage, and load variations. COMMUTATION CONTROLLER TUNING The commutation controller uses proportional and integral feedback (PI control) to provide a fast response with good long-term accuracy. The proportional and the integral gains can be adjusted independently for operation in the steady state and in the transient state. The commutation control loop is defined to be in steady state when the difference between the estimated motor speed and the target motor speed is less than 10 Hz. When the difference increases to greater than 10 Hz, the control loop is defined to be in the transient state. Once in the transient state, the speed difference must reduce below 5 Hz before the control loop returns to the steady state. In the steady state, the proportional and integral control loop gains are set by the CP[3:0] and CI[3:0] variables respectively, through the serial interface. In the transient state, the proportional and integral control loop gains are set by the CPT[3:0] and CIT[3:0] variables respectively. This allows the dynamic response of the commutation controller to be tuned to different system conditions if required. The control method used is tolerant to missing bemf zero crossing detection and will simply change the speed of the applied commutation sequence by an amount determined by the proportional gain of the control loop. This results in a much more stable system that does not lose synchronization due to impulse perturbations in the motor load torque. It also means that real loss of synchronization cannot be determined by missing bemf zero crossing detection and has to be determined in a different way. In the extreme case when a motor stalls due to excessive load on the output, there will be no bemf zero crossing detection and the frequency of the commutation sequence will be reduced at each commutation point to try and regain synchronization. If the resulting speed reduces below the low-speed threshold, set by the SL[3:0] variable, then the controller will enter the loss of synchronization state and either stop or attempt to restart the motor. In some cases, rather than a complete stall, it is also possible for the motor to vibrate at a whole fraction (subharmonic) of the commutation frequency produced by the controller. In this case, Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 36 A4964 Sensorless Sinusoidal Drive BLDC Controller the controller will still detect the bemf zero crossing but at a rate much higher than the motor is capable of running. If the resulting speed increases above the overspeed threshold, set by the SH[3:0] variable, then the controller will enter the loss of synchronization state and either stop or attempt to restart the motor. MOTOR STARTUP The sensorless commutation method used in the A4964 relies on the motor bemf voltage. This voltage must be high enough to allow detection of the zero crossing point. When the motor is stationary, or moving at very low speed, the bemf is either zero or at a level lower than can be detected by the bemf zero crossing detector, so the motor position cannot be determined. This means that a startup sequence must be used that will start the motor rotating and accelerate the motor to a sufficiently high speed for bemf zero crossings to be detected. This must be done without reference to the actual motor position. To achieve reliable startup over a wide range of motors, loads, supply and environmental conditions, the A4964 provides multiple programmable startup features. The basic sequence starts by checking the motor bemf to determine if the motor is already rotating. If so, special pre-rotation functions are implemented as described below. If no rotation is detected, then the normal startup sequence consists of an alignment time followed by open-loop commutation with increasing speed, then a short coast period before switching into the closed-loop commutation control system and the closed-loop speed control, if selected. Each of the startup features has several programmable variables, and the alignment and coast features can be completely disabled. The complete sequence is shown in Figure 17. ALIGNMENT The alignment feature can be used to move the motor into a known position. This helps to achieve a consistent startup pattern and helps avoid noise in the initial stages of the startup sequence. The duration of the alignment time (also known as hold time) is determined by the value of the HT[3:0] variable. If the alignment feature is not required, then it can be disabled by setting HT[3:0] to zero. During the alignment, the peak duty cycle is set to the value defined by the HD[4:0] variable. The peak value is then modified by the PWM generator to produce the duty cycles at each phase for the 0° position shown in Figure 6 and Figure 7. For two-phase modulation, the peak duty cycle for each phase is defined as: Phase A = (DH ÷ 2)% Phase B = 0 Phase C = DH% For three-phase modulation, the peak duty cycle for each phase is defined as: Phase A = 50% Phase B = 50% – (DH ÷ 2)% Phase C = 50% + (DH ÷ 2)% where DH is the peak PWM duty during alignment defined by HD[4:0]. The time to rise from zero to the programmed value can be selected as a percentage of the alignment time by the HR[1:0] variable. This can be 0%, 25%, 50%, or 100%. At 0%, the programmed value will be present for the full alignment time. For example, at 25%, it will ramp from zero to the programmed value for the first 25% of the alignment time, then hold at the programmed value for the remainder of the alignment time. At 100%, it will ramp from zero to the programmed value over the full alignment time. The integrated current limit remains active, if enabled, during the hold time in order to limit the inrush current and to limit the effects of increased supply voltage or low operating temperature. RAMP Following the alignment time, sinusoidal (DRM = 0) or trapezoidal (DRM = 1) waveforms are applied to the three phases to create a rotating magnetic field in the motor and start the motor running in the required direction. During this time, the motor position is ignored and the motor phases are driven in open-loop commutation mode. The starting speed of the rotating field is defined by the SF1[3:0] variable and the speed is ramped up linearly until it reaches the ramp end speed defined by SF2[3:0]. The slope of the speed ramp and the duration are defined by the speed increment, fSS, defined by the SFS[3:0] variable, and the step time, tSS, defined by the STS[3:0] variable. All speed variables define the electrical frequency as defined by the electrical period shown in Figure 6, and are set in hertz. When the ramp starts, the peak duty cycle applied to the bridge is defined by the contents of the SD1[3:0] variable. The peak duty cycle is then increased linearly up to the peak duty cycle applied to the bridge, defined by the contents of the SD2[3:0] variable at the end of the ramp. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 37 A4964 Sensorless Sinusoidal Drive BLDC Controller COAST At the end of the ramp period, if the STM bit is set to 1, the outputs will be disabled and the motor will coast for a short time. During this time, the motor bemf is sensed and the zero-crossing point detected in order to correctly synchronize the motor phase angle counter to the motor position and the drive frequency to the motor speed. Once three correct synchronization events have been detected, the motor phase drive is re-enabled and the motor runs with closed-loop commutation. Rotor Speed / bemf time Stator Field Frequency SFS SF2 STS time SF1 SD2 Bridge PWM Duty Cycle SD1 HD time HT Ramp Coast Align Accel. Run Closed-Loop Figure 17: Sensorless Start Sequence Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 38 A4964 Sensorless Sinusoidal Drive BLDC Controller To ensure a smooth transition into the full commutation closedloop operation, the peak duty cycle applied to the power bridge should be close to the duty cycle required for the present motor speed. This avoids large inrush or braking currents as the drive is re-enabled. The required duty cycle is determined using the measured motor speed, the speed resolution and the motor constant, KM, as: b fE × KM l 0. 1 DPK = × 100 (%) 1023 where DPK is the peak duty cycle applied to the bridge, fE is the motor electrical cycle frequency and KM is the motor constant set by the value in the KM[3:0] variable and can be between 0.3 and 1.05 in steps of 0.05. The actual motor motor electrical cycle frequency, fE, is defined by: fE = n × SR (Hz) where SR is the speed resolution defined by the SR[2:0] variable and n is a positive integer defined by DO[9:0] when RBS[2:0] = [001]. Calculation of the correct duty cycle is also used during the windmill detection phase if enabled. In many systems where the motor and load inertia is low and the friction load is high, it is more effective to go directly from ramp to closed-loop commutation without the coast period. In this case, STM can be set to zero to disable the coast function during startup. The coast function during startup is beneficial for high inertia loads such as fans and blowers and helps provide a low audible noise startup. Once in commutation closed-loop mode, the A4964 will synchronize the applied field, created by the motor phase angle counter and the sinusoidal PWM generator, to the motor position and ramp the speed to match the demand input. START WITH PRE-ROTATION (WINDMILLING) In some cases when motor start is required, the motor may still be coasting from a previously running state or it may be rotating by the action of the load on the motor. Setting the WIN bit to 1 will modify the startup sequence by initially monitoring the motor bemf for windmill bemf zero-crossing events in order to detect any prerotation. A windmill bemf zero-crossing event must be present for longer than the windmill bemf filter time, tbf, for the motor speed and direction to be determined. The windmill bemf fiter time is set through the serial interface using the BF variable. The motor speed is available from the readback register during this time. If no windmill bemf zero-crossing events are detected within 300 ms or the motor speed is less than the minimum windmill detection frequency, fWMF, defined by the WMF[3:0] variable, then the motor is assumed to be stationary and the normal start sequence is followed. If WIN is set to 0, then any pre-rotation will be ignored and the normal start sequence followed. If the bemf indicates that the motor is running in the opposite direction to that programmed, then a brake torque is applied by applying a PWM signal to all low-side MOSFETs until the bemf indicates that the motor is stationary. The low-side MOSFETs are switched at the programmed PWM frequency with the window brake duty cycle, DWB, defined by the contents of the WBD[3:0] variable. Once the motor speed is less than fWMF, then the motor is assumed to be stationary and the normal start sequence is followed. If the bemf indicates that the motor is running in the same direction to that programmed, then the alignment and ramp functions are not used and the startup sequence goes directly to coast and synchronization before switching directly to full commutation closed-loop operation. Motor Control Modes There are three motor control methods included in the A4964. These are: 1. open-loop speed (voltage) control 2. closed-loop torque (current) control 3. closed-loop speed control The control mode and all associated parameters are determined by the contents of the configuration and control registers. These registers can be changed on-the-fly through the SPI. The userdefined values in these registers are held in programmable non-volatile memory, allowing the A4964 to be pre-programmed with default values for a specific appliction and avoid the need to program the register contents at each power on. The motor movement can be controlled directly through the SPI or, in standalone mode, by a PWM applied to the LIN terminal. In SPI operating mode, selected by setting the OPM variable to 0, the running state, direction, and output of the motor are controlled by a combination of commands through the serial interface. These are a demand input variable, DI[9:0], plus three control bits, RUN, DIR, and BRK. In stand-alone operating mode, selected by setting the OPM variable to 1, the output of the motor is controlled by the duty cycle of a PWM input, which sets the value in the DI[9:0] demand input variable. The three control bits, RUN, DIR, and BRK can still control the running state of the motor through the serial interAllegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 39 A4964 Sensorless Sinusoidal Drive BLDC Controller face but the demand input is only accepted from the PWM signal applied to the LIN terminal. All configuration parameters can be modified in either mode. When RUN = 1, the A4964 is allowed to run the motor or to commence the startup sequence. When RUN = 0, all gate drive outputs go low, no commutation takes place, and the motor is allowed to coast. RUN = 0 overrides all other control inputs. The DIR bit determines the direction of rotation. Forward is defined as DIR = 0, reverse is when DIR = 1. The forward and reverse waveforms are defined in Figure 6, Figure 7, Figure 8, and Table 2. In SPI operating mode, the BRK bit can be set to apply an electrodynamic brake which will decelerate a rotating motor. It will also provide some holding torque for a stationary motor. When RUN = 1 and BRK = 1, all low-side MOSFETs will be turned on and all high-side MOSFETs turned off, effectively applying a short between the motor windings. This allows the reverse voltage generated by the rotation of the motor (motor bemf) to set up a current in the motor phase windings that will produce a braking torque. This braking torque will always oppose the direction of rotation of the motor. The strength of the braking or holding torque will depend on the motor parameters. No commutation takes place during braking and no current control is available. Care must be taken to ensure that the braking current does not exceed the capability of the low-side MOSFETs. In stand-alone operating mode, the BRK bit does not directly control braking, but can be set to enable braking when the PWM input is held low as described below. The 10-bit demand input variable, DI[9:0], sets the bridge PWM duty cycle for the open-loop speed control mode, the torque (current) reference for the current control mode, or the speed reference for the closed-loop speed control mode. For the speed control modes, the resolution is better than 0.1%. For the current control mode, only the most significant 8 bits are used and the demand input resolution is 0.5%. In standalone operating mode, DI[9:0] cannot be changed through the serial interface. PWM CONTROL INPUT In the stand-alone operating mode, selected by setting OPM to 1, the function of the LIN input terminal changes to a PWM input, the duty cycle of which provides a proportional demand input for the selected control mode and replaces the contents of DI[9:0]. It can be driven between ground and VBB and has hysteresis and a noise filter to improve noise performance. The sense of the PWM input can be selected as active high or active low using the IPI bit. When IPI is 0, the LIN input is active high. When IPI is 1, then the LIN input is inverted and active low. The PWM input, applied to the LIN terminal, is a low frequency signal, between 5 Hz and 1 kHz. The duty cycle of this signal is measured with a 10-bit counter system, giving better than 0.1% resolution in duty cycle. When IPI is 0, the duty cycle is the ratio of the PWM (active) high duration to the PWM period measured between rising edges of the PWM input signal. When IPI is 1, the duty cycle is the ratio of the PWM (active) low duration to the PWM period measured between falling edges of the PWM input signal. The measured duty cycle is written to the DI[9:0] variable at the end of each PWM measurement period when the PWM signal changes back to the active state. The A4964 can accept slight variation in the PWM frequency from cycle to cycle. However, any variation will be translated to a demand input variation. In standalone operating mode, the DIR and RUN bits still control the motor direction and activity. RUN must be set to 1 to permit the PWM input to control the motor output. The function of the BRK bit function changes to be a PWM brake enable as described below. When the PWM input changes from the inactive state, with DI = 0 and the motor in the brake or coast mode, the first write to DI will occur at the end of the first PWM cycle if the duty cycle is less than 100%. If the duty cycle is 100%, i.e. the PWM input goes from inactive to active, the first write to DI will occur at the end of the PWM timeout period, tPTO. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 40 A4964 Sensorless Sinusoidal Drive BLDC Controller inactive for a further PWM period, as shown in Figure 18, will force a brake condition if BRK is set to 1. The brake condition can only be active when RUN = 1 and BRK = 1. PWM DI[9:0] 0 512 Action Brake/Coast* Start & Run tPWM tPWM tPWM PWM DI[9:0] 512 1023 Action 810 Run tPTO PWM DI[9:0] 0 1023 Action Brake/Coast* 810 Start & Run tPTO tPTO 0 Action Brake/Coast* tPWM 1023 0 Start & Run Coast Brk/Ckst* tPWM tPWM For single-wire control systems, the DIAG output can be connected directly to the LIN terminal or to the LTX input to force the PWM signal, applied to the LIN terminal, into a low state in order to inform the remote ECU controlling the A4964 that a fault condition exists. As the PWM signal is always pulled low, the active high PWM input mode (IPI = 0) should be selected for this configuration. For the simple (active-low fault flag) DIAG mode, selected when DGS[1:0] is 0, a fault will pull the PWM signal low. This will simply stop the motor until the fault clears or is reset. tPTO PWM DI[9:0] Once enabled, the brake condition will be held until the PWM terminal is changed to its active state. If the motor operation is enabled, with RUN = 1, then the A4964 will initiate a start sequence once the PWM duty cycle is in the correct range to permit the start. During the start sequence, if the PWM signal is held inactive as described above, then the start sequence will be terminated and, if enabled, the brake condition will be forced. tPWM PWM DI[9:0] 303 0 Action Run Coast Brake/Coast* * Brake active is BRK = 1 Figure 18: PWM Timing (IPI = 0; PWM active high) When the duty cycle changes from a value less than 100% to 100%, the write of the maximum value 1023 to DI will occur after two tPWM periods from the previous inactive to active transition. When the PWM duty cycle changes back to a value less than 100%, the maximum value will remain in DI until the end of the first full PWM period at the second inactive to active transition after the 100% input. If the PWM signal remains in the inactive state for more than twice the length of time of the last measured period, then the A4964 will put the bridge into the PWM-off state permanently and allow the motor current to decay. Holding the PWM signal For the mode where DIAG is high for no fault and pulsed low when a fault is present (DGS[1:0] = [10]), the PWM duty cycle detector will ignore the PWM input signal when DIAG is low and maintain the value in DI at the previously detected level. DI will be updated at the end of the first full PWM period after DIAG goes high. The PWM period time is maintained from the previous duty cycle detection and is available when DIAG goes high to permit detection of an intended low level on the PWM signal, indicating a zero demand input. For the other two DIAG modes, the DIAG output should not be used to pull the LIN terminal low, as the FG signal will interfere with the PWM signal causing unpredictable results. See Diagnostics section for additional detail. OPEN-LOOP SPEED (VOLTAGE) CONTROL In motor control systems where application specific speed control is required the A4964 provides a simple variable duty PWM control mode. In this mode the demand input is directly converted to the duty cycle of the PWM applied to the motor bridge as shown in figure 19. The frequency of the PWM signal applied to the power bridge is determined by the value of the PW[5:0] variable. The resulting bridge PWM duty cycle is used as the peak duty cycle and is further modulated by the 3-phase sine or trapezoidal generator. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 41 A4964 Sensorless Sinusoidal Drive BLDC Controller phase trapezoidal mode with a 60° bemf window. 100% Bridge PWM Duty Cycle When operating in the current control mode, the demand input linearly adjusts the current limit threshold voltage, between 0 and VMIT as defined by the MIT variable. Although the demand input is 10 bits, only the 5 most significant bits will be effective. 0 0 Demand Input 1023 Figure 19: Bridge PWM versus Demand Input This control mode is equivalent to voltage mode or open-loop speed control. In this mode, the speed is not regulated and will vary with load and supply voltage. Current limiting will remain active if enabled. The A4964 does not limit the minimum or maximum peak duty cycle applied to the bridge. At 100% demand input, the motor will be running at full speed as determined by the load and the applied voltage. At very low duty cycles, there may not be sufficient current flowing in the motor to maintain sufficient speed for sensorless operation. However, the A4964 will not limit the minimum applied duty cycle in order to provide full flexibility for the speed control ECU to manage the motor operation. If the motor speed drops below the underspeed threshold, fSL, then the A4964 will indicate the loss of synchronization condition. If a loss of synchronization occurs when the RUN and RSC bits are set to 1, and the demand input is not 0%, then the start sequencer is reset and the start sequence immediately initiated. This cycle will continue until stopped by setting the demand input to 0 or setting either the RUN bit or the RSC bit to 0. If a loss of synchronization occurs and RSC = 0, the A4964 will remain in the loss of synchronization state until the demand input is set to 0%, the RUN bit is set to 0, or a serial read of the Status register with DSR = 0 occurs. CLOSED-LOOP TORQUE (CURRENT) CONTROL The fixed-frequency current limiting feature described above can be used to provide a closed-loop torque control by varying the current reference threshold voltage. Current control can be used in any of the drive modes, but the most accurate phase current control will only be achievable when the motor is driven in two- Current Limit Threshold VMIT 0 0 Demand Input 1023 Figure 20: Current Limit versus Demand Input If the motor load exceeds the available torque for the demanded current limit, then the motor speed will drop until the motor load matches the available torque. If the motor speed drops below the underspeed threshold, then the A4964 will indicate the loss of synchronization condition. If this condition occurs when the RUN and RSC bits are set to 1, and the demand input is not 0%, then the start sequencer is reset and the start sequence is immediately initiated. This cycle will continue until stopped by setting the demand input to 0 or setting either the RUN bit or the RSC bit to 0. If a loss of synchronization occurs and RSC = 0, the A4964 will remain in the loss of synchronization state until the demand input is set to 0%, the RUN bit is set to 0 or a serial read of the Status register with DSR = 0 occurs. CLOSED-LOOP SPEED CONTROL The A4964 includes a speed control loop to provide constant speed under varying supply, load, and temperature conditions. The required motor speed, fREF, is the product of the demand input and the speed control resolution defined by the SR[2:0] variable as defined by: fREF = DI × SR (Hz) where fREF is the required reference speed in Hz, DI is the 10-bit demand input, and SR is the speed resolution in Hz. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 42 A4964 Sensorless Sinusoidal Drive BLDC Controller The reference frequency defines the motor speed as the electrical cycle frequency. The motor speed in rpm can be calculated from: fE × 60 ~M = N PP where ωM is the motor speed in rpm, fE is the electrical cycle frequency, and NPP is the number of magnetic pole pairs in the motor. The maximum value of fREF for each value of SR is listed in table 3, which also shows the equivalent motor speed (in rpm) for several motor pole-pair options. The closed-loop speed controller compares the required reference speed to the motor speed. It then adjusts the duty cycle of the PWM signal applied to the bridge in a controlled manner until the motor speed matches the reference speed. Reference Speed fMAX SF2 Demand Input fRES (Hz) fMAX (Hz) 1 2 3 4 6 0 0.1 102.3 6138 3069 2046 1535 1023 1 0.2 204.6 12276 6138 4092 3069 2046 2 0.4 409.2 24552 12276 8184 6138 4092 3 0.8 819.4 49104 24552 16368 12276 8184 4 1.6 1636.8 98208 49104 32736 24552 16368 5 3.2 3273.6 – 98208 65472 49104 32736 As the reference speed reduces, the motor speed will follow until it is too low to maintain sensorless operation and the motor speed drops below the underspeed threshold set by the SL[3:0] variable. At this point, the A4964 will turn off all bridge MOSFETs, allowing the motor to coast. The LOS bit will be set to 1, indicating a loss of synchronization. If a loss of synchronization occurs when the RUN = 1 and RSC = 1 and when the demand input sets the reference speed to greater than SF2, then the start sequencer resets and the start sequence is initiated. This cycle will continue until stopped by setting the demand input to zero or setting either the RUN bit or the RSC bit to 0. No restart Coast Motor 0 Motor Pole-Pairs (Speed in rpm) SR If a loss of synchronization occurs and RSC = 0, the bridge MOSFETs will remain in this state until demand input is set to 0 or the RUN bit is set to 0. Restart operates if enabled 0 Table 3: Speed Range and Resolution 1023 Figure 21: Reference Speed versus Demand Input The relationship between the demand input and the motor reference speed is shown in Figure 21. As the demand input increases from 0 the bridge drive will be disabled allowing the motor to coast. This output state will remain until the reference speed is greater than the start ramp end speed set by SF2, at which point the start-up sequence is initiated and the motor is allowed to run. Once sensorless operation is achieved the motor speed will change to match the reference speed determined by the demand input. The speed then continues to match the demand without being affected by varying the steady-state supply voltage or load up to the torque limit. The torque limit is imposed by either the peak current limiter or effective applied voltage limited by the motor bemf. When using closed-loop speed control, the A4964 will continue to provide current limiting using the internal fixed-frequency current limiter. SPEED CONTROL DYNAMIC RESPONSE The dynamic response of the speed controller can be tuned to the motor and load dynamics using three variables: SG[3:0], SGL[4:0], and DF. The speed control loop operates as a sampled system where the sampling rate is the bridge PWM frequency. The bridge peak duty cycle is altered based on the value of the speed error and both are updated each bridge PWM period. When the motor speed is close to the reference speed, the control loop response is determined by the gain factor set by the SG[3:0] variable. This gain multiplies the speed error—the difference between the motor speed and the reference speed—to increase Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 43 A4964 Sensorless Sinusoidal Drive BLDC Controller or decrease the peak PWM duty cycle applied to the bridge. This causes the motor to accelerate or decelerate to minimize the speed error. The amount of acceleration or deceleration is therefore determined by the product of the speed error and the gain determined by SG. In general, the gain setting can be higher for low-inertia motor/load combinations with a high dynamic response and will be lower for high-inertia motor/load combinations with a low dynamic response. Speed When there is a large difference between the motor speed and the reference speed—for example, when a large step change in speed is required—the error will be large and this will cause a large change to the peak duty cycle applied to the bridge. If the speed change is from a low speed to a high speed, then the step change in the bridge PWM duty cycle will cause a large increase in current to provide the high acceleration torque to increase the speed of the motor. This sudden large increase in acceleration torque may cause an increase in audible noise or even some instability and speed overshoot. To avoid these undesirable outcomes, the maximum acceleration is limited by limiting the maximum speed error using the SGL[4:0] variable and SG[3:0] variable. This will limit the speed error value that used to determine the peak value of the bridge PWM and will in turn limit any step increase in the peak duty cycle and the resulting torque and acceleration. As for the gain setting variable, the error limit value can be higher for low-inertia motor/load combinations with a high dynamic response and will be lower for high-inertia motor/load combinations with a low dynamic response. Speed Loop in Control using SG case, this sudden large increase in deceleration torque may cause an increase in audible noise, some instability and possibly speed undershoot. To avoid this, the maximum deceleration is also limited by limiting the maximum speed error using the SGL[4:0] variable and SG[3:0] variable. However, in addition to these common effects of speed change, deceleration produces an additional undesirable outcome. During deceleration, the current will flow in the reverse direction back to the bridge supply. This reverse current may cause an increase in the bridge voltage depending on the ability of the bridge supply to absorb the energy delivered by the current. If the energy cannot be absorbed either by the supply or by any capacitors connected to the supply then the voltage may reach dangerous levels. To limit this effect, the deceleration factor variable, DF[1:0], can be used to enforce a lower deceleration limit in proportion to the acceleration limit. The acceleration limit is determined by the value of SGL × SG, and the deceleration limit by (SGL × SG) / DF. In general, the deceleration factor setting can be set to 1 for low-inertia motor/load combinations and to a higher value for high-inertia motor/load combinations. In cases where the supply is capable of absorbing the motor energy from the reverse current, for example high performance battery powered systems or systems with large low impedance supply capacitors, the value of DF[1:0] can also be set to 1. The effect of the acceleration and deceleration limits and dynamic limits are shown in Figure 22. SUPPLY VOLTAGE COMPENSATION Any change in the bridge supply voltage will change the relationship between applied duty cycle and resulting drive output. The two closed-loop control modes of the A4964 will automatically compensate for these changes if the rate of change is less than the response time of the control loop. However, the rate of change is faster than the control loop response time, then there will be a transient disturbance in the motor speed or torque output. Motor Speed Deceleration limited by (SGL × SG) / DF Speed Demand Acceleration limited by SGL × SG Time Figure 22: Speed Control Dynamic Response Limits If the speed change is from a high speed to a low speed, then the resulting step change in the bridge PWM duty cycle will attempt to apply a large reverse current to provide the high deceleration torque to reduce the speed of the motor. As for the acceleration To overcome these effects, the A4964 includes a duty cycle voltage compensation function for two nominal voltage levels, 12 V and 24 V. The nominal voltage is the bridge supply voltage at which the bridge duty cycle is unaltered. When the bridge supply voltage rises above the nominal voltage, then the bridge duty cycle is reduced in proportion. When the bridge supply voltage falls below the nominal voltage, then the bridge duty cycle is increased in proportion. Supply voltage compensation is only applied to the open-loop and closed-loop speed modes, and operates continuously when enabled. For the closed-loop speed mode, this means that any transient disturbance in the motor speed, caused by the change Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 44 A4964 Sensorless Sinusoidal Drive BLDC Controller in supply voltage, will be minimized. For the open-loop speed mode, it means that the duty cycle applied to the bridge will be continuously modulated to maintain the same effective voltage applied to the motor. Supply voltage compensation is not required for the closed-loop current control mode. In this mode, the current is controlled on a PWM cycle-by-cycle basis and is therefore unaffected by any change in supply voltage. The range of bridge supply voltage over which the duty cycle compensation is effective is limited in each case. For the 12 V nominal selection, the range is 7 V to 19 V. For the 24 V nominal selection, the range is 14 V to 38 V. The function is enabled and the nominal voltage selected by the contents of the DV[1:0] variable. When DV[1:0] = [0,0], the duty cycle compensation feature is disabled. When DV[1:0] = [0,1] or [1,1], the nominal voltage is 12 V. When DV[1:0] = [1,0], the nominal voltage is 24 V. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 45 A4964 Sensorless Sinusoidal Drive BLDC Controller Diagnostics programmable level. Multiple diagnostic features provide fault monitoring for the basic chip status, for the state of the external bridge and for the motor control function. Most of the non-critical diagnostics can be masked by setting the appropriate bit in the mask register. The detectable faults are listed in table 5.The fault status is available through the serial interface or through the DIAG output. The serial output, SDO, can also be programmed to provide a divided version of the system clock that can be used for clock frequency verification or system calibration. The status and diagnostic registers are described further in the serial interface section description below. DIAG OUTPUT DIAG is a battery-compliant open-drain pull-down output that provides the following four optional signals selected by the DGS[1:0] variable: DGS = 0: An active-low fault flag which will be low when a fault is present or a fault state is latched. SERIAL STATUS REGISTER DGS = 1: An FG speed signal providing a square wave at the electrical cycle frequency. The serial interface allows detailed diagnostic information to be read from the Status register at any time. DGS = 2: Time-based pulses to differentiate the fault groups as described in table 5 below. DIAG will be inactive when no fault is present. The first bit (bit 15) of the Status register contains a common fault flag, FF, which will be high if any of the fault bits in the registers have been set. This allows fault condition to be detected using the serial interface by simply taking STRn low. As soon as STRn goes low, the first bit in the Status register can be read to determine if a fault has been detected at any time since the last Status or Diagnostic register reset. In all cases, the fault bits in the diagnostic registers are latched and only cleared after the associated fault bit is read through the serial interface with DSR = 0. DGS = 3: Time-based pulses to differentiate the fault groups as described in table 5 below. DIAG will output the FG signal when no fault is present. When operating in stand-alone mode and DGS = 0 or 2, DIAG can be externally connected directly to the LIN terminal or to the LTX input to superimpose the fault information onto the PWM input. When DGS = 2, the PWM input duty cycle detection will ignore the state of the PWM signal when DIAG is low and maintain the last detected demand input. DIAGNOSTIC REGISTER The diagnostic register provides additional details of any VDS overvoltage or bootstrap undervoltage faults. It also provides an indication when the reported motor speed is above the maximum Further details on using the DIAG output for error reporting are provided in the applications section in this datasheet. Table 4: DIAG Pulse Definition and Fault Allocation DGS[1:0] 00 Fault Description 01 Fault Group 10 11 DIAG Output Priority No Fault Serial Error No Fault H FG H FG – System L FG L L 5 Undervoltage L FG L: 2.5 s / H: 1 s L: 2.5 s / H: 1 s 4 Over Temperature Temperature L FG L: 2 s / H: 1 s L: 2 s / H: 1 s 3 VDS Overvoltage Short Detect L FG L: 1 s / H: 1 s L: 1 s / H: 1 s 2 Loss of Synchronization Motor lock L FG L: 1.5 s / H: 1 s L: 1.5 s / H: 1 s 1 VBB POR Temperature Warning System Error VBB Undervoltage VLR Undervoltage VREG Undervoltage Bootstrap Undervoltage Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 46 A4964 Sensorless Sinusoidal Drive BLDC Controller DIAG FAULT WAVEFORMS Table 5 lists the output signal on the DIAG terminal for each fault and each setting of DGS. The faults are grouped into six groups. When DGS = 0, the DIAG output will be low when any fault is present. When DGS = 1, the FG speed signal will be present on DIAG. The FG signal will remain high when the motor is stationary. When DGS = 2 or 3, the faults are reported in six groups. Each group has a unique timing combination of low (active pull-down) and high (passive pull-up). If a fault is present when DGS = 2 or 3, the fault groups will be identified by the length of time that the DIAG output will be low. Except in the case of a system error, the DIAG output will be high for 1 second between each identifying time, ranging from 1 second to 2.5 seconds. The fault groups are each assigned a priority from 1 (low) to 5 (high); when more than one fault is present, the highest priority fault is reported. If system error is present, the DIAG output will be held low. FAULT ACTION The action taken for each fault is listed in Table 5a, Table 5b, and appendix A. When a fault is detected, a corresponding fault state is considered to exist. In some cases, the fault state only exists during the time the fault is detected. In other cases, when the fault is only detected for a short time, the fault state is latched (stored) until reset. The faults that are latched are indicated in Table 5. Some latched fault states are reset with specific actions, but all fault states are always reset when a power-on-reset state is present or when the associated fault bit is read through the serial interface with DSR = 0. Any fault bits that have been set in the diagnostic registers are only reset when a power-on-reset state is present or when the associated fault bit is read through the serial interface with DSR = 0. The fault conditions VBB POR (power-on-reset) and VREG undervoltage are considered critical to the safe operation of the A4964 and the system. If these faults are detected, then the gate drive outputs are automatically driven low and all MOSFETs in the bridge held in the off state. This state will remain until the fault is removed. Table 5a: Fault Response Actions (ESF = 0, no faults masked) Fault Description Disable Outputs RSC[7] Other Action Fault State Reset Re-enable Outputs No Fault No n/a n/a None n/a System Error Yes [1] n/a Yes RUN = 0 POR, RUN = 1 Serial Error No n/a No None POR or SPI [3] n/a n/a No Internal logic shutdown and reset Condition removed RUN = 1 0 Yes Demand input = 0, RUN = 0 or SPI [3][4] n/a 1 No Condition removed 0 Yes MCU reset First watchdog transition after 100 ms from MRSTn going high 1 Yes MCU reset First watchdog transition after 100 ms from MRSTn going high VBB POR Yes [1] VBB Undervoltage No VLR Undervoltage Yes [1] 1 Yes n/a No None n/a No None n/a No None No None VREG Undervoltage Yes [1] Bootstrap Undervoltage Yes [2] Temperature Warning No Overtemperature No n/a Yes [1] VDS Overvoltage Yes [2] Demand input reset [5], RUN reset [6], or SPI [3][4] First watchdog transition after 100 ms from MRSTn going high Condition removed PWM on Condition removed n/a Condition removed n/a Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] 0 Yes None 1 No Stop and restart Condition removed n/a No None PWM on gate drives low, all MOSFETs off. drive for the affected MOSFET low, only the affected MOSFET off. [3] Only when DSR = 0. [4] Serial read of Status or Diagnostic register. [2] Gate Demand input reset [5], RUN reset [6], or SPI [3][4] First watchdog transition after 100 ms from MRSTn going high Yes Yes [1] Loss of Synchronization None 0 Watchdog Fault [1] All Fault State Latched SPI [3][4] [5] Set demand input = 0 then set demand input to a new operating value. RUN bit = 0 then set RUN bit = 1. [7] Restart control bit. [6] Set Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 47 A4964 Sensorless Sinusoidal Drive BLDC Controller Table 5b: Fault Response Actions (ESF = 1, no faults masked) Fault Description Disable Outputs RSC[7] Fault State Latched Other Action Fault State Reset Re-enable Outputs No Fault No n/a n/a None n/a System Error Yes [1] n/a Yes RUN = 0 POR, RUN = 1 Serial Error No n/a No None POR or SPI [3] n/a VBB POR Yes [1] n/a No Internal logic shutdown and reset Condition removed RUN = 1 Yes Demand input reset [5] or RUN reset [6] VBB Undervoltage 0 Demand input = 0 or RUN = 0 Yes [1] 1 No VLR Undervoltage Watchdog Fault Yes [1] Yes [1] 0 Yes 1 Yes 0 Yes 1 Yes None SPI [3][4] Condition removed MCU reset First watchdog transition after 100 ms from MRSTn going high Demand input reset [5], RUN reset [6], or SPI [3][4] First watchdog transition after 100 ms from MRSTn going high MCU reset First watchdog transition after 100 ms from MRSTn going high Demand input reset [5], RUN reset [6] or SPI [3][4] First watchdog transition after 100 ms from MRSTn going high VREG Undervoltage Yes [1] n/a No None Bootstrap Undervoltage Yes [1] n/a Yes None Temperature Warning No n/a No None Condition removed n/a Overtemperature Yes [1] 0 Yes First watchdog transition after 100 ms from MRSTn going high Demand input reset [5], RUN reset [6], or SPI [3][4] 1 Yes VLR regulator shutdown and MCU reset Loss of Synchronization Yes [1] VDS Overvoltage Yes [1] 0 Yes None 1 No Stop and restart n/a Yes None [1] All gate drives low, all MOSFETs off. drive for the affected MOSFET low, only the affected MOSFET off. [3] Only when DSR = 0. [4] Serial read of Status or Diagnostic register. [2] Gate VBB undervoltage is not considered critical and the action taken depends on the state of the enable stop on fault bit, ESF. If a VBB undervoltage condition exists and ESF = 1, the gate drive outputs will be disabled and the motor will coast until the condition is removed. If the restart bit, RSC, is set to 1, then the motor will restart when the VBB undervoltage condition is removed. If RSC = 0, the motor will remain stationary until: • Demand input is set to 0 and then set to a new operating value (demand input reset), • RUN bit is set to 0 then RUN bit is set to 1 (RUN reset), • Status register is read through the serial interface with DSR = 0, or • Power-on-reset occurs. Condition removed Demand input reset [5] or RUN reset [6] Demand input = 0 or RUN = 0 SPI [3][4] First watchdog transition after 100 ms from MRSTn going high Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] SPI [3][4] Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] SPI [3][4] [5] Set demand input = 0 then set demand input to a new operating value. RUN bit = 0 then set RUN bit = 1. [7] Restart control bit. [6] Set The action taken when a short fault, bootstrap undervoltage, or overtemperature condition is detected is also determined by the state of ESF. When ESF = 1, any short fault condition, bootstrap undervoltage, or overtemperature condition will disable all the gate drive outputs and coast the motor. For short faults and bootstrap undervoltage, this fault state is latched and all gate drive outputs remain disabled until a demand input reset, a RUN bit reset, a serial read of the Diagnostic register with DSR = 0, or a power-on-reset occurs. For overtemperature fault conditions, the outputs will remain disabled until 10 ms after the condition is removed. When ESF = 0, no action will be taken for an overtemperature condition. For any short fault or bootstrap undervoltage condition, only the MOSFET associated with the detected fault will be Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 48 A4964 Sensorless Sinusoidal Drive BLDC Controller disabled. This fault state will be latched until the next PWM-on state for the associated phase. In some cases, this will allow the A4964 to continue to operate the motor in a reduced functional mode depending on the specific fault condition. When a loss of synchronization is detected, all the gate drive outputs are disabled and the motor coasts. If the restart bit, RSC, is set to 1, the A4964 immediately goes into a startup sequence. If RSC = 0, the loss of synchronization fault state is latched and all gate drive outputs remain disabled until a demand input reset, a RUN bit reset, a serial read of the Status register with DSR = 0, or a power-on-reset occurs. In all cases, any fault bits that have been set in the diagnostic registers are latched and only reset when a power-on-reset state is present or when the associated fault bit is read through the serial interface with DSR = 0. FAULT MASKS Individual diagnostics, except POR and system error, can be disabled by setting the corresponding bit in the mask register. If a bit is set to one in the mask register, then the corresponding diagnostic will be completely disabled. No fault states for the disabled diagnostic will be generated, no fault flags or diagnostic bits will be set, and no fault actions will be taken. See the mask register definition for bit allocation. Care must be taken when diagnostics are disabled to avoid potentially damaging conditions. CHIP-LEVEL DIAGNOSTICS Parameters, which are critical for safe operation of the A4964 and the external MOSFETs, are monitored. These include serial interface, chip temperature, minimum internal logic supply voltage, and the minimum motor supply voltage. Faults are latched in the Status or Diagnostic register when they occur and the register is only reset by a Status or Diagnostic register reset. CHIP FAULT STATE: POWER-ON RESET The supply to the logic sections of the A4964 is generated by an internal regulator from VBB and is monitored to ensure correct logical operation. The internal logic is guaranteed to operate with the voltage at the VBB terminal, VBB, down to VBBR. When VBB drops below the VBBR threshold, then the logical function of the A4964 cannot be guaranteed, all outputs will be immediately disabled and all the logic reset. The A4964 will enter a power-down state and all internal activity, other than the logic supply voltage monitor will be suspended. When VBB rises above the VBBR threshold, the A4964 will exit the power down state, all serial control registers will be reset to their power-on state, and all fault states will be reset. The FF bit and the POR bit in the Status register will be set to one to indicate that a power-on-reset has taken place. In general, the VSU, VRU, and VLU bits may also be set following a power-on-reset as the regulators may not have reached their respective rising undervoltage thresholds until after the register reset is completed. At power-up, the logic inputs and outputs will remain disabled until VLR rises above the rising undervoltage threshold, VLRON. If the WD mask bit is saved as 0 in non-volatile EEPROM (NWM), the MRSTn output will remain low for 10 ms. If the WD mask bit is saved as 1 in NWM, the MRSTn output will remain low for 10 ms or until the first valid serial transfer (whichever occurs first). After the MRSTn output goes high, the gate drive outputs will be re-enabled as described in the Fault Action section. The same power-on-reset sequence occurs for initial power-on or for a VBB “brown-out” where VBB only drops below VBBR momentarily. CHIP FAULT STATE: OVERTEMPERATURE Two temperature thresholds are provided. A hot warning and an overtemperature shutdown. • If the chip temperature rises above the temperature warning threshold, TJW, the thermal warning bit, TW, will be set in the Status register. No action will be taken by the A4964 when a thermal warning fault condition is present. When the temperature drops below TJW by more than the hysteresis value, TJWHys, the fault condition is removed. The thermal warning bit, TW, remains latched in the Status register until reset. • If the chip temperature rises above the over temperature threshold, TJF, the over temperature bit, OT, will be set in the Status register. If ESF = 1, all gate drive outputs will be disabled, the VLR regulator is shut down and MRSTn will go low. All A4964 functions other than the regulator remain active. When TJ drops by more than the overtemperature threshold (TJ < TJF – TJHyst), the regulator will remain shut down and MRSTn will remain low for 10 ms. After this timeout, MRSTn goes high and the regulator is re-enabled and attempts to restart. The overtemperature bit, OT, remains latched in the Status register until reset. If ESF = 0, no circuitry will be disabled and action must be taken by the user to limit the power dissipation in some way so as to prevent overtemperature damage to the chip and unpredictable device operation. When the temperature drops below TJF by more Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 49 A4964 Sensorless Sinusoidal Drive BLDC Controller than the hysteresis value, TJFHys, the fault condition is removed. The overtemperature bit, OT, remains latched in the Status register until reset. CHIP FAULT STATE: VBB UNDERVOLTAGE The VBB undervoltage monitor provides an indication that the main power supply has dropped below the desirable operating level. This monitor is provided as a system level function to indicate that the supply voltage has dropped to a voltage level where the motor may not be capable of providing full performance. When a VBB undervoltage state is present, the VSU bit in the Status register will be set, but the A4964 will still be capable of operating to the full specification. A VBB undervoltage condition will be present when the voltage at the VBB terminal, VBB, drops below the VBB undervoltage lockout threshold, VBBOFF. The VBB undervoltage condition is removed when VBB rises above the VBB undervoltage lockout threshold, VBBON. During a VBB undervoltage fault condition, if ESF = 1 all gate drive outputs will be disabled. When the fault condition is removed, the A4964 will enter the startup sequence if RSC = 1. If RSC = 0, the fault state will be latched and remain until the demand input is set to 0, the RUN bit is set to 0, the Status register is read with DSR = 0 or a power-on-reset occurs. If ESF = 0, no action will be taken. In all cases, the VSU bit remains set in the Status register until cleared. The VBB undervoltage monitor and fault action can be disabled by setting the VSU bit in the mask register. CHIP FAULT STATE: VREG UNDERVOLTAGE The internal charge-pump regulator supplies the low-side gate driver and the bootstrap charge current. It is critical to ensure that the regulated voltage at the VREG terminal, VREG, is sufficiently high before enabling any of the outputs. If VREG goes below the VREG undervoltage threshold, VROFF, the VREG undervoltage bit, VRU, will be set in the Status register, all gate drive outputs will go low, and the motor drive will coast. When VREG rises above VRON, the gate drive outputs are re-enabled. The VRU fault bit remains in the Status register until cleared. The VREG undervoltage monitor circuit is active during power up. All gate drives will remain low until VREG is greater than approximately 8 V. Note that this is sufficient to turn on standard threshold external power MOSFETs at a battery voltage as low as 5.5 V, but the on-resistance of the MOSFET may be higher than its specified maximum. CHIP FAULT STATE: VLR UNDERVOLTAGE The voltage at the VLR terminal, VLR, is monitored to ensure that the supply for any external controller is high enough to permit correct operation of the controller. If VLR drops below the falling undervoltage threshold, VLROFF, the regulator undervoltage bit, VLU, will be set in the Status register, the MRSTn output will go low to reset the external microcontroller and all gate drive outputs will be disabled. When VLR rises above the rising undervoltage threshold, VLRON, the MRSTn output will remain low. After 10 ms the MRSTn output will go high and the watchdog timer will be reset. The watchdog timer will remain reset for 100 ms and during this time the WDOG input will be ignored. The A4964 will then attempt to restart the motor on the first watchdog transition if the RUN and RSC bits are set to 1, and the demand input is at a level where starting the motor is permitted. If the RSC bit is set to 0, the gate drive outputs will remain disabled until the first watchdog transition and a demand input reset, a RUN bit reset, a serial read of the Status register with DSR = 0, or a power-on-reset occurs. The VLU fault bit remains in the Status register until cleared. CHIP FAULT STATE: VPP UNDERVOLTAGE During a NVM write operation, the voltage at the VPP terminal, VPP, is monitored to ensure that the programming supply remains high enough to ensure correct programming of the EEPROM memory cells. If VPP drops below the programming undervoltage level, VPPUV, during the save sequence, then the sequence will be terminated immediately and the FF and VPU bits will be set in the Status register. The SAV[1:0] bits will also indicate that the write was not successful. The VPU bit can only be set during a write sequence. For normal operation, the VPP undervoltage comparator is disabled. CHIP FAULT STATE: SERIAL ERROR The data transfer into the A4964 through the serial interface is monitored for two fault conditions: transfer length and parity. A transfer length fault is detected if there are more than 16 rising edges on SCK or if STRn goes high and there are fewer than 16 rising edges on SCK. A parity fault is detected if the total number of logic 1 states in the 16-bit transfer is an even number. In both cases, the write will be cancelled without writing data to the registers. In addition, the Status register will not be reset and the FF bit and SE bit will be set to indicate a data transfer error. No further action will be taken. The SE bit will remain in the Status register until the next successful serial write with DSR = 0 or a power-on reset occurs. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 50 A4964 Sensorless Sinusoidal Drive BLDC Controller CHIP FAULT STATE: SYSTEM ERROR If the SE bit is 1 at the same time as the POR bit is 1, then this indicates that a fault was detected when reading the NVM and the user-defined states have not been loaded into the control and configuration registers. In this case, the control and configuration registers will contain the default states and the RUN bit will be set to 0 to prevent any attempt to activate the outputs. The SE bit will remain in the Status register until the next successful SPI write or a power-on reset occurs. This gives an external microcontroller the opportunity to write the user-defined bits to the registers and activate the drive. If the A4964 is operating without an external microcontroller when system error is indicated, then it will be held in this state until the power is cycled off then on and another attempt is made to transfer the NVM contents into the registers. MOTOR FAULT: LOSS OF SYNCHRONIZATION The motor operation is controlled by a closed-loop position estimator system, so it does not have any direct, immediate means of determining whether the motor is synchronized to the rotating field generated by the A4964. A loss of synchronization can only be detected if the commutation controller attempts to drive the motor too fast (overspeed) or too slow (underspeed). The underspeed (low-speed) threshold, fSL, is defined as: fSL = 8 × n × fRES (Hz) where n is a positive integer defined by SL[3:0], fSL is the underspeed threshold, and fRES is the speed resolution defined by SR[2:0]. The overspeed (high speed) threshold, fSH, is defined as: fSH = [127 + (n × 128)] × fRES (Hz) where n is a positive integer defined by SH[3:0], fSH is the overspeed threshold, and fRES is the speed resolution defined by SR[2:0]. SH DI / DO SL 3 LSBs to 0 2 1 0 9 8 7 6 5 4 3 2 MSBs set to 0 3 2 1 0 LSBs to 0 1 Figure 23: Over- and Underspeed versus Reference Speed 0 These thresholds must be set to a suitable level to provide appropriate overspeed and underspeed limits for all motor control modes. The overspeed and underspeed thresholds are shown, in Figure 23, relative to the reference speed set by DI[9:0] and the actual speed reported by DO[9:0]. The four bits of the underspeed threhold variable, SL[3:0], have the same weighting as bits 6:3 of the reference speed variable DI. The least significant 3 bits of the overspeed threhold variable, SH[3:0], have the same weighting as the most significant 3 bits of the reference speed variable DI. The most significant bit of SH has twice the weighting of the most significant bit of DI. Relative to the reference speed, the overspeed threshold variable can be considered as an 11-bit value where the most significant bits are set by SH[3:0] and the least significant 7 bits are set to 1. The overspeed threshold can therefore be programmed between approximately 12% and 200% of the maximum reference speed and the underspeed threshold between 0% and 12.4% of the maximum reference speed. If the commutation controller attempts to drive the motor at less than the underspeed threshold or greater than the overspeed threhold, then the A4964 will indicate loss of synchronization. Note that the underspeed threshold, SL, should always be set to be lower than the minimum windmill frequency, fWMF, defined by WMF[3:0]. If it is set higher, then any use of windmill start below the underspeed threshold but above the minimum windmill frequency will immediately indicate loss of synchronization. In the extreme case when a motor stalls due to excessive load on the output, there will be no bemf zero crossing detection and the frequency of the commutation sequence will be reduced at each expected commutation point to try and regain synchronization. The resulting speed will eventually reduce below the underspeed threshold after a number of commutation cycles and the A4964 will set the LOS bit in the Status register to 1 and coast the motor. In some cases, rather than a complete stall, it is also possible for the motor to vibrate at a whole fraction (subharmonic) of the commutation frequency produced by the controller. In this case, the controller will still detect the bemf zero crossing, but at a rate much higher than the motor is capable of running. The commutation controller will increase the commutation rate to compensate and the resulting speed will increase above the overspeed threshold and the A4964 will set the LOS bit in the Status register to 1 and coast the motor. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 51 A4964 Sensorless Sinusoidal Drive BLDC Controller When loss of synchronization is detected, the controller will either stop or attempt to restart the motor depending on the state of the RUN bit, the restart control bit, RSC, and the demand input. If the RUN and RSC bits are set to 1, and the demand input is greater than the minimum limit for the motor to run in the selected motor control mode (see mode descriptions for details), then the start sequencer will reset and retry. This cycle will continue until stopped by taking the demand input to zero or setting either the RUN bit or the RSC bit to 0. If the RSC bit is set to 0, the motor will continue to coast until a demand input reset, a RUN bit reset, a serial read of the Status register with DSR = 0, or a power-on-reset occurs. The LOS bit will remain in the Status register until reset. Note that the VBRG terminal can withstand a negative voltage up to –5 V. This allows the terminal to remain connected directly to the top of the power bridge during negative transients where the body diodes of the power MOSFETs are used to clamp the negative transient. The same applies to the more extreme case where the MOSFET body diodes are used to clamp a reverse battery connection. MOSFET FAULT QUALIFICATION The output from each VDS overvoltage comparator is filtered by a VDS fault qualifier circuit. This circuit uses a timer to verify that the output from the comparator is indicating a valid VDS fault. The duration of the VDS fault qualifying timer, tVDQ, is determined by the contents of the VQT[5:0] variable as: tVDQ = n × 50 ns MOSFET FAULT DETECTION where n is a positive integer defined by VQT[5:0]. Faults on any external MOSFETs are determined by measuring the drain-source voltage of the MOSFET and comparing it to the drain-source overvoltage threshold, VDST, defined by the VT[5:0] variable. These bits provide the input to a 6-bit DAC with a least significant bit value of typically 50 mV. The output of the DAC produces VDST, approximately defined as: The qualifier can operate in one of two ways: debounce mode or blanking mode, selected by the VDQ bit. VDST = n × 50 mV where n is a positive integer defined by VT[5:0]. The drain-source voltage for any low-side MOSFET is measured between the GND terminal and the appropriate Sx terminal. Any low-side current sense voltage should be taken into account when setting the VDST level. The drain-source voltage for any high-side MOSFET is measured between the VBRG terminal and the appropriate Sx terminal. Using the VBRG terminal rather than VBB avoids adding any reverse diode voltage or high-side current sense voltage to the real high-side drain-source voltage and avoids false VDS fault detection. The VBRG terminal is an independent low-current sense input to the top of the MOSFET bridge. It should be connected independently and directly to the common connection point for the drains of the power bridge MOSFETs at the positive supply connection point in the bridge. The input current to the VBRG terminal is proportional to the drain-source threshold voltage, VDST, and is approximately: IVBRG = 72 × VDST + 52 where IVBRG is the current into the VBRG terminal in µA and VDST is the drain-source threshold voltage described above. In the default, debounce mode, a timer is started each time the comparator output indicates a VDS fault detection when the corresponding MOSFET is active. This timer is reset when the comparator changes back to indicate normal operation. If the debounce timer reaches the end of the timeout period, set by tVDQ, then the VDS fault is considered valid and the corresponding VDS fault bit, AH, AL, BH, BL, CH, or CL will be set in the Diagnostic register. In the optional, blanking mode, a timer is started when a gate drive is turned on. All VDS overvoltage comparator outputs are ignored (blanked) for the duration of the timeout period, set by tVDQ. If the comparator output indicates an overcurrent event when the MOSFET is switched on and the blanking timer is not active, then the VDS fault is considered valid and the corresponding VDS fault bit, AH, AL, BH, BL, CH, or CL will be set to 1 in the Diagnostic register. If a valid VDS fault is detected when ESF = 1, then this fault condition will be latched and all external MOSFETs will be immediately switched off and disabled until the fault is reset. If a valid VDS fault is detected when ESF = 0, then the external MOSFET where the fault is detected is immediately switched off by the A4964 but the remaining MOSFETs continue to operate. The MOSFET where the fault is detected will be switched on again the next time the internal bridge control switches it from off to on. To limit any damage to the external MOSFETs, when ESF = 0, Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 52 A4964 Sensorless Sinusoidal Drive BLDC Controller the A4964 should either be fully disabled by setting the demand input to 0 or by setting RUN to 0 through a serial write. Alternatively, setting the ESF bit to 1 will allow the A4964 to completely disable the MOSFETs as soon as a fault is detected. Any fault bits set to 1 in the Diagnostic register remain set until cleared. BOOTSTRAP UNDERVOLTAGE FAULT In addition to a monitor on VREG, the A4964 also monitors the individual bootstrap capacitor charge voltages to ensure sufficient high-side drive. Before a high-side drive can be turned on, the bootstrap capacitor voltage must be higher than the turn-on voltage limit. If this is not the case, then the A4964 will attempt to charge the bootstrap capacitor by activating the complementary low-side drive. Under normal circumstances, this will charge the capacitor above the turn-on voltage in a few microseconds and the high-side drive will then be enabled. The bootstrap voltage monitor remains active while the high-side drive is active and if the voltage drops below the turn-off voltage, a charge cycle is also initiated. In either case, if there is a fault that prevents the bootstrap capacitor charging within typically 200 µs, then the charge cycle will timeout, a bootstrap undervoltage condition is detected, and the corresponding bootstrap undervoltage fault bit, BA, BB, or BC is set to 1 in the Diagnostic register. If a bootstrap undervoltage condition is detected and ESF = 1, then all gate drive output will be disabled. In this case, the gate drive outputs will remain disabled and the bootstrap undervoltage fault state will be held until a demand input reset, a RUN bit reset, a serial read of the Diagnostic register with DSR = 0, or a power-on-reset occurs. When ESF = 0, only the high-side gate drive for the affected phase will be switched off and only for the remainder of the PWM period. At each PWM-on time, an attempt will be made to again turn on the high-side MOSFET. Any fault bits set to 1 in the Diagnostic register remain set until cleared. SYSTEM CLOCK VERIFICATION The SDO output can be set to provide a logic-level square wave output at a ratio of the internal clock frequency to allow verification of the system clock frequency and more precise calibration of the timing settings if required. When the CKS bit is set to 0, the SDO terminal operates as described in the serial interface description. When the CKS bit is set to 1, the SDO terminal will output the divided clock signal when STRn is held high. The division ratio, ND, is defined in the electrical characteristics table. When CKS = 1 and STRn is low, the serial interface will continue to accept data on SDI and output the normal serial data on SDO. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 53 A4964 Sensorless Sinusoidal Drive BLDC Controller SERIAL INTERFACE Serial Registers Definition (default values shown below each input register bit) 15 14 13 12 11 10 0: PWM config 0 0 0 0 0 WR 1: PWM config 0 0 0 0 1 WR 2: Bridge config 0 0 0 1 0 WR 3: Gate drive config 0 0 0 1 1 WR 4: Gate drive config 0 0 1 0 0 WR 5: Gate drive config 0 0 1 0 1 WR 6: Current limit 0 0 1 1 0 WR 7: VDS monitor 0 0 1 1 1 WR 8: VDS monitor 0 1 0 0 0 WR 9: Watchdog config 0 1 0 0 1 WR 10: Watchdog config 0 1 0 1 0 WR 11: Commutation 0 1 0 1 1 WR 12: Commutation 0 1 1 0 0 WR 13: BEMF config 0 1 1 0 1 WR 14: BEMF config 0 1 1 1 0 WR 15: Startup config 0 1 1 1 1 WR 16: Startup config 1 0 0 0 0 WR 9 8 MOD 7 6 5 4 3 2 1 PMD PW5 PW4 PW3 PW2 PW1 PW0 0 0 0 1 0 0 1 1 0 DP2 DP1 DP0 DD1 DD0 DS3 DS2 DS1 DS0 0 0 0 0 0 0 0 0 0 SA1 SA0 DT5 DT4 DT3 DT2 DT1 DT0 0 0 1 0 0 0 0 0 IR13 IR12 IR11 IR10 IR23 IR22 IR21 IR20 0 0 0 0 0 0 0 0 IF13 IF12 IF11 IF10 IF23 IF22 IF21 IF20 0 0 0 0 0 0 0 0 0 0 0 TRS3 TRS2 TRS1 TRS0 TFS3 TFS2 TFS1 TFS0 0 0 0 0 0 0 0 0 0 OBT4 OBT3 OBT2 OBT1 OBT0 VIL3 VIL2 VIL1 VIL0 0 0 1 1 1 1 1 1 1 MIT1 MIT0 VT5 VT4 VT3 VT2 VT1 VT0 0 0 0 1 1 1 1 1 0 VQT5 VQT4 VQT3 VQT2 VQT1 VQT0 0 VDQ 0 0 1 1 1 1 1 1 WM4 WM3 WM2 WM1 WM0 0 0 0 0 0 0 0 0 0 WC3 WC2 WC1 WC0 WW4 WW3 WW2 WW1 WW0 0 0 0 0 0 0 0 0 0 CP3 CP2 CP1 CP0 CI3 CI2 CI1 CI0 0 1 1 1 0 1 1 1 0 CPT3 CPT2 CPT1 CPT0 CIT3 CIT2 CIT1 CIT0 0 0 0 0 0 0 0 0 0 BW4 BW3 BW2 BW1 BW0 0 0 0 0 0 0 1 0 0 BS1 BS0 BF3 BF2 BF1 BF0 0 0 0 0 0 0 0 0 1 HT3 HT2 HT1 HT0 HD4 HD3 HD2 HD1 HD0 0 0 0 1 0 0 1 0 1 STM RSC KM3 KM2 KM1 KM0 HR1 HR0 0 0 0 1 1 1 0 0 0 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 0 P P P P P P P P P P P P P P P P P 54 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Registers Definition (default values shown below each input register bit) 15 14 13 12 11 10 17: Startup config 1 0 0 0 1 WR 18: Startup config 1 0 0 1 0 WR 19: Startup config 1 0 0 1 1 WR 20: Startup config 1 0 1 0 0 WR 21: Speed loop 1 0 1 0 1 WR 22: Speed loop 1 0 1 1 0 WR 23: Speed loop 1 0 1 1 1 WR 24: NVM Write 1 1 0 0 0 WR 25: System 1 1 0 0 1 WR 26: Phase advance 1 1 0 1 0 WR 27: Motor function 1 1 0 1 1 WR 28: Mask 1 1 1 0 0 WR 29: Readback Select 1 1 1 0 1 WR 30: Write Only 1 1 1 1 0 31: Read Only 1 1 1 1 1 FF POR SE VPU CLI 1 1 0 0 0 Status 9 0 0 0 8 7 6 5 4 3 2 1 WIN WMF2 WMF1 WMF0 WBD3 WBD2 WBD1 WBD0 0 0 1 0 0 1 1 1 SF23 SF22 SF21 SF20 SF13 SF12 SF11 SF10 0 1 1 1 0 1 1 1 SD23 SD22 SD21 SD20 SD13 SD12 SD11 SD10 0 1 1 1 0 1 1 1 STS3 STS2 STS1 STS0 SFS3 SFS2 SFS1 SFS0 0 0 1 0 0 0 1 1 1 SGL4 SGL3 SGL2 SGL1 SGL0 SG3 SG2 SG1 SG0 0 0 1 0 1 0 1 0 1 DV1 DV0 DF1 DF0 SR2 SR1 SR0 0 1 0 0 0 0 0 0 0 SL3 SL2 SL1 SL0 SH3 SH2 SH1 SH0 0 0 1 1 1 0 1 1 1 SAV1 SAV0 0 0 0 0 0 0 0 0 0 ESF VLR VRG OPM LWK IPI DIL CM1 CM0 1 0 1 0 0 0 0 0 0 PAM KIP1 KIP0 PA5 PA4 PA3 PA2 PA1 PA0 0 0 0 0 0 0 0 0 0 LEN GTS OVM1 OVM0 DRM BRK DIR RUN 0 0 0 0 0 0 0 0 0 WD LOS OT TW VSU VRU VLU BU VO 1 0 0 0 0 0 0 0 0 DGS1 DGS0 DSR LBR CKS RBS2 RBS1 RBS0 0 0 0 0 0 0 0 0 0 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 0 0 0 0 0 0 0 0 0 0 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 0 0 0 0 0 0 0 0 0 0 WD LOS OT TW VSU VRU VLU BU VO 0 0 0 0 0 0 0 0 0 0 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 0 P P P P P P P P P P P P P P P P 55 A4964 Sensorless Sinusoidal Drive BLDC Controller A three-wire synchronous serial interface, compatible with SPI, is used to control the features of the A4964. A fourth wire can be used to provide diagnostic feedback and readback of the register contents. The fourth wire can also be set to provide a logic-level square wave output at a ratio of the internal clock frequency as described in the Diagnostics section. data output on SDO. If WR is set to one, then the Status register is output. If WR is set to zero, then the contents of the register selected by the first five bits on SDI is output. The serial interface provides full access to all the features of the A4964. In addition to full control of the motor activity and output demand, it also provides access to all control options and programmable parameters. The last bit in any serial transfer, D[0], is a parity bit that is set to ensure odd parity in the complete 16-bit word. Odd parity means that the total number of 1s in any transfer should always be an odd number. A parity fault is detected if the total number of logic 1 states in the 16-bit transfer is an even number. This ensures that there is always at least one bit set to 1 and one bit set to 0 and allows detection of stuck-at faults on the serial input and output data connections. The parity bit is not stored but generated on each transfer. The serial interface timing requirements are specified in the electrical characteristics table and illustrated in Figure 2. Data is received on the SDI terminal and clocked through a shift register on the rising edge of the clock signal input on the SCK terminal. The STRn terminal is normally held high, and is only brought low to initiate a serial transfer. No data is clocked through the shift register when STRn is high, allowing multiple slave units to use common SDI, SCK, and SDO connections. Each slave then requires an independent STRn connection. After 16 data bits have been clocked into the shift register, STRn must be taken high to latch the data into the selected register. When this occurs, the internal control circuits act on the new data and the Status or Diagnostic registers are reset depending on the transfer. Diagnostic information or the contents of the registers is output on the SDO terminal msb first while STRn is low and changes to the next bit on each falling edge of SCK. The first bit, which is always the FF bit from the Status register, is output as soon as STRn goes low. In all cases, the first five bits output on SDO will always include the FF bit, the POR bit, the SE bit, and the VPU bit from the Status register. If a parity fault is detected, or there are more than 16 rising edges on SCK, or if STRn goes high and there are fewer than 16 rising edges on SCK, the write will be cancelled without latching data to the registers. In addition, the Status register will not be reset and the FF bit and SE bits will be set to indicate a data transfer error. CONFIGURATION AND CONTROL REGISTERS The serial data word is 16 bits, input msb first, the first five bits are defined as the register address. This provides 32 addressable registers, 30 of which are read/write, 1 is read only, and 1 write only. The registers are grouped as follows: • PWM frequency and dither configuration • Bridge dead time and MOSFET drive configuration The first five bits, D[15:11], in a serial word are the register address bits providing 32 addressable registers. In addition to these, there is a read-only Status register. Two of the addressable registers have special functions. Register address 30 is the writeonly demand input register and accepts a 10-bit demand input. Register address 31 is the read-only measurement output register and provides a 10-bit integer output from the internal data acquisition system. • Current limit configuration The remaining 30 registers provide configuration and control for the A4964. Each of these registers has a write bit, WR (bit 10), as the first bit after the register address. This bit must be set to one to write the subsequent bits into the selected register. If WR is zero, then the remaining data bits (bits 9 to 0) are ignored. For these registers, the state of the WR bit also determines the • System function configuration • VDS monitor configuration • Watchdog configuration • Commutation and bemf configuration • Start-up configuration • Speed loop configuration • Motor function control • Fault mask • Readback select and readback • Demand input Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 56 A4964 Sensorless Sinusoidal Drive BLDC Controller Register 0: PWM: Register 10: Watchdog: • MOD, Selects 2-phase or 3-phase modulation. • WC[3:0], 4-bit integer to set watchdog cycle count. • PMD, Selects the bridge PWM mode. • WW[4:0], 5-bit integer to set the watchdog window time. • PW[5:0], a 6-bit integer to set the PWM period. Register 11: Commutation: Register 1: PWM dither: • CP[3:0], 4-bits to set the steady-state phase control proportional gain. • DP[2:0], 3 bits to select the dither step period. • DD[1:0], 2 bits to select the dither dwell time. • DS[3:0], 3-bit integer to select the dither steps. Register 2: Bridge dead time: • SA[1:0], 2-bit integer to set sense amp gain. • DT[5:0], a 6-bit integer to set the dead time. • CI[3:0], 4-bits to set the steady-state phase controller integral gain. Register 12: Commutation: • CPT[3:0], 4-bits to set the transient phase control proportional gain. Register 3: Gate drive: • CIT[3:0], 4-bits to set the transient phase controller integral gain. • IR1[3:0], 4 bits to set turn-on current 1. Register 13: BEMF: • IR2[3:0], 4 bits to set turn-on current 2. • BW[4:0], 5-bit integer to set the BEMF detect window. Register 4: Gate drive: • IF1[3:0], 4 bits to set turn-off current 1. • IRF2[3:0], 4 bits to set turn-off current 2. Register 5: Gate drive: • TRS[3:0], 4-bit integer to set turn-on time. • TFS[3:0], 4-bit integer to set turn-off time. Register 14: BEMF: • BS[1:0], 2 bits to select the number of BEMF samples. • BF[3:0], 4 bits to select the windmill BEMF filter time. Register 15: Startup: • HT[3:0], a 4-bit integer to set the time of the initial alignment. Register 6: Current limit: • HD[3:0], a 4-bit integer to set the PWM duty cycle applied during the alignment time. • OBT[4:0], 5-bit integer to set the current limit blank time. Register 16: Startup: • VIL[3:0], 4-bit integer to set the current limit scale. • STM, enables the coast function during startup. Register 7: VDS & Current Sense: • RSC, enables restart after loss of synchronization. • MIT[1:0], 2-bit integer to set sense amp maximum threshold. • KM[3:0], 4-bit integer to set the motor constant. • VT[5:0], 6-bit integer to set the VDS limit. • HR[1:0], 2 bits to select the alignment duty cycle ramp time. Register 8: VDS: • VDQ, selects VDS qualifier mode. • VQT[5:0], 6-bit integer to set the VDS qualifier time. Register 17: Startup: • WIN, enables windmill detection at start-up Register 9: Watchdog: • WMF[2:0], 3-bit integer to select the minimum windmill detection frequency. • WM[4:0], 5-bit integer to set the minimum watchdog time. • WBD[3:0], 4-bit integer to select windmill brake duty cycle. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 57 A4964 Sensorless Sinusoidal Drive BLDC Controller Register 18: Startup: Register 26: Phase advance: • SF2[3:0], a 4-bit integer to set final start frequency. • PAM, selects the phase advance mode. • SF1[3:0], a 4-bit integer to set initial start frequency. • KIP[1:0], sets the auto phase advance control gain. Register 19: Startup: • SD2[3:0], a 4-bit integer to set initial start PWM duty. • SD1[3:0], a 4-bit integer to set final start PWM duty. Register 20: Startup: • STS[3:0], a 4-bit integer to set the start time step. • PA[5:0], a 6-bit integer to set the phase advance. Register 27: Motor function: • LEN, controls LIN standby/active state. • GTS, initiates go-to-sleep function. • SFS[3:0], a 4-bit integer to set the start frequency step. • OVM[1:0], selects overmodulation level. Register 21: Speed control loop: • DRM, selects drive mode. • SGL[5:0], a 5-bit integer to set the speed control loop acceleration limit. • BRK, brake control. • SG[3:0], a 4-bit integer to set the speed control loop proportional gain. • DIR, direction control. • RUN, enables the motor to start and run. Register 22: Speed control loop: Register 28: Fault mask: • DV[1:0], 2 bits to select the voltage compensation level. The Fault Mask Register contains a fault mask bit for each fault bit in the Status register other than FF, POR, and SE. If a bit is set to one in the mask register, then the corresponding diagnostic will be completely disabled. No fault states for the disabled diagnostic will be generated and no fault flags or diagnostic bits will be set. • DF[1:0], 2 bits to select the deceleration factor. • SR[2:0], 3 bits to select the speed control resolution. Register 23: Speed control loop: • SL[3:0], 4 bits to select the underspeed threshold. • SH[3:0], 4 bits to select the overspeed threshold. Register 29: Readback select: Register 24: NVM: • DGS[1:0], 2 bits to select output on the DIAG terminal. • SAV[1:0], controls and reports saving the register contents to the NVM. • DSR, disables reset on serial transfer. Register 25: System Functions: • ESF, the enable stop on fault bit that defines the action taken when a fault is detected. • VLR, selects logic regulator voltage. • VRG, selects gate drive regulator voltage. • LBR, selects select LIN baud rate. • CKS, selects divided system clock on SDO terminal. • RBS[2:0], 3 bits to select the data that will be read from register 31. Register 30 (Write only): Demand input: • LWK, selects the wake-up mode. • DI[9:0], 10-bit integer providing the demand input for the selected control mode. • IPI, selects the sense of the PWM input. Register 31 (Read only): Data acquisition: • DIL, disables current limit for speed modes. • DO[9:0], 10 bits providing the internal monitor data selected by RBS[2:0]. • OPM, selects the stand-alone operating mode. • CM[1:0], 2 bits to select the required control mode. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 58 A4964 Sensorless Sinusoidal Drive BLDC Controller STATUS AND DIAGNOSTIC REGISTERS There is one read-only Status register in addition to the 32 addressable registers. When any register transfer takes place, the first five bits output on SDO are always the most significant five bits of the Status register regardless of whether the addressed register is being read or written. When register 31 is addressed, the remaining eleven bits on SDO are always the ten bits of the selected output plus a parity bit. For all other registers, the sixth bit will be zero and the content of the remaining ten bits will depend on the state of the WR bit input on SDI. When WR is 1, the addressed register will be written and the remaining ten bits output on SDO will be the least significant nine bits of the Status register followed by a parity bit. When WR is 0, the addressed register will be read and the remaining ten bits will be the contents of the addressed register followed by a parity bit. The read-only Status register provides a summary of the chip, bridge, and motor status. The most significant three bits of the Status register indicate critical system faults. Bit 11 reports the state of the current control circuit. Bits 9 through 3 provide fault flags for specific individual diagnostic monitors, and bits 2 and 1 provide indicators for the contents of the Diagnostic register. The Diagnostic register is an additional register that can be selected for readback through register 31. This register contains detailed information on bootstrap undervoltage faults and VDS overvoltage faults for each MOSFET in the bridge. If a bootstrap undervoltage is detected, then bit 2 of the Status register, BU, will be set and the specific phase can be determined by reading bits BA, BB, and BC in the Diagnostic register. If a VDS overvoltage is detected, then bit 1 of the Status register, VO, will be set and the specific MOSFET can be determined by reading bits AH, AL, BH, BL, CH, and CL in the Diagnostic register. When selected for readback, the Diagnostic register contains an additional bit, OSR, in position DO9, which indicates if the actual motor speed is above the maximum speed reference level. OSR can be used as an additional most significant bit with the speed readback to double the range of the speed that can be reported. OSR will not set any bits in the status register and will be updated continuously by the speed monitor. Whenever a fault occurs, the corresponding flag bit in the Status or Diagnostic register will be set to 1 and latched until reset. Resetting the Status or Diagnostic register only affects latched faults that are no longer present. For any static faults that are still present, for example overtemperature, the fault flag will remain set after the register reset. Except for the BU and VO bits, bits 2 and 1 respectively, the fault flags in the Status register are only reset to 0 on the completion of a serial read of the Status register or when a power-on-reset occurs. The BU and VO bits are reset to 0 when the corresponding fault flags in the Diagnostic register are reset. The fault flags in the Diagnostic register are only reset to 0 on the completion of a serial read of the Diagnostic register or when a power-on-reset occurs. In some systems, it is preferable to be able to read the Status or Diagnostic register without causing a reset and allowing the A4964 to re-enable the outputs. The DSR (Disable Serial Reset) bit provides this functionality. When DSR is set to one, any valid read of any of the read-only registers will not result in that register being reset. When DSR = 0, any valid read of any of the readonly registers will reset the content of that register. This provides a way for the external controller to access the diagnostic information without automatically re-enabling any outputs, but retains a way to reset the faults under control of the controller. The first most significant bit in the Status register, bit 15, is the status register flag, FF. This is high if any fault bits in the Status register are set. When STRn goes low to start a serial write, SDO comes out of its high-impedance state and outputs the serial register fault flag. This allows the main controller to poll the A4964 through the serial interface to determine if a fault has been detected. If no faults have been detected, then the serial transfer may be terminated without generating a serial read fault by ensuring that SCK remains high while STRn is low. When STRn goes high, the transfer will be terminated and SDO will go into its high-impedance state. The second most significant bit in the Status register, bit 14, is the POR bit. At power-up or after a power-on-reset, the FF bit and the POR bit are set, indicating to the external controller that a power-on-reset has taken place. All other diagnostic bits are reset and all other registers are returned to their default state. Note that a power-on-reset only occurs when the output of the internal logic regulator rises above its undervoltage threshold. Power-on-reset is not affected by the state of the VBB supply voltage or VREG regulator output voltage. In general, the VSU, VRU, and VLU bits may also be set following a power-on-reset as the regulators may not have reached their respective rising undervoltage thresholds until after the register reset is completed. Bit 13 in the Status register is the SE bit. If the POR bit is 0, then the SE bit indicates if the previous serial transfer was not completed successfully. If SE is 1 when POR is 1, then this indicates that a fault was detected in the EEPROM and the user-defined values have not been loaded into the registers. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 59 A4964 Sensorless Sinusoidal Drive BLDC Controller READBACK REGISTER The read-only readback register, register 31, provides access to six additional measurements plus the Diagnostic register described above. The measurement to be output on SDO when register 31 is addressed is selected by the RBS[2:0] variable as shown in Table 6: Table 6: Read-Back Output Select RBS Register 31 Output 0 Diagnostic register 1 Motor speed 2 Average supply current 3 Supply voltage 4 Chip temperature 5 Demand input 6 Applied bridge peak duty cycle 7 Applied phase advance The first five bits of the readback register are always the most significant five bits of the Status register. The 10-bit readback value is the next ten bits followed by a parity bit. The motor speed measurement is relative to the speed resolution defined by SR[2:0] and therefore has the same range and resolution as the speed demand input through register 30. The motor speed is also available during windmill detection in the forward direction. The motor speed, fE,is defined as: fE = n × fRES (Hz) where n is a positive integer defined by DO[9:0], fRES is the speed resolution defined by SR[2:0], and fE is the electrical cycle frequency of the controller. The motor speed, ωM, can be calculated from : fE × 60 ~M = NPP (rpm) where ωM is the motor speed in rpm, fE is the electrical cycle frequency, and NPP is the number of pole-pairs in the rotor. This range can be extended by a factor of two by using the most significant bit of the diagnostic register, OSR, as bit 11 of the speed measurement. That is, when OSR = 1, the speed is defined as: fE = (n + 1024) × fRES (Hz) The update period for the motor speed measurement can be calculated from: 1 tDO = SEMF × f (ms) E where fE is the electrical cycle frequency and SEMF is the number of bemf samples per cycle. The average supply current measurement is derived from the average output of the sense amplifier and represents the average supply current into the motor. The average current value, ISAVG, is defined as: 1.76 × n ISAVG = AV × RSENSE (A) where n is a positive integer defined by DO[9:0], RSENSE is the sense resistor value in mΩ, AV is the gain of the sense amplifier as defined by the SA variable. The supply voltage measurement is a direct measurement of the VBRG voltage with a resolution of 53 mV and a range of 54 V. The supply voltage, VS, is defined as: VS = n × 0.0528 (V) where n is a positive integer defined by DO[9:0]. Used together, the average supply current and the supply voltage measurements can provide a measurement of the average electrical power into the motor. The chip junction temperature measurement is determined by the voltage of the internal temperature measurement diodes. The chip junction temperature, TJ, is defined as: TJ = 367.7 – (n × 0.451) (°C) where n is a positive integer defined by DO[9:0]. The temperature measurement result range is –93°C to 367°C, but the useable measurement range is –50°C to 190°C. The average supply current, supply voltage, and chip temperature measurements are updated every 2 ms. The remaining three selections provide a readback capability for the variables that can be modified internally by the A4964. The demand input can be written directly or can be derived from an input PWM duty cycle. The demand input readback simply provides the contents of DI[9:0] at the time of readback. The applied bridge peak duty cycle output provides the peak value of the duty cycle as determined by the motor control algorithm. The bridge duty cycle, DBR, is defined by: n DBR = 1023 ^%h where n is a positive integer defined by DO[9:0]. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 60 A4964 Sensorless Sinusoidal Drive BLDC Controller The applied phase advance, θADV, when PAM = 0 (manual) is defined by: θADV = n × 0.7°(elec) |n = 0..62 θADV = 60°(elec) |n = 63 where n is a positive integer defined by DO[9:0]. The applied phase advance, θADV, when PAM = 1 (automatic) is defined by: θADV = n × 0.7°(elec) where n is a positive integer defined by DO[9:0]. The applied bridge peak duty cycle and applied phase advance measurements are updated each bridge PWM period, tPW. Non-Volatile Memory The values in the configuration and control registers are held in non-volatile EEPROM (NVM), allowing the A4964 to be pre-programmed with different user-defined register values for each application, thus avoiding the need to program the register contents at each power on. The A4964 provides a simple method to write the contents of the registers into the NVM using the serial interface. When the SAV[1:0] bits in register 24 are changed from [01] to [10], in a single serial write, the present contents of registers 0 to 23, 25 to 29, except register 27 bit 7, and bits [10:3] of register 30 (DI[9:2]) are saved (written to NVM) as a single operation. The save sequence takes typically 400 ms to complete. It is not possible to save single register values. Although the motor may be operating during the save sequence, it is recommended that the motor drive is disabled before starting a save sequence to avoid any corruption caused by the electrical noise or any faults from the motor. Note that the GTS bit (register 27[7]) is not saved. This is to avoid a lockout condition where the A4964 is commanded to go to sleep as soon as the wake-up sequence is complete. The register save sequence requires a programming voltage, VPP, to be applied to the VBB terminal. VPP must be present on the VBB terminal for a period of time, tPRS, before the save sequence is started. VPP must remain on VBB until the save sequence is completed. During the save sequence, the SPI remains active for read only. Any attempt to write to the registers during the save sequence will cause the FF and SE bits to be set in the Status register. During the save sequence, the A4964 will automatically complete all the necessary steps to ensure that the NVM is correctly programmed and will complete the sequence by verifying that the contents of the NVM have been securely programmed. On successful completion of a save sequence, the SAV[1:0] bits will be set to 01. Register 24 should be read to determine if the save has completed successfully. If SAV[1:0] is reset to 00, then the save sequence has been terminated and has not completed successfully. If VPP drops below the programming undervoltage level, VPPUV, during the save sequence, then the sequence will be terminated immediately, the FF and VPU bits set in the Status register, and SAV[1:0] will be reset to 00. To externally verify the data saved in the NVM, the VBB supply must be cycled off then on to cause a power-on reset. Following a power-on reset, the contents of the NVM are copied to the serial registers which can then be read through the serial interface and verified. For guaranteed data retention reliability, the NVM in the A4964 should be written no more than 1000 times. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 61 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 0: PWM config 0 0 0 0 0 WR 1: PWM config 0 0 0 0 1 WR 2: Bridge config 0 0 0 1 0 WR 9 8 7 6 5 4 3 2 1 PMD PW5 PW4 PW3 PW2 PW1 PW0 0 0 0 1 0 0 1 1 0 DP2 DP1 DP0 DD1 DD0 DS3 DS2 DS1 DS0 0 0 0 0 0 0 0 0 0 SA1 SA0 DT5 DT4 DT3 DT2 DT1 DT0 0 0 1 0 0 0 0 0 MOD 0 Register 0: PWM Configuration Register 1: PWM Configuration (continued) MOD DD[1:0] Modulation Mode Select MOD PMD Modulation Mode 0 3-phase 1 2-phase PMD PW[5:0] PWM Mode DD1 DD0 D 0 0 1 ms 0 1 2 ms 1 0 5 ms 1 1 10 ms 0 Center aligned 1 Edge aligned Default D Bridge PWM Fixed Period tPW = 20.10 μs + (n × 0.8 μs) when PMD = 0 tPW = 20.05 μs + (n × 0.8 μs) when PMD = 1 where n is a positive integer defined by PW[5:0], e.g. when PW[5:0] = [10 0110] and PMD = 0 then tPW = 50.5 µs. The range of tPW is 20.1 µs to 70.5 µs when PMD = 0 and 20.05 µs to 70.45 µs when PMD = 1. DS[3:0] Dwell Time Default D The maximum number of steps is 15. Setting DS[3:0] to 0 will disable PWM dither. Register 2: Bridge and Sense Amp Configuration SA[1:0] Sense Amp Gain SA0 0 0 2.5 0 1 5 PWM Dither Step Period 1 0 10 t∆PW = –0.2 μs – (n × 0.2 μs) 1 1 20 Register 1: PWM Configuration The range of t∆PW is –0.2 µs to –1.6 µs. P PWM Dither Step Count SA1 where n is a positive integer defined by DP[2:0], e.g. when DP[2:0] = [101] then t∆PW = –1.2 µs. P The number of dither steps is directly defined by the integer value of DS[3:0], e.g. when DS[3:0] = [0111] then there will be 7 frequency steps. This is equivalent to 50 kHz to 14.2 kHz. DP[2:0] P PWM Dither Dwell Time Default Bridge PWM Mode Select 0 DT[5:0] Gain Default D Dead Time tDEAD = n × 50 ns where n is a positive integer defined by DT[5:0], e.g. when DT[5:0] = [01 0100] then tDEAD = 1 µs. The range of tDEAD is 100 ns to 3.15 µs. Selecting a value of 0, 1, or 2 will set the dead time to 100 ns. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 62 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 3: Gate drive config 0 0 0 1 1 WR 4: Gate drive config 0 0 1 0 0 WR 9 0 0 8 7 6 5 4 3 2 1 IR13 IR12 IR11 IR10 IR23 IR22 IR21 IR20 0 0 0 0 0 0 0 0 IF13 IF12 IF11 IF10 IF23 IF22 IF21 IF20 0 0 0 0 0 0 0 0 Register 3: Gate Drive Configuration Register 4: Gate Drive Configuration IR1[3:0] IF1[3:0] Turn-On Current 1 IR1 = n × –5 mA 0 P P Turn-Off Current 1 IF1 = n × 5 mA where n is a positive integer defined by IR1[3:0], e.g. when IR1[3:0] = [1000] then IR1 = –40 mA. where n is a positive integer defined by IF1[3:0], e.g. when IF1[3:0] = [1100] then IF1 = 60 mA. The range of IR1 is –5 mA to –75 mA. The range of IF1 is 5 mA to 75 mA. Selecting a value of 0 will set the gate drive to switch mode to turn on the MOSFET as quickly as possible. Selecting a value of 0 will set the gate drive to switch mode to turn off the MOSFET as quickly as possible. IR2[3:0] Turn-On Current 2 IR2 = n × –5 mA IF2[3:0] Turn-Off Current 2 IF2 = n × 5 mA where n is a positive integer defined by IR2[3:0], e.g. when IR2[3:0] = [0010] then IR2 = –10 mA. where n is a positive integer defined by IF2[3:0], e.g. when IF2[3:0] = [0011] then IF2 = 15 mA. The range of IR2 is –5 mA to –75 mA. The range of IF2 is 5 mA to 75 mA. Selecting a value of 0 will set the gate drive to switch mode to turn on the MOSFET as quickly as possible. Selecting a value of 0 will set the gate drive to switch mode to turn off the MOSFET as quickly as possible. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 63 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 5: Gate drive config 0 0 1 0 1 WR 6: Current limit config 0 0 1 1 0 WR 9 8 7 6 5 TRS3 TRS2 TRS1 TRS0 0 0 0 0 4 3 2 1 TFS3 TFS2 TFS1 TFS0 0 0 0 0 VIL3 VIL2 VIL1 VIL0 1 1 1 1 0 OBT4 OBT3 OBT2 OBT1 OBT0 0 0 1 1 1 Register 5: Gate Drive Configuration Register 6: Current Limit Configuration TRS[3:0] OBT[4:0] Current Limit Blank Time Slew Control Turn-On Time tRS = n × 50 ns where n is a positive integer defined by OBT[4:0], e.g. when OBT[4:0] = [1 0000] then tOCB = 3.6 µs. The range of tRS is 0 ns to 750 ns. The range of tOCB is 1 µs to 6.6 µs. Slew Control Turn-Off Time tFS = n × 50 ns where n is a positive integer defined by TFS[3:0], e.g. when TFS[3:0] = [1100] then tFS = 600 ns. The range of tFS is 0 ns to 750 ns. P P tOCB = (n + 2) × 200 ns where n is a positive integer defined by TRS[3:0], e.g. when TRS[3:0] = [0110] then tRS = 300 ns. TFS[3:0] 0 Setting a value of OBT = 0, 1, 2, and 3 will set the blank time to 1 µs. VIL[3:0] Current Limit Scale VILIM defined by Scale × Maximum Threshold: VIL3 VIL2 VIL1 VIL0 Scale 0 0 0 0 1/16 0 0 0 1 2/16 0 0 1 0 3/16 0 0 1 1 4/16 0 1 0 0 5/16 0 1 0 1 6/16 0 1 1 0 7/16 0 1 1 1 8/16 1 0 0 0 9/16 1 0 0 1 10/16 1 0 1 0 11/16 1 0 1 1 12/16 1 1 0 0 13/16 1 1 0 1 14/16 1 1 1 0 15/16 1 1 1 1 16/16 Default Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com D 64 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 7: VDS monitor 0 0 1 1 1 WR 8: VDS monitor 0 1 0 0 0 WR 9: Watchdog config 0 1 0 0 1 WR 10: Watchdog config 0 1 0 1 0 WR 9 8 7 MIT1 MIT0 0 0 0 VDQ 0 0 6 5 4 3 2 1 VT5 VT4 VT3 VT2 VT1 VT0 0 1 1 1 1 1 VQT5 VQT4 VQT3 VQT2 VQT1 VQT0 0 1 1 1 1 1 1 WM4 WM3 WM2 WM1 WM0 0 0 0 0 0 0 0 0 0 WC3 WC2 WC1 WC0 WW4 WW3 WW2 WW1 WW0 0 0 0 0 0 0 0 0 0 Register 7: VDS Monitor and Sense Amp Configuration Register 9: Watchdog Configuration MIT[1:0] WM[4:0] VT[5:0] Sense Amp Maximum Threshold Maximum Threshold Default 0 0 200 mV 0 1 100 mV where n is a positive integer defined by WM[4:0], e.g. when WM[4:0] = [0 1010] then tWM = 21 ms. 1 0 50 mV The range of tWM is 1 ms to 63 ms. 1 1 25 mV WC[3:0] where n is a positive integer defined by VT[5:0], e.g. when VT[5:0] = [01 1000] then VDST = 1.2 V The range of CWC is 1 to 15. VDS Fault Qualifier Mode 0 Debounce 1 Blank |n>0 where n is a positive integer defined by WC[4:0], e.g. when WC[3:0] = [1010] then CWC = 10. Register 8: VDS Monitor Configuration VDS Fault Qualifier P Watchdog Fail Cycle Count Before Sleep CWC = n The range of VDST is 0 to 3.15 V. VDQ P Register 10: Watchdog Configuration VDST = n × 50 mV VDQ P tWM = 1 + (n × 2) ms MIT0 VDS Overvoltage Threshold P Watchdog Minimum Time MIT1 D 0 Default D VQT[5:0] VDS Qualify Time tVDQ = n × 50 ns where n is a positive integer defined by VQT[5:0], e.g. when VQT[5:0] = [01 1000] then tVDQ = 1.2 µs. Setting WC[3:0] to [0000] disables the watchdog cycle counter. WW[4:0] Watchdog Window Time tWW = 10 + (n × 10) ms where n is a positive integer defined by WW[4:0], e.g. when WW[4:0] = [0 1010] then tWW = 110 ms. The range of tWW is 10 ms to 320 ms. The useable range of tVDQ is 600 ns to 3.15 µs. Setting a value of VQT = 0 may result in false VDS undervoltage fault detection. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 65 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 11: Commutation 0 1 0 1 1 WR 12: Commutation 0 1 1 0 0 WR 9 0 8 7 6 5 4 3 2 1 CP3 CP2 CP1 CP0 CI3 CI2 CI1 CI0 0 1 1 1 0 1 1 1 CIT3 CIT2 CIT1 CIT0 0 0 0 0 CPT3 CPT2 CPT1 CPT0 0 0 0 0 0 Register 11: Commutation Configuration Register 12: Commutation Configuration CP[3:0] CPT[3:0] Steady-State Commutation Controller Proportional Gain Position control proportional gain is KCP defined as: KCP = 2(n-7) KCP = 2(n-7) The range of KCP is 1/128 to 256. The range of KCP is 1/128 to 256. Position control proportional gain is KCI defined as: KCI = 2(n-7) P Transient Commutation Controller Proportional Gain where n is a positive integer defined by CP[3:0], e.g., when CP[3:0] = [1000] then KCP = 2. Steady-State Commutation Controller Integral Gain P Position control proportional gain is KCP defined as: where n is a positive integer defined by CP[3:0], e.g., when CP[3:0] = [1000] then KCP = 2. CI[3:0] 0 CIT[3:0] Transient Commutation Controller Integral Gain Position control proportional gain is KCI defined as: KCI = 2(n-7) where n is a positive integer defined by CI[3:0], e.g., when CI[3:0] = [1000] then KCI = 2. where n is a positive integer defined by CI[3:0], e.g., when CI[3:0] = [1000] then KCI = 2. The range of KCI is 1/128 to 256. The range of KCI is 1/128 to 256. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 66 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 13: BEMF config 0 1 1 0 1 WR 14: BEMF config 0 1 1 1 0 WR 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 BW4 BW3 BW2 BW1 BW0 0 0 1 0 0 BS1 BS0 BF3 BF2 BF1 BF0 0 0 0 0 0 1 Register 13: BEMF Configuration Register 14: BEMF Configuration BW[4:0] BS[1:0] BEMF Detection Window For values up to 30, the window is defined as: θBW = (n + 1) × 1.4°(elec) |n=0..30 θBW = 60°(elec) |n=31 where n is a positive integer defined by BW[4:0], e.g. when BW[4:0] = [0 1010] then θBW = 15.4°(elec). The range of θBW is 1.4° to 43.4° and 60°. Note: all angles refer to the electrical cycle. 0 P P BEMF Sampling BS1 BS0 0 0 1 0 1 2 1 0 3 1 1 6 BF[3:0] Samples per Cycle Default D Windmill BEMF Filter Time tBF defined by: BF3 BF2 BF1 BF0 Filter Time 0 0 0 0 0 0 0 0 1 200 µs 0 0 1 0 400 µs 0 0 1 1 600 µs 0 1 0 0 800 µs 0 1 0 1 1 ms 0 1 1 0 2 ms 0 1 1 1 4 ms 1 0 0 0 5 ms 1 0 0 1 6 ms 1 0 1 0 10 ms 1 0 1 1 12 ms 1 1 0 0 14 ms 1 1 0 1 16 ms 1 1 1 0 18 ms 1 1 1 1 20 ms Default Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com D 67 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 15: Startup config 0 1 1 1 1 WR 16: Startup config 1 0 0 0 0 WR 9 8 7 6 5 4 3 2 1 HT3 HT2 HT1 HT0 HD4 HD3 HD2 HD1 HD0 0 0 0 1 0 0 1 0 1 STM RSC KM3 KM2 KM1 KM0 HR1 HR0 0 0 0 1 1 1 0 0 0 Register 15: Startup Configuration Register 16: Startup Configuration HT[3:0] STM Alignment (Hold) Time STM where n is a positive integer defined by HT[3:0], e.g. when HT[3:0] = [0010] then tHOLD = 400 ms. HD[4:0] RSC Start Coast Mode 0 Coast disabled 1 Coast enabled RSC DH = (n + 1) × 3.125% The range of DH is 3.125% to 100%. P Default D Restart Control Peak PWM Duty During Alignment where n is a positive integer defined by HD[3:0], e.g. when HQ[3:0] = [0101] then DH = 18.75%. P Start Coast Mode Select tHOLD = n × 200 ms The range of tHOLD is 0 to 3 s. 0 KM[3:0] Restart Mode 0 No restart 1 Allow restart after loss of sync Default D Motor Constant (Ratio Between Speed and BEMF) KM = 0.3 + (n × 0.05) where n is a positive integer defined by KM[3:0], e.g. when KM[3:0] = [0110] then KM = 0.6. The range of KM is 0.3 to 1.05. HR[1:0] Alignment Duty Cycle Ramp Time HR1 HR0 0 0 Time to reach peak D 0 Default D 0 1 25% tHOLD 1 0 50% tHOLD 1 1 100% tHOLD Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 68 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 17: Startup config 1 0 0 0 1 WR 18: Startup config 1 0 0 1 0 WR 9 8 7 WIN 0 0 6 5 4 0 1 0 0 1 1 1 SF23 SF22 SF21 SF20 SF13 SF12 SF11 SF10 0 1 1 1 0 1 1 1 WIN SF2[3:0] Windmill Mode 0 Windmilling disabled 1 Windmilling enabled Default WMF[2:0] Minimum Windmill Detection Frequency fWM = 0.4 + (n × 3.2) Hz where n is a positive integer defined by WMF[3:0], e.g. when WMF[2:0] = [010] then fWM = 6.8 Hz. The range of fWM is 0.4 Hz to 22.8 Hz. WBD[3:0] Duty Cycle During Windmill Braking D 1 WMF2 WMF1 WMF0 WBD3 WBD2 WBD1 WBD0 Register 18: Startup Configuration WIN 2 0 Register 17: Startup Configuration Windmill Mode Select 3 0 P P Start Ramp Final Frequency fS2 = 10 + (n × 2.5) Hz where n is a positive integer defined by SF2[3:0], e.g. when SF2[3:0] = [0111] then fS2 = 27.5 Hz. The range of fS2 is 10 Hz to 47.5 Hz. SF1[3:0] Start Ramp Initial Frequency fS1 = 0.5 + (n × 0.5) Hz where n is a positive integer defined by SF1[3:0], e.g. when SF1[3:0] = [0111] then fS1 = 4 Hz. The range of fS1 is 0.5 Hz to 8 Hz. DWB = (n + 1) × 6.25% where n is a positive integer defined by WBD[3:0], e.g. when WBD[3:0] = [0111] then DWB = 50% The range of DWB is 6.25% to 100%. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 69 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 19: Startup config 1 0 0 1 1 WR 20: Startup config 1 0 1 0 0 WR 9 0 0 8 7 6 5 4 3 2 1 SD23 SD22 SD21 SD20 SD13 SD12 SD11 SD10 0 1 1 1 0 1 1 1 STS3 STS2 STS1 STS0 SFS3 SFS2 SFS1 SFS0 0 1 0 0 0 1 1 1 Register 19: Startup Configuration Register 20: Startup Configuration SD2[3:0] STS[3:0] Start Ramp Final Duty Cycle DS2 = (n + 1) × 6.25% where n is a positive integer defined by SD2[3:0], e.g. when SD2[3:0] = [0111] then DS2 = 50%. The range of DS2 is 6.25% to 100%. SD1[3:0] Start Ramp Initial Duty Cycle DS1 = (n + 1) × 6.25% where n is a positive integer defined by SD1[3:0], e.g. when SD1[3:0] = [0100] then DS1 = 31.25% The range of DS1 is 6.25% to 100%. 0 P P Start Ramp Step Time tSS = 10 ms |n=0 tSS = n × 20 ms |n=1..15 where n is a positive integer defined by STS[3:0], e.g. when STS[3:0] = [0100] then tSTS = 80 ms. The range of tSTS is 10 ms to 300 ms. SFS[3:0] Start Ramp Frequency Step fSS defined by: SFS3 SFS 2 SFS 1 SFS 0 Frequency Step 0 0 0 0 0.0125 Hz 0 0 0 1 0.025 Hz 0 0 1 0 0.05 Hz 0 0 1 1 0.1 Hz 0 1 0 0 0.2 Hz 0 1 0 1 0.4 Hz 0 1 1 0 0.8 Hz 0 1 1 1 1 Hz 1 0 0 0 1.5 Hz 1 0 0 1 2 Hz 1 0 1 0 2.5 Hz 1 0 1 1 3 Hz 1 1 0 0 5 Hz 1 1 0 1 8 Hz 1 1 1 0 10 Hz 1 1 1 1 15 Hz Default Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com D 70 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 21: Speed loop 1 0 1 0 1 WR 22: Speed loop 1 0 1 1 0 WR 23: Speed loop 1 0 1 1 1 WR 9 8 7 6 5 SGL4 SGL3 SGL2 SGL1 SGL0 3 2 1 SG3 SG2 SG1 SG0 1 0 1 0 1 SR2 SR1 SR0 0 0 0 0 0 0 SL2 SL1 SL0 SH3 SH2 SH1 SH0 1 1 1 0 1 1 1 0 0 1 0 DV1 DV0 DF1 DF0 0 1 0 SL3 0 0 4 0 P P P Register 21: Speed Control Loop Configuration Register 22: Speed Control Loop Configuration (continued) SGL[4:0] SR[2:0] Speed Control Acceleration Limit KSL = 6.3 + (n × 6.4) Hz where n is a positive integer defined by SGL[4:0], e.g. when SGL[4:0] = [0 0111] then KSL = 51.5 Hz. The range of KSL is 6.3 Hz to 204.7 Hz. SG[3:0] Speed Control Gain KS = 1 + (n × 2) where n is a positive integer defined by SG[3:0], e.g., when SG[3:0] = [1000] then KS = 9. The range of KS is 1 to 31. Speed Control Resolution SR2 SR1 SR0 Speed Resolution Default 0 0 0 0.1 Hz D 0 0 1 0.2 Hz 0 1 0 0.4 Hz 0 1 1 0.8 Hz 1 0 0 1.6 Hz 1 0 1 3.2 Hz 1 1 0 3.2 Hz 1 1 1 3.2 Hz Register 22: Speed Control Loop Configuration Register 23: Speed Control Loop Configuration DV[1:0] SL[3:0] Duty Cycle Compensation DV1 DV0 0 0 Disabled 0 1 12 V 1 0 24 V 1 1 12 V DF[1:0] Nominal supply voltage Default D DF0 0 0 Deceleration factor 1 0 1 2 1 0 5 1 1 10 fSL = 8 × n × fRES (Hz) where n is a positive integer defined by SL[3:0], fSL is the underspeed threshold, and fRES is the speed resolution defined by SR[2:0]. SH[3:0] Underspeed (High-Speed) Threshold fSH = [127 + (n × 128)] × fRES (Hz) Deceleration Factor DF1 Underspeed (Low-Speed) Threshold Default where n is a positive integer defined by SH[3:0], fSH is the underspeed threshold, and fRES is the speed resolution defined by SR[2:0]. D Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 71 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 24: NVM Write 1 1 0 0 0 WR 25: System 1 1 0 0 1 WR 9 8 7 6 5 4 3 2 1 SAV1 SAV0 0 0 0 0 0 0 0 0 0 ESF VLR VRG OPM LWK IPI DIL CM1 CM0 1 0 1 0 0 0 0 0 0 Register 24: Write NVM Control Register 25: System Configuration (continued) SAV[1:0] OPM Save Parameters to Non-Volatile Memory (NVM) When SAV[1:0] is changed from 01 to 10, the present contents of registers 0 to 23, 25 to 29, and bits [10:3] of register 30 (DI[9:2]) will be written to NVM. When the NVM save has completed successfully, SAV[1:0] will be set to 01 and can be read to verify completion of the write. If SAV[1:0] is reset to 00, the save has not completed successfully. ESF Stop on Fail 0 No stop on fail 1 Stop on fail SPI only 1 Stand-alone with SPI Default D Wake Mode Select Wake Mode Default 0 PWM Wake Mode 1 LIN Wake Mode D Default IPI PWM Input Sense (when OPM = 1) IPI D PWM Sense Default 0 True, Active high 1 Inverted, Active low D Logic Regulator Voltage VLR VRG P Enable Stop On Fail Select ESF VLR Operating Mode 0 LWK Register 25: System Configuration P Operating Mode Select OPM LWK 0 Logic Regulator Voltage 0 3.3 V 1 5V Default DIL D Disable Current Limit (Speed Modes) DIL Current Limit 0 Enabled 1 Disabled Default D Gate Drive Regulator Voltage VRG Gate Drive Regulator Voltage 0 8V 1 11 V Default D CM[1:0] Selects Motor Control Mode CM1 CM0 Motor Control Mode 0 0 Closed-loop speed 0 1 Closed-loop speed 1 0 Closed-loop current 1 1 Open-loop speed Default D Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 72 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 26: Phase advance 1 1 0 1 0 WR 27: Motor function 1 1 0 1 1 WR 9 8 7 6 5 4 3 2 1 PAM KIP1 KIP0 PA5 PA4 PA3 PA2 PA1 PA0 0 0 0 0 0 0 0 0 0 LEN GTS BRK DIR RUN 0 0 0 0 0 0 OVM1 OVM0 DRM 0 0 0 Register 26: Phase Advance Select Register 27: Motor Function Control (continued) PAM GTS Phase Advance Mode PAM KIP[1:0] PA[5:0] Phase Advance Mode 0 Manual 1 Automatic KIP1 KIP0 0 0 1 Gain GTS D 0 No change in state 1 No change in state 1→0 No change in state 0→1 Enter sleep state if enabled 0 1 2 1 0 4 1 1 8 Default D |n=0..62 θADV = 60°(elec) |n=63 DRM where n is a positive integer defined by PA[5:0], e.g. when PA[5:0] = [00 1000] then θADV = 5.6°. BRK Note: All angles refer to the electrical cycle. Lin Enable LEN LIN State 0 Standby 1 Active OVM0 0 0 None (100%) 0 1 112.5% 1 0 125% 1 1 150% Default Default D DIR D Drive mode 0 Sinusoidal 1 Trapezoidal Default D Default D Brake Function Select Brake Mode Default 0 Brake disabled 1 Brake enabled D Rotation Direction Select DIR RUN Overmodulation Drive Mode Select BRK Register 27: Motor Function Control LEN Sleep transition OVM1 DRM The range of θADV is 0 to 43.4° and 60°. P OVM[1:0] Overmodulation Select Phase Advance θADV = n × 0.7°(elec) P Go to Sleep Command Default Auto Phase Advance Control Gain 0 Direction Default 0 Forward (Figure 6, Figure 7, and Table 1) 1 Reverse (Figure 6, Figure 7, and Table 1) D Run enable RUN Motor running status 0 Disable outputs, coast motor 1 Start and run motor Default D Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 73 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 10 1 1 1 0 0 WR FF POR SE VPU CLI 28: Mask Status 9 8 7 6 5 4 3 2 1 WD LOS OT TW VSU VRU VLU BU VO 1 0 0 0 0 0 0 0 0 WD LOS OT TW VSU VRU VLU BU VO 0 0 0 0 0 0 0 0 0 Register 28: Mask Register Status Register WD Watchdog FF Status register flag (not including CLI) LOS Loss of bemf synchronization POR Power-on-reset OT Overtemperature SE Serial transfer error TW Temperature warning VPU VPP undervoltage VSU VBB undervoltage CLI Current limit* VRU VREG undervoltage WD Watchdog VLU VLR undervoltage LOS Loss of bemf synchronization BU Bootstrap undervoltage OT Overtemperature VO VDS overvoltage TW Temperature warning VSU VBB undervoltage VRU VREG undervoltage VLU VLR undervoltage BU Bootstrap undervoltage VO VDS fault xx Fault Mask 0 Fault detection permitted 1 Fault detection disabled Default D xx Fault 0 No fault detected 1 Fault detected 0 P P *The state of the CLI bit is not reported by the Status register flag. CLI reporting is described in the Current Limit section Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 74 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 29: Readback Select 15 14 13 12 11 10 1 1 1 0 1 WR 9 8 7 DGS1 DGS0 0 6 DSR 0 0 0 5 4 3 LBR CKS 0 0 0 Register 29: Readback Select (continued) DGS[1:0] Selects output DIAG terminal. RBS[2:0] Selects data output on register 31 DGS0 0 0 Active low fault flag 0 1 FG; high when motor is stationary 1 1 DSR Enabled 1 Disabled 0 P 0 RBS2 RBS1 RBS0 Register 31 contents Default D 0 0 0 Diagnostic register D 0 0 1 Motor speed 0 1 0 Average supply current Pulse output; high when no fault present Pulse output; FG when no fault present Reset on serial read 0 0 1 1 Supply voltage 1 0 0 Chip temperature 1 0 1 Demand input 1 1 0 Applied bridge peak duty cycle 1 1 1 Applied phase advance Default D Selects LIN baud rate LBR CKS 1 0 Default Serial reset of fault state and fault bit DSR LBR 0 DIAG Output 1 RBS2 RBS1 RBS0 Register 29: Readback Select DGS1 2 LIN Baud Rate 0 10 kHz 1 20 kHz Default D Selects output on SDO when STRn = 1 CKS SDO Output (STRn = 1) 0 High impedance 1 Divided system clock Default D Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 75 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 15 14 13 12 11 1 1 1 1 0 30: Write Only 10 9 8 7 6 5 4 3 2 1 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 0 0 0 0 0 0 0 0 0 0 0 P Register 30: Demand input (Write Only) DI[9:0] (CM=0,1) Speed Reference fREF = n × fRES (Hz) where n is a positive integer defined by DI[9:0], fREF is the reference speed for the control loop, fRES is the speed resolution defined by SR[2:0]. DI[9:0] (CM=2) Current Limit VILIM = n.OR.0h01F ×VMIT 1023 where n is a positive integer defined by DI[9:0], (note: n is logically OR’d with 0h01F to restrict selection to the most significant 5 bits), and VMIT is the maximum threshold voltage of the sense amplifier as defined by the MIT variable. DI[9:0] (CM=3) Bridge PWM Duty Cycle n DPK = 1023 % where n is a positive integer defined by DI[9:0], and DPK is the bridge peak duty cycle. In sinsoidal drive mode, DPK is modulated by the sine generator to produce the actual bridge PWM duty cycle for each PWM period. In trapezoidal drive mode, DPK is the duty cycle applied to the bridge. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 76 A4964 Sensorless Sinusoidal Drive BLDC Controller Serial Register Reference 31: Read Only 15 14 13 12 11 1 1 1 1 1 10 9 8 7 6 5 4 3 2 1 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 0 0 0 0 0 0 0 0 0 0 Register 31: Readback Register (Read Only) Register 31: Readback Register (Read Only) (continued) Bits 15 - 13 DO[9:0] (RBS=1) FF Status register flag POR Power-on-reset SE Serial transfer error The contents of DO[9:0] are selected by the RBS[2:0] variable as follows: DO[9:0] Motor Speed (continued) The OSR bit can be used as an additional 11th bit with twice the significance of bit DO9. The motor speed is also available during windmill detection in the forward direction. DO[9:0] (RBS=2) DO9 OSR Over speed range DO8 BA Bootstrap fault detected on Phase A high-side DO7 BB Bootstrap fault detected on Phase B high-side DO6 BC Bootstrap fault detected on Phase C high-side DO5 AH VDS fault detected on Phase A high-side DO4 AL VDS fault detected on Phase A low-side DO3 BH VDS fault detected on Phase B high-side DO2 BL VDS fault detected on Phase B low-side DO1 CH VDS fault detected on Phase C high-side DO0 CL VDS fault detected on Phase C low-side (RBS=1) P Diagnostic register (RBS=0) D0[9:0] 0 xx Fault 0 No fault detected 1 Fault detected Motor Speed fE = n × fRES (Hz) where n is a positive integer defined by DO[9:0], fRES is the speed resolution defined by SR[2:0], and fE is the electrical cycle frequency of the controller. The motor speed can be calculated from: fE ×60 ~M = NPP (rpm) where ωM is the motor speed in rpm, fE is the electrical cycle frequency, and NPP is the number of pole-pairs in the rotor. Average Supply Current n ISAVG = 1.76 × AV × RSENSE (A) where n is a positive integer defined by DO[9:0], RSENSE is the sense resistor value in mΩ, and AV is the gain of the sense amplifier as defined by the SA variable. DO[9:0] (RBS=3) Supply Voltage VS = n × 0.0528 (V) where n is a positive integer defined by by DO[9:0]. The measurement range is 0 to 50.4 V. DO[9:0] (RBS=4) Chip Temperature TJ = 367.7 – (n × 0.451) (°C) where n is a positive integer defined by by DO[9:0]. The result range is –93°C to 367°C, but the useable measurement range is –50°C to 190°C. DO[9:0] (RBS=5) Demand Input Readback contents of DI[9:0]. DO[9:0] (RBS=6) Applied Bridge Peak Duty Cycle n DBR = 1023 (%) where n is a positive integer defined by DO[9:0]. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 77 A4964 Sensorless Sinusoidal Drive BLDC Controller Register 31: Readback Register (Read Only) (continued) DO[9:0] (RBS=7) Applied Phase Advance The applied phase advance, θADV, when PAM = 0 (manual) is defined by: θADV = n ×0.7°(elec) |n = 0..62 θADV = 60°(elec) |n = 63 where n is a positive integer defined by DO[9:0]. The applied phase advance, θADV, when PAM = 1 (automatic) is defined by: θADV = n × 0.7°(elec) where n is a positive integer defined by DO[9:0]. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 78 A4964 Sensorless Sinusoidal Drive BLDC Controller APPLICATIONS INFORMATION Dead Time Selection is transferred from CBOOT to the MOSFET gate. The choice of power MOSFET and external series gate resistance determines the selection of the dead time. The dead time, tDEAD, should be made long enough to ensure that one MOSFET has stopped conducting before the complementary MOSFET starts conducting. This should also account for the tolerance and variation of the MOSFET gate capacitance, the series gate resistance and the on-resistance of the driver in the A4964. To keep the voltage drop due to charge sharing small, the charge in the bootstrap capacitor, QBOOT, should be much larger than QGATE, the charge required by the gate: VGHA-VSA A factor of 20 is a reasonable value. QBOOT = CBOOT × VBOOT = QGATE × 20 CBOOT = (QGATE × 20) / VBOOT VGLA VGSL QBOOT ≫ QGATE where VBOOT is the voltage across the bootstrap capacitor. tdead The voltage drop, ∆V, across the bootstrap capacitor as the MOSFET is being turned on can be approximated by: ∆V = QGATE / CBOOT Vt0 VGSH Figure 24: Minimum Dead Time Figure 24 shows the typical switching characteristics of a pair of complementary MOSFETs. Ideally, one MOSFET should start to turn on just after the other has completely turned off. The point at which a MOSFET starts to conduct is the threshold voltage Vt0. The dead time should be long enough to ensure that the gatesource voltage of the MOSFET that is switching off is just below Vt0 before the gate-source voltage of the MOSFET that is switching on rises to Vt0. This will be the minimum theoretical dead time, but in practice the dead time will have to be longer than this to accommodate variations in MOSFET and driver parameters for process variations and over temperature. Bootstrap Capacitor Selection The A4964 requires three bootstrap capacitors: CA, CB, and CC. To simplify this description of the bootstrap capacitor selection criteria, generic naming is used here. So, for example, CBOOT, QBOOT, and VBOOT refer to any of the three capacitors, and QGATE refers to any of the six associated MOSFETs. CBOOT must be correctly selected to ensure proper operation of the device: too large and time will be wasted charging the capacitor, resulting in a limit on the maximum duty cycle and PWM frequency; too small and there can be a large voltage drop at the time the charge so for a factor of 20, ∆V will be 5% of VBOOT. The maximum voltage across the bootstrap capacitor under normal operating conditions is VREG max. However, in some circumstances the voltage may transiently reach a maximum of 18 V, which is the clamp voltage of the Zener diode between the Cx terminal and the Sx terminal. In most applications, with a good ceramic capacitor the working voltage can be limited to 16 V. Bootstrap Charging It is good practice to ensure the high-side bootstrap capacitor is completely charged before a high-side PWM cycle is requested. The time required to charge the capacitor, tCHARGE, in µs, is approximated by: tCHARGE = (CBOOT × ∆V) / IDBOOT where CBOOT is the value of the bootstrap capacitor in nF, ∆V is the required voltage of the bootstrap capacitor, and IDBOOT is the bootstrap diode current limit, typically 500 mA. At power up and when the drivers have been disabled for a long time, the bootstrap capacitor can be completely discharged. In this case, ∆V can be considered to be the full high-side drive voltage. Otherwise, ∆V is the amount of voltage dropped during the charge transfer, which should be 400 mV or less. The capacitor is charged whenever the Sx terminal is pulled low and current flows from CREG, the capacitor connected to the VREG terminal through the internal bootstrap diode circuit to CBOOT. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 79 A4964 Sensorless Sinusoidal Drive BLDC Controller VREG Capacitor Selection The internal reference, VREG, supplies current for the low-side gate-drive circuits and the charging current for the bootstrap capacitors. When a low-side MOSFET is turned on, the gatedrive circuit will provide the high transient current to the gate that is necessary to turn the MOSFET on quickly. This current, which can be several hundred milliamperes, cannot be provided directly by the limited output of the VREG regulator but must be supplied by an external capacitor, CREG, connected between the VREG terminal and GND. The turn-on current for the high-side MOSFET is similar in value but is mainly supplied by the bootstrap capacitor. However, the bootstrap capacitor must then be recharged from CREG through the VREG terminal. Unfortunately, the bootstrap recharge can occur a very short time after the low-side turn-on occurs. This means that the value of CREG between VREG and GND should be high enough to minimize the transient voltage drop on VREG for the combination of a low-side MOSFET turn-on and a bootstrap capacitor recharge. For block commutation control (trapezoidal drive),where only one high-side and one low-side are switching during each PWM period, a minimum value of 20 × CBOOT is reasonable. For sinusoidal control schemes, a minimum value of 40 × CBOOT is recommended. As the maximum working voltage of CREG will never exceed VREG, the part’s voltage rating can be as low as 15 V. However, it is recommended that a capacitor rated to at least twice the maximum working voltage should be used to reduce any impact operating voltage may have on capacitance value. For best performance, CREG should be ceramic rather than electrolytic. If the required value of CREG is too large for a single ceramic capacitor, then a low ESR electrolytic capacitor may be used, with a ceramic capacitor greater than 100 nF in parallel to provide the initial current peak. CREG should be mounted as close to the VREG terminal as possible. Braking In the A4964, setting the BRK bit to 1 when RUN = 1 will enable dynamic braking by forcing all low-side MOSFETs on and all high-side MOSFETs off. This will effectively short-circuit the back-emf of the motor, creating a braking torque. During braking, the load current, IBRAKE, can be approximated by: IBRAKE = VBEMF / RL where VBEMF is the voltage generated by the motor and RL is the resistance of the phase winding. Care must be taken during braking to ensure that the power MOSFETs’ maximum ratings are not exceeded. Dynamic braking is equivalent to slow decay with synchronous rectification and all phases enabled. The A4964 can also be used to perform regenerative braking. This is equivalent to using fast decay with synchronous rectification. Note that the supply must be capable of managing the reverse current, for example, by connecting a resistive load or dumping the current to a battery or capacitor. Current Sense Amplifier The output of the sense amplifier takes two paths. One path is to a comparator to set the current limit, and the other is to a filter an analog-to-digital converter (ADC) to provide a digital average current measurement. The current limit comparator operates on the output of the sense amplifier. This output is compared to current limit threshold voltage, VILIM, to indicate to the PWM control circuit when the bridge current is greater than the current limit threshold. The value of VILIM can be set in two ways, depending on the motor control method selected. When either of the speed control modes are selected, the value of VILIM is determined by: VILIM = VMIT × VISC where VMIT is the maximum threshold of the sense amplifier as defined by the MIT variable, and VISC is the current limit scale as defined by the VIL variable. When the closed-loop current control mode is selected, VILIM is determined by demand input. This sets the required value of VILIM as a ratio of the maximum threshold (VMIT). For example, when the demand input is 256 and VMIT is 200 mV, then VILIM will be 50 mV. In this mode, only the 5 most significant bits of the 10-bit demand input are used to set the value of VILIM. The relationship between the threshold voltage and the threshold current is defined as: ILIM = VILIM / RSENSE where RSENSE is the value of the sense resistor. As the average current filter and ADC also operates on the output of the sense amplifier, the average current value calculation is also dependent on the sense resistor value, and the amplifier gain Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 80 A4964 Sensorless Sinusoidal Drive BLDC Controller and is defined as: Systems with Low-Level Input Requirements where n is a positive integer defined by DO[9:0], RSENSE is the sense resistor value in mΩ, and AV is the gain of the sense amplifier as defined by the SA variable. In systems where the PWM input does not require negative voltage protection and the ECU requires a lower voltage level on the PWM signal before an error feedback is recognised, then the pull-down on the PWM signal can be driven directly by the DIAG output, as shown in Figure 25d, or by an additional pulldown transistor, as shown in Figure 25b. n ISAVG = 1.76 × AV × RSENSE (A) Single-Wire PWM Diagnostic Feedback When operating in LIN mode, the diagnostic information will usually be transmitted to the ECU (central electronic control unit) through the LIN protocol message. When operating in single-wire PWM mode, any diagnostic or error information can be transmitted to the ECU by pulling the incoming PWM signal line to a low level. The PWM source at the ECU must be a passive (resistor) pull-up with active pull-down for this to be possible. The specific method employed for this function will depend on the source of the error information and the requirements of the PWM interface to the ECU. Systems with Negative Voltage Requirements In systems where the PWM input must be able to withstand a significant negative voltage with respect to ground, then the circuit used to pull down the PWM signal must include reverse voltage protection. In these cases, the pull-down output of the LIN terminal on the A4964 can be used to pull the PWM input down to the LIN dominant output voltage level. The PWM source in the ECU must be able to recognise this level (max 2 V) as a valid low level on the PWM signal, indicating and error feedback signal is present. The pull-down output of the LIN terminal on the A4964 is controlled by the LTX input. When the LTX input is low, the LIN output pull-down will be active. When LTX is high, the LIN output pull-down will be off. The LTX input can be driven directly by the DIAG output when the A4964 is used without an external MCU, as shown in Figure 25c. In this case, the internal pull-up in the LTX input will provide the logic high level input. If a faster response is required, this pull-up resistor can be supplemented by an external pull-up resistor connected to the logic regulator output, VLR. Alternatively, when an external MCU is used to manage the interface to the ECU, a logic output from the MCU can be used to drive the LTX input directly, as shown in Figure 25a. The DIAG output is capable of sinking 4 mA at an output voltage of 0.4 V. To ensure the output low level on the DIAG output does not exceed the maximum voltage, the total pull-up resistance connected to the PSM signal node must have a high enough value to ensure that the current into the DIAG output does not exceed 4 mA during normal operation. For example, if the maximum bus voltage during operation is 16 V, then the resistance must be greater than 3.9 kΩ. If the bus must operate at 28 V, then then the resistance must be greater than 6.9 kΩ. The DIAG output is also capable of surviving a voltage up to 50 V without damage and so will not be damaged should the PWM signal reach these levels during a load-dump event. As described above, for the case where the DIAG output is used, any additional external pull-down transistor must also be capable of pulling the PWM signal to the required level and may also have to survive any load-dump voltage on the PWM signal. A4964 PWM Signal Error Signal A4964 PWM Signal LIN LTX LIN LTX LRX MCU LRX MCU DIAG a: MCU using LTX DIAG b: MCU using Transistor A4964 PWM Signal VLR A4964 PWM Signal LIN LIN LTX LTX LRX LRX DIAG DIAG Optional c: DIAG using LTX b: DIAG to PWM Figure 25: Error Signal Feedback Options Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 81 A4964 Sensorless Sinusoidal Drive BLDC Controller LAYOUT RECOMMENDATIONS Careful consideration must be given to PCB layout when designing high-frequency, fast-switching, high-current circuits: • The two ground terminals of the QFN (EV) package, both designated GND, are internally connected, but must also be connected together on the PCB close to the device for correct operation. This common point should return separately to the negative side of the motor supply filtering capacitor. This will minimize the effect of switching noise on the device logic and analog reference. • The ground terminal of the QFP (JP) package should return separately to the negative side of the motor supply filtering capacitor. • The exposed thermal pad should be connected to the GND terminals. • Minimize stray inductance by using short, wide copper tracks at the drain and source terminals of all power MOSFETs and the input power bus. Particular care should be taken around the common source of the low-side power MOSFETs and the sense resistor. This will minimize voltages induced by fast switching of large load currents. • Consider the addition of small (100 nF) ceramic decoupling capacitors across the source and drain of the power MOSFETs to limit fast transient voltage spikes caused by track inductance. • Keep the gate discharge return connections Sx as short as possible. Any inductance on these tracks will cause negative transitions on the corresponding A4964 terminals, which may exceed the absolute maximum ratings. If this is likely, consider the use of clamping diodes to limit the negative excursion on these terminals with respect to the GND terminals. • Decoupling for the supply should be provided by typically a 10 µF low ESR electrolytic capacitor and 100 nF ceramic capacitor in parallel. These should be connected between VBB and GND. The ceramic capacitor in particular should be mounted as close to the A4964 terminals as possible. • The VREG capacitor should be connected between VREG and GND as close to the A4964 terminals as possible. For larger values of capacitance, a low ESR electrolytic capacitor may be used with a ceramic capacitor greater than 100 nF in parallel. In this case, the ceramic capacitor in particular should be mounted as close to the A4964 terminals as possible. • The bootstrap capacitors should be mounted close to the associated terminals of the A4964. • Gate charge drive paths and gate discharge return paths may carry a large transient current pulse. Therefore the traces from GHx, GLx, and Sx (x = A, B or C) should be as short and wide as possible to reduce the track inductance. • The inputs to the sense amplifier, CSP and CSM, should take the form of independent tracks directly to the terminals of the sense resistor, and for best results should be matched in length and route. • A low-cost diode can be placed in the connection to VBB to provide reverse battery protection. In reverse battery conditions, it is possible to use the body diodes of the power MOSFETs to clamp the reverse voltage to approximately 4 V. In this case, the additional diode in the VBB connection will prevent damage to the A4964 and the VBRG input will survive the reverse voltage. Optional reverse battery protection VBB +Supply VBRG CA CB CC Motor SA SB SC A4964 PAD GND CSP CSM GND Supply Common RSENSE Controller Supply Ground Power Ground Figure 26: Supply Routing Suggestions Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 82 A4964 Sensorless Sinusoidal Drive BLDC Controller INPUT / OUTPUT STRUCTURES C VBB 16 V GH 56 V CP1 CP2 VREG VBRG VBB VLR 30 kΩ 25 Ω S VREG 16 V GL Figure 27a: Gate Drive Outputs 6V 7.5 V 20 V HV Clamp 16 V 56 V 56 V LIN 40 V 7.5 V 50 V Figure 27b: Supplies Figure 27c: LIN Bus I/O VLR VBIAS VLR VBIAS 50 kΩ SDI SCK WDOG 1 kΩ 1 kΩ STRn 100 kΩ 115 kΩ IG 125 kΩ 7.5 V 6V 7.5 V 50 kΩ HV Clamp 6V 56 V Figure 27d: Logic Inputs with Pull-Down Figure 27e: Logic Inputs with Pull-Up 125 kΩ Figure 27f: HV Compliant Logic Inputs VLR 25 Ω 50 Ω SDO MRSTn 7.5 V Figure 27g: Logic Output CSM CSP DIAG HV Clamp 6V 7.5 V Figure 27h: Current Sense Amp Inputs 56 V Figure 27i: HV Compliant Output Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 83 A4964 Sensorless Sinusoidal Drive BLDC Controller PACKAGE OUTLINE DRAWINGS 9.00 ±0.20 7.00 ±0.20 0.55 1.65 7º 3.5° ±3.5 0º 0.80 0.15 +0.05 –0.06 B 9.00 ±0.20 7.00 ±0.20 5.00 5.00±0.04 32 1.00 REF A 1 0.60 ±0.15 32 2 0.25 BSC 5.00±0.04 1 2 SEATING PLANE GAUGE PLANE 5.00 8.60 Branded Face 32X SEATING PLANE 0.10 C +0.08 0.37 –0.07 8.60 0.80 BSC C 1.60 MAX 1.40 ±0.05 0.15 0.05 C PCB Layout Reference View For Reference Only; not for tooling use (reference MS-026 BBAHD) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface); exact dimensions may vary with device C Reference land pattern layout (reference IPC7351 QFP80P900X900X160-32BM); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Figure 28: JP Package, 32 Pin QFP with Exposed Thermal Pad Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 84 A4964 Sensorless Sinusoidal Drive BLDC Controller For Reference Only – Not for Tooling Use (Reference JEDEC MO-220VJJD-3, except pin count) Dimensions in millimeters – NOT TO SCALE Exact case and lead configuration at supplier discretion within limits shown 0.50 0.30 6.00 ±0.15 36 36 1.15 1 2 1 2 A 4.15 6.00 ±0.15 D C 37X 0.08 0.90 ±0.10 C 5.80 4.15 5.80 SEATING PLANE +0.05 0.25 –0.07 C PCB Layout Reference View 0.50 0.55 ±0.20 B 4.15 2 1 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P600X600X100-37V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 36 4.15 Figure 29: EV Package, 36 Pin QFN with Exposed Thermal Pad Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 85 A4964 Sensorless Sinusoidal Drive BLDC Controller APPENDIX A: FAULT RESPONSE ACTIONS Table A1a: Fault Response Actions (ESF = 0, VLU masked) Fault Description No Fault System Error Serial Error VBB POR VBB Undervoltage Disable Outputs RSC [7] Fault State Latched Other Action Fault State Reset Re-Enable Outputs No n/a n/a None n/a Yes [1] n/a Yes RUN = 0 POR, RUN = 1 No n/a No None POR or SPI [3] n/a n/a No Internal logic shutdown & reset Condition removed RUN = 1 0 Yes Demand input = 0, RUN = 0, or SPI [3][4] n/a 1 No 0 Yes 1 Yes Yes [1] No None Condition removed First watchdog transition after 100 ms from MRSTn going high Demand input reset [5], RUN reset [6], or SPI [3][4] Watchdog Fault Yes [1] VREG Undervoltage Yes [1] n/a No None Condition removed Bootstrap Undervoltage Yes [2] n/a No None PWM on MCU reset First watchdog transition after 100 ms from MRSTn going high Temperature Warning No n/a No None Condition removed n/a Overtemperature No n/a No None Condition removed n/a Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] Loss of Synchronization Yes [1] VDS Overvoltage Yes [2] [1] All 0 Yes SPI [3][4] 1 No Stop and restart Condition removed n/a No None PWM on gate drives low, all MOSFETs off. Gate drive for the affected MOSFET low, only the affected MOSFET off. [3] Only when DSR = 0. [4] Serial read of Status or Diagnostic register. [2] None Set demand input = 0 then set demand input to a new operating value. Set RUN bit = 0 then set RUN bit = 1. [7] Restart control bit. [5] [6] Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 86 A4964 Sensorless Sinusoidal Drive BLDC Controller Table A1b: Fault Response Actions (ESF = 1, VLU masked) Fault Description No Fault System Error Serial Error VBB POR VBB Undervoltage Disable Outputs RSC [7] Fault State Latched Other Action Fault State Reset Re-Enable Outputs No n/a n/a None n/a Yes [1] n/a Yes RUN = 0 POR, RUN = 1 No n/a No None POR or SPI [3] n/a Yes [1] n/a No Internal logic shutdown & reset Condition removed RUN = 1 Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] Yes [1] 0 1 Watchdog Fault Yes [1] VREG Undervoltage Yes [1] Bootstrap Undervoltage Yes [1] Yes None No SPI [3][4] Condition removed 0 Yes 1 Yes n/a No None n/a Yes None MCU reset First watchdog transition after 100 ms from MRSTn going high Demand input reset [5], RUN reset [6], or SPI [3][4] First watchdog transition after 100 ms from MRSTn going high Condition removed Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] SPI [3][4] Temperature Warning Overtemperature Loss of Synchronization VDS Overvoltage No Yes [1] Yes [1] Yes [1] n/a No None n/a Yes VLR regulator shutdown & MCU reset 0 Yes None Condition removed n/a First watchdog transition after 100 ms from MRSTn going high Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] SPI [3][4] 1 No Stop and restart n/a Yes None Condition removed Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] SPI [3][4] [1] All gate drives low, all MOSFETs off. Gate drive for the affected MOSFET low, only the affected MOSFET off. [3] Only when DSR = 0. [4] Serial read of Status or Diagnostic register. [2] Set demand input = 0 then set demand input to a new operating value. Set RUN bit = 0 then set RUN bit = 1. [7] Restart control bit. [5] [6] Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 87 A4964 Sensorless Sinusoidal Drive BLDC Controller Table A2a: Fault Response Actions (ESF = 0, WD masked) Fault Description No Fault System Error Serial Error VBB POR VBB Undervoltage Disable Outputs RSC [7] Fault State Latched Other Action Fault State Reset Re-Enable Outputs No n/a n/a None n/a Yes [1] n/a Yes RUN = 0 POR, RUN = 1 No n/a No None POR or SPI [3] n/a Yes [1] n/a No Internal logic shutdown & reset Condition removed RUN = 1 0 Yes Demand input = 0, RUN = 0, or SPI [3][4] n/a 1 No 0 Yes 1 Yes n/a No No None Condition removed 10 ms after condition removed when MRSTn goes high Demand input reset [5], RUN reset [6], or SPI [3][4] VLR Undervoltage Yes [1] VREG Undervoltage Yes [1] Bootstrap Undervoltage Yes [2] n/a No None Temperature Warning No n/a No None Condition removed Overtemperature No n/a No None Condition removed n/a Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] Loss of Synchronization VDS Overvoltage [1] All Yes [1] Yes [2] 10 ms after condition removed when MRSTn goes high None Condition removed PWM on n/a 0 Yes None 1 No Stop and restart Condition removed n/a No None PWM on SPI [3][4] gate drives low, all MOSFETs off. Gate drive for the affected MOSFET low, only the affected MOSFET off. [3] Only when DSR = 0. [4] Serial read of Status or Diagnostic register. [2] MCU reset Set demand input = 0 then set demand input to a new operating value. Set RUN bit = 0 then set RUN bit = 1. [7] Restart control bit. [5] [6] Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 88 A4964 Sensorless Sinusoidal Drive BLDC Controller Table A2b: Fault Response Actions (ESF = 1, WD masked) Fault Description No Fault System Error Serial Error VBB POR VBB Undervoltage Disable Outputs RSC [7] Fault State Latched Other Action Fault State Reset Re-Enable Outputs No n/a n/a None n/a Yes [1] n/a Yes RUN = 0 POR, RUN = 1 No n/a No None POR or SPI [3] n/a Yes [1] n/a No Internal logic shutdown & reset Condition removed RUN = 1 Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] Yes [1] 0 1 VLR Undervoltage Yes [1] VREG Undervoltage Yes [1] Bootstrap Undervoltage Yes [1] Yes None No SPI [3][4] Condition removed 0 Yes 1 Yes n/a No None n/a Yes None MCU reset 10 ms after condition removed when MRSTn goes high Demand input reset [5], RUN reset [6], or SPI [3][4] 10 ms after condition removed when MRSTn goes high Condition removed Demand input reset [5] or RUN reset [6] Demand input = 0 or RUN = 0 SPI [3][4] Temperature Warning Overtemperature Loss of Synchronization No Yes [1] Yes [1] n/a n/a 0 VDS Overvoltage Yes Yes None Condition removed n/a VLR regulator shutdown & MCU reset 10 ms after condition removed when MRSTn goes high Demand input reset [5], RUN reset [6], or SPI [3][4] None 10 ms after condition removed when MRSTn goes high Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] SPI [3][4] 1 Yes [1] No n/a No Yes Stop and restart None Condition removed Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] SPI [3][4] [1] All gate drives low, all MOSFETs off. Gate drive for the affected MOSFET low, only the affected MOSFET off. [3] Only when DSR = 0. [4] Serial read of Status or Diagnostic register. [2] Set demand input = 0 then set demand input to a new operating value. Set RUN bit = 0 then set RUN bit = 1. [7] Restart control bit. [5] [6] Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 89 A4964 Sensorless Sinusoidal Drive BLDC Controller Table A3a: Fault Response Actions (ESF = 0, VLR and WD masked) Fault Description No Fault System Error Serial Error VBB POR VBB Undervoltage Disable Outputs RSC [7] Fault State Latched Other Action Fault State Reset Re-Enable Outputs No n/a n/a None n/a Yes [1] n/a Yes RUN = 0 POR, RUN = 1 No n/a No None POR or SPI [3] n/a Yes [1] n/a No Internal logic shutdown & reset Condition removed RUN = 1 0 Yes Demand input = 0, RUN = 0, or SPI [3][4] n/a 1 No No None Condition removed VREG Undervoltage Yes [1] n/a No None Condition removed Bootstrap Undervoltage Yes [2] n/a No None PWM on Temperature Warning No n/a No None Condition removed n/a Overtemperature No n/a No None Condition removed n/a Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] Loss of Synchronization Yes [1] VDS Overvoltage Yes [2] [1] All 0 Yes SPI [3][4] 1 No Stop and restart Condition removed n/a No None PWM on gate drives low, all MOSFETs off. Gate drive for the affected MOSFET low, only the affected MOSFET off. [3] Only when DSR = 0. [4] Serial read of Status or Diagnostic register. [2] None Set demand input = 0 then set demand input to a new operating value. Set RUN bit = 0 then set RUN bit = 1. [7] Restart control bit. [5] [6] Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 90 A4964 Sensorless Sinusoidal Drive BLDC Controller Table A3b: Fault Response Actions (ESF = 1, VLR and WD masked) Fault Description No Fault System Error Serial Error VBB POR Disable Outputs RSC [7] Fault State Latched Other Action Fault State Reset Re-Enable Outputs No n/a n/a None n/a Yes [1] n/a Yes RUN = 0 POR, RUN = 1 No n/a No None POR or SPI [3] n/a Yes [1] n/a No Internal logic shutdown & reset Condition removed RUN = 1 Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] VBB Undervoltage Yes [1] VREG Undervoltage Yes [1] Bootstrap Undervoltage Yes [1] 0 Yes 1 No n/a No n/a Yes None SPI [3][4] Condition removed None None Condition removed Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] SPI [3][4] Temperature Warning Overtemperature Loss of Synchronization No n/a No None Yes [1] n/a Yes VLR regulator shutdown & MCU reset Yes [1] 0 VDS Overvoltage None n/a 10 ms after condition removed when MRSTn goes high Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] SPI [3][4] 1 Yes [1] Yes Condition removed n/a No Yes Stop and restart None Condition removed Demand input = 0 or RUN = 0 Demand input reset [5] or RUN reset [6] SPI [3][4] [1] All gate drives low, all MOSFETs off. Gate drive for the affected MOSFET low, only the affected MOSFET off. [3] Only when DSR = 0. [4] Serial read of Status or Diagnostic register. [2] Set demand input = 0 then set demand input to a new operating value. Set RUN bit = 0 then set RUN bit = 1. [7] Restart control bit. [5] [6] Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 91 A4964 Sensorless Sinusoidal Drive BLDC Controller Revision History Number Date – June 8, 2017 Description 1 September 15, 2017 2 December 4, 2017 Initial release Updated Speed Error values (p. 14), Figure 12 (p. 27), Peak Duty Cycle equation (p. 39), and Chip Fault State: VLR Undervoltage description (p. 50). Updated VLR Regulator section (p. 23), Current Limit section (p. 34), Figure 20 (p. 42), and Readback Register section (p. 60). Copyright ©2017, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 92